128K x 8
Radiation Hardened
Static RAM – 5 V
190A325
198A592
BAE SYSTEMS • 9300 Wellington Road • Manassas, Virginia 20110-4122
Product Description
Radiation
•Fabricated with Bulk CMOS 0.5 µm Process
•Total Dose Hardness through 1x106 rad(Si)
•Neutron Hardness through 1x1014 N/cm2
•Dynamic and Static Transient Upset Hardness
through 1x109 rad(Si)/s
•Soft Error Rate of < 1x10-11 Upsets/Bit-Day
•Dose Rate Survivability through 1x1012 rad(Si)/s
•Latchup Free
Features
Other
•Read/Write Cycle Times ≤25 ns, 30 ns, 40 ns (-55 to
125°C)
•SMD Number 5962H96877
•Asynchronous Operation
•CMOS or TTL Compatible I/O
•Single 5 V ±10% Power Supply
•Low Operating Power
•Packaging Options
•40-Lead Flat Pack (0.775” x 0.710”)
•40-Lead Flat Pack - Small Cavity (0.775” x 0.650”)
32-Lead Flat Pack (0.652” x 0.820”)
General Description
The 128K x 8 radiation hardened static RAM
is a high performance 131,072 word x 8-bit
static random access memory with industry-
standard functionality. It is fabricated with
BAE SYSTEMS’ radiation hardened
technology and is designed for use in
systems operating in radiation
environments. The RAM operates over the
full military temperature range and requires
a single 5 V ±10% power supply. The RAM
is available with either TTL or CMOS
compatible I/O. Power consumption is
typically less than 20 mW/MHz in operation,
and less than 10 mW in the low power
disabled mode. The RAM read operation is
fully asynchronous, with an associated
typical access time of 19 nanoseconds.
BAE SYSTEMS’ enhanced bulk CMOS
technology is radiation hardened through
the use of advanced and proprietary design,
layout, and process hardening techniques.
2
Functional Diagram
Signal Definitions
A: 0-16
DQ: 0-7
S
–Address input pins that select a particular
eight-bit word within the memory array.
–Bi-directional data pins that serve as data
outputs during a read operation and as data
inputs during a write operation.
–Negative chip select, when at a low level,
allows normal read or write operation. When at
a high level, S forces the SRAM to a
precharge condition, holds the data output
drivers in a high impedance state and disables
the data input buffers only. If this signal is not
used, it must be connected to GND.
–Negative write enable, when at a low level, activates a
write operation and holds the data output drivers in a
high impedance state. When at a high level, W allows
normal read operation.
–Negative output enable, when at a high level holds the
data output drivers in a high impedance state. When at
a low level, the data output driver state is defined by S,
W, and E. If this signal is not used it must be connected
to GND.
–Chip enable, when at a high level allows normal
operation. When at a low level, E forces the SRAM to a
precharge condition, holds the data output drivers in a
high impedance state and disables all the input buffers
except the S input buffer. If this signal is not used, it
must be connected to VDD.
W
G
E
Notes:
1) VIN for don’t care (X) inputs = VIL or VIH.
2) When G = high, I/O is high-Z.
3) To dissipate the minimum amount of
standby power when in standby mode:
S= VDD and E = GND. All other input
levels may float.
Truth Table
A0
A1 - A2
A3
A9 - A16
W
G
S
E
DQ0-DQ7 A4-A8
Top/Bottom Decoder
Block Address Decoder
L/R Side/Block
Row Address Decoder ((256 x 32) x 2 x 4) x 8 x 2
Memory Cell Array
8 Bit Word Input/Output
Column Address Decoder
Mode Inputs(1),(2)
E
High
High
X
Low
S
Low
Low
High
X
W
Low
High
X
X
G
X
Low
X
X
I/O
Data-In
Data-Out
High-Z
High-Z
Power
Active
Active
Standby
Standby
Write
Read
Standby
Standby(3)
3
Notes:
Note:
1)All voltages referenced to GND.
The substrate of this module is connected directly to Ground.
Power shall be applied to the device only in the following
sequences to prevent damage due to excessive currents:
•Power-Up Sequence: GND, VDD, Inputs
•Power-Down Sequence: Inputs, VDD, GND
Absolute Maximum Ratings
Recommended Operating Conditions
Power Sequencing
Minimum
+4.5
0.0
-55
0.0
0.0
+2.0
+3.5
Units
Volt
Volt
Celsius
Volt
Volt
Supply Voltage
Parameters(1)
Supply Voltage Reference
Case Temperature
Input Logic “Low” - CMOS
Input Logic “Low” - TTL
Input Logic “High” - TTL
Input Logic “High” - CMOS
Symbol
VDD
GND
TC
VIL
VIH
Maximum
+5.5
0.0
+125
+1.5
+0.8
VDD
VDD
Minimum
-65°C
-55°C
-0.5 V
-0.5 V
-0.5 V
(Class II)
Storage Temperature Range (Ambient)
Applied Conditions(1)
Operating Temperature Range
Positive Supply Voltage
Input Voltage(2)
Output Voltage(2)
Power Dissipation(3)
Lead Temperature (Soldering 5 sec)
Electrostatic Discharge Sensitivity(4)
Maximum
+150°C
+125°C
+7.0 V
VDD+ 0.5 V
2.0 W
+250°C
VDD+ 0.5 V
1) Stresses above the absolute maximum rating may cause permanent
damage to the device. Extended operation at the maximum levels may
degrade performance and affect reliability. All voltages are with
reference to the module ground leads.
2) Maximum applied voltage shall not exceed +7.0 V.
3) Guaranteed by design; not tested.
4) Class as defined in MIL-STD-883, Method 3015.
4
1) Typical operating conditions:
-55 °C ≤ Tcase ≤ +125°C; 4.5 V ≤ VDD ≤ 5.5 V; unless otherwise specified.
2) Guaranteed by design and verified by periodic characterization.
300 ± 10%Ω
2.8V
50 pF + 10%
Output Load Circuit
DC Electrical Characteristics
Note:
Symbol Test Conditions(1) Device Type Limits
Minimum Maximum Units
IDD1
VOH
F = FMAX = 1/tAVAV(min)
S = VIL = GND
E = VIH = VDD
No Output Load
S = VIH = VDD
E = VIL= GND
F = 0 MHz
VDD= 2.5 V
VDD = VDR
0 V ≤ VIN ≤ 5.5 V
CMOS
CMOS
TTL
TTL
By Design/
Verified By
Characterization
IOH = -200 µA
IOH= -4 mA
IOL = 200 µA
IOL= 8 mA
All
All
All
All
All
All
All
All
All
All
All
All
All
180
2.0
2.0
1.0
4.0
2.5
3.5
2.0
-5
-10
0.4
VDD - 0.5 V
0.05
1.5
0.8
5
10
7
10
mA
mA
mA
mA
V
V
V
µA
µA
pF
pF
V
V
Test
Supply Current
(Cycling Selected)
Supply Current
(Cycling De-Selected)
Supply Current
(Standby)
Data Retention Current
Data Retention Voltage
High Level Input Voltage
Low Level Input Voltage
Input Leakage
Output Leakage
Cin
Cout
High Level Output Voltage
Low Level Output Voltage
IDD2
IDD3
IDR
VOL
VDR
VIH
VIL
IILK
IOLK
F = FMAX = 1/tAVAV(min)
S = VIH = VDD
E = VIL= GND
0 V ≤ VOUT ≤ 5.5 V
By Design/
Verified By
Characterization
(2)
(2)
Note:
1)Test conditions: input switching levels VIL/VIH = 0.5 V/VDD -0.5 V (CMOS), VIL/VIH = 0 V/3 V (TTL), input rise
and fall times < 5 ns, input and output timing reference levels shown in the Tester AC Timing Characteristics
table, capacitive output loading CL = 50 pF. For CL > 50 pF, derate access times by 0.02 ns/pF (typical).
-55°C ≤ Tcase ≤ +125°C; 4.5 V ≤ VDD ≤ 5.5 V; unless otherwise specified.
5
Read Cycle AC Timing Characteristics(1)
Worst Case By Speed Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Test
Read Cycle Time
Output Hold After Address Change
Chip Select to Output Active
Chip Enable to Output Active
Output Enable to Output Active
Address Access Time
Chip Select Access Time
Chip Enable Access Time
Chip Select to Output Disable
Chip Disable to Output Disable
Output Enable to Output Disable
Output Enable Access Time
Minimum or
Maximum
Minimum
Minimum
Minimum
Minimum
Minimum
Maximum
Maximum
Maximum
Maximum
Maximum
Maximum
Maximum
-30
30
0
0
0
30
30
30
12
12
12
12
40FP - 0
32FP - 2
-40
40
40FP - 0
32FP - 2
0
0
0
40
40
40
15
15
15
15
-25
25
40FP - 0
32FP - 2
0
0
0
25
25
25
12
12
12
10
Symbol
tAVAV
tAVQV
tAXQX
tSLQV
tSLQX
tSHQZ
tEHQV
tEHQX
tELQZ
tGLQV
tGLQX
tGHQZ
Read Cycle Timing Diagram
Valid Address
Valid Data
High Impedance
Address
E
S
G
Data
Out
tAVAV
tAVQV
tSLQV
tSLQX tEHQV
tEHQX
tGLQV
tGLQX
tAXQX
tSHQZ
tELQZ
tSHQZ
Note:
1) Test conditions: input switching levels VIL/VIH = 0.5 V/VDD - 0.5 V (CMOS), VIL/VIH = 0 V/3 V (TTL), input rise and
fall times < 5 ns, input and output timing reference levels shown in the Tester AC Timing Characteristics table,
capacitive output loading = 50 pF. -55°C ≤ Tcase ≤ +125°C; 4.5 V ≤ VDD ≤ 5.5 V; unless otherwise specified.
tAVAV
Valid Address
Valid Data
High ImpedanceHigh Impedance
High Impedance High Impedance
Address
tAVWH
tSLWH
tEHWH
tWLWH
tAVWL tWLQZ tWHQX
tWHDX
tWHWL
tDVWH
S
E
W
Data
Out
Data
In
tWHAX
6
Write Cycle AC Timing Characteristics(1)
Worst Case By Speed
-30
30
24
24
0
24
24
24
0
5
12
24
0
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Test
Write Cycle Time
Chip Select to End of Write
Address Setup to End of Write
Address Hold After End of Write
Write Pulse Width Access Time
Write Pulse Width
Data Setup to End of Write
Address Setup to Start of Write
Data Hold After End of Write
Write Enable to Output Disable
Chip Enable to End of Write
Output Active After End of Write
Minimum or
Maximum
Minimum
Minimum
Minimum
Minimum
Minimum
Minimum
Minimum
Minimum
Minimum
Maximum
Minimum
Minimum
-40
40
30
30
0
30
30
30
0
5
15
30
0
-25
25
19
19
0
19
19
19
0
5
12
19
1
Symbol
tAVAV
tWLWH
tSLWH
tDVWH
tAVWH
tWHDX
tAVWL
tWHAX
tWLQZ
tWHQX
tWLWH
tEHWH
Write Cycle Timing Diagram
7
Dynamic Electrical Characteristics
Read Cycle
The RAM is asynchronous in operation, allowing the read
cycle to be controlled by address, chip select (S), or chip
enable (E) (refer to Read Cycle Timing diagram). To
perform a valid read operation, both chip select and output
enable (G) must be low and chip enable and write enable
(W) must be high. The output drivers can be controlled
independently by the G signal. Consecutive read cycles can
be executed with S held continuously low, and with E held
continuously high, and toggling the addresses.
For an address-activated read cycle, S and E must be valid
prior to or coincident with the activating address edge
transition(s). Any amount of toggling or skew between
address edge transitions is permissible; however, data
outputs will become valid tAVQV time following the latest
occurring address edge transition. The minimum address
activated read cycle time is tAVQV . When the RAM is
operated at the minimum address-activated read cycle time,
the data outputs will remain valid on the RAM I/O until tAXQX
time following the next sequential address transition.
To control a read cycle with S, all addresses and E must be
valid prior to or coincident with the enabling S edge
transition. Address or E edge transitions can occur later
than the specified setup times to S; however, the valid data
access time will be delayed. Any address edge transition,
that occurs during the time when S is low, will initiate a new
read access, and data outputs will not become valid until
tAVQV time following the address edge transition. Data
outputs will enter a high impedance state tSHQZ time
following a disabling S edge transition.
To control a read cycle with E, all addresses and S must be
valid prior to or coincident with the enabling E edge
transition. Address or S edge transitions can occur later
than the specified setup times to E; however, the valid data
access time will be delayed. Any address edge transition
that occurs during the time when E is high will initiate a new
read access, and data outputs will not become valid until
tAVQV time following the address edge transition. Data
outputs will enter a high impedance state tELQZ time
following a disabling E edge transition.
Write Cycle
The write operation is synchronous with respect to the
address bits, and control is governed by write enable (W),
chip select (S), or chip enable (E) edge transitions (refer
to Write Cycle Timing diagrams). To perform a write
operation, both W and S must be low, and E must be
high. Consecutive write cycles can be performed with W
or S held continuously low, or E held continuously high. At
least one of the control signals must transition to the
opposite state between consecutive write operations.
The write mode can be controlled via three different
control signals: W, S, and E. All three modes of control
are similar except the S and E controlled modes actually
disable the RAM during the write recovery pulse. Only the
W controlled mode is shown in the table and diagram on
the previous page for simplicity. However, each mode of
control provides the same write cycle timing
characteristics. Thus, some of the parameter names
referenced below are not shown in the write cycle table or
diagram, but indicate which control pin is in control as it
switches high or low.
To write data into the RAM, W and S must be held low
and E must be held high for at least tWLWH /tSLSH /tEHEL time.
Any amount of edge skew between the signals can be
tolerated and any one of the control signals can initiate or
terminate the write operation. For consecutive write
operations, write pulses must be separated by the
minimum specified tWHWL /tSHSL /tELEH time. Address inputs
must be valid at least tAVWL /tAVSL /tAVEH time before the
enabling W/S/E edge transition, and must remain valid
during the entire write time. A valid data overlap of write
pulse width time of tDVWH /tDVSH /tDVEL, and an address valid to
end of write time of tAVWH /tAVSH /tAVEL also must be provided
for during the write operation. Hold times for address
inputs and data inputs with respect to the disabling W/S/E
edge transition must be a minimum of tWHAX /tSHAX /tELAX time
and tWHDX /tSHDX /tELDX time, respectively. The minimum write
cycle time is tAVAV.
8
Radiation Characteristics
Total Ionizing Radiation Dose
The SRAM will meet all stated functional and electrical
specifications over the entire operating temperature range
after a total ionizing radiation dose of 1x106 rad(Si). All
electrical and timing performance parameters will remain
within specifications after rebound at VDD = 5.5 V and T =
125°C extrapolated to ten years of operation. Total dose
hardness is assured by wafer level testing of process monitor
transistors and RAM product using 10 keV X-ray and Co60
radiation sources. Transistor gate threshold shift correlations
have been made between 10 keV X-rays applied at a dose
rate of 1x105 rad(Si)/min at T = 25°C and gamma rays (Cobalt
60 source) to ensure that wafer level X-ray testing is
consistent with standard military radiation test environments.
Transient Pulse Ionizing Radiation
The SRAM is capable of writing, reading, and retaining stored
data during and after exposure to a transient ionizing radiation
pulse of ≤ 50 ns duration up to 1x109 rad(Si)/s, when applied
under recommended operating conditions. To ensure validity
of all specified performance parameters before, during, and
after radiation (timing degradation during transient pulse
radiation is ≤ 10%), stiffening capacitance can be placed on
the package between the package (chip) VDD and GND with
the inductance between the package (chip) and stiffening
capacitance kept to a minimum. If there are no operate-
through or valid stored data requirements, typical de-coupling
capacitors should be mounted on the circuit board as close as
possible to each device.
The SRAM will meet any functional or electrical
specification after exposure to a radiation pulse of ≤ 50 ns
duration up to 1x1012 rad(Si)/s, when applied under
recommended operating conditions. Note that the current
conducted during the pulse by the RAM inputs, outputs,
and power supply may significantly exceed the normal
operating levels. The application design must
accommodate these effects.
Neutron Radiation
The SRAM will meet any functional or timing specification
after a total neutron fluence of up to 1x1014 cm-2 applied
under recommended operating or storage conditions. This
assumes an equivalent neutron energy of 1 MeV.
Soft Error Rate
The SRAM has a soft error rate (SER) performance of
<1x10-11 upsets/bit-day, under recommended operating
conditions. This hardness level is defined by the Adams
90% worst case cosmic ray environment.
Latchup
The SRAM will not latch up due to any of the above
radiation exposure conditions when applied under
recommended operating conditions.
Radiation Hardness Ratings (1),(2)
Notes:
1) Measured at room temperature unless otherwise stated. Verification test per TRB approved test plan.
2) Device electrical characteristics are guaranteed for post irradiation levels at 25°C.
3) 90% worst case particle environment, geosynchronous orbit, 0.025’’ of aluminum shielding.
Specification set using the CREME code upset rate calculation method with a 2 µm epi thickness.
4) Immune for LET ≤ 120 MeV/mg/cm 2.
ConditionsCharacteristics
Total Dose
Single Event Upset (3)
Prompt Dose Upset
Single Event Induced Latchup
Survivability
Single Event Upset(3)
Neutron Fluence
Units
rad(Si)
Upsets/Bit-Day
rad(Si)/s
Immune (4)
rad(Si)/s
Upsets/Bit-Day
N/cm 2
Maximum
1E - 10
1E - 11
Symbol
RTD
SEU2
RPRU
SEL
RS
SEU1
RNF
Minimum
1E + 06
1E + 09
1E + 12
1E + 14
20 - 50 ns Pulse Width
Tcase = 25°C and 125°C
MIL-STD-883, TM 1019.5
Condition A
20 - 50 ns Pulse Width
Tcase = 125°C
-55°C ≤ Tcase ≤ 80°C
-55°C ≤ Tcase ≤ 125°C
-55°C ≤ Tcase ≤ 125°C
VDD = 5.5 V
9
*Input rise and fall times <5 ns
Tester AC Timing Characteristics
Radiation Hardness Assurance Reliability
BAE SYSTEMS’ reliability starts with an overall product
assurance system that utilizes a quality system involving all
employees including operators, process engineers and
product assurance personnel. An extensive wafer lot
acceptance methodology, using in-line electrical data as well
as physical data, assures product quality prior to assembly. A
continuous reliability monitoring program evaluates every lot
at the wafer level, utilizing test structures as well as product
testing. Test structures are placed on every wafer, allowing
correlation and checks within-wafer, wafer-to-wafer, and from
lot-to-lot.
Reliability attributes of the CMOS process are characterized
by testing both irradiated and non-irradiated test structures.
The evaluations allow design model and process changes to
be incorporated for specific failure mechanisms, i.e., hot
carriers, electromigration, and time dependent dielectric
breakdown. These enhancements to the operation create a
more reliable product.
The process reliability is further enhanced by accelerated
dynamic life tests of both irradiated and non-irradiated test
structures. Screening and testing procedures from the
customer are followed to qualify the product.
A final periodic verification of the quality and reliability of the
product is validated by a TCI (Technology Conformance
Inspection).
BAE SYSTEMS has two QML screen levels (Q and V) to meet
full compliant space applications. For limited performance and
evaluation situations, BAE SYSTEMS offers an engineering
screen level.
Screening Levels
BAE SYSTEMS provides a superior quality level of radiation
hardness assurance for our products. The excellent product
quality is sustained via the use of our qualified QML operation
which requires process control with statistical process control,
radiation hardness assurance procedures and a rigid
computer controlled manufacturing operation monitoring and
tracking system.
The BAE SYSTEMS technology is built with resistance to
radiation effects. Our product is designed to exhibit < 1e -11
fails/bit-day in a 90% worst case geosynchronous orbit under
worst case operating conditions. Total dose hardness is
assured by irradiating test structures on every lot and total
dose exposure with Cobalt 60 testing performed quarterly on
TCI lots to assure the product is meeting the QML radiation
hardness requirements.
TTL I/O Configuration CMOS I/O Configuration
3 V
VDD- 0.4 V
3.4 V
0.4 V
2.4 V
1.5 V
High Z
High Z
High Z = 2.9 V
0 V 1.5 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . .
. . . . . . . . . .
. . . . . . . . . . . . . . . .
. . . . . . . .
. . . . . . . .
0.5 V
Input
Levels*
Output
Sense
Levels
3.4 V
0.4 V
2.4 V
High Z
High Z
High Z = 2.9 V
VDD/2
VDD- 0.4 V
VDD/2
VDD- 0.5 V
10
Pin Listing Input
A0
A1
A2
A3
A4
Signal
F/2
F/4
F/8
F/16
F/32
Input
W
DQ0 . . . 7
S
G
E
Signal
F/262144
F
VIL
VIH First Half
VIL Second Half
VIH
Input
A12
A13
A14
A15
A16
A11 Signal
F/8192
F/16384
F/32768
F/65536
F/131072
F/4096
Input
A6
A7
A8
A9
A10
A5 Signal
F/128
F/256
F/512
F/1024
F/2048
F/64
Standard Screening Procedure
Stress Methodology
There are two methods of burn-in defined. For “Static” burn-in,
all possible addresses are written with a logic “1” for half of the
burn-in duration and a logic “0” for the remaining half. For
“Dynamic” burn-in, all possible addresses are written with
alternating high and low data.
All I/O pins specified in the static and dynamic burn-in pin lists
are driven through individual series resistors (1.6K Ω ±10%).
The burn-in circuit diagram is shown at right.
Voltage Levels
• Vin(0): 0.0 V to + 0.4 V
–VIL = Low level for all programmed signals
•Vin(1): + 5.4 V to + 6.0 V
–VIH = High level for all programmed signals
• V1: + 5.5 V (-0% / +10%)
–All VDD pins are tied to this level
•Vsx: Float or GND
–All GND pins are tied to this level
V1
C1 C1 = 0.1 µF (±10%)
R = 1.6KΩ (±10%)
S
E
W
G
DQ0
DIN
DQ7
A0
A16
•
•
•
•
•
•
•
•
R
R
R
R
R
R
R
R
128K x 8
SRAM
The dynamic
burn-in pin listing
is shown at right.
F = square wave,
100 KHz to
1.0 MHz.
X
X
Sample
X
X
X
X
X
X
X
X
X
X
X
X
Sample
X
X
X
X
X
X
X
X
X
X
X
X
X
Alternate Method Used
Die Traceability
MIL-STD-883, TM 2010
5.5 V, 125°C, 144 Hours
Meets Group A
< 5% Fallout
MIL-STD-883, TM 2009
Wafer Lot Acceptance
Serialization
Destructive Bond Pull
Internal Visual
Temperature Cycle
Constant Acceleration
PIND
Radiography
Electrical Test
Dynamic Burn-In
Electrical Test
Static Burn-In
Final Electrical
PDA
Fine and Gross Leak
External Visual
Comments
QV
Flow QML Level
Burn-In Circuit
Notes:
1) Part mark per device specification.
2) ‘‘QML’’ may not be required per device specification
3) Dimensions are in inches.
4) Lead width: .008 ± .002.
5) Lead Height: .006 ± .002.
6) Unless otherwise specified, all tolerances are ± .005.
7A9
12A16
9A13
14DQ1
11A15
16GND
5A12
3A2
1NC
6A11
2A0
8A10
13DQ0
10A14
15DQ2
4A1
A726
DQ721
G24
DQ519
S22
DQ317
A528
E30
VDD
32
A627
A331
A825
DQ620
23 A4
DQ418
W
29
Top
View
11
A=1.802
B=.652 ± .008
C=.820
D=.755 ± .008
E=.400 ± .020
F=.175 ± .010
G=.050 ± .003
H=.017
J=.130 ± .013
K=.035
L=.550
A=1.635
B=.775 ± .008
C=.710
D=.475
E=.285 ± .015
F=.135
G=.025 ± .002
H=.006 + .0015
.006 - .0010
J=.125 ± .013
K=.030
L=.635 ± .010
JK
L
A
B
Lead 1
Lead 16
Lead 32
Lead 17 G
(Pitch)
H
(Width)
C D
EF
(1), (2)
Packaging
7A10
12A15
17NC
9A1
14DQ0
11A14
16DQ2
5A11
3VDD
1A0
6A9
2GND
8A2
13A16
18VDD
10A13
15DQ1
4A12
19GND 20NC
A634
S29
DQ324
A832
DQ627
A430
DQ425
E36
VDD
38
A340
A535
GND39
A733
DQ728
VDD
23
G31
DQ526
W37
GND22 NC21
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32-Lead Flat Pack Pinout 40-Lead Flat Pack Pinout
32-Lead Flat Pack 40-Lead Flat Pack
The 128Kx 8 SRAM is offered in a custom 40-lead FP or
a 32-lead FP. All packages are constructed of multilayer
ceramic (AI2O3) and feature internal power and ground
planes.
Optional capacitors can be mounted to the package to
maximize supply noise decoupling and increase board
packing density. These capacitors attach directly to the
internal package power and ground planes. This design
minimizes resistance and inductance of the bond wire and
package, both of which are critical in a transient radiation
environment. All NC pins must be connected to either VDD,
GND or an active driver to prevent charge build up in the
radiation environment. (NC = no connect.)
A
B
Lead 1
Lead 20
(1), (2)
Lead 40
Lead 21 G
(Pitch)
H
(Width)
C D
EF
JK
L
128K x 8 CMOS Memory Device (5 V)
•Part Number 190A325-
128K x 8 TTL Memory Device (5 V)
•Part Number 198A592-
X
Cleared for Public Domain Release
©2001 BAE SYSTEMS, All Rights Reserved
BAE SYSTEMS • 9300 Wellington Road • Manassas, Virginia 20110-4122
BAE SYSTEMS
An ISO 9001, AS9000, ISO 14001,
and SEI CMM Level 4 Company
9300 Wellington Road, Manassas, VA 20110-4122
866-530-8104
http://www.baesystems-iews.com/space/
0035_128K_8_SRAM.ppt
BAE SYSTEMS reserves the right to make changes to
any products herein to improve reliability, function or
design. BAE SYSTEMS does not assume liability arising
out of the application or use of any product or circuit
described herein, neither does it convey any license
under its patent rights nor the rights of others.
Ordering Information
YZ
X Y Z
Z
Screen
Designation
X
Package
Designation
1=40-Lead FP
2 =32-Lead FP 1=QML VV
3=Engineering
4=QML VQ
5=QML QQ
7=Customer Specific
Y
Speed
Designation
2 = 25 ns
3 = 30 ns
4 = 40 ns
