ASAHI KASEI [AK4529]
MS0082-E-00 2001/3
- 1 -
GENERAL DESCRIPTION
The AK4529 is a single chip CODEC that includes two channels of ADC and eight channels of DAC. The
ADC outputs 24bit data and the DAC accepts up to 24bit input data. The ADC has the Enhanced Dual Bit
architecture with wide dynamic range. The DAC introduces the new developed Advanced Multi-Bit
architecture, and achieves wider dynamic range and lower outband noise. An auxiliary digital audio input
interface maybe used instead of the ADC for passing audio data to the primary audio output port. Control
may be set directly by pins or programmed through a separate serial interface.
The AK4529 has a dynamic range of 102dB for ADC, 106dB for DAC and is well suited for digital surround
for home theater and car audio. An AC-3 system can be built with a IEC60958(SPDIF) receiver such as
the AK4112A. The AK4529 is available in a small 44pin LQFP package which will reduce system space.
*AC-3 is a trademark of Dolby Laboratories.
FEATURES
o 2ch 24bit ADC
- 64x Oversampling
- Sampling Rate up to 96kHz
- Linear Phase Digital Anti-Alias Filter
- Single-Ended Input
- S/(N+D): 92dB
- Dynamic Range, S/N: 102dB
- Digital HPF for offset cancellation
- I/F format: MSB justified, I2S or TDM
- Overflow flag
o 8ch 24bit DAC
- 128x Oversampling
- Sampling Rate up to 96kHz
- 24bit 8 times Digital Filter
- Single-Ended Outputs
- On-chip Switched-Capacitor Filter
- S/(N+D): 90dB
- Dynamic Range, S/N: 106dB
- I/F format: MSB justified, LSB justified(20bit,24bit), I2S or TDM
- Individual channel digital volume with 256 levels and 0.5dB step
- Soft mute
- De-emphasis for 32kHz, 44.1kHz and 48kHz
- Zero Detect Function
o High Jitter Tolerance
o TTL Level Digital I/F
o 3-wire Serial and I2C Bus µP I/F for mode setting
o Master clock:256fs, 384fs or 512fs for fs=32kHz to 48kHz
128fs, 192fs or 256fs for fs=64kHz to 96kHz
o Power Supply: 4.5 to 5.5V
o Power Supply for output buffer: 2.7 to 5.5V
o Small 44pin LQFP
High Performance Multi-channel Audio CODEC
AK4529
ASAHI KASEI [AK4529]
MS0082-E-00 2001/3
- 2 -
n Block Diagram
Audio
I/F
LPF
LPF
DAC DATT
LPF
DAC DATT
LPF
DAC DATT
LPF
DAC DATT
LPF
DA
C
DATT
LOUT1
ROUT1
LOUT2
ROUT2
LOUT3
ROUT3
DAC DATT
AK4529
ADC HPF
ADC HPF
RIN
LIN
LRCK
BICK
SDOUT1
SDOUT2
SDOUT3
AC3
SDIN
MCKO
LRCK
BICK
XTI
XTO DIR
SDTO
AK4112A
RX4RX3RX2RX1
LRCK
BICK
SDTI1
SDTI2
SDTI3
DAUX
SDOS
MCLK
LRCK
BICK
SDOUT
SDIN1
SDIN2
SDIN3
MCLK
SDTO
Format
Converter
SDOUT4
SDTI4
SDIN4
LPF
DA
C
DATT
LPF
DAC DATT
LOUT4
ROUT4
Block Diagram (DIR and AC-3 DSP are external parts)
ASAHI KASEI [AK4529]
MS0082-E-00 2001/3
- 3 -
n Ordering Guide
AK4529VQ -40 ∼ +85°C 44pin LQFP(0.8mm pitch)
AKD4529 Evaluation Board for AK4529
n Pin Layout
S
DOS
TDM
1
I2C
4
4
2
S
MUTE 3
B
ICK 4
L
RCK 5
S
DTI1 6
S
DTI2 7
S
DTI3 8
S
DTO 9
D
AUX 10
D
FS 11
LOOP0/SDA/CDTI
4
3
DIF1/SCL/CCLK
42
41
4
0
MCLK
3
9
DZF1
3
8
AVSS
37
AVDD
3
6
VREFH
3
5
VCOM
3
4
SDTI4 12
DZFE
13
TVDD 14
DVDD 15
DVSS 16
17
TST 18
CAD1
19
CAD0 20
LOUT4
21
ROUT4 22
33
32
31
30
29
28
27
26
25
24
23
DZF2/OVF
RIN
LIN
NC
NC
ROUT1
LOUT1
ROUT2
LOUT2
ROUT3
LOUT3
AK4529VQ
Top View
PDN
DIF0/CSN
P/S
ASAHI KASEI [AK4529]
MS0082-E-00 2001/3
- 4 -
n Compatibility with AK4527B
1. Functions
Functions AK4527B AK4529
DAC channel 6ch 8ch
ADC Full-differential input
(with single-ended use capability) Single-ended input
DATT transition time 7424/fs (fixed) 7424/fs, 1024/fs or 256/fs
I2C bus auto increment Not available Available
TDM I/F format Not available Available
2. Pin Configuration
pin# AK4527 AK4529
12 NC SDTI4
19 NC CAD1
20 NC CAD0
21 CAD1 LOUT4
22 CAD0 ROUT4
29 LIN- NC
30 LIN+ NC
31 RIN- LIN
32 RIN+ RIN
44 LOOP1 TDM
3. Register
Addr Changed items
00H TDM (TDM I/F format mode) is added.
08H DEMD1-0 (DAC4 De-emphasis) are added.
09H ATS1-0 (DATT transition time) are added.
0AH DZFM3 (Zero detection mode) is added.
0BH ATT7-0 (LOUT4 output volume control) are added.
0CH ATT7-0 (ROUT4 output volume control) are added.
ASAHI KASEI [AK4529]
MS0082-E-00 2001/3
- 5 -
PIN/FUNCTION
No. Pin Name I/O Function
1 SDOS I SDTO Source Select Pin (Note 1)
“L”: Internal ADC output, “H”: DAUX input
SDOS pin should be set to “L” when TDM= “1”.
2 I2C I Control Mode Select Pin
“L”: 3-wire Serial, “H”: I2C Bus
3 SMUTE I Soft Mute Pin (Note 1)
When this pin goes to “H”, soft mute cycle is initialized.
When returning to “L”, the output mute releases.
4 BICK I Audio Serial Data Clock Pin
5 LRCK I Input Channel Clock Pin
6 SDTI1 I DAC1 Audio Serial Data Input Pin
7 SDTI2 I DAC2 Audio Serial Data Input Pin
8 SDTI3 I DAC3 Audio Serial Data Input Pin
9 SDTO O Audio Serial Data Output Pin
10 DAUX I AUX Audio Serial Data Input Pin
11 DFS I Double Speed Sampling Mode Pin (Note 1)
“L”: Normal Speed, “H”: Double Speed
12 SDTI4 I DAC4 Audio Serial Data Input Pin
13 DZFE I Zero Input Detect Enable Pin
“L”: mode 7 (disable) at parallel mode,
zero detect mode is selectable by DZFM3-0 bits at serial mode
“H”: mode 0 (DZF1 is AND of all eight channels)
14 TVDD - Output Buffer Power Supply Pin, 2.7V∼5.5V
15 DVDD - Digital Power Supply Pin, 4.5V∼5.5V
16 DVSS - Digital Ground Pin, 0V
17 PDN I Power-Down & Reset Pin
When “L”, the AK4529 is powered-down and the control registers are reset to default
state. If the state of P/S or CAD0-1 changes, then the AK4529 must be reset by PDN.
18 TST I Test Pin
This pin should be connected to DVSS.
19 CAD1 I Chip Address 1 Pin
20 CAD0 I Chip Address 0 Pin
21 LOUT4 O DAC4 Lch Analog Output Pin
22 ROUT4 O DAC4 Rch Analog Output Pin
ASAHI KASEI [AK4529]
MS0082-E-00 2001/3
- 6 -
No. Pin Name I/O Function
23 LOUT3 O DAC3 Lch Analog Output Pin
24 ROUT3 O DAC3 Rch Analog Output Pin
25 LOUT2 O DAC2 Lch Analog Output Pin
26 ROUT2 O DAC2 Rch Analog Output Pin
27 LOUT1 O DAC1 Lch Analog Output Pin
28 ROUT1 O DAC1 Rch Analog Output Pin
29 NC - No Connect
No internal bonding.
30 NC - No Connect
No internal bonding.
31 LIN I Lch Analog Input Pin
32 RIN I Rch Analog Input Pin
DZF2 O Zero Input Detect 2 Pin (Note 2)
When the input data of the group 1 follow total 8192 LRCK cycles with “0” input data,
this pin goes to “H ”.
33
OVF O Analog Input Overflow Detect Pin (Note 3)
This pin goes to “H” if the analog input of Lch or Rch is overflows.
34 VCOM O Common Voltage Output Pin, AVDD/2
Large external capacitor around 2.2µF is used to reduce power-supply noise.
35 VREFH I Positive Voltage Reference Input Pin, AVDD
36 AVDD - Analog Power Supply Pin, 4.5V∼5.5V
37 AVSS - Analog Ground Pin, 0V
38 DZF1 O Zero Input Detect 1 Pin (Note 2)
When the input data of the group 1 follow total 8192 LRCK cycles with “0” input data,
this pin goes to “H”.
39 MCLK I Master Clock Input Pin
40 P/S I Parallel/Serial Select Pin
“L”: Serial control mode, “H”: Parallel control mode
DIF0 I Audio Data Interface Format 0 Pin in parallel control mode41 CSN I Chip Select Pin in 3-wire serial control mode
This pin should be connected to DVDD at I2C bus control mode
DIF1 I Audio Data Interface Format 1 Pin in parallel control mode42 SCL/CCLK I Control Data Clock Pin in serial control mode
I2C = “ L”: CCLK (3-wire Serial), I2C = “H”: SCL (I2C Bus)
LOOP0 I Loopback Mode 0 Pin in parallel control mode
Enables digital loop-back from ADC to 4 DACs.
43
SDA/CDTI I/O Control Data Input Pin in serial control mode
I2C = “ L”: CDTI (3-wire Serial), I2C = “H”: SDA (I2C Bus)
44 TDM I TDM I/F Format Mode Pin (Note 1)
“L”: Normal format, “H”: TDM format
Notes: 1. SDOS, SMUTE, DFS, and TDM pins are ORed with register data if P/S = “L”.
2. The group 1 and 2 can be selected by DZFM3-0 bits if P/S = “L” and DZFE = “L”.
3. This pin becomes OVF pin if OVFE bit is set to “1” at serial control mode.
4. All input pins should not be left floating.
ASAHI KASEI [AK4529]
MS0082-E-00 2001/3
- 7 -
ABSOLUTE MAXIMUM RATINGS
(AVSS, DVSS=0V; Note 5)
Parameter Symbol min max Units
Power Supplies Analog
Digital
Output buffer
|AVSS-DVSS| (Note 6)
AVDD
DVDD
TVDD
∆GND
-0.3
-0.3
-0.3
-
6.0
6.0
6.0
0.3
V
V
V
V
Input Current (any pins except for supplies) IIN - ±10 mA
Analog Input Voltage VINA -0.3 AVDD+0.3 V
Digital Input Voltage VIND -0.3 DVDD+0.3 V
Ambient Temperature (power applied) Ta -40 85 °C
Storage Temperature Tstg -65 150 °C
Notes: 5. All voltages with respect to ground.
6. AVSS and DVSS must be connected to the same analog ground plane.
WARNING: Operation at or beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
RECOMMENDED OPERATING CONDITIONS
(AVSS, DVSS=0V; Note 5)
Parameter Symbol min typ max Units
Power Supplies
(Note 7) Analog
Digital
Output buffer
AVDD
DVDD
TVDD
4.5
4.5
2.7
5.0
5.0
5.0
5.5
5.5
5.5
V
V
V
Notes: 5. All voltages with respect to ground.
7. The power up sequence between AVDD, DVDD and TVDD is not critical.
WARNING: AKM assumes no responsibility for the usage beyond the conditions in this datasheet.
ASAHI KASEI [AK4529]
MS0082-E-00 2001/3
- 8 -
ANALOG CHARACTERISTICS
(Ta=25°C; AVDD, DVDD, TVDD=5V; AVSS, DVSS=0V; VREFH=AVDD; fs=44.1kHz; BICK=64fs;
Signal Frequency=1kHz; 24bit Data; Measurement Frequency=20Hz∼20kHz at 44.1kHz, 20Hz~40kHz at fs=96kHz;
unless otherwise specified)
Parameter min typ max Units
ADC Analog Input Characteristics
Resolution 24 Bits
S/(N+D) (-0.5dBFS) fs=44.1kHz
fs=96kHz 84
- 92
86 dB
dB
DR (-60dBFS) fs=44.1kHz, A-weighted
fs=96kHz
fs=96kHz, A-weighted
94
88
93
102
96
102
dB
dB
dB
S/N (Note 8) fs=44.1kHz, A-weighted
fs=96kHz
fs=96kHz, A-weighted
94
88
93
102
96
102
dB
dB
dB
Interchannel Isolation 90 1 10 d B
DC Accuracy
Interchannel Gain Mismatch 0. 2 0.3 dB
Gain Drift 20 - ppm/°C
In put Voltage fs=44.1kHz AIN=0.62xVREFH
fs=96kHz AIN=0.65xVREFH 2.90
3.05 3.10
3.25 3.30
3.45 Vpp
Vpp
Input Resistance (Note 9) 15 25 kΩ
Power Supply Rejection (Note 10) 50 dB
DAC Analog Output Characteristics
Resolution 24 Bits
S/(N+D) fs=44.1kHz
fs=96kHz 80
78 90
88 dB
dB
DR (-60dBFS) fs=44.1kHz, A-weighted
fs=96kHz
fs=96kHz, A-weighted
95
88
94
106
100
106
dB
dB
dB
S/N (Note 11) fs=44.1kHz, A-weighted
fs=96kHz
fs=96kHz, A-weighted
95
88
94
106
100
106
dB
dB
dB
Interchannel Isolation 9 0 1 10 dB
DC Accuracy
Interchannel Gain Mismatch 0. 2 0. 5 dB
Gain Drift 2 0 - ppm/°C
Output Voltage AOUT=0.6xVREFH 2.75 3.0 3.25 Vpp
Load Resistance 5 kΩ
Power Supply Rejection (Note 10) 50 dB
Power Supplies
Power Supply Current (AVDD+DVDD+TVDD)
Normal Operation (PDN = “H”)
AVDD
DVDD+TVDD fs=44.1kHz (Note 12)
fs=96kHz
Power-down mode (PDN = “L”) (Note 13)
42
28
42
80
63
42
63
200
mA
mA
mA
µA
Notes: 8. S/N measured by CCIR-ARM is 98dB(@fs=44.1kHz).
9. Input resistance is 16kΩ typically at fs=96kHz.
10. PSR is applied to AVDD, DVDD and TVDD with 1kHz, 50mVpp. VREFH pin is held a constant voltage.
11. S/N measured by CCIR-ARM is 102dB(@fs=44.1kHz).
12. TVDD=0.1mA(typ).
13. In the power-down mode. All digital input pins including clock pins (MCLK, BICK, LRCK) are held DVSS.
ASAHI KASEI [AK4529]
MS0082-E-00 2001/3
- 9 -
FILTER CHARACTERISTICS
(Ta=25°C; AVDD, DVDD=4.5∼5.5V; TVDD=2.7∼5.5V; fs=44.1kHz; DEM=OFF)
Parameter Symbol min typ max Units
ADC Digital Filter (Decimation LPF):
Passband (Note 14) -0.005dB
-0.02dB
-0.06dB
-6.0dB
PB 0
-
-
-
20.02
20.20
22.05
19.76
-
-
-
kHz
kHz
kHz
kHz
Stopband SB 24.34 kHz
Passband Ripple PR ±0.005 dB
Stopband Attenuation SA 80 dB
Group Delay (Note 15) GD 27.6 1/fs
Group Delay Distortion ∆GD 0µs
ADC Digital Filter (HPF):
Frequency Response (Note 14) -3dB
-0.5dB
-0.1dB
FR 0.9
2.7
6.0
Hz
Hz
Hz
DAC Digital Filter:
Passband (Note 14) -0.1dB
-6.0dB PB 0
- 22.05 20.0
-kHz
kHz
Stopband SB 24.2 kHz
Passband Ripple PR ±0.02 dB
Stopband Attenuation SA 56 dB
Group Delay (Note 15) GD 21.9 1/fs
DAC Digital Filter + Analog Filter:
Frequency Response: 0 ∼ 20.0kHz
40.0kHz (Note 16) FR
FR ±0.2
±0.3 dB
dB
Notes: 14. The passband and stopband frequencies scale with fs.
For example, 20.02kHz at –0.02dB is 0.454 x fs. The reference frequency of these responses is 1kHz.
15. The calculating delay time which occurred by digital filtering. This time is from setting the input of analog
signal to setting the 24bit data of both channels to the output register for ADC.
For DAC, this time is from setting the 20/24bit data of both channels on input register to the output of analog
signal.
16. fs=96kHz.
DC CHARACTERISTICS
(Ta=25°C; AVDD, DVDD=4.5∼5.5V; TVDD=2.7∼5.5V)
Parameter Symbol min typ max Units
High-Level Input Voltage
Low-Level Input Voltage VIH
VIL 2.2
--
--
0.8 V
V
High-Level Output Voltage
(SDTO pin: Iout=-100µA)
(DZF1, DZF2/OVF pins: Iout=-100µA)
Low-Level Output Voltage
(SDTO, DZF1, DZF2/OVF pins: Iout= 100µA)
(SDA pin: Iout= 3mA)
VOH
VOH
VOL
VOL
TVDD-0.5
AVDD-0.5
-
-
-
-
-
-
-
-
0.5
0.4
V
V
V
V
Input Leakage Current Iin - - ±10 µA
ASAHI KASEI [AK4529]
MS0082-E-00 2001/3
- 10 -
SWITCHING CHARACTERISTICS
(Ta=25°C; AVDD, DVDD= 4.5 ∼5.5V; TVDD=2.7∼5.5V; CL=20pF)
Parameter Symbol min typ max Units
Master Clock Timing
256fsn, 128fsd:
Pulse Width Low
Pulse Width High
384fsn, 192fsd:
Pulse Width Low
Pulse Width High
512fsn, 256fsd:
Pulse Width Low
Pulse Width High
fCLK
tCLKL
tCLKH
fCLK
tCLKL
tCLKH
fCLK
tCLKL
tCLKH
8.192
27
27
12.288
20
20
16.384
15
15
12.288
18.432
24.576
MHz
ns
ns
MHz
ns
ns
MHz
ns
ns
LRCK Timing
TDM= “0”
Normal Speed Mode
Double Speed Mode
Duty Cycle
fsn
fsd
Duty
32
64
45
48
96
55
kHz
kHz
%
TDM= “1”
LRCK frequency
“H” time
“L” time
fsn
tLRH
tLRL
32
1/256fs
1/256fs
48 kHz
ns
ns
Audio Interface Timing
TDM= “0”
BICK Period
BICK Pulse Width Low
Pulse Width High
LRCK Edge to BICK “↑” (Note 17)
BICK “↑” to LRCK Edge (Note 17)
LRCK to SDTO(MSB)
BICK “↓” to SDTO
SDTI1-4, DAUX Hold Time
SDTI1-4, DAUX Setup Time
tBCK
tBCKL
tBCKH
tLRB
tBLR
tLRS
tBSD
tSDH
tSDS
160
65
65
45
45
40
25
40
40
ns
ns
ns
ns
ns
ns
ns
ns
ns
TDM= “1”
BICK Period
BICK Pulse Width Low
Pulse Width High
LRCK Edge to BICK “↑” (Note 17)
BICK “↑” to LRCK Edge (Note 17)
BICK “↓” to SDTO
SDTI1 Hold Time
SDTI1 Setup Time
tBCK
tBCKL
tBCKH
tLRB
tBLR
tBSD
tSDH
tSDS
81
32
32
20
20
10
10
20
ns
ns
ns
ns
ns
ns
ns
ns
Notes: 17. BICK rising edge must not occur at the same time as LRCK edge.
ASAHI KASEI [AK4529]
MS0082-E-00 2001/3
- 11 -
Parameter Symbol min typ max Units
Control Interface Timing (3-wire Serial mode):
CCLK Period
CCLK Pulse Width Low
Pulse Width High
CDTI Setup Time
CDTI Hold Time
CSN “H” Time
CSN “↓” to CCLK “↑”
CCLK “↑” to CSN “↑”
Rise Time of CSN
Fall Time of CSN
Rise Time of CCLK
Fall Time of CCLK
tCCK
tCCKL
tCCKH
tCDS
tCDH
tCSW
tCSS
tCSH
tR1
tF1
tR2
tF2
200
80
80
40
40
150
50
50 20
20
20
20
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Control Interface Timing (I2C Bus mode):
SCL Clock Frequency
Bus Free Time Between Transmissions
Start Condition Hold Time (prior to first clock pulse)
Clock Low Time
Clock High Time
Setup Time for Repeated Start Condition
SDA Hold Time from SCL Falling (Note 18)
SDA Setup Time from SCL Rising
Rise Time of Both SDA and SCL Lines
Fall Time of Both SDA and SCL Lines
Setup Time for Stop Condition
Pulse Width of Spike Noise Suppressed by Input Filter
fSCL
tBUF
tHD:STA
tLOW
tHIGH
tSU:STA
tHD:DAT
tSU:DAT
tR
tF
tSU:STO
tSP
-
4.7
4.0
4.7
4.0
4.7
0
0.25
-
-
4.0
0
100
-
-
-
-
-
-
-
1.0
0.3
-
50
kHz
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
ns
Power-down & Reset Timing
PDN Pulse Width (Note 19)
PDN “↑” to SDTO valid (Note 20) tPD
tPDV 150 522 ns
1/fs
Notes: 18. Data must be held for sufficient time to bridge the 300 ns transition time of SCL.
19. The AK4529 can be reset by bringing PDN “ L” to “H” upon power-up.
20. These cycles are the number of LRCK rising from PDN rising.
21. I2C is a registered trademark of Philips Semiconductors.
Purchase of Asahi Kasei Microsystems Co., Ltd I2C components conveys a license under the Philips
I2C patent to use the components in the I2C system, provided the system conform to the I2C
specifications defined by Philips.
ASAHI KASEI [AK4529]
MS0082-E-00 2001/3
- 12 -
n Timing Diagram 1/fCLK
tCLKL
VIH
tCLKH
MCLK VIL
1/fsn, 1/fsd
LRCK VIH
VIL
tBCK
tBCKL
VIH
tBCKH
BICK VIL
Clock Timing (TDM= “0”)
1/fCLK
tCLKL
VIH
tCLKH
MCLK VIL
1/fs
LRCK VIH
VIL
tLRLtLRH
tBCK
tBCKL
VIH
tBCKH
BICK VIL
Clock Timing (TDM= “1”)
ASAHI KASEI [AK4529]
MS0082-E-00 2001/3
- 13 -
tLRB
LRCK
VIH
BICK VIL
tLRS
SDTO 50%TVDD
tBSD
VIH
VIL
tBLR
tSDS
SDTI VIH
VIL
tSDH
Audio Interface Timing (TDM= “0”)
tLRB
LRCK
VIH
BICK VIL
SDTO 50%TVDD
tBSD
VIH
VIL
tBLR
tSDS
SDTI VIH
VIL
tSDH
Audio Interface Timing (TDM= “1”)
ASAHI KASEI [AK4529]
MS0082-E-00 2001/3
- 14 -
tCSS
CSN
VIH
CCLK VIL
VIH
CDTI VIL
VIH
VIL
C1 C0 R/W A4
tCCKL tCCKH
tCDS tCDH
WRITE Command Input Timing (3-wire Serial mode)
CSN
VIH
CCLK VIL
VIH
CDTI VIL
VIH
VIL
D3 D2 D1 D0
tCSW
tCSH
WRITE Data Input Timing (3-wire Serial mode)
tHIGH
SCL
SDA VIH
tLOW
tBUF
tHD:STA
tR tF
tHD:DAT tSU:DAT tSU:STA
Stop Start Start Stop
tSU:STO
VIL
VIH
VIL
tSP
I2C Bus mode Timing
tPD
VIL
PDN
tPDV
SDTO 50%TVDD
VIH
Power-down & Reset Timing
ASAHI KASEI [AK4529]
MS0082-E-00 2001/3
- 15 -
OPERATION OVERVIEW
n System Clock
The external clocks, which are required to operate the AK4529, are MCLK, LRCK and BICK. There are two methods to
set MCLK frequency. In Manual Setting Mode (ACKS = “0”: Default), the sampling speed is set by DFS (Table 1). The
frequency of MCLK at each sampling speed is set automatically. (Table 2, 3). In Auto Setting Mode (ACKS = “1”), as
MCLK frequency is detected automatically (Table 4), and the internal master clock becomes the appropriate frequency
(Table 5), it is not necessary to set DFS.
MCLK should be synchronized with LRCK but the phase is not critical. External clocks (MCLK, BICK) should always be
present whenever the AK4529 is in normal operation mode (PDN = “H”). If these clocks are not provided, the AK4529
may draw excess current because the device utilizes dynamic refreshed logic internally. If the external clocks are not
present, the AK4529 should be in the power-down mode (PDN = “L”) or in the reset mode (RSTN = “0” ). After exiting
reset at power-up etc., the AK4529 is in the power-down mode until MCLK and LRCK are input.
DFS Sampling Speed (fs)
0 Normal Speed Mode 32kHz~ 48kHz
1 Double Speed Mode 64kHz~96kHz Default
Table 1. Sampling Speed (Manual Setting Mode)
LRCK MCLK (MHz) BICK (MHz)
fs 256fs 384fs 512fs 64fs
32.0kHz 8.1920 12.2880 16.3840 2.0480
44.1kHz 11.2896 16.9344 22.5792 2.8224
48.0kHz 12.2880 18.4320 24.5760 3.0720
Table 2. System Clock Example (Normal Speed Mode @Manual Setting Mode)
LRCK MCLK (MHz) BICK (MHz)
fs 128fs 192fs 256fs 64fs
88.2kHz 11.2896 16.9344 22.5792 5.6448
96.0kHz 12.2880 18.4320 24.5760 6.1440
Table 3. System Clock Example (Double Speed Mode @Manual Setting Mode)
(Note: At double speed mode(DFS = “1”), 128fs and 192fs are not available for ADC.)
MCLK Sampling Speed
512fs Normal
256fs Double
Table 4. Sampling Speed (Auto Setting Mode)
ASAHI KASEI [AK4529]
MS0082-E-00 2001/3
- 16 -
LRCK MCLK (MHz)
fs 256fs 512fs Sampling
Speed
32.0kHz - 16.3840
44.1kHz - 22.5792
48.0kHz - 24.5760 Normal
88.2kHz 22.5792 -
96.0kHz 24.5760 - Double
Table 5. System Clock Example (Auto Setting Mode)
n De-emphasis Filter
The AK4529 includes the digital de-emphasis filter (tc=50/15µs) by IIR filter. This filter corresponds to three sampling
frequencies (32kHz, 44.1kHz, 48kHz). De-emphasis of each DAC can be set individually by register data of DEMA1-C0
(DAC1: DEMA1-0, DAC2: DEMB1-0, DAC3: DEMC1-0, see “Register Definitions”).
Mode Sampling Speed DEM1 DEM0 D E M
0 Normal Speed 0 0 44.1kHz
1 Normal Speed 0 1 OFF
2 Normal Speed 1 0 48kHz
3 Normal Speed 1 1 32kHz
4 Double Speed 0 0 OFF
5 Double Speed 0 1 OFF
6 Double Speed 1 0 OFF
7 Double Speed 1 1 OFF
Default
Table 6. De-emphasis control
n Digital High Pass Filter
The ADC has a digital high pass filter for DC offset cancel. The cut-off frequency of the HPF is 0.9Hz at fs=44.1kHz and
also scales with sampling rate (fs).
ASAHI KASEI [AK4529]
MS0082-E-00 2001/3
- 17 -
n Audio Serial Interface Format
When TDM= “L”, four modes can be selected by the DIF1-0 as shown in table 7. In all modes the serial data is MSB-first,
2’s compliment format. The SDTO is clocked out on the falling edge of BICK and the SDTI/DAUX are latched on the
rising edge of BICK.
Figures 1∼4 shows the timing at SDOS = “ L”. In this case, the SDTO outputs the ADC output data. When SDOS = “H”,
the data input to DAUX is converted to SDTO’s format and output from SDTO. Mode 2, 3, 6 and 7 in SDTI input formats
can be used for 16-20bit data by zeroing the unused LSBs.
Mode TDM DIF1 DIF0 SDTO SDTI1-4, DAUX LRCK BICK
0 0 0 0 24bit, Left justified 20bit, Right justified H/L ≥ 48fs
1 0 0 1 24bit, Left justified 24bit, Right justified H/L ≥ 48fs
2 0 1 0 24bit, Left justified 24bit, Left justified H/L ≥ 48fs
3 0 1 1 24bit, I2S 24bit, I2S L/H ≥ 48fs Default
Table 7. Audio data formats (Normal format)
The audio serial interface format becomes the TDM I/F format if TDM pin is set to “H ”. In the TDM mode, the serial data
of all DAC (eight channels) is input to the SDTI1 pin. The input data to SDTI2-4 pins is ignored. BICK should be fixed to
256fs. “H” time and “L” time of LRCK should be 1/256fs at least. Four modes can be selected by the DIF1-0 as shown in
table 8. In all modes the serial data is MSB-first, 2’s compliment format. The SDTO is clocked out on the falling edge of
BICK and the SDTI1 are latched on the rising edge of BICK. SDOS and LOOP1-0 should be set to “0” at the TDM mode.
TDM mode cannot be used in double speed mode.
Mode TDM DIF1 DIF0 SDTO SDTI1 Sync BICK
4 1 0 0 24bit, Left justified 20bit, Right justified ↑256fs
5 1 0 1 24bit, Left justified 24bit, Right justified ↑256fs
6 1 1 0 24bit, Left justified 24bit, Left justified ↑256fs
7 1 1 1 24bit, I2S 24bit, I2S↓256fs
Table 8. Audio data formats (TDM format)
ASAHI KASEI [AK4529]
MS0082-E-00 2001/3
- 18 -
LRCK
BICK
(
64fs
)
SDTO
(
o
)
0 1 2 12 13 14 24 25 31 0 1 2 12 13 14 24 25 31 0
23
1
22 023 22 12 11 10 0 23
SDTI
(
i
)
118 019 8 7 118 019 8 7
Lch Data Rch Data
Don’t Care Don’t Care
12 11 10
SDTO-23:MSB, 0:LSB; SDTI-19:MSB, 0:LSB
Figure 1. Mode 0 Timing
LRCK
BICK
(
64fs
)
SDTO
(
o
)
0 1 2 8 9 10 24 25 31 0 1 2 8 9 10 24 25 31 0
23
1
22 023 22 16 15 14 0 23
SDTI
(
i
)
122 023 8 7 122 023 8 7
23:MSB, 0:LSB Lch Data Rch Data
Don’t Care Don’t Care
16 15 14
Figure 2. Mode 1 Timing
LRCK
BICK
(
64fs
)
SDTO(o)
0 1 2 18192021 310 1 2 0
23
1
22 123 22 23
SDTI
(
i
)
2223 0 2223
23:MSB, 0:LSB Lch Data Rch Data
Don’t Care
2
21
28 29 30
23
0
19 20 21 31
1
0Don’t Care
2
21
28 29 30
0
Figure 3. Mode 2 Timing
LRCK
BICK
(
64fs
)
SDTO
(
o
)
0 1 2 3 23 24 25 26 0 0 1
SDTI
(
i
)
3129 30
23 22 1
2223 0
23:MSB, 0:LSB Lch Data Rch Data
Don’t Care
2
21
0
2 3 23 24 25 26 03129 30
23 22 1
2223 0 Don’t Care
2
21
0
1
Figure 4. Mode 3 Timing
ASAHI KASEI [AK4529]
MS0082-E-00 2001/3
- 19 -
LRCK
BICK(256fs)
SDTO(o)
SDTI1(i)
22 0
Lch
32 BICK
256 BICK
18 0
L1
32 BICK
18 0
R1
32 BICK
18 0
L2
32 BICK
18 0
R2
32 BICK
18 0
L3
32 BICK
18 0
R3
32 BICK
18 0
L4
32 BICK
18 0
R4
32 BICK
22 0
Rch
32 BICK
2223
19 19 19 19 19
23
19 19 19
23
19
Figure 5. Mode 4 Timing
LRCK
BICK(256fs)
SDTO(o)
SDTI1(i)
22 0
Lch
32 BICK
256 BICK
22 0
L1
32 BICK
22 0
R1
32 BICK
22 0
L2
32 BICK
22 0
R2
32 BICK
22 0
L3
32 BICK
22 0
R3
32 BICK
22 0
L4
32 BICK
22 0
R4
32 BICK
22 0
Rch
32 BICK
2223
23 23 23 23 23
23
23 23 23
23
23
Figure 6. Mode 5 Timing
LRCK
BICK(256fs)
SDTO(o)
SDTI1(i)
22 0
Lch
32 BICK
256 BICK
22 0
L1
32 BICK
22 0
R1
32 BICK
22 0
L2
32 BICK
22 0
R2
32 BICK
22 0
L3
32 BICK
22 0
R3
32 BICK
22 0
L4
32 BICK
22 0
R4
32 BICK
22 0
Rch
32 BICK
22
22
23
23 23 23 23 23
23
23 23 23
23
23
Figure 7. Mode 6 Timing
LRCK
BICK(256fs)
SDTO(o)
SDTI1(i)
23 0
Lch
32 BICK
256 BICK
23 0
L1
32 BICK
23 0
R1
32 BICK
23 0
L2
32 BICK
23 0
R2
32 BICK
23 0
L3
32 BICK
23 0
R3
32 BICK
23 0
L4
32 BICK
23 0
R4
32 BICK
23 0
Rch
32 BICK
23
23
Figure 8. Mode 7 Timing
ASAHI KASEI [AK4529]
MS0082-E-00 2001/3
- 20 -
n
Overflow Detection
The AK4529 has overflow detect function for analog input. Overflow detect function is enable if OVFE bit is set to “1” at
serial control mode. OVF pin goes to “H” if analog input of Lch or Rch overflows (more than -0.3dBFS). OVF output for
overflowed analog input has the same group delay as ADC (GD = 27.6/fs = 626µs@fs=44.1kHz). OVF is “L” for 522/fs
(=11.8ms @fs=44.1kHz) after PDN = “↑”, and then overflow detection is enabled.
n Zero Detection
The AK4529 has two pins for zero detect flag outputs. Channel grouping can be selected by DZFM3-0 bits if P/S = “L”
and DZFE = “L” (table 9). DZF1 pin corresponds to the group 1 channels and DZF2 pin corresponds to the group 2
channels. However DZF2 pin becomes OVF pin if OVFE bit is set to “1”. Zero detection mode is set to mode 0 if DZFE=
“H” regardless of P/S pin. DZF1 is AND of all eight channels and DZF2 is disabled (“L”) at mode 0. Table 10 shows the
relation of P/S, DZFE, OVFE and DZF.
When the input data of all channels in the group 1(group 2) are continuously zeros for 8192 LRCK cycles, DZF1(DZF2)
pin goes to “ H”. DZF1(DZF2) pin immediately goes to “L” if input data of any channels in t he group 1(group 2) is not
zero after going DZF1(DZF2) “H”.
DZFM AOUT
Mode 3210 L1 R1 L2 R2 L3 R3 L4 R4
0 0000 DZF1 DZF1 DZF1 DZF1 DZF1 DZF1 DZF1 DZF1
1 0001 DZF1 DZF1 DZF1 DZF1 DZF1 DZF2 DZF2 DZF2
2 0010 DZF1 DZF1 DZF1 DZF1 DZF2 DZF2 DZF2 DZF2
3 0011 DZF1 DZF1 DZF1 DZF2 DZF2 DZF2 DZF2 DZF2
4 0100 DZF1 DZF1 DZF2 DZF2 DZF2 DZF2 DZF2 DZF2
5 0101 DZF1 DZF2 DZF2 DZF2 DZF2 DZF2 DZF2 DZF2
6 0110 DZF2 DZF2 DZF2 DZF2 DZF2 DZF2 DZF2 DZF2
7 0111 disable (DZF1=DZF2 = “L”)
8 1000 DZF1 DZF1 DZF1 DZF1 DZF1 DZF1 DZF1 DZF2
9 1001 DZF1 DZF1 DZF1 DZF1 DZF1 DZF1 DZF2 DZF2
10 1010
11 1011
12 1100
13 1101
14 1110
15 1111
disable (DZF1=DZF2 = “L”)
Default
Table 9. Zero detect control
P/S pin DZFE pin OVFE bit DZF mode DZF1 pin DZF2/OVF pin
“L” disable Mode 7 “L” “L”“H” (parallel mode) “H” disable Mode 0 AND of 6ch “L”
“0” Selectable Selectable Selectable“L” “1” Selectable Selectable OVF output
“0 ” Mode 0 AND of 6ch “L”
“L” (serial mode)
“H” “ 1 ” Mode 0 AND of 6ch OVF output
Table 10. DZF1-2 pins outputs
ASAHI KASEI [AK4529]
MS0082-E-00 2001/3
- 21 -
n
Digital Attenuator
AK4529 has channel-independent digital attenuator (256 levels, 0.5dB step). Attenuation level of each channel can be set
by each ATT7-0 bits (table 11).
ATT7-0 Attenuation Level
00H 0dB
01H -0.5dB
02H -1.0dB
::
FDH -126.5dB
FEH -127.0dB
FFH MUTE (-∞)
Default
Table 11. Attenuation level of digital attenuator
Transition time between set values of ATT7-0 bits can be selected by ATS1-0 bits (table 12).
Mode ATS1 ATS0 ATT speed
0 0 0 7424/fs
1 0 1 1024/fs
2 1 0 256/fs
Default
Table 12. Transition time between set values of ATT7-0 bits
The transition between set values is soft transition of 7425 levels in mode 0. It takes 7424/fs (168ms@fs=44.1kHz) from
00H(0dB) to FFH(MUTE) in mode 0. If PDN pin goes to “L”, the ATTs are initialized to 00H. The ATTs are 00H when
RSTN = “0”. When RSTN return to “1”, the ATTs fade to their current value. Digital attenuator is independent of soft
mute function.
ASAHI KASEI [AK4529]
MS0082-E-00 2001/3
- 22 -
n Soft mute operation
Soft mute operation is performed at digital domain. When the SMUTE pin goes to “H”, the output signal is attenuated by
-∞ during 1024 LRCK cycles. When the SMUTE pin is returned to “L”, the mute is cancelled and the output attenuation
gradually changes to 0dB during 1024 LRCK cycles. If the soft mute is cancelled within 1024 LRCK cycles after starting
the operation, the attenuation is discontinued and returned to 0dB. The soft mute is effective for changing the signal
source without stopping the signal transmission.
SMUTE
Attenuation
DZF1,2
1024/fs
0dB
-∞
AOUT
1024/fs
8192/fs
GD GD
(1)
(2)
(3)
(4)
Notes:
(1) The output signal is attenuated by -∞ during 1024 LRCK cycles (1024/fs).
(2) Analog output corresponding to digital input have the group delay (GD).
(3) If the soft mute is cancelled within 1024 LRCK cycles, the attenuation is discontinued and returned to 0dB.
(4) When the input data of all channels in the group are continuously zeros for 8192 LRCK cycles, DZF pin
corresponding to the group goes to “H ”. DZF pin immediately goes to “L” if input data of any channel in the group
is not zero after going DZF “H”.
Figure 9. Soft mute and zero detection
n System Reset
The AK4529 should be reset once by bringing PDN = “L” upon power-up. The AK4529 is powered up and the internal
timing starts clocking by LRCK “↑” after exiting reset and power down state by MCLK. The AK4529 is in the power-
down mode until MCLK and LRCK are input.
ASAHI KASEI [AK4529]
MS0082-E-00 2001/3
- 23 -
n Power-Down
The ADC and DACs of AK4529 are placed in the power-down mode by bringing PDN “L” and both digital filters are
reset at the same time. PDN “L” also reset the control registers to their default values. In the power-down mode, the
analog outputs go to VCOM voltage and DZF1-2 pins go to “L”. This reset should always be done after power-up. In case
of the ADC, an analog initialization cycle starts after exiting the power-down mode. Therefore, the output data, SDTO
becomes available after 522 cycles of LRCK clock. In case of the DAC, an analog initialization cycle starts after exiting
the power-down mode. The analog outputs are VCOM voltage during the initialization. Figure 10 shows the power-up
sequence.
The ADC and DACs can be powered-down individually by PWADN and PWDAN bits. In this case, the internal register
values are not initialized. When PWADN = “0”, SDTO goes to “L”. When PWDAN = “0”, the analog outputs go to
VCOM voltage and DZF1-2 pins go to “H”. Because some click noise occurs, the analog output should muted externally
if the click noise influences system application.
ADC Internal
State
PDN 522/fs
Normal Operation Power-down Init Cycle Normal Operation
(1)
Don’t care
GD GD
Clock In
MCLK,LRCK,SCLK
ADC In
(Analog)
“0”data
ADC Out
(Digital)
Normal Operation Power-down Normal Operation
DAC Internal
State
“0”data
DAC In
(Digital)
DAC Out
(Analog)
GD
External
Mute Mute ON
GD
(3)
(3)
(4) (5)
(6) (6)
(9)
516/fs
Init Cycle
(2)
DZF1/DZF2
(7)
(8)
10∼11/fs (10)
Notes:
(1) The analog part of ADC is initialized after exiting the power-down state.
(2) The analog part of DAC is initialized after exiting the power-down state.
(3) Digital output corresponding to analog input and analog output corresponding to digital input have the group delay
(GD).
(4) ADC output is “0” data at the power-down state.
(5) Click noise occurs at the end of initialization of the analog part. Please mute the digital output externally if the click
noise influences system application.
(6) Click noise occurs at the falling edge of PDN and at 512/fs after the rising edge of PDN.
(7) When the external clocks (MCLK, BICK and LRCK) are stopped, the AK4529 should be in the power-down mode.
(8) DZF pins are “L” in the power-down mode (PDN = “L”).
(9) Please mute the analog output externally if the click noise (6) influences system application.
(10) DZF= “L” for 10∼11/fs after PDN= “↑”.
Figure 10. Power-down/up sequence example
ASAHI KASEI [AK4529]
MS0082-E-00 2001/3
- 24 -
n Reset Function
When RSTN = “0”, ADC and DACs are powered-down but the internal register are not initialized. The analog outputs go
to VCOM voltage, DZF1-2 pins go to “H” and SDTO pin goes to “L”. Because some click noise occurs, the analog output
should muted externally if t he click noise influences system application. Figure 11 shows the power-up sequence.
ADC Internal
State
RSTN bit
Normal Operation Digital Block Power-down Normal Operation
D o n’t care
GD GD
Clock In
MCLK,LRCK,SCLK
ADC In
(Analog)
“0”data
ADC Out
(Digital)
Normal Operation Normal Operation
DAC Internal
State
“0”data
DAC In
(Digital)
DAC Out
(Analog)
GD GD
(2)
(2)
(3) (4)
(6) (6)
DZF1/DZF2
(7)
Internal
RSTN bit
Digital Block Power-down
1~2/fs (9)4~5/fs (9)
4∼5/fs (8)
(5)
516/fs
Init Cycle
(1)
Notes:
(1) The analog part of ADC is initialized after exiting the reset state.
(2) Digital output corresponding to analog input and analog output corresponding to digital input have the group delay
(GD).
(3) ADC output is “0” data at the power-down state.
(4) Click noise occurs when the internal RSTN bit becomes “ 1” . Please mute the digital output externally if the click
noise influences system application.
(5) The analog outputs go to VCOM voltage.
(6) Click noise occurs at 4∼5/fs after RSTN bit becomes “ 0 ”, and occurs at 1∼2/fs after RSTN bit becomes “ 1”. This
noise is output even if “0” data is input.
(7) The external clocks (MCLK, BICK and LRCK) can be stopped in the reset mode. When exiting the reset mode, “1”
should be written to RSTN bit after the external clocks (MCLK, BICK and LRCK) are fed.
(8) DZF pins go to “H” when the RSTN bit becomes “0”, and go to “L” at 6~7/fs aft e r RSTN bit becomes “1”.
(9) There is a delay, 4 ~5/fs from RSTN bit “0” to the internal RSTN bit “ 0” .
Figure 11. Reset sequence example
ASAHI KASEI [AK4529]
MS0082-E-00 2001/3
- 25 -
n Serial Control Interface
The AK4529 can control its functions via registers. Internal registers may be written by 2 types of control mode. The chip
address is determined by the state of the CAD0 and CAD1 inputs. PDN = “L” initializes the registers to their default
values. Writing “0” to the RSTN bit can initialize the internal timing circuit. But in this case, the register data is not be
initialized. When the state of P/S pin is changed, the AK4529 should be reset by PDN pin.
* Writing to control register is invalid when PDN = “L” or the MCLK is not fed.
* AK4529 does not support the read command.
(1) 3-wire Serial Control Mode (I2C = “L”)
Internal registers may be written to the 3 wire µP interface pins (CSN, CCLK and CDTI). The data on this interface
consists of Chip address (2bits, CAD0/1), Read/Write (1bit, Fixed to “1”, Write only), Register address (MSB first,
5bits) and Control data (MSB first, 8bits). Address and data is clocked in on the rising edge of CCLK and data is
clocked out on the falling edge. For write operations, data is latched after a low-to-high transition of CSN. The clock
speed of CCLK is 5MHz(max). The CSN pin should be held to “H” except for access.
CDTI
CCLK
CSN
C1
012345678 9 10 11 12 13 14 15
D4D5D6D7A1A2A3A4R/WC0 A0
D1D2D3
C1-C0: Chip Address (C1=CAD1, C0=CAD0)
R/W: Read/Write (Fixed to “1”, Write only)
A4-A0: Register Address
D7-D0: Control Data
Figure 12. 3-wire Serial Control I/F Timing
ASAHI KASEI [AK4529]
MS0082-E-00 2001/3
- 26 -
(2) I2C-bus Control Mode (I2C= “H”)
AK4529 supports the standard-mode I2C-bus (max:100kHz). Then AK4529 cannot be incorporated in a fast-mode
I2C-bus system (max:400kHz). The CSN pin should be connected to DVDD at the I2C-bus mode.
Figure 13 shows the data transfer sequence at the I2C-bus mode. All commands are preceded by a START condition.
A HIGH to LOW transition on the SDA line while SCL is HIGH indicates a START condition (figure 17). After the
START condition, a slave address is sent. This address is 7 bits long followed by an eighth bit which is a data
direction bit (R/W) (figure 14). The most significant five bits of the slave address are fixed as “00100”. The next t wo
bits are CAD1 and CAD0 (device address bits). These two bits identify the specific device on the bus. The hard-
wired input pins (CAD1 pin and CAD0 pin) set them. If the slave address match that of the AK4529 and R/W bit is
“0”, the AK4529 generates the acknowledge and the write operation is executed. If R/W bit is “1”, the AK4529
generates the not acknowledge since the AK4529 can be only a slave-receiver. The master must generate the
acknowledge-related clock pulse and release the SDA line (HIGH) during the acknowledge clock pulse (figure 18).
The second byte consists of the address for control registers of the AK4529. The format is MSB first, and those most
significant 3-bits are fixed to zeros (figure 15). Those data after the second byte contain control data. The format is
MSB first, 8bits (figure 16). The AK4529 generates an acknowledge after each byte has been received. A data
transfer is always terminated by a STOP condition generated by the master. A LOW to HIGH transition on the SDA
line while SCL is HIGH defines a STOP condition (figure 17).
The AK4529 is capable of more than one byte write operation by one sequence. After receipt of the third byte, the
AK4529 generates an acknowledge, and awaits the next data again. The master can transmit more than one byte
instead of terminating the write cycle after the first data byte is transferred. After the receipt of each data, the internal
5bits address counter is incremented by one , and the next data is taken into next address automatically. If the address
exceed 1FH prior to generating the stop condition, the address counter will “roll over” to 00H and the previous data
will be overwritten.
The data on the SDA line must be stable during the HIGH period of the clock. The HIGH or LOW state of the data
line can only change when the clock signal on the SCL line is LOW (figure 19) except for the START and the STOP
condition.
SDA
S
T
A
R
T
A
C
K
A
C
K
SSlave
Address A
C
K
Sub
Address(n) Data(n) P
S
T
O
P
Data(n+x)
A
C
K
Data(n+1)
A
C
K
R/W
A
C
K
Figure 13. Data transfer sequence at the I2C-bus mode
00100CAD1 CAD0 R/W
(Those CAD1/0 should match with CAD1/0 pins)
Figure 14. The first byte
0 0 0 A4 A3 A2 A1 A0
Figure 15. The second byte
D7 D6 D5 D4 D3 D2 D1 D0
Figure 16. Byte structure after the second byte
ASAHI KASEI [AK4529]
MS0082-E-00 2001/3
- 27 -
SCL
SDA
stop conditionstart condition
SP
Figure 17. START and STOP conditions
SCL FROM
MASTER
acknowledge
DATA
OUTPUT BY
MASTER
DATA
OUTPUT BY
SLAVE(AK4529)
1 98
START
CONDITION
not acknowledge
clock pulse for
acknowledgement
S
2
Figure 18. Acknowledge on the I2C-bus
SCL
SDA
data line
stable;
data valid
change
of data
allowed
Figure 19. Bit transfer on the I2C-bus
ASAHI KASEI [AK4529]
MS0082-E-00 2001/3
- 28 -
n Mapping of Program Registers
Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0
00H Control 1 0 0 0 TDM DIF1 DIF0 0 SMUTE
01H Control 2 0 0 LOOP1 LOOP0 SDOS DFS ACKS 0
02H LOUT1 Volume Control ATT7 ATT6 ATT5 ATT4 ATT3 ATT2 ATT1 ATT0
03H ROUT1 Volume Control ATT7 ATT6 ATT5 ATT4 ATT3 ATT2 ATT1 ATT0
04H LOUT2 Volume Control ATT7 ATT6 ATT5 ATT4 ATT3 ATT2 ATT1 ATT0
05H ROUT2 Volume Control ATT7 ATT6 ATT5 ATT4 ATT3 ATT2 ATT1 ATT0
06H LOUT3 Volume Control ATT7 ATT6 ATT5 ATT4 ATT3 ATT2 ATT1 ATT0
07H ROUT3 Volume Control ATT7 ATT6 ATT5 ATT4 ATT3 ATT2 ATT1 ATT0
08H De-emphasis DEMD1 DEMD0 DEMA1 DEMA0 DEMB1 DEMB0 DEMC1 DEMC0
09H ATT speed 0 0 ATS1 ATS0 0 0 0 RSTN
0AH Zero detect OVFE DZFM3 DZFM2 DZFM1 DZFM0 PWVRN PWADN PWDAN
0BH LOUT4 Volume Control ATT7 ATT6 ATT5 ATT4 ATT3 ATT2 ATT1 ATT0
0CH ROUT4 Volume Control ATT7 ATT6 ATT5 ATT4 ATT3 ATT2 ATT1 ATT0
Note: For addresses from 0DH to 1FH, data is not written.
When PDN goes to “L”, the registers are initialized to their default values.
When RSTN bit goes to “0”, the internal timing is reset and DZF1-2 pins go to “H”, but registers are not initialized
to their default values.
SMUTE, DFS, SDOS and TDM are ORed with pins.
ASAHI KASEI [AK4529]
MS0082-E-00 2001/3
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n
Register Definitions
Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0
00H Control 1 0 0 0 TDM DIF1 DIF0 0 SMUTE
Default 0 0 0 0 1 0 0 0
SMUTE: Soft Mute Enable
0: Normal operation
1: All DAC outputs soft-muted
Register bit of SMUTE is ORed with the SMUTE pin if P/S = “L”.
DIF1-0: Audio Data Interface Modes (see table 7, 8.)
Initial: “10”, mode 2
TDM: TDM Format Select
0: Normal format
1: TDM format
Register bit of TDM is ORed with the TDM pin if P/S = “L”.
TDM pin should be “H” if TDM mode is used.
ASAHI KASEI [AK4529]
MS0082-E-00 2001/3
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Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0
01H Control 2 0 0 LOOP1 LOOP0 SDOS DFS ACKS 0
Default 0 0 0 0 0 0 0 0
ACKS: Master Clock Frequency Auto Setting Mode Enable
0: Disable, Manual Setting Mode
1: Enable, Auto Setting Mode
Master clock frequency is detected automatically at ACKS bit “1 ” . In this case, the setting of DFS are
ignored. When this bit is “ 0”, DFS sets the sampling speed mode.
DFS: Sampling speed mode (see table 1.)
0: Normal speed
1: Double speed
Register bit of DFS is ORed with DFS pin if P/S = “L”.
The setting of DFS is ignored at ACKS bit “1”.
SDOS: SDTO source select
0: ADC
1: DAUX
Register bit of SDOS is ORed with SDOS pin if P/S = “L”.
SDOS should be set to “0” at TDM bit “1”.
LOOP1-0: Loopback mode enable
00: Normal (No loop back)
01: LIN → LOUT1, LOUT2, LOUT3, LOUT4
RIN → ROUT1, ROUT2, ROUT3, ROUT4
The digital ADC output (DAUX input if SDOS = “1”) is connected to the digital DAC input. In this
mode, the input DAC data to SDTI1-3 is ignored. The audio format of SDTO at loopback mode
becomes mode 2 at mode 0, and mode 3 at mode 1, respectively.
10: SDTI1(L) → SDTI2(L), SDTI3(L), SDTI4(L)
SDTI1(R) → SDTI2(R), SDTI3(R), SDTI4(R)
In this mode the input DAC data to SDTI2-4 is ignored.
11: N/A
LOOP1-0 should be set to “00” a t TDM bit “1”.
ASAHI KASEI [AK4529]
MS0082-E-00 2001/3
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Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0
02H LOUT1 Volume Control ATT7 ATT6 ATT5 ATT4 ATT3 ATT2 ATT1 ATT0
03H ROUT1 Volume Control ATT7 ATT6 ATT5 ATT4 ATT3 ATT2 ATT1 ATT0
04H LOUT2 Volume Control ATT7 ATT6 ATT5 ATT4 ATT3 ATT2 ATT1 ATT0
05H ROUT2 Volume Control ATT7 ATT6 ATT5 ATT4 ATT3 ATT2 ATT1 ATT0
06H LOUT3 Volume Control ATT7 ATT6 ATT5 ATT4 ATT3 ATT2 ATT1 ATT0
07H ROUT3 Volume Control ATT7 ATT6 ATT5 ATT4 ATT3 ATT2 ATT1 ATT0
0BH LOUT4 Volume Control ATT7 ATT6 ATT5 ATT4 ATT3 ATT2 ATT1 ATT0
0CH ROUT4 Volume Control ATT7 ATT6 ATT5 ATT4 ATT3 ATT2 ATT1 ATT0
Default 0 0 0 0 0 0 0 0
ATT7-0: Attenuation Level (see table 10.)
Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0
08H De-emphasis DEMD1 DEMD0 DEMA1 DEMA0 DEMB1 DEMB0 DEMC1 DEMC0
Default 0 1 0 1 0 1 0 1
DEMA1-0: De-emphasis response control for DAC1 data on SDTI1 (see table 6.)
Initial: “01”, OFF
DEMB1-0: De-emphasis response control for DAC2 data on SDTI2 (see table 6.)
Initial: “01”, OFF
DEMC1-0: De-emphasis response control for DAC3 data on SDTI3 (see table 6.)
Initial: “01”, OFF
DEMD1-0: De-emphasis response control for DAC4 data on SDTI4 (see table 6.)
Initial: “01”, OFF
ASAHI KASEI [AK4529]
MS0082-E-00 2001/3
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Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0
09H ATT speed 0 0 ATS1 ATS0 0 0 0 RSTN
Default 0 0 0 0 0 0 0 1
RSTN: Internal timing reset
0: Reset. DZF1-2 pins go to “H”, but registers are not initialized.
1: Normal operation
ATS1-0: Digital attenuator transition time setting (see table 11.)
Initial: “00”, mode 0
Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0
0AH Zero detect OVFE DZFM3 DZFM2 DZFM1 DZFM0 PWVRN PWADN PWDAN
Default 0 1111 1 1 1
PWDAN: Power-down control of DAC1-4
0: Power-down
1: Normal operation
PWADN: Power-down control of ADC
0: Power-down
1: Normal operation
PWVRN: Power-down control of reference voltage
0: Power-down
1: Normal operation
DZFM3-0: Zero detect mode select (see table 9.)
Initial: “0111”, disable
OVFE: Overflow detection enable
0: Disable, pin#33 becomes DZF2 pin.
1: Enable, pin#33 becomes OVF pin.
ASAHI KASEI [AK4529]
MS0082-E-00 2001/3
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SYSTEM DESIGN
Figure 20 shows the system connection diagram. An evaluation board is available which demonstrates application
circuits, the optimum layout, power supply arrangements and measurement results.
Condition: TVDD=5V, 3-wire serial control mode, CAD1-0 = “00”
TDM 44
43
42
41
40
39
38
37
36
35
34
SDOS1
2
3
4
5
6
7
8
9
11
10
I2C
BICK
LRCK
SDTI1
SDTI2
SDTI3
SDTO
DAUX
DFS
RIN
CDTI
CCL
K
MCL
K
DZF1
AVSS
VREFH
AVD
D
VCO
M
SDTI4
DZF2 33
32
31
30
29
28
27
26
25
24
23
12
13
14
15
16
17
18
19
20
21
22
DVDD
DZFE
TVDD
DVSS
TST
CAD1
CAD0
LOUT4
ROUT4
LIN
NC
NC
ROUT1
LOUT1
ROUT2
LOUT2
ROUT3
LOUT3
AK4529
+
0.1u
0.1u
2.2u
+
5
uP
Analog GroundDigital Ground
(DIR)
DSP
Analog 5V
+10u
Audio
(MPEG/
AC3)
Digital
Audio
Source
PDN
CSN
P/
S
SMUTE
0.1u
10u
MUTE
MUTE
MUTE
MUTE
MUTE
MUTE
Power-down
control
MUTE
MUTE
Figure 20. Typical Connection Diagram
ASAHI KASEI [AK4529]
MS0082-E-00 2001/3
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Analog GroundDigital Ground
System
Controller
TDM
SDOS1
2
3
4
5
6
7
8
9
11
10
I2C
BICK
LRCK
SDTI1
SDTI2
SDTI3
SDTO
DAUX
DFS
RIN
LOOP0/SDA/CDTI
DIF1/SCL/CCL
K
MCLK
DZF1
AVSS
VREFH
AVDD
VCOM
SDTI4
DZF2/OVF
12
13
14
15
16
17
18
19
20
21
22
DVDD
DZFE
TVDD
DVSS
TST
CAD1
CAD0
LOUT4
ROUT4
LIN
NC
NC
ROUT1
LOUT1
ROUT2
LOUT2
ROUT3
LOUT3
AK4529
PDN
DIF0/CSN
P/S
SMUTE
33
32
31
30
29
28
27
26
25
23
24
44
43
42
41
40
39
38
37
36
35
34
Figure 21. Ground Layout
Note: AVSS and DVSS must be connected to the same analog ground plane.
1. Grounding and Power Supply Decoupling
The AK4529 requires careful attention to power supply and grounding arrangements. AVDD and DVDD are usually
supplied from analog supply in system. Alternatively if AVDD and DVDD are supplied separately, the power up
sequence is not critical. AVSS and DVSS of the AK4529 must be connected to analog ground plane. System analog
ground and digital ground should be connected together near to where the supplies are brought onto the printed circuit
board. Decoupling capacitors should be as near to the AK4529 as possible, with the small value ceramic capacitor being
the nearest.
2. Voltage Reference Inputs
The voltage of VREFH sets the analog input/output range. VREFH pin is normally connected to AVDD with a 0.1µF
ceramic capacitor. VCOM is a signal ground of this chip. An electrolytic capacitor 2.2µF parallel with a 0.1µF ceramic
capacitor attached to VCOM pin eliminates the effects of high frequency noise. No load current may be drawn from
VCOM pin. All signals, especially clocks, should be kept away from the VREFH and VCOM pins in order to avoid
unwanted coupling into the AK4529.
3. Analog Inputs
ADC inputs are single-ended and internally biased to VCOM. The input signal range scales with the supply voltage and
nominally 0.62 x VREFH Vpp (typ)@fs=44.1kHz. The ADC output data format 2’s compliment. The DC offset is
removed by the internal HPF.
The AK4529 samples the analog inputs at 64fs. The digital filter rejects noise above the stop band except for multiples of
64fs. The AK4529 includes an anti-aliasing filter (RC filter) to attenuate a noise around 64fs.
ASAHI KASEI [AK4529]
MS0082-E-00 2001/3
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4. Analog Outputs
The analog outputs are also single-ended and centered around the VCOM voltage. The input signal range scales with the
supply voltage and nominally 0.6 x VREFH Vpp. The DAC input data format is 2’s complement. The output voltage is a
positive full scale for 7FFFFFH(@24bit) and a negative full scale for 800000H(@24bit). The ideal output is VCOM
voltage for 000000H(@24bit). The internal analog filters remove most of the noise generated by the delta-sigma
modulator of DAC beyond the audio passband.
DC offsets on analog outputs are eliminated by AC coupling since DAC outputs have DC offsets of a few mV.
n Peripheral I/F Example
The AK4529 can accept the signal of device with a nominal 3.3V supply because of TTL input. The power supply for
output buffer (TVDD) of the AK4529 should be 3.3V when the peripheral devices operate at a nominal 3.3V supply.
Figure 22 shows an example with the mixed system of 3.3V and 5V.
3.3V Analog
5V Analog
3.3V Digital
5V Digital
PLL I/F
Audio signal
DSP
AK4112A
Analog Digital
Control signal
uP &
Others
AK4529
5V for input
3.3V for output
Figure 22. Power supply connection example
ASAHI KASEI [AK4529]
MS0082-E-00 2001/3
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n Applications
1) Zoran AC3 decoder, ZR38650
Analog Input
AK4529
MCLK
BICK
LRCK SCKA
SCKIN
WSA
SDTI4
SPFRX Digital Input
ZR38650
SDA
SCKB
WSB
SDB
SDC
SDD
SDG
SDTI3
SDTI2
SDTI1
SDTO
Analog Output
Figure 23. Application circuit example (ZR38650)
2) Yamaha AC3 decoder, YSS912
Analog Input
AK4529
MCLK
BICK
LRCK BICK
MCKO
LRCK
SDTO
SDTI4
RX
AK4112A
Digital Input
256fs
SDBCK0
SDWCK0
SDIA0
YSS912
SDIA1
SDOB0
SDOB1
SDOB2
SDOB3
SDTI3
SDTI2
SDTI1
SDTO
Analog Output
Figure 24. Application circuit example (YSS912)
3) Motorola AC3 decoder, DSP56362
Analog Input
AK4529
MCLK
BICK
LRCK BICK
MCKO
LRCK
SDTO
SDTI4
RX
AK4112A
Digital Input
256fs
SCKR
ACI
FSR
SDI0
DSP56362
SDI1
SCKT
FST
SDO0
SDO1
SDO2
SDO3
SDTI3
SDTI2
SDTI1
SDTO
Analog Output
Figure 25. Application circuit example (DSP56362)
ASAHI KASEI [AK4529]
MS0082-E-00 2001/3
- 37 -
PACKAGE
0.15
0.17±0.05
0.37±0.10
10.00
1.70max
111
23
33
44pin LQFP
(
Unit: mm
)
10.00
12.80±0.30
34
44
0.80
22
12
12.80±0.30
0∼0.2
0°∼10°
0.60±0.20
n
Package & Lead frame material
Package molding compound: Epoxy
Lead frame material: Cu
Lead frame surface treatment: Solder plate
ASAHI KASEI [AK4529]
MS0082-E-00 2001/3
- 38 -
MARKING
AK4529VQ
XXXXXXX
1
1) Pin #1 indication
2) Date Code: XXXXXXX(7 digits)
3) Marking Code: AK4529VQ
4) Asahi Kasei Logo
IMPORTANT NOTICE
• These products and their specifications are subject to change without notice. Before considering any
use or application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM) sales office or authorized
distributor concerning their current status.
• AKM assumes no liability for infringement of any patent, intellectual property, or other right in the
application or use of any information contained herein.
• Any export of these products, or devices or systems containing them, may require an export license
or other official approval under the law and regulations of the country of export pertaining to customs
and tariffs, currency exchange, or strategic materials.
• AKM products are neither intended nor authorized for use as critical components in any safety, life
support, or other hazard related device or system, and AKM assumes no responsibility relating to
any such use, except with the express written consent of the Representative Director of AKM. As
used here:
(a) A hazard related device or system is one designed or intended for life support or maintenance of
safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its
failure to function or perform may reasonably be expected to result in loss of life or in significant
injury or damage to person or property.
(b) A critical component is one whose failure to function or perform may reasonably be expected to
result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or
system containing it, and which must therefore meet very high standards of performance and
reliability.
• It is the responsibility of the buyer or distributor of an AKM product who distributes, disposes of, or
otherwise places the product with a third party to notify that party in advance of the above content
and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability
for and hold AKM harmless from any and all claims arising from the use of said product in the
absence of such notification.