S-8224A/B Series www.ablic.com www.ablicinc.com BATTERY PROTECTION IC FOR 2-SERIAL TO 4-SERIAL CELL PACK (SECONDARY PROTECTION) Rev.1.3_00 (c) ABLIC Inc., 2017-2018 The S-8224A/B Series is used for secondary protection of lithium-ion rechargeable batteries, and incorporates high-accuracy voltage detection circuits and delay circuits. Short-circuits between cells accommodate series connection of two cells to four cells. The S-8224B Series limits its CO pin output voltage to 11.5 V max., so a FET with the gate withstand voltage of 12 V can be used. Features * High-accuracy voltage detection circuit for each cell Overcharge detection voltage n (n = 1 to 4) 3.600 V to 4.700 V (50 mV step) * * * * * * * * * * * Accuracy 20 mV (Ta = +25C) Accuracy 25 mV (Ta = -10C to +60C) Overcharge hysteresis voltage n (n = 1 to 4)*1 0.0 mV to -550 mV (50 mV step) -300 mV to -550 mV Accuracy 20% -100 mV to -250 mV Accuracy 50 mV -50 mV Accuracy 25 mV 0.0 mV Accuracy -25 mV to +20 mV Delay times for overcharge detection are generated only by an internal circuit (external capacitors are unnecessary) Overcharge detection delay time is selectable: 1 s, 2 s, 4 s, 6 s, 8 s Overcharge release delay time is selectable: 2 ms, 64 ms Built-in timer reset delay circuit Output control function via CTL pin Output form is selectable (S-8224A Series): CMOS output, Nch open-drain output Output logic is selectable (S-8224A Series): Active "H", active "L" CO pin output voltage is limited to 11.5 V max. (S-8224B Series)*2 High-withstand voltage: Absolute maximum rating 28 V Wide operation voltage range: 3.6 V to 28 V Wide operation temperature range: Ta = -40C to +85C Low current consumption During operation (VCU - 1.0 V for each cell): 0.25 A typ., 0.6 A max. (Ta = +25C) During overdischarge (VCU x 0.5 V for each cell): 0.3 A max. (Ta = +25C) Lead-free (Sn 100%), halogen-free *1. Select the overcharge hysteresis voltage calculated as the following formula. (Overcharge detection voltage n) + (Overcharge hysteresis voltage n) 3.4 V *2. Only output logic active "H" is available. Application * Lithium-ion rechargeable battery packs (for secondary protection) Package * SNT-8A 1 BATTERY PROTECTION IC FOR 2-SERIAL TO 4-SERIAL CELL PACK (SECONDARY PROTECTION) Rev.1.3_00 S-8224A/B Series Block Diagrams 1. S-8224A Series 1. 1 CMOS output product VDD VC1 Overcharge detection comparator 1 + - VC2 Overcharge detection comparator 2 + - VC3 Overcharge detection comparator 3 Control logic Delay circuit Oscillator + - VC4 Overcharge detection comparator 4 + - VSS CTL CO pin output control circuit Figure 1 2 CO BATTERY PROTECTION IC FOR 2-SERIAL TO 4-SERIAL CELL PACK (SECONDARY PROTECTION) Rev.1.3_00 S-8224A/B Series 1. 2 Nch open-drain output product VDD VC1 Overcharge detection comparator 1 + - VC2 Overcharge detection comparator 2 + - Control logic VC3 Overcharge detection comparator 3 CO Delay circuit Oscillator + - VC4 Overcharge detection comparator 4 + - VSS CTL CO pin output control circuit Figure 2 3 BATTERY PROTECTION IC FOR 2-SERIAL TO 4-SERIAL CELL PACK (SECONDARY PROTECTION) Rev.1.3_00 S-8224A/B Series 2. S-8224B Series VDD VC1 Overcharge detection comparator 1 + - VC2 Overcharge detection comparator 2 + CO pin output voltage limit circuit - Control logic VC3 Overcharge detection comparator 3 Delay circuit Oscillator + - VC4 Overcharge detection comparator 4 + - VSS CTL CO pin output control circuit Figure 3 4 CO BATTERY PROTECTION IC FOR 2-SERIAL TO 4-SERIAL CELL PACK (SECONDARY PROTECTION) Rev.1.3_00 S-8224A/B Series Product Name Structure 1. Product name S-8224 x xx - xxxx U Environmental code U: Lead-free (Sn 100%), halogen-free Package abbreviation and IC packing specifications*1 I8T1: SNT-8A, Tape Serial code*2 Sequentially set from AA to AZ Product type A: CMOS output, Nch open-drain output B: CO pin output voltage 11.5 V max. *1. Refer to the tape drawing. *2. Refer to "3. Product name list". 2. Package Table 1 Package Drawing Codes Package Name SNT-8A Dimension PH008-A-P-SD Tape PH008-A-C-SD Reel PH008-A-R-SD Land PH008-A-L-SD 5 BATTERY PROTECTION IC FOR 2-SERIAL TO 4-SERIAL CELL PACK (SECONDARY PROTECTION) Rev.1.3_00 S-8224A/B Series 3. Product name list 3. 1 S-8224A Series Table 2 Overcharge Overcharge Overcharge Overcharge Hysteresis Detection Release Detection Product Name *1 *2 Voltage Delay Time Delay Time Voltage [VHC] [VCU] [tCL] [tCU] S-8224AAS-I8T1U 4.450 V -400 mV 4s 64 ms S-8224AAT-I8T1U 4.350 V -400 mV 4s 64 ms S-8224AAU-I8T1U 4.500 V -400 mV 4s 64 ms S-8224AAV-I8T1U 4.550 V -400 mV 6s 64 ms S-8224AAW-I8T1U 4.450 V -400 mV 6s 64 ms S-8224AAX-I8T1U 4.350 V -400 mV 6s 64 ms S-8224ABA-I8T1U 4.400 V -400 mV 6s 64 ms S-8224ABB-I8T1U 4.500 V -400 mV 6s 64 ms S-8224ABC-I8T1U 4.600 V -400 mV 4s 64 ms S-8224ABD-I8T1U 4.300 V -400 mV 2s 64 ms *1. Overcharge detection delay time 1 s / 2 s / 4 s / 6 s / 8 s is selectable. *2. Overcharge release delay time 2 ms / 64 ms is selectable. *3. Output form CMOS output / Nch open-drain output is selectable. *4. Output logic active "H" / active "L" is selectable. *3 Output Form CMOS output CMOS output CMOS output CMOS output CMOS output CMOS output CMOS output CMOS output CMOS output CMOS output Output Logic Active "H" Active "H" Active "H" Active "H" Active "H" Active "H" Active "H" Active "H" Active "H" Active "H" Remark Please contact our sales office for the products with detection voltage value other than those specified above. 3. 2 S-8224B Series Table 3 Product Name S-8224BAA-I8T1U S-8224BAB-I8T1U S-8224BAC-I8T1U Overcharge Detection Voltage [VCU] 4.350 V 4.450 V 4.350 V Overcharge Hysteresis Voltage [VHC] -400 mV -400 mV -400 mV Overcharge Detection *1 Delay Time [tCU] 4s 6s 4s Overcharge Release *2 Delay Time [tCL] 2 ms 64 ms 64 ms Output Logic Active "H" Active "H" Active "H" *1. Overcharge detection delay time 1 s / 2 s / 4 s / 6 s / 8 s is selectable. *2. Overcharge release delay time 2 ms / 64 ms is selectable. *3. Only output logic active "H" is available. Remark Please contact our sales office for the products with detection voltage value other than those specified above. 6 *3 *4 BATTERY PROTECTION IC FOR 2-SERIAL TO 4-SERIAL CELL PACK (SECONDARY PROTECTION) Rev.1.3_00 S-8224A/B Series Pin Configuration 1. SNT-8A Top view 1 2 3 4 Table 4 8 7 6 5 Figure 4 Pin No. 1 2 Symbol VDD VC1 3 VC2 4 VC3 5 VC4 6 VSS 7 8 CTL CO Description Positive power supply input pin Positive voltage connection pin of battery 1 Negative voltage connection pin of battery 1 Positive voltage connection pin of battery 2 Negative voltage connection pin of battery 2 Positive voltage connection pin of battery 3 Negative voltage connection pin of battery 3 Positive voltage connection pin of battery 4 Negative power supply input pin Negative voltage connection pin of battery 4 CO pin output control pin FET gate connection pin for charge control 7 BATTERY PROTECTION IC FOR 2-SERIAL TO 4-SERIAL CELL PACK (SECONDARY PROTECTION) Rev.1.3_00 S-8224A/B Series Absolute Maximum Ratings Table 5 (Ta = +25C unless otherwise specified) Item Input voltage between VDD pin and VSS pin Symbol Applied Pin VDS VDD VC1 VIN VC2, VC3, VC4 CTL Input pin voltage CO pin output voltage S-8224A Series CMOS output Nch open-drain output S-8224B Series Operation ambient temperature Storage temperature Caution VCO CO Topr Tstg - - Absolute Maximum Rating VSS - 0.3 to VSS + 28 VSS - 0.3 to VSS + 28 VDD - 28 to VDD + 0.3 VSS - 0.3 to VDD + 0.3 VSS - 0.3 to VDD + 0.3 VSS - 0.3 to VSS + 28 VSS - 0.3 to VDD + 0.3 -40 to +85 -40 to +125 Unit V V V V V V V C C The absolute maximum ratings are rated values exceeding which the product could suffer physical damage. These values must therefore not be exceeded under any conditions. Thermal Resistance Value Table 6 Item Condition Board A Board B Junction-to-ambient thermal resistance*1 JA SNT-8A Board C Board D Board E *1. Test environment: compliance with JEDEC STANDARD JESD51-2A Remark 8 Symbol Refer to " Power Dissipation" and "Test Board" for details. Min. - - - - - Typ. 211 173 - - - Max. - - - - - Unit C/W C/W C/W C/W C/W BATTERY PROTECTION IC FOR 2-SERIAL TO 4-SERIAL CELL PACK (SECONDARY PROTECTION) Rev.1.3_00 S-8224A/B Series Electrical Characteristics Table 7 Item Symbol Condition (Ta = +25C unless otherwise specified) Test Min. Typ. Max. Unit Circuit Detection voltage Overcharge detection voltage n (n = 1, 2, 3, 4) Ta = +25C VCUn Ta = -10C to +60C*1 -550 mV VHC -300 mV -250 mV VHC -100 mV Overcharge hysteresis voltage n (n = 1, 2, 3, 4) VHCn VHC = -50 mV VHC = 0.0 mV Input voltage Operation voltage between VDD pin and VSS pin CTL pin input voltage "H" CTL pin input voltage "L" Output voltage CO pin output voltage "H" Input Current Current consumption during operation Current consumption during overdischarge VC1 pin input current VCn pin input current (n = 2, 3, 4) CTL pin input current "H" CTL pin input current "L" Output Current - - VCTLH VCTLL VCOH IOPE IOPED IVC1 IVCn ICTLH ICTLL CO pin source current ICOH CO pin sink current ICOL CO pin leakage current ICOLL Delay Time Overcharge detection delay time tCU Overcharge release delay time - VDSOP tCL S-8224B Series V1 = V2 = V3 = V4 = VCU - 1.0 V V1 = V2 = V3 = V4 = VCU x 0.5 V V1 = V2 = V3 = V4 = VCU - 1.0 V V1 = V2 = V3 = V4 = VCU - 1.0 V - - S-8224A Series (CMOS output product), S-8224B Series - S-8224A Series (Nch open-drain output product) - tCL = 2 ms tCL = 64 ms VCU - 0.020 VCU - 0.025 VHC x 1.2 VHC - 0.050 VHC - 0.025 VHC - 0.025 VCU VCU VHC VHC VHC VHC VCU + 0.020 VCU + 0.025 VHC x 0.8 VHC + 0.050 VHC + 0.025 VHC + 0.020 V 1 V 1 V 1 V 1 V 1 V 1 3.6 - 28 V - VDD x 0.95 - - - - VDD x 0.4 V V 2 2 5.0 8.0 11.5 V 2 - 0.25 0.6 A 3 - - 0.3 A 3 - - 0.3 A 4 -0.3 0 0.3 A 4 0.6 -0.15 1.3 - 2.0 - A A 4 4 - - -20 A 5 20 - - A 5 - - 0.1 A 5 tCU x 0.8 1.6 51.2 6 - - tCU 2.0 64 12 - - tCU x 1.2 3.0 76.8 20 2.5 10 s ms ms ms ms ms 1 1 1 1 2 1 Overcharge timer reset delay time tTR - CTL pin response delay time tCTL - Transition time to test mode tTST - *1. Since products are not screened at high and low temperature, the specification for this temperature range is guaranteed by design, not tested in production. 9 BATTERY PROTECTION IC FOR 2-SERIAL TO 4-SERIAL CELL PACK (SECONDARY PROTECTION) Rev.1.3_00 S-8224A/B Series Test Circuits 1. Overcharge detection voltage, overcharge hysteresis voltage (Test circuit 1) Set SW1 to OFF in CMOS output product of the S-8224A Series and in the S-8224B Series, and set SW1 to ON in Nch open-drain output product of the S-8224A Series. 1. 1 Overcharge detection voltage n (VCUn) Set V0 = 0 V, V1 = V2 = V3 = V4 = VCU - 0.05 V in test circuit 1. The overcharge detection voltage 1 (VCU1) is the V1 voltage when the CO pin output inverts after the voltage of V1 has been gradually increased. Overcharge detection voltage (VCUn) (n = 2 to 4) can be determined in the same way as when n = 1. 1. 2 Overcharge hysteresis voltage n (VHCn) Set V0 = 0 V, V1 = VCU + 0.05 V, V2 = V3 = V4 = 2.5 V. The overcharge hysteresis voltage 1 (VHC1) is the difference between V1 voltage and VCU1 when the CO pin output inverts again after the V1 voltage has been gradually decreased. Overcharge hysteresis voltage (VHCn) (n = 2 to 4) can be determined in the same way as when n = 1. 2. CTL pin input voltage (Test circuit 2) Set SW1 to OFF in CMOS output product of the S-8224A Series and in the S-8224B Series, and set SW1 to ON in Nch open-drain output product of the S-8224A Series. 2. 1 CTL pin input voltage "H" (VCTLH) Set V1 = V2 = V3 = V4 = 3.5 V, V5 = 0 V. The CTL pin input voltage "H" (VCTLH) is the V5 voltage when the CO pin output inverts after the voltage of V5 has been gradually increased. 2. 2 CTL pin input voltage "L" (VCTLL) Set V5 =14 V. The CTL pin input voltage "L" (VCTLL) is the V5 voltage when the CO pin output inverts after the voltage of V5 has been gradually decreased. 3. Output voltage (S-8224B Series) (Test circuit 2) 3. 1 CO pin output voltage "H" The CO pin output voltage "H" (VCOH) is the voltage between the CO pin and the VSS pin when V1 = V2 = V3 = V4 = 3.5 V, V5 = 0 V. 4. Input current (Test circuit 4) 4. 1 CTL pin input current "H" (ICTLH) Set SW2 and SW3 to ON and OFF, respectively. The CTL pin input current "H" (ICTLH) is the current that flows through the CTL pin when V1 = V2 = V3 = V4 = 3.5 V. 4. 2 CTL pin input current "L" (ICTLL) Set SW2 and SW3 to OFF and ON, respectively. The CTL pin input current "L" (ICTLL) is the current that flows through the CTL pin when V1 = V2 = V3 = V4 = 3.5 V. 10 BATTERY PROTECTION IC FOR 2-SERIAL TO 4-SERIAL CELL PACK (SECONDARY PROTECTION) Rev.1.3_00 S-8224A/B Series 5. Output current (Test circuit 5) 5. 1 CMOS output product in S-8224A Series Set SW4 and SW5 to OFF. 5. 1. 1 Active "H" (1) CO pin source current (ICOH) Set SW4 to ON after setting V1 to V4 = 3.5 V, V5 = 0 V, V6 = 0.5 V. I1 is the CO pin source current (ICOH) at that time. (2) CO pin sink current (ICOL) Set SW5 to ON after setting V1 to V4 = 3.5 V, V5 = 14 V, V7 = 0.5 V. I2 is the CO pin sink current (ICOL) at that time. 5. 1. 2 Active "L" (1) CO pin source current (ICOH) Set SW4 to ON after setting V1 to V4 = 3.5 V, V5 = 14 V, V6 = 0.5 V. I1 is the CO pin source current (ICOH) at that time. (2) CO pin sink current (ICOL) Set SW5 to ON after setting V1 to V4 = 3.5 V, V5 = 0 V, V7 = 0.5 V. I2 is the CO pin sink current (ICOL) at that time. 5. 2 Nch open-drain output product in S-8224A Series Set SW4 and SW5 to OFF. 5. 2. 1 Active "H" (1) CO pin leakage current (ICOLL) Set SW5 to ON after setting V1 to V4 = 7 V, V5 = 0 V, V7 = 28 V. I2 is the CO pin leakage current (ICOLL) at that time. (2) CO pin sink current (ICOL) Set SW5 to ON after setting V1 to V4 = 3.5 V, V5 = 14 V, V7 = 0.5 V. I2 is the CO pin sink current (ICOL) at that time. 5. 2. 2 Active "L" (1) CO pin leakage current (ICOLL) Set SW5 to ON after setting V1 to V4 = 3.5 V, V5 = 14 V, V7 = 28 V. I2 is the CO pin leakage current (ICOLL) at that time. (2) CO pin sink current (ICOL) Set SW5 to ON after setting V1 to V4 = 3.5 V, V5 = 0 V, V7 = 0.5 V. I2 is the CO pin sink current (ICOL) at that time. 5. 3 S-8224B Series Set SW4 and SW5 to OFF. 5. 3. 1 CO pin source current (ICOH) Set SW5 to ON after setting V1 to V4 = 3.5 V, V5 = 0 V, V7 = VCOH - 0.5 V. I2 is the CO pin source current (ICOH) at that time. 5. 3. 2 CO pin sink current (ICOL) Set SW5 to ON after setting V1 to V4 = 3.5 V, V5 = 14 V, V7 = 0.5 V. I2 is the CO pin sink current (ICOL) at that time. 11 BATTERY PROTECTION IC FOR 2-SERIAL TO 4-SERIAL CELL PACK (SECONDARY PROTECTION) Rev.1.3_00 S-8224A/B Series 6. Overcharge detection delay time (tCU), overcharge release delay time (tCL) (Test circuit 1) Set SW1 to OFF in CMOS output product of the S-8224A Series and in the S-8224B Series, and set SW1 to ON in Nch open-drain output product of the S-8224A Series. Increase V1 up to 5.2 V after setting V0 = 0 V, V1 = V2 = V3 = V4 = 3.5 V. The overcharge detection delay time (tCU) is the time period until the CO pin output inverts. After that, decrease V1 down to 3.5 V. The overcharge release delay time (tCL) is the time period until the CO pin output inverts. 7. CTL pin response delay time (tCTL) (Test circuit 2) Set SW1 to OFF in CMOS output product of the S-8224A Series and in the S-8224B Series, and set SW1 to ON in Nch open-drain output product of the S-8224A Series. Decrease V5 down to 0 V after setting V1 = V2 = V3 = V4 = 3.5 V, V5 = 14 V. The CTL pin response delay time (t CTL) is the time period until the CO pin output inverts. 8. Overcharge timer reset delay time (tTR) (Test circuit 1) Set SW1 to OFF in CMOS output product of the S-8224A Series and in the S-8224B Series, and set SW1 to ON in Nch open-drain output product of the S-8224A Series. Increase V1 up to 5.2 V (first rise), and decrease V1 down to 3.5 V within the overcharge detection delay time (tCU) after setting V0 = 0 V, V1 = V2 = V3 = V4 = 3.5 V. After that, increase V1 up to 5.2 V again (second rise), and detect the time period until the CO pin output inverts. When the period from when V1 has fallen to the second rise is short, CO pin output inverts after tCU has elapsed since the first rise. If the period is gradually made longer, CO pin output inverts after tCU has elapsed since the second rise. The overcharge timer reset delay time (tTR) is the period from V1 fall until the second rise at that time. 9. Transition time to test mode (tTST) (Test circuit 1) Set SW1 to OFF in CMOS output product of the S-8224A Series and in the S-8224B Series, and set SW1 to ON in Nch open-drain output product of the S-8224A Series. Increase V0 up to 8.5 V, and decrease V0 again to 0 V after setting V0 = 0 V, V1 = V2 = V3 = V4 = 3.5 V. When the period from when V0 was raised to when it has fallen is short, if an overcharge detection operation is performed subsequently, the delay time is tCU. However, when the period from when V0 is raised to when it has fallen is gradually made longer, the delay time during the subsequent overcharge detection operation is shorter than tCU. The transition time to test mode (tTST) is the period from when V0 was raised to when it has fallen at that time. 12 BATTERY PROTECTION IC FOR 2-SERIAL TO 4-SERIAL CELL PACK (SECONDARY PROTECTION) Rev.1.3_00 S-8224A/B Series 100 k 100 k SW1 S-8224A/B Series V0 VDD CO VC1 CTL V V1 VC2 VSS VC3 VDD CO VC1 CTL V1 V4 V2 SW1 S-8224A/B Series V5 VC2 VSS VC3 VC4 V4 V2 VC4 V3 V V3 Figure 5 Test Circuit 1 Figure 6 Test Circuit 2 SW2 IOPE IOPED S-8224A/B Series S-8224A/B Series VDD CO VC1 CTL IVC1 A A V1 VC2 VSS VC3 IVC2 V2 IVC3 A A V4 V2 V1 VC4 VDD CO VC1 CTL VC2 VSS VC3 VC4 A ICTLH A ICTLL SW3 IVC4 A V4 V3 V3 Figure 7 Test Circuit 3 Figure 8 Test Circuit 4 V6 A I1 SW4 S-8224A/B Series VDD CO VC1 CTL VC2 VSS VC3 VC4 V1 V2 SW5 V5 V4 V3 A I2 V V7 Figure 9 Test Circuit 5 13 BATTERY PROTECTION IC FOR 2-SERIAL TO 4-SERIAL CELL PACK (SECONDARY PROTECTION) Rev.1.3_00 S-8224A/B Series Operation Remark Refer to " Battery Protection IC Connection Examples". 1. Normal status If the voltage of each of the batteries is lower than "the overcharge detection voltage (VCU) + the overcharge hysteresis voltage (VHC)", the CO pin output changes to "L" (active "H") or "H" (active "L"). This is called normal status. 2. Overcharge status When the voltage of one of the batteries exceeds VCU during charging under normal conditions and the status is retained for the overcharge detection delay time (tCU) or longer, CO pin output inverts. This status is called overcharge status. Connecting FET to the CO pin provides charge control and a second protection. If the voltage of each of the batteries is lower than VCU + VHC and the status is retained for the overcharge release delay time (tCL) or longer, S-8224A/B Series changes to normal status. 3. Overcharge timer reset function When an overcharge release noise that forces the voltage of one of the batteries temporarily below VCU is input during tCU from when VCU is exceeded to when charging is stopped, tCU is continuously counted if the time the overcharge release noise persists is shorter than the overcharge timer reset delay time (tTR). Under the same conditions, if the time the overcharge release noise persists is tTR or longer, counting of tCU is reset once. After that, when VCU has been exceeded, counting tCU resumes. 14 BATTERY PROTECTION IC FOR 2-SERIAL TO 4-SERIAL CELL PACK (SECONDARY PROTECTION) Rev.1.3_00 S-8224A/B Series 4. CTL pin The S-8224A/B Series has control pins. In the S-8224A/B Series, the CTL pin is used to control the output voltage of the CO pin. The CTL pin takes precedence over the overcharge detection circuit. Table 8 Status Set by CTL Pin CTL Pin CO Pin Normal status*1 "H" Open Detection status "L" Detection status *1. The status is controlled by the overcharge detection circuit. - *1 CTL + Pull-down resistor *1. In the S-8224A/B Series, the inversion voltage "H" to "L" or "L" to "H" of the CTL pin is the VDD pin voltage - 2.8 V typ., and does not have the hysteresis. Figure 10 Internal Equivalent Circuit of CTL Pin Caution In the S-8224A/B Series, since the CTL pin implements high resistance of 7 M to 24 M for pull down, be careful of external noise application. If an external noise is applied, the CO pin may become "H". Perform thorough evaluation using the actual application. 15 BATTERY PROTECTION IC FOR 2-SERIAL TO 4-SERIAL CELL PACK (SECONDARY PROTECTION) Rev.1.3_00 S-8224A/B Series 5. Test mode In the S-8224A/B Series, the overcharge detection delay time (tCU) can be shortened by entering the test mode. The test mode can be set by retaining the VDD pin voltage 8.5 V or more higher than the VC1 pin voltage for at least 10 ms (V1 = V2 = V3 = V4 = 3.5 V, Ta = +25 C). The status is retained by the internal latch and the test mode is retained even if the VDD pin voltage is decreased to the same voltage as that of the VC1 pin. If the CO pin becomes detection status when the delay time has elapsed after overcharge detection, the latch for retaining the test mode is reset and the S-8224A/B Series exits from the test mode. VDD pin voltage VC1 pin voltage 8.5 V or higher Pin voltage VCUn VHCn Battery voltage (n = 1 to 4) Test mode tTST = 10 ms max. CO pin (Active "H") CO pin (Active "L") 32 ms typ. Caution tCL 1. Set the test mode when no batteries are overcharged. 2. The overcharge timer reset delay time (tTR) is not shortened in the test mode. Figure 11 16 BATTERY PROTECTION IC FOR 2-SERIAL TO 4-SERIAL CELL PACK (SECONDARY PROTECTION) Rev.1.3_00 S-8224A/B Series Timing Charts 1. Overcharge detection operation VHCn VCUn Battery voltage (n = 1 to 4) tTR or longer tTR or shorter tTR or shorter CTL pin CO pin (Active "H") CO pin (Actve "L") tCU tCL Figure 12 17 BATTERY PROTECTION IC FOR 2-SERIAL TO 4-SERIAL CELL PACK (SECONDARY PROTECTION) Rev.1.3_00 S-8224A/B Series 2. Overcharge timer reset operation VHCn tTR or shorter tTR or shorter tTR or longer VCUn Battery voltage (n = 1 to 4) tCU or shorter tTR CO pin (Active "H") Timer reset tCU CO pin (Active "L") Figure 13 18 BATTERY PROTECTION IC FOR 2-SERIAL TO 4-SERIAL CELL PACK (SECONDARY PROTECTION) Rev.1.3_00 S-8224A/B Series Battery Protection IC Connection Examples 1. 4-serial cell SCP EB+ VDD RVDD CVDD VC1 R1 BAT1 C1 VC2 R2 BAT2 C2 S-8224A/B Series VC3 R3 BAT3 BAT4 *1 C3 VC4 R4 FET CO DP C4 VSS CTL External input RCTL EB- *1. The S-8224B Series limits its CO pin output voltage to 11.5 V max., so a FET with the gate withstand voltage of 12 V can be used. Figure 14 Table 9 Constants for External Components No. Part Min. Typ. Max. Unit 0.3 1 R1 to R4 1 10 k 0.01 2 C1 to C4, CVDD 0.1 1 F 300 3 RVDD 330 1000 Caution 1. The above constants are subject to change without prior notice. 2. It has not been confirmed whether the operation is normal or not in circuits other than the above example of connection. In addition, the example of connection shown above and the constant will not guarantee successful operation. Perform thorough evaluation using the actual application to set the constant. 3. Set the same constants to R1 to R4 and to C1 to C4 and CVDD. 4. Since the CO pin may become detection status transiently when the battery is being connected, be sure to connect the positive terminal of BAT1 last in order to prevent the terminal protection fuse from cutoff. 19 BATTERY PROTECTION IC FOR 2-SERIAL TO 4-SERIAL CELL PACK (SECONDARY PROTECTION) Rev.1.3_00 S-8224A/B Series 2. 3-serial cell SCP EB+ VDD RVDD CVDD VD1 R1 BAT1 C1 VC2 R2 BAT2 C2 S-8224A/B Series VC3 R3 BAT3 FET *1 C3 VC4 CO DP VSS CTL External input RCTL EB- *1. The S-8224B Series limits its CO pin output voltage to 11.5 V max., so a FET with the gate withstand voltage of 12 V can be used. Figure 15 Table 10 Constants for External Components No. Part Min. Typ. Max. Unit 0.3 1 10 1 R1 to R3 k 0.01 0.1 1 2 C1 to C3, CVDD F 300 330 1000 3 RVDD Caution 1. The above constants are subject to change without prior notice. 2. It has not been confirmed whether the operation is normal or not in circuits other than the above example of connection. In addition, the example of connection shown above and the constant will not guarantee successful operation. Perform thorough evaluation using the actual application to set the constant. 3. Set the same constants to R1 to R3 and to C1 to C3 and CVDD. 4. Since the CO pin may become detection status transiently when the battery is being connected, connect the positive terminal of BAT1 last in order to prevent the protection fuse from cutoff. 20 BATTERY PROTECTION IC FOR 2-SERIAL TO 4-SERIAL CELL PACK (SECONDARY PROTECTION) Rev.1.3_00 S-8224A/B Series 3. 2-serial cell SCP EB+ VDD RVDD CVDD VC1 R1 BAT1 C1 VC2 R2 BAT2 S-8224A/B Series C2 VC3 VC4 FET CO DP VSS CTL External input RCTL EB- Figure 16 Table 11 Constants for External Components No. Part Min. Typ. Max. Unit 0.3 1 10 1 R1 to R2 k 0.01 0.1 1 2 C1 to C2, CVDD F 300 330 1000 3 RVDD Caution 1. The above constants are subject to change without prior notice. 2. It has not been confirmed whether the operation is normal or not in circuits other than the above example of connection. In addition, the example of connection shown above and the constant will not guarantee successful operation. Perform thorough evaluation using the actual application to set the constant. 3. Set the same constants to R1 to R2, and to C1 to C2 and CVDD. 4. Since the CO pin may become detection status transiently when the battery is being connected, connect the positive terminal of BAT1 last in order to prevent the protection fuse from cutoff. 21 BATTERY PROTECTION IC FOR 2-SERIAL TO 4-SERIAL CELL PACK (SECONDARY PROTECTION) Rev.1.3_00 S-8224A/B Series Precaution * Do not connect batteries charged with VCU + VHC or higher. * If the connected batteries include a battery charged with VCU + VHC or higher, the S-8224A/B series may become overcharge status after all pins are connected. * In some application circuits, even if an overcharged battery is not included, the order of connecting batteries may be restricted to prevent transient output of the CO pin detection pulses when the batteries are connected. Perform thorough evaluation with the actual application circuit. * Before the battery connection, short-circuit the battery side pins RVDD and R1, shown in the figures in " Battery Protection IC Connection Examples". * The application conditions for the input voltage, output voltage, and load current should not exceed the power dissipation. * Do not apply to this IC an electrostatic discharge that exceeds the performance ratings of the built-in electrostatic protection circuit. * ABLIC Inc. claims no responsibility for any disputes arising out of or in connection with any infringement of patents owned by a third party by products including this IC. 22 BATTERY PROTECTION IC FOR 2-SERIAL TO 4-SERIAL CELL PACK (SECONDARY PROTECTION) Rev.1.3_00 S-8224A/B Series Example of Application Circuit 1. Overheat protection via PTC SCP EB+ VDD RVDD CVDD VC1 R1 BAT1 C1 VC2 R2 BAT2 C2 S-8224A/B Series VC3 R3 BAT3 R4 BAT4 FET*1 C3 VC4 CO VSS CTL C4 First protection IC PTC CCTL EB- *1. The S-8224B Series limits its CO pin output voltage to 11.5 V max., so a FET with the gate withstand voltage of 12 V can be used. Figure 17 Caution 1. The above connection example will not guarantee successful operation. Perform thorough evaluation using the actual application. 2. A pull-down resistor is included in the CTL pin. To perform overheat protection via the PTC in the S-8224A/B Series, connect the PTC before connecting batteries. 3. When the power fluctuation is large, connect the power supply of the PTC to the VDD pin of the S-8224A/B Series. 4. Since the CO pin may become detection status transiently when the battery is being connected, connect the positive terminal of BAT1 last in order to prevent the three terminal protection fuse from cutoff. [For SCP, contact] Global Sales & Marketing Division, Dexerials Corporation Gate City Osaki East Tower 8F, 1-11-2 Osaki, Shinagawa-ku, Tokyo, 141-0032, Japan TEL +81-3-5435-3946 Contact Us: http://www.dexerials.jp/en/ [For PTC, contact] Murata Manufacturing Co., Ltd. Thermistor Products Department Nagaokakyo-shi, Kyoto, 617-8555, Japan TEL +81-75-955-6863 Contact Us: http://www.murata.com/contact/index.html 23 BATTERY PROTECTION IC FOR 2-SERIAL TO 4-SERIAL CELL PACK (SECONDARY PROTECTION) Rev.1.3_00 S-8224A/B Series Characteristics (Typical Data) 1. Detection voltage 1. 2 VCU + VHC vs. Ta 1. 1 VCU vs. Ta 4.520 4.200 4.510 4.150 VCU + VHC [V] VCU [V] VCU = 4.500 V 4.500 4.490 4.480 40 25 0 25 Ta [C] 4.100 4.050 4.000 40 25 75 85 50 VHC = -400 mV 0 25 Ta [C] 50 75 85 2. Current consumption 2. 1 IOPE vs. Ta 2. 2 IOPED vs. Ta VDD = 14 V VDD = 9 V 0.5 0.3 IOPED [A] IOPE [A] 0.4 0.3 0.2 0.2 0.1 0.1 0.0 40 25 0 25 Ta [C] 75 85 50 2. 3 IOPE vs. VDD Ta = +25C 80 IOPE [A] 60 40 20 0 0 5 10 15 20 VDD [V] 25 30 3. Delay time 3. 1 tCU vs. Ta VDD = 15.7 V 2.0 tCU [s] 1.5 1.0 0.5 0.0 24 40 25 0 25 Ta [C] 50 75 85 0.0 40 25 0 25 Ta [C] 50 75 85 BATTERY PROTECTION IC FOR 2-SERIAL TO 4-SERIAL CELL PACK (SECONDARY PROTECTION) Rev.1.3_00 S-8224A/B Series 4. CTL pin 4. 1 VCTLL vs. Ta 4. 2 ICTLH vs. Ta VDD = 14 V 12.0 2.5 11.5 2.0 ICTLH [A] VCTLL [V] VDD = 14 V 11.0 10.5 10.0 1.5 1.0 0.5 40 25 0 25 Ta [C] 75 85 50 40 25 0 25 Ta [C] 75 85 50 5. Output current 5. 1 ICOH vs. VDD (S-8224A Series) 5. 2 ICOH vs. VDD (S-8224B Series) Ta = +25C Ta = +25C 80 10 20 120 ICOH [A] ICOH [A] 100 140 160 180 200 0 5 10 15 20 VDD [V] 25 40 50 30 5. 3 ICOL vs. VDD 30 0 5 10 15 20 VDD [V] Ta = +25C 100 0.10 80 0.08 ICOLL [A] ICOL [A] 30 5. 4 ICOLL vs. VDD Ta = +25C 60 40 20 0 25 0.06 0.04 0.02 0 5 10 15 20 VDD [V] 25 30 0.00 0 5 10 15 20 VDD [V] 25 30 6. Output voltage 6. 1 VCOH vs. VDD 12 VCOH [V] 10 8 6 4 2 0 0 5 10 15 20 VDD [V] 25 30 25 BATTERY PROTECTION IC FOR 2-SERIAL TO 4-SERIAL CELL PACK (SECONDARY PROTECTION) Rev.1.3_00 S-8224A/B Series Marking Specifications 1. SNT-8A 8 Top view 7 6 5 (1) (2) to (4) (5), (6) (7) to (11) (1) (2) (3) (4) Blank Product code (Refer to Product name vs. Product code) Blank Lot number (5) (6) (7) (8) (9) (10) (11) 1 2 3 4 Product name vs. Product code Product name S-8224AAS-I8T1U S-8224AAT-I8T1U S-8224AAU-I8T1U S-8224AAV-I8T1U S-8224AAW-I8T1U S-8224AAX-I8T1U S-8224ABA-I8T1U S-8224ABB-I8T1U S-8224ABC-I8T1U S-8224ABD-I8T1U 26 (2) 5 5 5 5 5 5 6 6 6 6 Product code (3) (4) R S R T R U R V R W R Y Z A Z B Z C Z D Product name S-8224BAA-I8T1U S-8224BAB-I8T1U S-8224BAC-I8T1U (2) 5 5 5 Product code (3) (4) S A S B S C BATTERY PROTECTION IC FOR 2-SERIAL TO 4-SERIAL CELL PACK (SECONDARY PROTECTION) Rev.1.3_00 S-8224A/B Series Power Dissipation SNT-8A Tj = 125C max. Power dissipation (PD) [W] 1.0 0.8 B 0.6 A 0.4 0.2 0.0 0 25 50 75 100 125 150 175 Ambient temperature (Ta) [C] Board A B C D E Power Dissipation (PD) 0.47 W 0.58 W - - - 27 SNT-8A Test Board ICMountArea (1) Board A Item Size [mm] Material Number of copper foil layer Copper foil layer [mm] 1 2 3 4 Thermal via Specification 114.3 x 76.2 x t1.6 FR-4 2 Land pattern and wiring for testing: t0.070 74.2 x 74.2 x t0.070 - (2) Board B Item Size [mm] Material Number of copper foil layer Copper foil layer [mm] Thermal via 1 2 3 4 Specification 114.3 x 76.2 x t1.6 FR-4 4 Land pattern and wiring for testing: t0.070 74.2 x 74.2 x t0.035 74.2 x 74.2 x t0.035 74.2 x 74.2 x t0.070 - No. SNT8A-A-Board-SD-1.0 ABLIC Inc. 1.970.03 8 7 6 5 3 4 +0.05 1 0.5 2 0.08 -0.02 0.480.02 0.20.05 No. PH008-A-P-SD-2.1 TITLE SNT-8A-A-PKG Dimensions No. PH008-A-P-SD-2.1 ANGLE UNIT mm ABLIC Inc. +0.1 o1.5 -0 2.250.05 4.00.1 2.00.05 o0.50.1 0.250.05 0.650.05 4.00.1 4 321 5 6 78 Feed direction No. PH008-A-C-SD-2.0 TITLE SNT-8A-A-Carrier Tape No. PH008-A-C-SD-2.0 ANGLE UNIT mm ABLIC Inc. 12.5max. 9.00.3 Enlarged drawing in the central part o130.2 (60) (60) No. PH008-A-R-SD-1.0 TITLE SNT-8A-A-Reel No. PH008-A-R-SD-1.0 QTY. ANGLE UNIT mm ABLIC Inc. 5,000 0.52 2.01 2 0.52 0.2 0.3 1. 2. 1 (0.25 mm min. / 0.30 mm typ.) (1.96 mm ~ 2.06 mm) 1. 2. 3. 4. 0.03 mm SNT 1. Pay attention to the land pattern width (0.25 mm min. / 0.30 mm typ.). 2. Do not widen the land pattern to the center of the package (1.96 mm to 2.06mm). Caution 1. Do not do silkscreen printing and solder printing under the mold resin of the package. 2. The thickness of the solder resist on the wire pattern under the package should be 0.03 mm or less from the land pattern surface. 3. Match the mask aperture size and aperture position with the land pattern. 4. Refer to "SNT Package User's Guide" for details. 1. 2. (0.25 mm min. / 0.30 mm typ.) (1.96 mm ~ 2.06 mm) TITLE No. PH008-A-L-SD-4.1 SNT-8A-A -Land Recommendation PH008-A-L-SD-4.1 No. ANGLE UNIT mm ABLIC Inc. Disclaimers (Handling Precautions) 1. All the information described herein (product data, specifications, figures, tables, programs, algorithms and application circuit examples, etc.) is current as of publishing date of this document and is subject to change without notice. 2. The circuit examples and the usages described herein are for reference only, and do not guarantee the success of any specific mass-production design. ABLIC Inc. is not liable for any losses, damages, claims or demands caused by the reasons other than the products described herein (hereinafter "the products") or infringement of third-party intellectual property right and any other right due to the use of the information described herein. 3. ABLIC Inc. is not liable for any losses, damages, claims or demands caused by the incorrect information described herein. 4. Be careful to use the products within their ranges described herein. Pay special attention for use to the absolute maximum ratings, operation voltage range and electrical characteristics, etc. ABLIC Inc. is not liable for any losses, damages, claims or demands caused by failures and / or accidents, etc. due to the use of the products outside their specified ranges. 5. Before using the products, confirm their applications, and the laws and regulations of the region or country where they are used and verify suitability, safety and other factors for the intended use. 6. When exporting the products, comply with the Foreign Exchange and Foreign Trade Act and all other export-related laws, and follow the required procedures. 7. The products are strictly prohibited from using, providing or exporting for the purposes of the development of weapons of mass destruction or military use. ABLIC Inc. is not liable for any losses, damages, claims or demands caused by any provision or export to the person or entity who intends to develop, manufacture, use or store nuclear, biological or chemical weapons or missiles, or use any other military purposes. 8. The products are not designed to be used as part of any device or equipment that may affect the human body, human life, or assets (such as medical equipment, disaster prevention systems, security systems, combustion control systems, infrastructure control systems, vehicle equipment, traffic systems, in-vehicle equipment, aviation equipment, aerospace equipment, and nuclear-related equipment), excluding when specified for in-vehicle use or other uses by ABLIC, Inc. Do not apply the products to the above listed devices and equipments. ABLIC Inc. is not liable for any losses, damages, claims or demands caused by unauthorized or unspecified use of the products. 9. In general, semiconductor products may fail or malfunction with some probability. The user of the products should therefore take responsibility to give thorough consideration to safety design including redundancy, fire spread prevention measures, and malfunction prevention to prevent accidents causing injury or death, fires and social damage, etc. that may ensue from the products' failure or malfunction. The entire system in which the products are used must be sufficiently evaluated and judged whether the products are allowed to apply for the system on customer's own responsibility. 10. The products are not designed to be radiation-proof. The necessary radiation measures should be taken in the product design by the customer depending on the intended use. 11. The products do not affect human health under normal use. However, they contain chemical substances and heavy metals and should therefore not be put in the mouth. The fracture surfaces of wafers and chips may be sharp. Be careful when handling these with the bare hands to prevent injuries, etc. 12. When disposing of the products, comply with the laws and ordinances of the country or region where they are used. 13. The information described herein contains copyright information and know-how of ABLIC Inc. The information described herein does not convey any license under any intellectual property rights or any other rights belonging to ABLIC Inc. or a third party. Reproduction or copying of the information from this document or any part of this document described herein for the purpose of disclosing it to a third-party is strictly prohibited without the express permission of ABLIC Inc. 14. For more details on the information described herein or any other questions, please contact ABLIC Inc.'s sales representative. 15. This Disclaimers have been delivered in a text using the Japanese language, which text, despite any translations into the English language and the Chinese language, shall be controlling. 2.4-2019.07 www.ablic.com