White Electronic Designs W78M64VP-XSBX 8Mx64 Flash 3.3V Page Mode Multi-Chip Package FEATURES Secured Silicon Sector region Access Times of 110, 120ns * 128-word sector for permanent, secure identification through an 8-word random Electronic Serial Number, accessible through a command sequence Packaging * 159 PBGA, 13x22mm - 1.27mm pitch Page Mode * Page size is 8 words: Fast page read access from random locations within the page. * May be programmed and locked at the factory or by the customer Uniform Sector Architecture 100,000 erase cycles per sector typical * One hundred twenty-eight 64 kword 20-year data retention typical Single power supply operation * 3 volt read, erase, and program operations * This product is subject to change without notice. I/O Control * All input levels (address, control, and DQ input levels) and outputs are determined by voltage on VIO input. Write operation status bits indicate program and erase operation completion Suspend and Resume commands for program and erase operations Hardware Reset# input resets device WP#/ACC Input * Accelerates programming time for greater throughput. * Protects first and last sector regardless of sector protection settings White Electronic Designs Corp. reserves the right to change products or specifications without notice. November 2009 Rev. 10 (c) 2010 White Electronic Designs Corp. All rights reserved 1 White Electronic Designs Corporation * (602) 437-1520 * www.whiteedc.com White Electronic Designs W78M64VP-XSBX FIG 1: PIN CONFIGURATION FOR W78M64VP-XSBX (TOP VIEW) FIG 2: PIN DESCRIPTION 1 A 2 3 4 5 6 7 8 9 10 GND GND GND VCC VIO GND GND GND VCC B VIO GND DQ41 WE3# VIO DQ57 DNU WE4# VCC VIO C VCC DQ33 DQ43 DQ45 DQ47 DQ49 DQ59 DQ61 DQ63 VCC D VIO DQ40 DQ35 DQ37 DQ39 DQ56 DQ51 DQ53 DQ55 VIO E VCC DQ32 DQ42 DQ44 DQ46 DQ48 DQ58 DQ60 DQ62 VCC F GND CS3# DQ34 DQ36 DQ38 CS4# DQ50 DQ52 DQ54 GND G GND OE# A0 A22 VCC A12 A16 A21 A20 GND H GND A2 WP#/ACC A11 GND VIO A7 A10 A15 GND J GND A3 A6 A9 VCC GND A1 RESET# A13 GND K GND A4 A17 RY/BY# GND A14 A5 A18 A8 GND L GND DQ17 WE2# DQ29 DNU* DQ9 DQ4 WE1# A19 GND M VIO DQ24 DQ19 DQ21 DQ31 DQ1 DQ11 DQ6 DQ15 VIO DQ0-63 A0-22 WE#1-4 CS#1-4 OE# RESET# WP#/ACC RY/BY# VCC VIO GND DNU FIG 3: BLOCK DIAGRAM WE1# CS1# N VCC DQ16 DQ26 DQ28 DQ23 DQ8 DQ3 DQ13 DQ7 VCC P VIO CS2# DQ18 DQ20 DQ30 DQ0 DQ10 DQ5 DQ14 VIO R VCC VCC DQ25 DQ27 DQ22 CS1# DQ2 DQ12 GND VCC T VIO GND GND GND VIO VCC GND GND GND VIO Data Inputs/Outputs Address Inputs Write Enables Chip Selects Output Enable Hardware Reset Hardware Write Protection/Acceleration Ready/Busy Output Power Supply Versatile I/O Input Ground Do Not Use WE2# CS2# WE3# WE4# CS3# CS4# RY/BY# RESET# OE# A0-22 8M X 16 8M X 16 8M X 16 8M X 16 WP#/ACC DQ0-15 DQ16-31 DQ32-47 DQ48-63 * Ball L5 is reserved for A23 for future upgrades. White Electronic Designs Corp. reserves the right to change products or specifications without notice. November 2009 Rev. 10 (c) 2010 White Electronic Designs Corp. All rights reserved 2 White Electronic Designs Corporation * (602) 437-1520 * www.whiteedc.com White Electronic Designs W78M64VP-XSBX GENERAL DESCRIPTION DEVICE OPERATION TABLE The W78M64VP-XSBX is a 512Mb, 3.3 volt-only Page Mode memory device. The device must be setup appropriately for each operation. Table 2 describes the required state of each control pin for any particular operation. The device offers fast page access times allowing high speed microprocessors to operate without wait states. To eliminate bus contention the device has separate chip enable (CS#), write enable (WE#) and output enable (OE#) controls. READ All memories require access time to output array data. In a read operation, data is read from one memory location at a time. Addresses are presented to the device in random order, and the propagation delay through the device causes the data on its outputs to arrive with the address on its inputs. The device offers uniform 64 Kword (128Kb) Sectors: PAGE MODE FEATURES The device defaults to reading array data after device powerup or hardware reset. To read data from the memory array, the system must first assert a valid address on A22-A0, while driving OE# and CE# to VIL. WE# must remain at VIH. All addresses are latched on the falling edge of CE#. Data will appear on DQ15-DQ0 after address access time (tACC), which is equal to the delay from stable addresses to valid output data. The page size is 8 words. After initial page access is accomplished, the page mode operation provides fast read access speed of random locations within that page. STANDARD FLASH MEMORY FEATURES The device requires a 3.3 volt power supply for both read and write functions. Internally generated and regulated voltages are provided for the program and erase operations Page Mode Features The OE# signal must be driven to VIL. Data is output on DQ15-DQ0 pins after the access time (tOE) has elapsed from the falling edge of OE#, assuming the tACC access time has been meet. DEVICE OPERATIONS PAGE READ MODE This section describes the read, program, erase, handshaking, and reset features of the Flash devices. Operations are initiated by writing specific commands or a sequence with specific address and data patterns into the command registers ( see Table 38 and Table 39). The command register itself does not occupy andy addressable memory location; rather, it is composed of latches that store the commands, along with the address and data information needed to execute the command. The contents of the register serves as input to the internal state machine and the state machine outputs dictate the function of the device. Writing incorrect address and data values or writing them in an improper sequence may place the device in an unknown state, in which case the system must pull the RESET# pin low or power cycle the device to return the device to the reading array data mode. The device is capable of fast page mode read and is compatible with the page mode Mask ROM read operation. This mode provides faster read access speed for random locations within a page. The page size of the device is 8 words. The appropriate page is selected by the higher address bits A(22)-A3. Address bits A2-A0 in word mode determine the specific word within a page. The microprocessor supplies the specific word location. The random or initial page access is equal to tACC or tCE and subsequent page read accesses (as long as the locations specified by the microprocessor falls within that page) is equivalent to tACC. When CE# is deasserted and reasserted for a subsequent access, the access time is tACC or tCE. Fast page mode accesses are obtained by keeping the "read-page addresses" constant and changing the "intra-read page" addresses. White Electronic Designs Corp. reserves the right to change products or specifications without notice. November 2009 Rev. 10 (c) 2010 White Electronic Designs Corp. All rights reserved 3 White Electronic Designs Corporation * (602) 437-1520 * www.whiteedc.com White Electronic Designs W78M64VP-XSBX AUTOSELECT PROGRAM/ERASE OPERATIONS The Autoselect mode provides manufacturer ID, Device identification, and sector protection information, through identifier codes output from the internal register (separate from the memory array) on DQ7-DQ0. This mode is primarily intended for programming equipment to automatically match a device to be programmed with its corresponding programming algorithm (see Table 4). The Autoselect codes can also be accessed in-system. These devices are capable of several modes of programming and or erase operations which are described in detail in the following sections. There are two methods to access autoselect codes. One uses the autoselect command, the other applies VID on address pin A9. The Unlock Bypass feature allows the host system to send program commands to the Flash device without first writing unlock cycles within the command sequence. See Unlock Bypass section for details on the Unlock Bypass function. During a write operation, the system must drive CE# and WE# to VIL and OE# to VIH when providing address, command, and data. Addresses are latched on the last falling edge of WE# or CE#, while data is latched on the 1st rising edge of WE# or CE#. When using programming equipment, the autoselect mode requires VID (11.5 V to 12.5 V) on address pin A9. Address pins must be as shown in Table 3. Note the following: When the Embedded Program algorithm is complete, the device returns to the read mode. To access Autoselect mode without using high voltage on A9, the host system must issue the Autoselect command. The system can determine the status of the program operation by reading the DQ status bits. Refer to the Write Operation Status for information on these status bits. The Autoselect command sequence may be written to an address within a sector that is either in the read or erase-suspend-read mode. An "0" cannot be programmed back to a "1." A succeeding read shows that the data is still "0." The Autoselect command may not be written while the device is actively programming or erasing. Only erase operations can convert a "0" to a "1." The system must write the reset command to return to the read mode (or erase-suspend-read mode if the sector was previously in Erase Suspend). Any commands written to the device during the Embedded Program/Erase are ignored except the Suspend commands. It is recommended that A9 apply VID after powerup sequence is completed. In addition, it is recommended that A9 apply from VID to VIH/VIL before power-down the VCC/VIO. Secured Silicon Sector, Autoselect, and CFI functions are unavailable when a program operation is in progress. A hardware reset and/or power removal immediately terminates the Program/Erase operation and the See Table 39 for command sequence details. When verifying sector protection, the sector address must appear on the appropriate highest order address bits (see Table 5 to Table 6). The remaining address bits are don't care. When all necessary bits have been set as required, the programming equipment may then read the corresponding identifier code on DQ15-DQ0. The Autoselect codes can also be accessed in-system through the command register. Program/Erase command sequence should be reinitiated once the device has returned to the read mode to ensure data integrity. Programming is allowed in any sequence and across sector boundaries for single word programming operation. See Write Buffer Programming when using the write buffer. Programming to the same word address multiple times without intervening erases is permitted. White Electronic Designs Corp. reserves the right to change products or specifications without notice. November 2009 Rev. 10 (c) 2010 White Electronic Designs Corp. All rights reserved 4 White Electronic Designs Corporation * (602) 437-1520 * www.whiteedc.com White Electronic Designs SINGLE WORD PROGRAMMING W78M64VP-XSBX the operation aborts. (Number loaded = the number of locations to program minus 1. For example, if the system programs 6 address locations, then 05h should be written to the device.) Single word programming mode is one method of programming the Flash. In this mode, four Flash command write cycles are used to program an individual Flash address. The data for this programming operation could be 8 or 16-bits wide. The system then writes the starting address/data combination. This starting address is the first address/data pair to be programmed, and selects the "write-buffer-page" address. All subsequent address/data pairs must fall within the elected-write-buffer-page. While the single word programming method is supported by most Spansion devices, in general Single Word Programming is not recommended for devices that support Write Buffer Programming. See Table 38 for the required bus cycles and FIG: 4 for the flowchart. When the Embedded Program algorithm is complete, the device then returns to the read mode and addresses are no longer latched. The system can determine the status of the program operation by reading the DQ status bits. Refer to Write Operation Status for information on these status bits. The "write-buffer-page" is selected by using the addresses AMAX-A5. The "write-buffer-page" addresses must be the same for all address/data pairs loaded into the write buffer. (This means Write Buffer Programming cannot be performed across multiple "write-buffer-pages." This also means that Write Buffer Programming cannot be performed across multiple sectors. If the system attempts to load programming data outside of the selected "write-buffer-page", the operation ABORTs.) During programming, any command (except the Suspend Program command) is ignored. The Secured Silicon Sector, Autoselect, and CFI functions are unavailable when a program operation is inprogress. After writing the Starting Address/Data pair, the system then writes the remaining address/data pairs into the write buffer. Note that if a Write Buffer address location is loaded multiple times, the "address/data pair" counter is decremented for every data load operation. Also, the last data loaded at a location before the "Program Buffer to Flash" confirm command is the data programmed into the device. It is the software's responsibility to comprehend ramifications of loading a write-buffer location more than once. The counter decrements for each data load operation, NOT for each unique write-buffer-address location. Once the specified number of write buffer locations have been loaded, the system must then write the "Program Buffer to Flash" command at the Sector Address. Any other address/data write combinations abort the Write Buffer Programming operation. The Write Operation Status bits should be used while monitoring the last address location loaded into the write buffer. This eliminates the need to store an address in memory because the system can load the last address location, issue the program confirm command at the last loaded address location, and then check the write operation status at that same address. DQ7, DQ6, DQ5, DQ2, and DQ1 should be monitored to determine the device status during Write Buffer Programming. A hardware reset immediately terminates the program operation. The program command sequence should be reinitiated once the device has returned to the read mode, to ensure data integrity. Programming to the same address multiple times continuously (for example, "walking" a bit within a word) is permitted. WRITE BUFFER PROGRAMMING Write Buffer Programming allows the system to write a maximum of 32 words in one programming operation. This results in a faster effective word programming time than the standard "word" programming algorithms. The Write Buffer Programming command sequence is initiated by first writing two unlock cycles. This is followed by a third write cycle containing the Write Buffer Load command written at the Sector Address in which programming occurs. At this point, the system writes the number of "word locations minus 1" that are loaded into the page buffer at the Sector Address in which programming occurs. This tells the device how many write buffer addresses are loaded with data and therefore when to expect the "Program Buffer to Flash" confirm command. The number of locations to program cannot exceed the size of the write buffer or The write-buffer "embedded" programming operation can be suspended using the standard suspend/resume commands. Upon successful completion of the Write Buffer Programming operation, the device returns to READ mode. White Electronic Designs Corp. reserves the right to change products or specifications without notice. November 2009 Rev. 10 (c) 2010 White Electronic Designs Corp. All rights reserved 5 White Electronic Designs Corporation * (602) 437-1520 * www.whiteedc.com White Electronic Designs W78M64VP-XSBX time between these additional cycles must be less than 50 s. Any sector erase address and command following the exceeded time-out (50s) may or may not be accepted. Any command other than Sector Erase or Erase Suspend during the time-out period resets that sector to the read mode. The system can monitor DQ3 to determine if the sector erase timer has timed out. The time-out begins from the rising edge of the final WE# pulse in the command sequence. The Write Buffer Programming Sequence is ABORTED under any of the following conditions: Load a value that is greater than the page buffer size during the "Number of Locations to Program" step. Write to an address in a sector different than the one specified during the Write-Buffer-Load command. Write an Address/Data pair to a different writebuffer-page than the one selected by the "Starting Address" during the "write buffer data loading" stage of the operation. When the Embedded Erase algorithm is complete, the sector returns to reading array data and addresses are no longer latched. The system can determine the status of the erase operation by reading DQ7 or DQ6/DQ2 in the erasing sector. Refer to Section write operation status section for information on these status bits. Writing anything other than the Program to Buffer Flash Command after the specified number of "data load" cycles. The ABORT condition is indicated by DQ1 = 1, DQ7 = DATA# (for the "last address location loaded"), DQ6 = TOGGLE, DQ5 = 0. This indicates that the Write Buffer Programming Operation was ABORTED. A "Write-to- Buffer-Abort reset" command sequence is required when using the write buffer Programming features in Unlock Bypass mode. Note that the Secured Silicon sector, autoselect, and CFI functions are unavailable when a program operation is in progress. Once the sector erase operation has begun, only the Erase Suspend command is valid. All other commands are ignored. However, note that a hardware reset immediately terminates the erase operation. If that occurs, the sector erase command sequence should be reinitiated once that sector has returned to reading array data, to ensure the sector is properly erased. The Unlock Bypass feature allows the host system to send program commands to the Flash device without first writing unlock cycles within the command sequence. See Unlock Bypass Section for details on the Unlock Bypass function. Write buffer programming is allowed in any sequence of memory (or address) locations. These flash devices are capable of handling multiple write buffer programming operations on the same write buffer address range without intervening erases. FIG: 6 illustrates the algorithm for the erase operation. Refer to Erase and Programming Performance Section for parameters and timing diagrams. Use of the write buffer is strongly recommended for programming when multiple words are to be programmed. CHIP ERASE COMMAND SEQUENCE Chip erase is a six-bus cycle operation as indicated by Table 39. These commands invoke the Embedded Erase algorithm, which does not require the system to preprogram prior to erase. The Embedded Erase algorithm automatically preprograms and verifies the entire memory to an all zero data pattern prior to electrical erase. After a successful chip erase, all locations of the chip contain FFFFh. The system is not required to provide any controls or timings during these operations. The Command Definitions shows the address and data requirements for the chip erase command sequence. SECTOR ERASE The sector erase function erases one or more sectors in the memory array. (See Table 38 and FIG: 6.) The device does not require the system to preprogram a sector prior to erase. The Embedded Erase algorithm automatically programs and verifies the entire memory to an all zero data pattern prior to electrical erase. After a successful sector erase, all locations within the erased sector contain FFFFh. The system is not required to provide any controls or timings during these operations. When the Embedded Erase algorithm is complete, that sector returns to the read mode and addresses are no longer latched. The system can determine the status of the erase operation by using DQ7 or DQ6/DQ2. Refer to "Write Operation Status" for information on these status bits. After the command sequence is written, a sector erase timeout of no less than tSEA occurs. During the timeout period, additional sector addresses may be written. Loading the sector erase buffer may be done in any sequence, and the number of sectors may be from one sector to all sectors. The White Electronic Designs Corp. reserves the right to change products or specifications without notice. November 2009 Rev. 10 (c) 2010 White Electronic Designs Corp. All rights reserved 6 White Electronic Designs Corporation * (602) 437-1520 * www.whiteedc.com White Electronic Designs W78M64VP-XSBX To resume the sector erase operation, the system must write the Erase Resume command. The address of the erasesuspended sector is required when writing this command. Further writes of the Resume command are ignored. Another Erase Suspend command can be written after the chip has resumed erasing. The Unlock Bypass feature allows the host system to send program commands to the Flash device without first writing unlock cycles within the command sequence. See Unlock Bypass Section for details on the Unlock Bypass function. Any commands written during the chip erase operation are ignored. However, note that a hardware reset immediately terminates the erase operation. If that occurs, the chip erase command sequence should be reinitiated once that sector has returned to reading array data, to ensure the entire array is properly erased. PROGRAM SUSPEND/PROGRAM RESUME COMMANDS The Program Suspend command allows the system to interrupt an embedded programming operation or a "Write to Buffer" programming operation so that data can read from any non-suspended sector. When the Program Suspend command is written during a programming process, the device halts the programming operation within 15 s maximum (5 s typical) and updates the status bits. Addresses are "don't-cares" when writing the Program Suspend command. ERASE SUSPEND/ERASE RESUME COMMANDS The Erase Suspend command allows the system to interrupt a sector erase operation and then read data from, or program data to, any sector not selected for erasure. The sector address is required when writing this command. This command is valid only during the sector erase operation, including the minimum tSEA time-out period during the sector erase command sequence. The Erase Suspend command is ignored if written during the chip erase operation. After the programming operation has been suspended, the system can read array data from any nonsuspended sector. The Program Suspend command may also be issued during a programming operation while an erase is suspended. In this case, data may be read from any addresses not within a sector in Erase Suspend or Program Suspend. If a read is needed from the Secured Silicon Sector area, then user must use the proper command sequences to enter and exit this region. When the Erase Suspend command is written during the sector erase operation, the device requires a maximum of 20 s (5 s typical) to suspend the erase operation. However, when the Erase Suspend command is written during the sector erase time-out, the device immediately terminates the time-out period and suspends the erase operation. The system may also write the Autoselect Command Sequence when the device is in Program Suspend After the erase operation has been suspended, the device enters the erase-suspend-read mode. The system can read data from or program data to any sector not selected for erasure. (The device "erase suspends" all sectors selected for erasure.) Reading at any address within erase-suspended sectors produces status information on DQ7-DQ0. The system can use DQ7, or DQ6, and DQ2 together, to determine if a sector is actively erasing or is erase-suspended. mode. The device allows reading Autoselect codes in the suspended sectors, since the codes are not stored in the memory array. When the device exits the Autoselect mode, the device reverts to Program Suspend mode, and is ready for another valid operation. See Autoselect Section. After the Program Resume command is written, the device reverts to programming. The system can determine the status of the program operation using the write operation status bits, just as in the standard program operation. See Write Operation Status Section for more information. After an erase-suspended program operation is complete, the device returns to the erase-suspend-read mode. The system can determine the status of the program operation using write operation status bits, just as in the standard program operation. The system must write the Program Resume command (address bits are "don't care") to exit the Program Suspend mode and continue the programming operation. Further writes of the Program Resume command are ignored. Another Program Suspend command can be written after the device has resumed programming. In the erase-suspend-read mode, the system can also issue the Autoselect command sequence. Refer to Write Buffer Programming Section and the Autoselect Section. White Electronic Designs Corp. reserves the right to change products or specifications without notice. November 2009 Rev. 10 (c) 2010 White Electronic Designs Corp. All rights reserved 7 White Electronic Designs Corporation * (602) 437-1520 * www.whiteedc.com White Electronic Designs W78M64VP-XSBX ACCELERATED PROGRAM WRITE OPERATION STATUS Accelerated single word programming and write buffer programming operations are enabled through the WP#/ ACC pin. This method is faster than the standard program command sequences. The device provides several bits to determine the status of a program or erase operation. The following subsections describe the function of DQ1, DQ2, DQ3, DQ5, DQ6, and DQ7. Note DQ7: DATA# POLLING The accelerated program functions must not be used more than 10 times per sector. If the system asserts VHH on this input, the device automatically enters the aforementioned Unlock Bypass mode and uses the higher voltage on the input to reduce the time required for program operations. The system can then use the Write Buffer Load command sequence provided by the Unlock Bypass mode. Note that if a "Write-to-Buffer-Abort Reset" is required while in Unlock Bypass mode, the full 3-cycle RESET command sequence must be used to reset the device. Removing VHH from the ACC input, upon completion of the embedded program operation, returns the device to normal operation. The Data# Polling bit, DQ7, indicates to the host system whether an Embedded Program or Erase algorithm is in progress or completed, or whether the device is in Erase Suspend. Data# Polling is valid after the rising edge of the final WE# pulse in the command sequence. Note that the Data# Polling is valid only for the last word being programmed in the write-buffer-page during Write Buffer Programming. Reading Data# Polling status on any word other than the last word to be programmed in the write-buffer-page returns false status information. During the Embedded Program algorithm, the device outputs on DQ7 the complement of the datum programmed to DQ7. This DQ7 status also applies to programming during Erase Suspend. When the Embedded Program algorithm is complete, the device outputs the datum programmed to DQ7. The system must provide the program address to read valid status information on DQ7. If a program address falls within a protected sector, Data# polling on DQ7 is active, then that sector returns to the read mode. Sectors must be unlocked prior to raising WP#/ACC to VHH. The WP#/ACC pin must not be at VHH for operations other than accelerated programming, or device damage may result. It is recommended that WP#/ACC apply VHH after power-up sequence is completed. In addition, it is recommended that WP#/ACC apply from VHH to VIH/ VIL before powering down VCC/VIO. During the Embedded Erase Algorithm, Data# polling produces a "0" on DQ7. When the Embedded Erase algorithm is complete, or if the device enters the Erase Suspend mode, Data# Polling produces a "1" on DQ7. The system must provide an address within any of the sectors selected for erasure to read valid status information on DQ7. UNLOCK BYPASS This device features an Unlock Bypass mode to facilitate shorter programming commands. Once the device enters the Unlock Bypass mode, only two write cycles are required to program data, instead of the normal four cycles. After an erase command sequence is written, if all sectors selected for erasing are protected, Data# Polling on DQ7 is active for approximately 100 s, then the device returns to the read mode. If not all selected sectors are protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. However, if the system reads DQ7 at an address within a protected sector, the status may not be valid. This mode dispenses with the initial two unlock cycles required in the standard program command sequence, resulting in faster total programming time. The Command Definitions shows the requirements for the unlock bypass command sequences. During the unlock bypass mode, only the Read, Program, Write Buffer Programming, Write-to-Buffer-Abort Reset, and Unlock Bypass Reset commands are valid. To exit the unlock bypass mode, the system must issue the two-cycle unlock bypass reset command sequence. The first cycle must contain the sector address and the data 90h. The second cycle need only contain the data 00h. The sector then returns to the read mode. Just prior to the completion of an Embedded Program or Erase operation, DQ7 may change asynchronously with DQ6-DQ0 while Output Enable (OE#) is asserted low. That is, the device may change from providing status information to valid data on DQ7. Depending on when the system samples the DQ7 output, it may read the status or valid data. Even if the device has completed the program or erase operation and DQ7 has White Electronic Designs Corp. reserves the right to change products or specifications without notice. November 2009 Rev. 10 (c) 2010 White Electronic Designs Corp. All rights reserved 8 White Electronic Designs Corporation * (602) 437-1520 * www.whiteedc.com White Electronic Designs W78M64VP-XSBX DQ2: TOGGLE BIT II valid data, the data outputs on DQ6-DQ0 may be still invalid. Valid data on DQ7-D00 appears on successive read cycles. The "Toggle Bit II" on DQ2, when used with DQ6, indicates whether a particular sector is actively erasing (that is, the Embedded Erase algorithm is in progress), or whether that sector is erase-suspended. Toggle Bit II is valid after the rising edge of the final WE# pulse in the command sequence. DQ2 toggles when the system reads at addresses within those sectors that have been selected for erasure. But DQ2 cannot distinguish whether the sector is actively erasing or is erase-suspended. DQ6, by comparison, indicates whether the device is actively erasing, or is in Erase Suspend, but cannot distinguish which sectors are selected for erasure. Thus, both status bits are required for sector and mode information. Refer to Table 18 to compare outputs for DQ2 and DQ6. See the following for more information: Table 18, shows the outputs for Data# Polling on DQ7. FIG: 7, shows the Data# Polling algorithm; and FIG: 22, shows the Data# Polling timing diagram. DQ6: TOGGLE BIT I Toggle Bit I on DQ6 indicates whether an Embedded Program or Erase algorithm is in progress or complete, or whether the device has entered the Erase Suspend mode. Toggle Bit I may be read at any address, and is valid after the rising edge of the final WE# pulse in the command sequence (prior to the program or erase operation), and during the sector erase time-out. During an Embedded Program or Erase algorithm operation, successive read cycles to any address that is being programmed or erased causes DQ6 to toggle. When the operation is complete, DQ6 stops toggling. READING TOGGLE BITS DQ6/DQ2 Whenever the system initially begins reading toggle bit status, it must read DQ7-DQ0 at least twice in a row to determine whether a toggle bit is toggling. Typically, the system would note and store the value of the toggle bit after the first read. After the second read, the system would compare the new value of the toggle bit with the first. If the toggle bit is not toggling, the device has completed the program or erases operation. The system can read array data on DQ7-DQ0 on the following read cycle. However, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the system also should note whether the value of DQ5 is high (see DQ5: Exceeded Timing Limits). If it is, the system should then determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as DQ5 went high. If the toggle bit is no longer toggling, the device has successfully completed the program or erases operation. If it is still toggling, the device did not complete the operation successfully, and the system must write the reset command to return to reading array data. The remaining scenario is that the system initially determines that the toggle bit is toggling and DQ5 has not gone high. The system may continue to monitor the toggle bit and DQ5 through successive read cycles, determining the status as described in the previous paragraph. Alternatively, it may choose to perform other system tasks. In this case, the system must start at the beginning of the algorithm when it returns to determine the status of the operation. Refer to FIG: 7 for more details. After an erase command sequence is written, if all sectors selected for erasing are protected, DQ6 toggles for approximately 100s, then returns to reading array data. If not all selected sectors are protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. The system can use DQ6 and DQ2 together to determine whether a sector is actively erasing or is erase suspended. When the device is actively erasing (that is, the Embedded Erase algorithm is in progress), DQ6 toggles. When the device enters the Erase Suspend mode, DQ6 stops toggling. However, the system must also use DQ2 to determine which sectors are erasing or erase-suspended. Alternatively, the system can use DQ7 (see DQ7: Data# Polling). If a program address falls within a protected sector, DQ6 toggles for approximately 1s after the program command sequence is written, then returns to reading array data. DQ6 also toggles during the erase-suspend-program mode, and stops toggling once the Embedded Program Algorithm is complete. Toggle Bit I on DQ6 requires either OE# or CE# to be deasserted and reasserted to show the change in state. White Electronic Designs Corp. reserves the right to change products or specifications without notice. November 2009 Rev. 10 (c) 2010 White Electronic Designs Corp. All rights reserved 9 White Electronic Designs Corporation * (602) 437-1520 * www.whiteedc.com White Electronic Designs NOTE W78M64VP-XSBX the Embedded Erase algorithm has begun; all further commands (except Erase Suspend) are ignored until the erase operation is complete. If DQ3 is "0," the device accepts additional sector erase commands. To ensure the command has been accepted, the system software should check the status of DQ3 prior to and following each sub-sequent sector erase command. If DQ3 is high on the second status check, the last command might not have been accepted. Table 18 shows the status of DQ3 relative to the other status bits. When verifying the status of a write operation (embedded program/erase) of a memory sector, DQ6 and DQ2 toggle between high and low states in a series of consecutive and contiguous status read cycles. In order for this toggling behavior to be properly observed, the consecutive status bit reads must not be interleaved with read accesses to other memory sectors. If it is not possible to temporarily prevent reads to other memory sectors, then it is recommended to use the DQ7 status bit as the alternative method of determining the active or inactive status of the write operation. DQ1: WRITE TO BUFFER ABORT DQ1 indicates whether a Write to Buffer operation was aborted. Under these conditions DQ1 produces a "1". The system must issue the "Write to Buffer Abort Reset" command sequence to return the device to reading array data. See Write Buffer Programming for more details. DQ5: EXCEEDED TIMING LIMITS DQ5 indicates whether the program or erase time has exceeded a specified internal pulse count limit. Under these conditions DQ5 produces a "1," indicating that the program or erase cycle was not successfully completed. The device does not output a 1 on DQ5 if the system tries to program a 1 to a location that was previously programmed to 0. Only an erase operation can change a 0 back to a 1. Under this condition, the device ignores the bit that was incorrectly instructed to be programmed from a 0 to a 1, while any other bits that were correctly requested to be changed from 1 to 0 are programmed. Attempting to program a 0 to a 1 is masked during the programming operation. Under valid DQ5 conditions, the system must write the reset command to return to the read mode (or to the erase-suspend-read mode if a sector was previously in the erase-suspendprogram mode). WRITING COMMANDS/COMMAND SEQUENCES During a write operation, the system must drive CE# and WE# to VIL and OE# to VIH when providing an address, command, and data. Addresses are latched on the last falling edge of WE# or CE#, while data is latched on the 1st rising edge of WE# or CE#. An erase operation can erase one sector, multiple sectors, or the entire device. Table 1 indicate the address space that each sector occupies. The device address space is divided into uniform 64KW/128KB sectors. A sector address is the set of address bits required to uniquely select a sector. ICC2 in "DC Characteristics" represents the active current specification for the write mode. "AC Characteristics" contains timing specification tables and timing diagrams for write operations. DQ3: SECTOR ERASE TIMEOUT STATE INDICATOR After writing a sector erase command sequence, the system may read DQ3 to determine whether or not erasure has begun. (The sector erase timer does not apply to the chip erase command.) If additional sectors are selected for erasure, the entire time-out also applies after each additional sector erase command. When the time-out period is complete, DQ3 switches from a "0" to a "1." If the time between additional sector erase commands from the system can be assumed to be less than tSEA, then the system need not monitor DQ3. See Sector Erase for more details. RY/BY# The RY/BY# is a dedicated, open-drain output pin that indicates whether an Embedded Algorithm is in progress or complete. The RY/BY# status is valid after the rising edge of the final WE# pulse in the command sequence. Since RY/ BY# is an open-drain output, several RY/BY# pins can be tied together in parallel with a pull-up resistor to VCC. This feature allows the host system to detect when data is ready to be read by simply monitoring the RY/BY# pin, which is a dedicated output and controlled by CE# (not OE#). After the sector erase command is written, the system should read the status of DQ7 (Data# Polling) or DQ6 (Toggle Bit I) to ensure that the device has accepted the command sequence, and then read DQ3. If DQ3 is "1," White Electronic Designs Corp. reserves the right to change products or specifications without notice. November 2009 Rev. 10 (c) 2010 White Electronic Designs Corp. All rights reserved 10 White Electronic Designs Corporation * (602) 437-1520 * www.whiteedc.com White Electronic Designs HARDWARE RESET W78M64VP-XSBX If the program command sequence is written to a sector that is in the Erase Suspend mode, writing the reset command returns that sector to the erasesuspend-read mode. The RESET# input provides a hardware method of resetting the device to reading array data. When RESET# is driven low for at least a period of tRP (RESET# Pulse Width), the device immediately terminates any operation in progress, tristates all outputs, resets the configuration register, and ignores all read/write commands for the duration of the RESET# pulse. The device also resets the internal state machine to reading array data. The reset command may be written during an Autoselect command sequence. If a sector has entered the Autoselect mode while in the Erase Suspend mode, writing the reset command returns that sector to the erase-suspendread mode. To ensure data integrity Program/Erase operations that were interrupted should be reinitiated once the device is ready to accept another command sequence. If DQ1 goes high during a Write Buffer Programming operation, the system must write the "Write to Buffer abort Reset" command sequence to RESET the device to reading array data. The standard RESET command does not work during this condition. When RESET# is held at VSS, the device draws VCC reset current (ICC5). If RESET# is held at VIL, but not at VSS, the standby current is greater. RESET# may be tied to the system reset circuitry which enables the system to read the boot-up firmware from the Flash memory upon a system reset. To exit the unlock bypass mode, the system must issue a two-cycle unlock bypass reset command sequence [see Command Definitions for details]. SOFTWARE RESET ADVANCED SECTOR PROTECTION/ UNPROTECTION Software reset is part of the command set (see Table 12.1 on page 69) that also returns the device to arrayread mode and must be used for the following conditions: The Advanced Sector Protection/Unprotection feature disables or enables programming or erase operations in any or all sectors and can be implemented through software and/ or hardware methods, which are independent of each other. This section describes the various methods of protecting data stored in the memory array. An overview of these methods in shown in FIG: 8. 1. to exit Autoselect mode 2. when DQ5 goes high during write status operation that indicates program or erase cycle was not successfully completed 3. exit sector lock/unlock operation. 4. to return to erase-suspend-read mode if the device was previously in Erase Suspend mode. LOCK REGISTER As shipped from the factory, all devices default to the persistent mode when power is applied, and all sectors are unprotected. The device programmer or host system must then choose which sector protection method to use. Programming (setting to "0") any one of the following two one-time programmable, non-volatile bits locks the part permanently in that mode: 5. after any aborted operations The following are additional points to consider when using the reset command: This command resets the sectors to the read and address bits are ignored. Reset commands are ignored during program and erase operations. Lock Register Persistent Protection Mode Lock Bit (DQ1) The reset command may be written between the cycles in a program command sequence before programming begins (prior to the third cycle). This resets the sector to which the system was writing to the read mode. Lock Register Password Protection Mode Lock Bit (DQ2) White Electronic Designs Corp. reserves the right to change products or specifications without notice. November 2009 Rev. 10 (c) 2010 White Electronic Designs Corp. All rights reserved 11 White Electronic Designs Corporation * (602) 437-1520 * www.whiteedc.com White Electronic Designs NOTES W78M64VP-XSBX 6. The specific sector address (A22-A16) are written at the same time as the program command. 1. If the password mode is chosen, the password must be programmed before setting the corresponding lock register bit. 7. If the PPB Lock Bit is set, the PPB Program or erase command does not execute and times-out without programming or erasing the PPB. 2. After the Lock Register Bits Command Set Entry command sequence is written, reads and writes for Sector 0 are disabled, while reads from other sectors are allowed until exiting this mode. 8. There are no means for individually erasing a specific PPB and no specific sector address is required for this operation. 3. If both lock bits are selected to be programmed (to zeros) at the same time, the operation aborts. 9. Exit command must be issued after the execution which resets the device to read mode and reenables reads and writes for Sector 0. 4. Once the Password Mode Lock Bit is programmed, the Persistent Mode Lock Bit is permanently disabled, and no changes to the protection scheme are allowed. Similarly, if the Persistent Mode Lock Bit is programmed, the Password Mode is permanently disabled. 10. The programming state of the PPB for a given sector can be verified by writing a PPB Status Read Command to the device as described by the flow chart shown in FIG: 9. After selecting a sector protection method, each sector can operate in any of the following three states: DYNAMIC PROTECTION BITS 1. Constantly locked. The selected sectors are protected and can not be reprogrammed unless PPB lock bit is cleared via a password, hardware reset, or power cycle. Dynamic Protection Bits are volatile and unique for each sector and can be individually modified. DYBs only control the protection scheme for unprotected sectors that have their PPBs cleared (erased to "1"). By issuing the DYB Set or Clear command sequences, the DYBs are set (programmed to "0") or cleared (erased to "1"), thus placing each sector in the protected or unprotected state respectively. This feature allows software to easily protect sectors against inadvertent changes yet does not prevent the easy removal of protection when changes are needed. 2. Dynamically locked. The selected sectors are protected and can be altered via software commands. 3. Unlocked. The sectors are unprotected and can be erased and/or programmed. PERSISTENT PROTECTION BITS The Persistent Protection Bits are unique and nonvolatile for each sector and have the same endurances as the Flash memory. Preprogramming and verification prior to erasure are handled by the device, and therefore do not require system monitoring. NOTES 1. The DYBs can be set (programmed to "0") or cleared (erased to "1") as often as needed. When the parts are first shipped, the PPBs are cleared (erased to "1") and upon power up or reset, the DYBs can be set or cleared depending upon the ordering option chosen. NOTES 1. Each PPB is individually programmed and all are erased in parallel. 2. If the option to clear the DYBs after power up is chosen, (erased to "1"), then the sectors may be modified depending upon the PPB state of that sector (see Table 20). 2. While programming PPB for a sector, array data can be read from any other sector, except Sector 0 (used for Data# Polling) and the sector in which sector PPB is being programmed. 3. The sectors would be in the protected state If the option to set the DYBs after power up is chosen (programmed to "0"). 3. Entry command disables reads and writes for the sector selected. 4. It is possible to have sectors that are persistently locked with sectors that are left in the dynamic state. 4. Reads within that sector return the PPB status for that sector. 5. The DYB Set or Clear commands for the dynamic sectors signify protected or unprotected state of the sectors respectively. However, if there is a need to 5. All Reads must be performed using the read mode. White Electronic Designs Corp. reserves the right to change products or specifications without notice. November 2009 Rev. 10 (c) 2010 White Electronic Designs Corp. All rights reserved 12 White Electronic Designs Corporation * (602) 437-1520 * www.whiteedc.com White Electronic Designs W78M64VP-XSBX programmed as a "0" results in a time-out with the cell as a "0". change the status of the persistently locked sectors, a few more steps are required. First, the PPB Lock Bit must be cleared by either putting the device through a power-cycle, or hardware reset. The PPBs can then be changed to reflect the desired settings. Setting the PPB Lock Bit once again locks the PPBs, and the device operates normally again. 3. The password is all "1"s when shipped from the factory. 4. All 64-bit password combinations are valid as a password. 5. There is no means to verify what the password is after it is set. 6. To achieve the best protection, it is recommended to execute the PPB Lock Bit Set command early in the boot code and protect the boot code by holding WP#/ ACC = VIL. Note that the PPB and DYB bits have the same function when WP#/ACC = VHH as they do when ACC =VIH. 6. The Password Mode Lock Bit, once set, prevents reading the 64-bit password on the data bus and further password programming. 7. The Password Mode Lock Bit is not erasable. 8. The lower two address bits (A1-A0) are valid during the Password Read, Password Program, and Password Unlock. PERSISTENT PROTECTION BIT LOCK BIT 9. The exact password must be entered in order for the unlocking function to occur. The Persistent Protection Bit Lock Bit is a global volatile bit for all sectors. When set (programmed to "0"), it locks all PPBs and when cleared (programmed to "1"), allows the PPBs to be changed. There is only one PPB Lock Bit per device. 10. The Password Unlock command cannot be issued any faster than 1 s at a time to prevent a hacker from running through all the 64-bit combinations in an attempt to correctly match a password. NOTES 11. Approximately 1 s is required for unlocking the device after the valid 64-bit password is given to the device. 1. No software command sequence unlocks this bit unless the device is in the password protection mode; only a hardware reset or a power-up clears this bit. 12. Password verification is only allowed during the password programming operation. 2. The PPB Lock Bit must be set (programmed to "0") only after all PPBs are conFIG:d to the desired settings. 13. All further commands to the password region are disabled and all operations are ignored. PASSWORD PROTECTION METHOD 14. If the password is lost after setting the Password Mode Lock Bit, there is no way to clear the PPB Lock Bit. The Password Protection Method allows an even higher level of security than the Persistent Sector Protection Mode by requiring a 64-bit password for unlocking the device PPB Lock Bit. In addition to this password requirement, after power up and reset, the PPB Lock Bit is set "0" to maintain the password mode of operation. Successful execution of the Password Unlock command by entering the entire password clears the PPB Lock Bit, allowing for sector PPBs modifications. 15. Entry command sequence must be issued prior to any of any operation and it disables reads and writes for Sector 0. Reads and writes for other sectors excluding Sector 0 are allowed. 16. If the user attempts to program or erase a protected sector, the device ignores the command and returns to read mode. 17. A program or erase command to a protected sector enables status polling and returns to read mode without having modified the contents of the protected sector. NOTES 1. There is no special addressing order required for programming the password. Once the Password is written and verified, the Password Mode Locking Bit must be set in order to prevent access. 18. The programming of the DYB, PPB, and PPB Lock for a given sector can be verified by writing individual status read commands DYB Status, PPB Status, and PPB Lock Status to the device. 2. The Password Program Command is only capable of programming "0"s. Programming a "1" after a cell is White Electronic Designs Corp. reserves the right to change products or specifications without notice. November 2009 Rev. 10 (c) 2010 White Electronic Designs Corp. All rights reserved 13 White Electronic Designs Corporation * (602) 437-1520 * www.whiteedc.com White Electronic Designs HARDWARE DATA PROTECTION METHODS W78M64VP-XSBX WRITE PULSE "GLITCH PROTECTION" Noise pulses of less than 5 ns (typical) on OE#, CE# or WE# do not initiate a write cycle. The device offers two main types of data protection at the sector level via hardware control: POWER-UP WRITE INHIBIT When WP#/ACC is at VIL, the either the highest or lowest sector is locked (device specific). If WE# = CE# = RESET# = VIL and OE# = VIH during power up, the device does not accept commands on the rising edge of WE#. The internal state machine is automatically reset to the read mode on power-up. There are additional methods by which intended or accidental erasure of any sectors can be prevented via hardware means. The following subsections describes these methods: POWER CONSERVATION MODES WP#/ACC METHOD STANDBY MODE The Write Protect feature provides a hardware method of protecting one outermost sector. This function is provided by the WP#/ACC pin and overrides the previously discussed Sector Protection/Unprotection method. When the system is not reading or writing to the device, it can place the device in the standby mode. In this mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state, independent of the OE# input. The device enters the CMOS standby mode when the CE# and RESET# inputs are both held at VCC 0.3 V. The device requires standard access time (tCE) for read access, before it is ready to read data. If the device is deselected during erasure or programming, the device draws active current until the operation is completed. ICC4 in "DC Characteristics" represents the standby current specification If the system asserts VIL on the WP#/ACC pin, the device disables program and erase functions in the highest or lowest sector independently of whether the sector was protected or unprotected using the method described in Advanced Sector Protection/Unprotection. If the system asserts VIH on the WP#/ACC pin, the device reverts to whether the boot sectors were last set to be protected or unprotected. That is, sector protection or unprotection for these sectors depends on whether they were last protected or unprotected. AUTOMATIC SLEEP MODE The automatic sleep mode minimizes Flash device energy consumption. The device automatically enables this mode when addresses remain stable for tACC + 30 ns. The automatic sleep mode is independent of the CE#, WE#, and OE# control signals. Standard address access timings provide new data when addresses are changed. While in sleep mode, output data is latched and always available to the system. ICC6 represents the automatic sleep mode current specification. The WP#/ACC pin must be held stable during a command sequence execution. WP# has an internal pull-up; when unconnected, WP# is set at VIH. NOTE If WP#/ACC is at VIL when the device is in the standby mode, the maximum input load current is increased. LOW VCC WRITE INHIBIT When VCC is less than VLKO, the device does not accept any write cycles. This protects data during VCC power-up and power-down. The command register and all internal program/erase circuits are disabled, and the device resets to reading array data. Subsequent writes are ignored until VCC is greater than VLKO. The system must provide the proper signals to the control inputs to prevent unintentional writes when VCC is greater than VLKO. HARDWARE RESET# INPUT OPERATION The RESET# input provides a hardware method of resetting the device to reading array data. When RESET# is driven low for at least a period of tRP, the device immediately terminates any operation in progress, tristates all outputs, and ignores all read/write commands for the duration of the RESET# pulse. The device also resets the internal state White Electronic Designs Corp. reserves the right to change products or specifications without notice. November 2009 Rev. 10 (c) 2010 White Electronic Designs Corp. All rights reserved 14 White Electronic Designs Corporation * (602) 437-1520 * www.whiteedc.com White Electronic Designs W78M64VP-XSBX FACTORY LOCKED SECURED SILICON SECTOR machine to reading array data. The operation that was interrupted should be reinitiated once the device is ready to accept another command sequence to ensure data integrity. The Factory Locked Secured Silicon Sector is always protected when shipped from the factory and has the Secured Silicon Sector Indicator Bit (DQ7) permanently set to a "1". This prevents cloning of a factory locked part and ensures the security of the ESN and customer code once the product is shipped to the field. When RESET# is held at VSS 0.3 V, the device draws ICC reset current (ICC5). If RESET# is held at VIL but not within VSS 0.3 V, the standby current is greater. RESET# may be tied to the system reset circuitry and thus, a system reset would also reset the Flash memory, enabling the system to read the boot-up firmware from the Flash memory. These devices are available pre-programmed with one of the following: A random, 8 Word secure ESN only within the Secured Silicon Sector (at addresses 000000H 000007H) OUTPUT DISABLE (OE#) When the OE# input is at VIH, output from the device is disabled. The outputs are placed in the high impedance state. (With the exception of RY/BY#.) Both a random, secure ESN and customer code through the Spansion programming service. SECURED SILICON SECTOR FLASH MEMORY REGION CUSTOMER LOCKABLE SECURED SILICON SECTOR Secured Silicon Sector Flash Memory Region The Secured Silicon Sector provides an extra Flash memory region that enables permanent part identification through an Electronic Serial Number (ESN). The Secured Silicon Sector is 128 words in length and all Secured Silicon reads outside of the 128-word address range returns invalid data. The Secured Silicon Sector Indicator Bit, DQ7, (at Autoselect address 03h) is used to indicate whether or not the Secured Silicon Sector is locked when shipped from the factory. The Customer Lockable Secured Silicon Sector is always shipped unprotected (DQ7 set to "0"), allowing customers to utilize that sector in any manner they choose. If the security feature is not required, the Secured Silicon Sector can be treated as an additional Flash memory space. Please note the following: Once the Secured Silicon Sector area is protected, the Secured Silicon Sector Indicator Bit is permanently set to "0." Please note the following general conditions: The Secured Silicon Sector can be read any number of times, but can be programmed and locked only once. The Secured Silicon Sector lock must be used with caution as once locked, there is no procedure available for unlocking the Secured Silicon Sector area and none of the bits in the Secured Silicon Sector memory space can be modified in any way. On power-up, or following a hardware reset, the device reverts to sending commands to the normal address space. Reads outside of sector SA0 return memory array data. Sector SA0 is remapped from memory array to Secured Silicon Sector array. The accelerated programming (ACC) and unlock bypass functions are not available when the Secured Silicon Sector is enabled. Once the Secured Silicon Sector Entry Command is issued, the Secured Silicon Sector Exit command must be issued to exit Secured Silicon Sector Mode. Once the Secured Silicon Sector is locked and verified, the system must write the Exit Secured Silicon Sector Region command sequence which return the device to the memory array at sector 0. The Secured Silicon Sector is not accessible when the device is executing an Embedded Program or Embedded Erase algorithm. The ACC function and unlock bypass modes are not available when the Secured Silicon Sector is enabled. White Electronic Designs Corp. reserves the right to change products or specifications without notice. November 2009 Rev. 10 (c) 2010 White Electronic Designs Corp. All rights reserved 15 White Electronic Designs Corporation * (602) 437-1520 * www.whiteedc.com White Electronic Designs W78M64VP-XSBX SECURED SILICON SECTOR ENTRY/ EXIT COMMAND SEQUENCES The system can access the Secured Silicon Sector region by issuing the three-cycle Enter Secured Silicon Sector command sequence. The device continues to access the Secured Silicon Sector region until the system issues the four-cycle Exit Secured Silicon Sector command sequence. See Command Definitions [Secured Silicon Sector Command Table, Appendix Table 39 (Pg 30) for address and data requirements for both command sequences. The Secured Silicon Sector Entry Command allows the following commands to be executed Read customer and factory Secured Silicon areas Program the customer Secured Silicon Sector After the system has written the Enter Secured Silicon Sector command sequence, it may read the Secured Silicon Sector by using the addresses normally occupied by sector SA0 within the memory array. This mode of operation continues until the system issues the Exit Secured Silicon Sector command sequence, or until power is removed from the device. White Electronic Designs Corp. reserves the right to change products or specifications without notice. November 2009 Rev. 10 (c) 2010 White Electronic Designs Corp. All rights reserved 16 White Electronic Designs Corporation * (602) 437-1520 * www.whiteedc.com White Electronic Designs W78M64VP-XSBX TABLE 1 SECTOR & MEMORY ADDRESS MAP Uniform Sector Size Sector Count Sector Count Sector Range Address Range (16-bit) Notes SA00 0000000h - 000FFFFh Sector Starting Address 07F0000 - 7FFFFF Sector Ending Address 128 : SA127 TABLE 2 DEVICE OPERATIONS Operation CE# OE# WE# RESET# Addresses (Note 1) WP3/ACC DQ0 - DQ7 DQ8 - DQ15 Read L L H H X AIN DOUT DOUT Write (Program/Erase) L H L H (Note 2) AIN (Note 3) (Note 3) Accelerated Program L H L H VHH AIN (Note 3) (Note 3) Standby VCC 0.3V X X VCC 0.3V H X High-Z High-Z Output Disable L H H H X X High-Z High-Z Reset X X X L X X High-Z High-Z Legend L = Logic Low = VIL, H = Logic High = VIH, VHH = 11.5-12.5V, X = Don't Care, AIN = Address In, DIN = Data In, DOUT = Data Out Notes 1. Addresses are AMax:A0 in word mode; AMax. 2. If WP# = VIL, on the outermost sector remians protected. If WP# = VIH, the outermost secotr is unprotected. WP# has an internal pull-up; when uconnected, WP# is a VIH. All sectors are unprotected wen shipped from the factory ( The Secured Silicon Sector can be factory protected depending on version ordered.) 3. DIN or DOUT as required by command sequence, data polling, or sector protect algorithm. TABLE 3 AUTOSELECT CODES, (HIGH VOLTAGE METHOD) Description Amax A14 to to A16 A10 OE# WE# L L H X X VID X L Sector Group Protection Verification L L H SA X VID X Secured Silicon Sector Indicator Bit (DQ7), WP# protects highest address sector L L H X X VID L L H X X VID Device ID Cycle 1 Cycle 2 Cycle 3 Secured Silicon Sector Indicator Bit (DQ7), WP# protects lowest address sector A9 A8 to A5 to A3 to A7 A4 A2 CE# A1 A0 DQ8 to DQ15 DQ7 to DQ0 L H H L H H H L H 22 22 22 7Eh 21h 01h L L H L X 01h (unprotected), 00h (unprotected) X L L H H X 99h (factory locked), 19h (not factory locked) X L L H H X 89h (factory locked), 09h (not facotry locked) Legend L = Logic Low = VIL, H = Logic High = VIH, SA = Sector Address, X = Don't care. VID = 11.5V to 12.5V White Electronic Designs Corp. reserves the right to change products or specifications without notice. November 2009 Rev. 10 (c) 2010 White Electronic Designs Corp. All rights reserved 17 White Electronic Designs Corporation * (602) 437-1520 * www.whiteedc.com White Electronic Designs W78M64VP-XSBX TABLE 4 AUTOSELECT ADDRESSES IN SYSTEM Uniform Sector Size Manufacturer ID Device ID, Word 1 Device ID, Word 2 Device ID, Word 3 Sector Count (Base) + 00h (Base) + 01h (Base) + 0Eh (Base) + 0Fh Secure Device Verify (Base) + 03h Sector Protect Verify (SA) + 02h Read Data (word mode) xx02h 227Eh 2221h 2201h XX19h = Note Factory Locked. XX99h = Factory locked XX09h = Note Factory Locked. XX89h = Factory locked xx01h = Locked. XX00h = Unlocked TABLE 5 AUTOSELECT ENTRY IN SYSTEM Cycle Unlock Cycle 1 Unlock Cycle 2 Auto select Command Operation Word Address Base + 555h Base + 2AAh Base + 555h Write Data 0x00AAh 0x0055h 0x0090h TABLE 6 AUTOSELECT EXIT Cycle Unlock Cycle 1 Operation Write Word Address Base + XXXh Data 0x00F0h Note 1. Any offset within the device works. 2. base = base address. TABLE 7 SINGLE WORD PROGRAM (LLD Function = lld_ProgramCmd) Cycle Unlock Cycle 1 Unlock Cycle 2 Program Setup Program Operation Word Address Base + 555h Base + 2AAh Base + 555h Word Address Write Data 00AAh 0055h 00A0h Data White Electronic Designs Corp. reserves the right to change products or specifications without notice. November 2009 Rev. 10 (c) 2010 White Electronic Designs Corp. All rights reserved 18 White Electronic Designs Corporation * (602) 437-1520 * www.whiteedc.com White Electronic Designs W78M64VP-XSBX TABLE 8 WRITE BUFFER PROGRAM (LLD Functions Used = lld_WriteToBufferCmd, lld_ProgramBufferToFlashCmd) Cycle 1 2 3 4 5 to 36 Last Description Unlock Unlock Write Buffer Load Command Write Word Count Operation Word Address Base + 555h Base + 2AAh Sector Address Sector Address Write Number of words (N) loaded into the write buffer can be from 1 to 32 words. Load Buffer Word N Program Address, Word N Write Write Buffer to Flash Sector Address Data 00AAh 0055h 0025h Word Count (N-1)h Word N 0029h Notes 1. Base = Base Address. 2. Last = Last cycle of write buffer program operation; depending on number of words written, the total number of cycles may be from 6 to 37. 3. For maximum efficiency, it is recommended that the write buffer be loaded with the highest number of words (N words) possible. TABLE 9 SECTOR ERASE (LLD Function = lld_SectorEraseCmd) Cycle 1 2 3 4 5 6 Description Operation Word Address Unlock Base + 555h Unlock Base + 2AAh Setup Command Base + 555h Write Unlock Base + 555h Unlock Base + 2AAh Sector Erase Command Sector Address Unlimited additional sectors may be selected for erase; command(s) must be written within 50s Data 00AAh 0055h 0080h 00AAh 0055h 0030h Notes 1. Base = Base Address. 2. Last = Last cycle of write buffer program operation; depending on number of words written, the total number of cycles may be from 6 to 37. 3. For maximum efficiency, it is recommended that the write buffer be loaded with the highest number of words (N words) possible. TABLE 10 SECTOR ERASE (LLD Function = lld_SectorEraseCmd) Cycle 1 2 3 4 5 6 Description Unlock Unlock Setup Command Unlock Unlock Chip Erase Command Operation Word Address Base + 555h Base + 2AAh Base + 555h Base + 555h Base + 2AAh Base + 555h Write Data 00AAh 0055h 0080h 00AAh 0055h 0010h White Electronic Designs Corp. reserves the right to change products or specifications without notice. November 2009 Rev. 10 (c) 2010 White Electronic Designs Corp. All rights reserved 19 White Electronic Designs Corporation * (602) 437-1520 * www.whiteedc.com White Electronic Designs W78M64VP-XSBX TABLE 11 ERASE SUSPEND (LLD Function = lld_EraseSuspendCmd) Cycle 1 Operation Write Word Address Base + XXXh Data 00B0h TABLE 12 ERASE RESUME (LLD Function = lld_EraseSuspendCmd) Cycle 1 Operation Write Word Address Sector Address Data 0030h TABLE 13 PROGRAM SUSPEND (LLD Function = lld_ProgramSuspendCmd) Cycle 1 Operation Write Word Address Base + XXXh Data 00B0h TABLE 14 PROGRAM RESUME (LLD Function = lld_ProgramSuspendCmd) Cycle 1 Operation Write Word Address Base + XXXh Data 0030h TABLE 15 UNLOCK BYPASS ENTRY (LLD Function = lld_UnlockBypassEntryCmd) Cycle 1 2 3 Description Unlock Unlock Entry Command Word Address Base + 555h Base + 2AAh Base + 555h Data 00AAh 0055h 0020h TABLE 16 UNLOCK BYPASS PROGRAM (LLD Function = lld_UnlockBypassProgramCmd) Cycle 1 2 Description Program Setup Command Program Command Word Address Base + xxxh Program Address Data 00AAh 0055h TABLE 17 UNLOCK BYPASS PROGRAM (LLD Function = lld_UnlockBypassProgramCmd) Cycle 1 2 Description Reset Cycle 1 Reset Cycle 2 Word Address Base + xxxh Base + xxxh Data 0090h 0000h White Electronic Designs Corp. reserves the right to change products or specifications without notice. November 2009 Rev. 10 (c) 2010 White Electronic Designs Corp. All rights reserved 20 White Electronic Designs Corporation * (602) 437-1520 * www.whiteedc.com White Electronic Designs W78M64VP-XSBX TABLE 18 WRITE OPERATION STATUS Status Standard Mode Program Suspend Mode Erase Suspend Mode Program Suspend Read Erase-Suspend Read Embedded Program Algorithm Embedded Erase Algorithm Program-Suspended Sector Non-Suspend Sector Erase-Suspended Sector Non-Erase Suspended Sector DQ7 (Note 2) DQ6 DQ5 (Note 1) DQ3 DQ2 (Note 2) DQ1 RY/BY# DQ7# Toggle 0 N/A No toggle 0 0 0 Toggle 0 1 Toggle N/A 0 1 Invalid (not allowed) 1 Data 1 No toggle 0 N/A Toggle N/A Data 1 1 Erase-Suspend-Program (Embedded Program) DQ7# Toggle 0 N/A N/A N/A 0 Busy (Note 3) DQ7# Toggle 0 N/A N/A 0 0 Abort (Note 4) DQ7# Toggle 0 N/A N/A 1 0 Write-to-Buffer Notes 1. DQ5 switches to 1 when an Embedded Program, Embedded Erase, or Write-to-Buffer operation has exceeded the maximum timing limits. Refer toDQ5: Exceeded Timing Limits on page 39 for more information. 2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details. 3. The Data# Polling algorithm should be used to monitor the last loaded write-buffer address location. 4. DQ1 switches to 1 when the device has aborted the write-to-buffer operation TABLE 19 SOFTWARE FUNCTIONS RESET (LLD Function = lld_ResetCmd) Cycle Reset Command Operation Write Word Address Base + xxxh Data 00F0h TABLE 20 LOCK REGISTER DQ15-3 Don't Care DQ2 Password Protection Mode Lock Bit DQ1 Persistent Protection Mode Lock Bit DQ0 Secured Silicon Sector Protection Bit White Electronic Designs Corp. reserves the right to change products or specifications without notice. November 2009 Rev. 10 (c) 2010 White Electronic Designs Corp. All rights reserved 21 White Electronic Designs Corporation * (602) 437-1520 * www.whiteedc.com White Electronic Designs W78M64VP-XSBX TABLE 21 SECTOR PROTECTION SCHEMES: DYB, PPB AND PPB LOCK BIT COMBINATIONS Uniques Device PPB Lock Bit 0 = locked 1 = unlock Any Sector 0 Any Sector 0 Any Sector 0 Any Sector 0 Any Sector 1 Any Sector 1 Any Sector 1 Any Sector 1 Sector PPB 0 = locked 1 = unlock 0 0 1 1 0 0 1 1 Sector DYB 0 = locked 1 = unlock x x 1 0 x x 0 1 Sector Protection Status Protected through PPB Protected through PPB Unportected Protected through PPB Protected through PPB Protected through PPB Protected through PPB Unportected Table 21 contains all possible combinations of the DYB, PPB, and PPB Lock Bit relating to the status of the sector. In summary, if the PPB Lock Bit is locked (set to "0"), no changes to the PPBs are allowed. The PPB Lock Bit can only be unlocked (reset to "1") through a hardware reset or power cycle. TABLE 22 LOCK REGISTER Secured Silicon Sector Address Range 000000h-000007h 000008h-000007Fh Customer Lockable ESN Factory Locked ExpressFlash Factory Locked Determined by customer ESN Unavailable ESN or determinded by customer Determinined by customer TABLE 23 SECURED SILICON SECTOR ENTRY (LLD Function = lld_SecSiSectorEntryCmd) Cycle Unlock Cycle 1 Unlock Cycle 2 Entry Cycle Operation Word Address Base + 555h Base + 2AAh Base + 555h Write Data 00AAh 0055h 0088h Note: Base = Base Address. TABLE 24 SECURED SILICON SECTOR PROGRAM (LLD Function = lld_ProgramCmd) Cycle Unlock Cycle 1 Unlock Cycle 2 Program Setup Program Operation Word Address Base + 555h Base + 2AAh Base + 555h Word Address Write Data 00AAh 0055h 0088h Data Word Note: Base = Base Address. White Electronic Designs Corp. reserves the right to change products or specifications without notice. November 2009 Rev. 10 (c) 2010 White Electronic Designs Corp. All rights reserved 22 White Electronic Designs Corporation * (602) 437-1520 * www.whiteedc.com White Electronic Designs W78M64VP-XSBX TABLE 25 SECURED SILICON SECTOR EXIT (LLD Function = lld_SecSiSectorExitCmd) Cycle Unlock Cycle 1 Unlock Cycle 2 Exit Cycle 3 Exit Cycle 4 Operation Word Address Base + 555h Base + 2AAh Base + 555h Base + 000h Write Data 00AAh 0055h 0088h 0000h Note: Base = Base Address. TABLE 26 ABSOLUTE MAXIMUM RATINGS Description Storage Temperature Ambient Temperature with Power Applied Rating -55C to +125C All Inputs and I/Os except as noted below (Note 1) VCC (Note 1) VIO A9 and ACC (Note 2) Voltage with Respect to Ground -0.5V to VCC + 0.5V -0.5V to +4.0 V -0.5V to +4.0 V 0.5V to +12.5V Notes 1. Minimum DC voltage on input or I/Os is -0.5 V. During voltage transitions, inputs or I/Os may undershoot VSS to -2.0 V for periods of up to 20 ns. See FIG: 11. Maximum DC voltage on input or I/Os is VCC + 0.5 V. During voltage transitions inputs or I/Os may overshoot to VCC + 2.0 V for periods up to 20 ns. See FIG: 12. 2. Minimum DC input voltage on pins A9 and ACC is -0.5V. During voltage transitions, A9 and ACC may overshoot VSS to -2.0 V for periods of up to 20 ns. See FIG: 11. Maximum DC voltage on pins A9 and ACC is +12.5 V, which may overshoot to 14.0 V for periods up to 20 ns. 3. No more than one output may be shorted to ground at a time. Duration of the short circuit should not be greater than one second. 4. Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this data sheet is not implied. Exposure of the device to absolute maximum rating conditions for extended periods may affect device reliability. TABLE 27 CAPACITANCE TABLE 28 RECOMMENDED OPERATING CONDITIONS TA = +25C, f = 1.0MHz Parameter WE# capacitance CS# capacitance Data I/O capacitance Address input capacitance RY/BY# OE# capacitance Symbol CWE CCS CI/O CAD CRB COE Max 13 25 15 30 40 35 Unit pF pF pF pF pF pF Parameter Supply Voltage I/O Supply Voltage Operating Temp. (Mil.) Operating Temp. (Ind.) Symbol VCC VIO TA TA Min 3.0 3.0 -55 -40 Max 3.6 3.6 +125 +85 Unit V V C C Note: For all AC and DC specifications: VIO = VCC TABLE 29 DATA RETENTION This parameter is guaranteed by design but not tested. Parameter Pattern Data Retention Time Test Conditions 150C 125C Min 10 20 Unit Years Years White Electronic Designs Corp. reserves the right to change products or specifications without notice. November 2009 Rev. 10 (c) 2010 White Electronic Designs Corp. All rights reserved 23 White Electronic Designs Corporation * (602) 437-1520 * www.whiteedc.com White Electronic Designs W78M64VP-XSBX TABLE 30 DC CHARACTERISTICS Parameter Symbol ILI Input Load Current VIN = VSS to VCC VCC = VCC max ILIT ILO ICC1 IIO2 ICC2 ICC3 ICC4 A9 Input Load Current (3) Output Leakage Current VCC active Read Current (1) VIO Non-active Output (3) VCC Intra-Page Read Current (1) VCC Active Erase/Program CUrrent (2, 3) VCC Standby Current ICC5 VCC Reset Current ICC6 Automatic Sleep Mode (3, 4) IACC ACC Accelerated Program Current (3) VCC = VCC max; 12.5V VOUT = VSS to VCC, VCC =VCC max CE# =VIL, OE# = VIH, VCC = VCC max, f = 5MHz CE# =VIL, OE# = VIH CE# =VIL, OE# = VIH, VCC = VCC max, f = 10MHz CE# =VIL, OE# = VIH, VCC = VCC max CE#, RESET# =VCC 0.3V, OE# = VIH, VCC = VCC max VIL = VSS + 0.3V/-0.1V VCC = VCC max; RESET# = VSS 0.3V VCC = VCC max, VIH = VCC 0.3V, WP#/ACC = VIH CE# = VIL, OE# = VIH WP#/ACC pin VCC = VCC max, WP#/ACC = VHH VCC pin VIL VIH VHH VID Input Low Voltage (5) Input High Voltage (5) Voltage for Program Acceleration (3) Voltage for Autoselect and Temporary Sector Unportect (3) Output Low Voltage (5) Output High Voltage (5) Low VCC Lock-Out Voltage (3) VOL VOH VLKO Parameter Description (Notes) Test Conditions Min WP/ACC (3) Others -0.1 0.7 x VIO 11.5 11.5 VCC = 2.7 - 3.6V VCC = 2.7 - 3.6V IOL = 100A IOH = 100A 0.85 x VIO 2.3 Max Unit 20 8 140 4 440 40 40 360 20 A A A mA mA mA mA A 2 mA 20 A 80 320 0.3 x VIO VIO + 0.3 12.5 12.5 mA 0.15 x VIO V V V 2.5 V V V V Notes 1. The ICC current listed is typically less than 2 mA/MHz, with OE# at VIH. 2. ICC active while Embedded Erase or Embedded Program or Write Buffer Programming is in progress. 3. Not 100% tested. 4. Automatic sleep mode enables the lower power mode when addresses remain stable tor tACC + 30 ns. 5. VIO = 1.65-3.6 V 6. VCC = 3 V and VIO = 3V or 1.8V. When VIO is at 1.8V, I/O pins cannot operate at 3V. White Electronic Designs Corp. reserves the right to change products or specifications without notice. November 2009 Rev. 10 (c) 2010 White Electronic Designs Corp. All rights reserved 24 White Electronic Designs Corporation * (602) 437-1520 * www.whiteedc.com White Electronic Designs W78M64VP-XSBX TABLE 31 AC TEST CONDITIONS Parameter Input Pulse Levels Input Rise and Fall Input and Output Reference Level Output Timing Reference Level Typ VIL - 0, VIH = 2.5 5 1.5 1.5 FIG: 4 TEST SETUP Unit V ns V V 3.3 V 2.7 k Device Under Test Notes: VZ is programmable from -2V to +7V. IOL & IOH programmable from 0 to 16 mA. Tester Impedance Z0 = 50 VZ is typically the midpoint of VOH and VOL. IOL & IOH are adjusted to similate a typical resistive load circuit. ATE tester Includes jig capacitance. CL 6.2 k TABLE 32 TEST SPECIFICATIONS Test Condition All Speeds Output Load Output Load Capacitance, CL (including jig capacitance) Input Rise and Fall Times Input Pulse Levels Input timing measurement reference levels (See Note) Output timing measurement reference levels Unit 1 TTL gate 30 5 0.0-VIO 0.5VIO 0.5VIO pF ns V V V Note: If VIO < VCC, the reference level is 0.5 VIO. TABLE 33 AC CHARACTERISTICS - READ-ONLY OPERATIONS VCC = 3.3V 0.3V, -55C TA +125C Parameter Symbol Read Cycle Time Address Access Time Chip Select Access Time Page Access Time Output Enable to Output Valid (1) Chip Select High to Output High Z Output Enable High to Output High Z Output Hold from Addresses, CS# or OE# Change, Whichever occurs first Read Output Enable Hold Time Toggle and Data# Polling Chip Enable Hold Time tAVAV tAVQV tELQV -110 Min Max 110 110 110 25 25 20 20 -120 Min Max 120 120 120 25 25 20 20 Unit tGLQV tEHQZ tGHQZ tRC tACC tCE tPACC tOE tDF tDF tAXQX tOH 0 0 ns tOEH 0 0 ns 10 10 ns 35 35 ns tCEH ns ns ns ns ns ns ns Note: 1. tOE for data polling Zs 45ns when VIO = 1.65 to 2.7V and 35ns when VIO = 2.7 to 3V. White Electronic Designs Corp. reserves the right to change products or specifications without notice. November 2009 Rev. 10 (c) 2010 White Electronic Designs Corp. All rights reserved 25 White Electronic Designs Corporation * (602) 437-1520 * www.whiteedc.com White Electronic Designs W78M64VP-XSBX TABLE 34 AC CHARACTERISTICS - HARDWARE RESET (1) Parameter RESET# Pin Low (During Embedded Algorithms) to Read Mode RESET# Pin Low (NOT During Embedded Algorithms) to Read Mode RESET# Pulse Width RESET# High Time Before Read RESET# Low to Standby Mode RY/BY# Recovery Time Symbol Min Max Unit tready 35 s tready tRP tRH tRPD tRB 35 35 200 10 0 s s ns s ns TABLE 35 POWER-UP SEQUENCE TIMINGS Parameter Reset Low Time from rising edge of VCC (or last Reset pulse) to rising edge of RESET# Reset Low Time from rising edge of VIO (or last Reset pulse) to rising edge of RESET# Reset High Time before Read Symbol tVCS tVIOS tRH Min 35 35 200 Max Unit s s s Notes 1. VIO < VCC + 200 mV. 2. VIO and VCC ramp must be synchronized during power up. 3. If RESET# is not stable for tVCS or tVIOS: The device does not permit any read and write operations. A valid read operation returns FFh. A hardware reset is required. 4. VCC maximum power-up current (RST=VIL) is 20 mA. White Electronic Designs Corp. reserves the right to change products or specifications without notice. November 2009 Rev. 10 (c) 2010 White Electronic Designs Corp. All rights reserved 26 White Electronic Designs Corporation * (602) 437-1520 * www.whiteedc.com White Electronic Designs W78M64VP-XSBX TABLE 36 AC CHARACTERISTICS - WRITE/ERASE/PROGRAM OPERATIONS - WE# CONTROLLED VCC = 3.3V 0.3V, -55C TA +125C Parameter Symbol Write Cycle Time Chip Select Setup Time (3) Write Enable Pulse Width Address Setup Time Data Setup Time Data Hold Time Address Hold Time Write Enable Pulse Width High (3) Duration of Byte Programming Operation Sector Erase (2) Read Recovery Time before Write (3) VCC Setup Time (3) Chip Programming Time (4) Address Setup Time to OE# low during toggle bit polling tAVAV tELWL tWLWH tAVWL tDVWH tWHDX tWLAX tWHWL tWHWH1 tWHWH2 tGHWL tVCS tWC tCS tWP tAS tDS tDH tAH tWPH tASO -110 Min Max 110 0 35 0 30 0 45 30 480 5 0 35 200 15 -120 Min Max 120 0 35 0 30 0 45 30 480 5 0 35 200 15 Unit ns ns ns ns ns ns ns ns s sec ns s sec ns Notes: 1. Typical value for tWHWH1 is 6s. 2. Typical value for tWHWH2 is 0.5 sec. 3. Guaranteed by design, but not tested. 4. Typical value is 50 sec. The typical chip program time is considerably less than the maximum chip programming time listed, since most bytes program faster than the maximum program times listed. TABLE 37 AC CHARACTERISTICS - ALTERNATE CS# CONTROLLED ERASE AND PROGRAM OPERATIONS Parameter JEDEC tAVAV tAVWL tELAX tDVEH tEHDX tWHEH tGHEL tWLEL tEHWH tELEH tEHEL tWHWH1 tWHWH1 tWHWH2 Description Std tWS tAS tAH tDS tDH tCH tGHEL tWS tWH tCP tCPH tWHWH1 tWHWH1 tWHWH2 Speed Options Write Cycle Time Address Setup Time Address Hold Time Data Setup Time Data Hold Time CE# Hold Time Read Recovery Time Before Write (OE# High to WE# Low) WE# Setup Time WE# Hold Time CS# Pulse Width CS# Pulse Width High (1) Programming Operation Accelerated Programming Operation Sector Erase Operation Min Min Min Min Min Min Min Min Min Min Min Typ Typ Typ 110 110 0 45 30 0 0 0 0 0 35 30 480 13.5 0.5 Unit 120 120 0 50 30 0 0 0 0 0 35 30 480 13.5 0.5 ns ns ns ns ns ns ns ns ns ns ns s s sec Note: 1. Not tested. White Electronic Designs Corp. reserves the right to change products or specifications without notice. November 2009 Rev. 10 (c) 2010 White Electronic Designs Corp. All rights reserved 27 White Electronic Designs Corporation * (602) 437-1520 * www.whiteedc.com White Electronic Designs W78M64VP-XSBX TABLE 38 ERASE AND PROGRAMMING PERFORMANCE VCC = 3.3V 0.3V, -55C TA +125C Parameter Sector Erase Time Chip Erase Time Total Write Buffer Time (Note 3) Total Accelerated Write Buffer Programming Time (Note 3) Ship Program Time Typ (Note 1) 0.5 64 480 432 123 Max (Note 2) 3.5 256 Unit Comments sec sec s s sec Excludes 00h programming prior to erasure (Note 4) Excludes system level overhead (Note 5) Notes 1. Typical program and erase times assume the following conditions: 25C, 3.6V VCC, 10,000 cycles, checker board pattern. 2. Under corst case conditions of -40C, VCC = 3.0V, 100,000 cycle. 3. Effective write buffer specification is based upon 32-word write buffer operation. 4. In the pre-programming step of the embedded erase algorithm, all bits are programmed to 00H before erasure. 5. System0level overhead is the time required to execute the two-or four-bus-cycle sequence for the program command. See table 38 and 39. White Electronic Designs Corp. reserves the right to change products or specifications without notice. November 2009 Rev. 10 (c) 2010 White Electronic Designs Corp. All rights reserved 28 White Electronic Designs Corporation * (602) 437-1520 * www.whiteedc.com White Electronic Designs W78M64VP-XSBX Command Read (6) AutoSelect (8, 9) Reset (7) Cycles TABLE 39 MEMORY ARRAY COMMAND DEFINITIONS Bus Cycles (Note 1-5) First Second Addr Data 1 RA RD Third Fouth Addr Data Addr Data Addr Fifth Data 1 XXX F0 Manufacturer ID 4 555 AA 2AA 55 555 90 X00 01 Device ID (8) 4 555 AA 2AA 55 555 90 X01 227E Sector Protect Verify (10) 4 555 AA 2AA 55 555 90 [SA]X02 (10) Secure Device Verify (11) 4 555 AA 2AA 55 555 90 X03 (11) 1 55 98 CFI Query (12) Sixth Addr Data Addr Data X0E (8) X0F (8) WBL PD WBL PD 4 555 AA 2AA 55 555 A0 PA PD Write to Buffer 3 555 AA 2AA 55 SA 25 SA WC Program Buffer to Flash (Confirm) 1 SA 29 Write-to-Buffer-Abort Reset 3 555 AA 2AA 55 555 F0 Enter 3 555 AA 2AA 55 555 20 Program (14) 2 XXX A0 PA PD Sector Erase (14) 2 XXX 80 SA 30 Chip Erase (14) 2 XXX 80 XXX 10 Reset (15) 2 XXX 90 XXX 00 Chip Erase 6 555 AA 2AA 55 555 80 555 AA 2AA 55 555 10 Sector Erase 6 555 AA 2AA 55 555 80 555 AA 2AA 55 SA 30 Erase Suspend/Program Suspend (16) 1 XXX B0 Erase Resume/Program Resume (17) 1 XXX 30 Secured Silicon Sector Entry 3 555 AA 2AA 55 555 88 Secured SIlicon Sector Exit (18) 4 555 AA 2AA 55 555 90 XX 00 Unlock Bypass Program Legend X = Don't care RA = Address of the memory to be read. RD = Data read from location RA during read operation. PA = Address of the memory location to be programmed. Addresses latch on the falling edge of the WE# or CE# pulse, whichever happens later. PD = Data to be programmed at location PA. Data latches on the rising edge of the WE# or CE# pulse, whichever happens first. SA = Address of the sector to be verified (in autoselect mode) or erased. Address bits Amax-A16 uniquely select any sector. WBL = Write Buffer Location. The address must be within the same write buffer page as PA. WC = Word Count is the number of write buffer locations to load minus 1. Notes 1. See Table 2 for description of bus operations. 2. All values are in hexadecimal. 3. All bus cycles are write cycles unless otherwise noted. 4. Data bits DQ15-DQ8 are don't cares for unlock and command cycles. 5. Address bits AMAX:A16 are don't cares for unlock and command cycles, unless SA or PA required. (AMAX is the Highest Address pin.). 6. No unlock or command cycles required when reading array data. 7. The Reset command is required to return to reading array data when device is in the autoselect mode, or if DQ5 goes high (while the device is providing status data). 8. See Table 3 for device ID values and definitions. 9. The fourth, fifth, and sixth cycles of the autoselect command sequence are read cycles. 10. The data is 00h for an unprotected sector and 01h for a protected sector. See Autoselect for more information. This is same as PPB Status Read except that the protect and unprotect statuses are inverted here. 11. The data value for DQ7 is "1" for a serialized, protected Secured Silicon Sector region and "0" for an unserialized, unprotected region. See data and definitions. 12. Command is valid when device is ready to read array data or when device is in autoselect mode. 13. Command sequence returns device to reading array after being placed in a Write-toBuffer-Abort state. Full command sequence is required if resetting out of abort while in Unlock Bypass mode. 14. The Unlock-Bypass command is required prior to the Unlock-Bypass- Program command. 15. The Unlock-Bypass-Reset command is required to return to reading array data when the device is in the unlock bypass mode. 16. The system can read and program/program suspend in non-erasing sectors, or enter the autoselect mode, when in the Erase Suspend mode. The Erase Suspend command is valid only during a sector erase operation. 17. The Erase Resume/Program Resume command is valid only during the Erase Suspend/Program Suspend modes. 18. The Exit command returns the device to reading the array. White Electronic Designs Corp. reserves the right to change products or specifications without notice. November 2009 Rev. 10 (c) 2010 White Electronic Designs Corp. All rights reserved 29 White Electronic Designs Corporation * (602) 437-1520 * www.whiteedc.com White Electronic Designs W78M64VP-XSBX Volatile Global Volatile Global Non-Volatile Freeze Password Lock Register Command Cycles TABLE 40 SECTOR PROTECTION COMMAND DEFINITIONS Bus Cycles (Note 1-5) First Second Third Addr Data Addr Data Addr AA 2AA 55 555 XXX DATA 00 Data Fouth Addr Data Command Set Entry 3 555 Program (6) 2 XXX A0 Read (6) 1 00 RD Command Set Exit (7, 8) 2 XXX 90 XXX Command Set Entry 3 555 AA 2AA 55 Password Program (9) 2 XXX A0 PWAx PWDx Password Read (10) 4 00 PWD0 01 PWD 1 02 PWD 2 03 PWD 3 00 25 00 03 00 PWD 0 01 PWD 1 00 29 Password Unlock (10) 7 Command Set Exit (7, 8) 2 XXX 90 XXX 00 PPB Command Set Entry 3 555 AA 2AA 55 PPB Program (11, 12) 2 XXX A0 SA 00 All PPB Erase (13) 2 XXX 80 00 30 PPB Status Read (12) 1 SA RD (0) PPB Command Set Exit (7, 8) 2 XXX 90 XXX 00 PPB Lock Command Set Entry 3 555 AA 2AA 55 PPB Lock Set (12) 2 XXX A0 XXX 00 PPB Lock Command Set Exit (7, 8) 1 XXX RD (0) PPB Lock Command Set Exit (7, 8) 2 XXX 90 XXX 00 DYB Command Set Entry 3 555 AA 2AA 55 DYB Set (11, 12) 2 XXX A0 SA 00 DYB Clear (12) 2 XXX A0 SA 01 DYB Status Read (12) 1 SA RD (0) DYB Command Set Exit (7, 8) 2 XXX 90 XXX 00 Legend X = Don't care RD(0) = Read data. SA = Sector Address. Address bits Amax-A16 uniquely select any sector. Fifth Sixth Addr Data Addr Data 02 PWD 2 03 PWD 3 555 555 555 555 PWD = Password PWDx = Password word0, word1, word2, and word3. Data = Lock Register Contents: PD(0) = Secured Silicon Sector Protection Bit, PD(1) = Persistent Protection Mode Lock Bit, PD(2) = Password Protection Mode Lock Bit. Notes 1. See Table 2 for description of bus operations. 2. All values are in hexadecimal. 3. All bus cycles are write cycles unless otherwise noted. 4. Data bits DQ15-DQ8 are don't cares for unlock and command cycles. 5. Address bits AMAX:A16 are don't cares for unlock and command cycles, unless SA or PA required. (AMAX is the Highest Address pin.) 6. All Lock Register bits are one-time programmable. Program state = "0" and the erase state = "1." The Persistent Protection Mode Lock Bit and the Password Protection Mode Lock Bit cannot be programmed at the same time or the Lock Register Bits Program operation aborts and returns the device to read mode. Lock Register bits that are reserved for future use default to "1's." The Lock Register is shipped out as 7. 8. 9. 10. 11. 12. 13. "FFFF's" before Lock Register Bit program execution. The Exit command returns the device to reading the array. If any Command Set Entry command was written, an Exit command must be issued to reset the device into read mode. For PWDx, only one portion of the password can be programmed per each "A0" command. Note that the password portion can be entered or read in any order as long as the entire 64-bit password is entered or read. If ACC = VHH, sector protection matches when ACC = VIH. Protected State = "00h," Unprotected State = "01h." The All PPB Erase command embeds programming of all PPB bits before erasure. White Electronic Designs Corp. reserves the right to change products or specifications without notice. November 2009 Rev. 10 (c) 2010 White Electronic Designs Corp. All rights reserved 30 White Electronic Designs Corporation * (602) 437-1520 * www.whiteedc.com White Electronic Designs W78M64VP-XSBX FIG: 5 SINGLE WORD PROGRAM Write Unlock Cycles: Address 555h, Data AAh Address 2AAh, Data 55h Unlock Cycle 1 Unlock Cycle 2 Write Program Command: Address 555h, Data A0h Setup Command Program Address (PA), Program Data (PD) Program Data to Address: PA, PD Perform Polling Algorithm (see Write Operation Status flowchart) Yes Polling Status = Busy? No Yes Polling Status = Done? Error condition (Exceeded Timing Limits) No PASS. Device is in read mode. FAIL. Issue reset command to return to read array mode. White Electronic Designs Corp. reserves the right to change products or specifications without notice. November 2009 Rev. 10 (c) 2010 White Electronic Designs Corp. All rights reserved 31 White Electronic Designs Corporation * (602) 437-1520 * www.whiteedc.com White Electronic Designs W78M64VP-XSBX FIG: 6 WRITE BUFFER PROGRAMMING OPERATION Write Unlock Cycles: Address 555h, Data AAh Address 2AAh, Data 55h Unlock Cycle 1 Unlock Cycle 2 Issue Write Buffer Load Command: Address SA, Data 25h Load Word Count to Program Program Data to Address: SA, wc wc = number of words - 1 Yes Confirm command: SA = 0x29h wc = 0? No Write Next Word, Decrement wc: wc = wc - 1 No Perform Polling Algorithm Write Buffer Abort Desired? (see Write Operation Status flowchart) Yes Polling Status = Done? Write to a Different Sector Address to Cause Write Buffer Abort Yes No No Error? Yes Yes Write Buffer Abort? No RESET. Issue Write Buffer Abort Reset Command FAIL. Issue reset command to return to read array mode. PASS. Device is in read mode. White Electronic Designs Corp. reserves the right to change products or specifications without notice. November 2009 Rev. 10 (c) 2010 White Electronic Designs Corp. All rights reserved 32 White Electronic Designs Corporation * (602) 437-1520 * www.whiteedc.com White Electronic Designs W78M64VP-XSBX FIG: 7 SECTOR ERASE OPERATION Write Unlock Cycles: Address 555h, Data AAh Address 2AAh, Data 55h Unlock Cycle 1 Unlock Cycle 2 Write Sector Erase Cycles: Address 555h, Data 80h Address 555h, Data AAh Address 2AAh, Data 55h Sector Address, Data 30h No Command Cycle 1 Command Cycle 2 Command Cycle 3 Specify first sector for erasure Select Additional Sectors? Yes Write Additional Sector Addresses * Each additional cycle must be written within tSEA timeout * The host system may monitor DQ3 or wait tSEA to ensure acceptance of erase commands * No limit on number of sectors No Poll DQ3. DQ3 = 1? Yes Last Sector Selected? * Commands other than Erase Suspend or selecting additional sectors for erasure during timeout reset device to reading array data No Yes Perform Write Operation Status Algorithm Yes Status may be obtained by reading DQ7, DQ6 and/or DQ2. Done? No DQ5 = 1? No Error condition (Exceeded Timing Limits) Yes PASS. Device returns to reading array. FAIL. Write reset command to return to reading array. Notes 1. See table 12.1 on page 69 for earse command sequence. 2. See DQ3: Sector Erase Timeout State Indicator on page 39 for information on the sector erase timeout. White Electronic Designs Corp. reserves the right to change products or specifications without notice. November 2009 Rev. 10 (c) 2010 White Electronic Designs Corp. All rights reserved 33 White Electronic Designs Corporation * (602) 437-1520 * www.whiteedc.com White Electronic Designs W78M64VP-XSBX FIG: 8 WRITE OPERATION STATUS FLOWCHART START - DQ 6 toggles when programming - DQ 6 and DQ 2 toggle when erasing - DQ 2 toggles when erase suspend - DQ 1 set when program error - DQ 5 set when time out Read_1 Read_2 Read_3 DQ6 Toggles between Read_1 & Read_2 and Read_2 & Read_3 NO Read_1 Read_2 NO YES WriteBuffer program and Read_1 DQ1 is set YES RETURN WRITE ABORT YES RETURN TIME OUT DQ2 Toggles NO RETURN DONE NO YES Read_1 DQ5 is set RETURN SUSPEND White Electronic Designs Corp. reserves the right to change products or specifications without notice. November 2009 Rev. 10 (c) 2010 White Electronic Designs Corp. All rights reserved 34 White Electronic Designs Corporation * (602) 437-1520 * www.whiteedc.com White Electronic Designs W78M64VP-XSBX FIG: 9 ADVANCED SECTOR PROTECTION/UNPROTECTION Hardware Methods S oftware Methods Lock Register (One Time Programmable) WP#/ACC = VIL (Highest or Lowest Sector Locked) Password Method Persistent Method (DQ2) (DQ1) 64-bit Password (One Time Protect) PPB Lock Bit1,2,3 0 = PPBs Locked 1 = PPBs Unlocked 1. Bit is volatile, and defaults to "1" on reset. 2. Programming to "0" locks all PPBs to their current state. 3. Once programmed to "0", requires hardware reset to unlock. Memory Array Persistent Protection Bit (PPB)4,5 Sector 0 PPB 0 DYB 0 Sector 1 PPB 1 DYB 1 Sector 2 PPB 2 DYB 2 Sector N-2 PPB N-2 DYB N-2 Sector N-1 PPB N-1 DYB N-1 PPB N DYB N Sector N 3 3. N = Highest Address Sector. Dynamic Protection Bit (DYB)6,7,8 4. 0 = Sector Protected, 1 = Sector Unprotected. 5. PPBs programmed individually, but cleared collectively 6. 0 = Sector Protected, 1 = Sector Unprotected. 7. Protect effective only if PPB Lock Bit is unlocked and corresponding PPB is "1" (unprotected). 8. Volatile Bits: defaults to user choice upon power-up (see ordering options). White Electronic Designs Corp. reserves the right to change products or specifications without notice. November 2009 Rev. 10 (c) 2010 White Electronic Designs Corp. All rights reserved 35 White Electronic Designs Corporation * (602) 437-1520 * www.whiteedc.com White Electronic Designs W78M64VP-XSBX FIG: 10 PPB PROGRAM ALGORITHM Enter PPB Command Set. Addr = BA Program PPB Bit. Addr = SA Read Byte Twice Addr = SA0 No DQ6 = Toggle? Yes No DQ5 = 1? Wait 500 s Yes Read Byte Twice Addr = SA0 DQ6 = Toggle? No Read Byte. Addr = SA Yes No DQ0 = '0' (Pgm.)? FAIL Yes Issue Reset Command PASS Exit PPB Command Set White Electronic Designs Corp. reserves the right to change products or specifications without notice. November 2009 Rev. 10 (c) 2010 White Electronic Designs Corp. All rights reserved 36 White Electronic Designs Corporation * (602) 437-1520 * www.whiteedc.com White Electronic Designs W78M64VP-XSBX FIG: 11 LOCK REGISTER PROGRAM ALGORITHM Write Unlock Cycles: Address 555h, Data AAh Address 2AAh, Data 55h Unlock Cycle 1 Unlock Cycle 2 Write Enter Lock Register Command: Address 555h, Data 40h XXXh = Address don't care Program Lock Register Data Address XXXh, Data A0h Address XXXh*, Data PD Program Data (PD): See text for Lock Register definitions Caution: Lock register can only be progammed once. Perform Polling Algorithm (see Write Operation Status flowchart) Yes Done? No No DQ5 = 1? Error condition (Exceeded Timing Limits) Yes PASS. Write Lock Register Exit Command: Address XXXh, Data 90h Address XXXh, Data 00h Device returns to reading array. FAIL. Write rest command to return to reading array. White Electronic Designs Corp. reserves the right to change products or specifications without notice. November 2009 Rev. 10 (c) 2010 White Electronic Designs Corp. All rights reserved 37 White Electronic Designs Corporation * (602) 437-1520 * www.whiteedc.com White Electronic Designs W78M64VP-XSBX FIG: 12 MAXIMUM NEGATIVE OVERSHOOT WAVERFORM 20 ns 20 ns +0 .8 V -0 .5 V -2 .0 V 20 n s FIG: 13 MAXIMUM POSITIVE OVERSHOOT WAVERFORM 20 ns VCC +2.0 V VCC +0.5 V +2.0 V 20 ns 20 ns FIG. 14 AC TEST CIRCUIT IOL Current Source VZ~ 1.5v (Bipolar Supply) D.U.T. CEFF = 50 pf IOH Current Source White Electronic Designs Corp. reserves the right to change products or specifications without notice. November 2009 Rev. 10 (c) 2010 White Electronic Designs Corp. All rights reserved 38 White Electronic Designs Corporation * (602) 437-1520 * www.whiteedc.com White Electronic Designs W78M64VP-XSBX FIG 15: AC WAVEFORMS FOR READ OPERATIONS tRC Addresses Addresses Stable tACC CS# tCEH tDF tRH OE# tOE tOEH tCE WE# tOH High Z Outputs High Z Output Valid RESET# RY/BY# OV FIG 16: PAGE READ OPERATION TIMINGS Same Page A22-A3 A2-A0 Aa Ab tPACC tACC Data Qa Ac tPACC Qb Ad tPACC Qc Qd CS# OE# White Electronic Designs Corp. reserves the right to change products or specifications without notice. November 2009 Rev. 10 (c) 2010 White Electronic Designs Corp. All rights reserved 39 White Electronic Designs Corporation * (602) 437-1520 * www.whiteedc.com White Electronic Designs W78M64VP-XSBX FIG. 17: RESET TIMINGS NOT DURING EMBEDDED ALGORITHMS RY/BY# CS#, OE# tRH RESET# tRP tReady FIG. 18: RESET TIMINGS DURING EMBEDDED ALGORITHMS tReady RY/BY# tRB CS#, OE# RESET# tRP White Electronic Designs Corp. reserves the right to change products or specifications without notice. November 2009 Rev. 10 (c) 2010 White Electronic Designs Corp. All rights reserved 40 White Electronic Designs Corporation * (602) 437-1520 * www.whiteedc.com White Electronic Designs W78M64VP-XSBX FIG. 19: POWER-UP SEQUENCE TIMINGS VCC VCC min VIO VIO min tRH CE# tVIOS tVCS RESET# FIG. 20: PROGRAM OPERATION Program Command Sequence (last two cycles) tAS tWC Addresses Read Status Data (last two cycles) 555h PA PA PA tAH CS# tCH OE# tWHWH1 tWP WE# tWPH tCS tDS tDH A0h Data PD Status tBUSY DOUT tRB RY/BY# VCC tVCS NOTES: 1. PA is the address of the memory location to be programmed. 2. PD is the data to be programmed at byte address. 3. DOUT is the output of the data written to the device. White Electronic Designs Corp. reserves the right to change products or specifications without notice. November 2009 Rev. 10 (c) 2010 White Electronic Designs Corp. All rights reserved 41 White Electronic Designs Corporation * (602) 437-1520 * www.whiteedc.com White Electronic Designs W78M64VP-XSBX FIG 21: ACCELERATED PROGRAM TIMING DIAGRAM VHH WP#/ACC VIL or VIH VIL or VIH tVHH Notes: 1. Not 100% tested 2. CE#, OE# = VIL 3. 4. tVHH OE#, = VIL See figure 4 and Table 32 for test specifications FIG 22: CHIP/SECTOR ERASE OPERATION TIMINGS Program Command Sequence (last two cycles) tAS tWC Addresses Read Status Data (last two cycles) 2AAh SA 555h for chip erase CS# VA VA tAH tCH OE# tWHWH2 tWP WE# tWPH tCS tDS tDH 55h Data 30h Status DOUT 10 for Chip Erase tBUSY tRB RY/BY# VCC tVCS Notes: 1. SA = Sector Address (for Sector Erase), VA = Valid Address for reading status data (see "write operation status") 2. These waveforms are for word mode. White Electronic Designs Corp. reserves the right to change products or specifications without notice. November 2009 Rev. 10 (c) 2010 White Electronic Designs Corp. All rights reserved 42 White Electronic Designs Corporation * (602) 437-1520 * www.whiteedc.com White Electronic Designs W78M64VP-XSBX FIG 23: DATA# POLLING TIMINGS (DURING EMBEDDED ALGORITHMS) tRC Addresses VA VA VA tACC tCS CS# tCH tOE OE# tOEH WE# tDF tOH High Z DQ7 Complement Complement DQ6-DQ0 Status Data Status Data True Valid Data High Z True Valid Data tBUSY RY/BY# Notes: 1. VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data read cycle. 2. TOE for data polling is 35ns when VIO = 2.7 to 3.6V. 3. CE# does not need to go high between status bit reads. White Electronic Designs Corp. reserves the right to change products or specifications without notice. November 2009 Rev. 10 (c) 2010 White Electronic Designs Corp. All rights reserved 43 White Electronic Designs Corporation * (602) 437-1520 * www.whiteedc.com White Electronic Designs W78M64VP-XSBX FIG 24: TOGGLE BIT TIMINGS (DURING EMBEDDED ALGORITHMS) tAHT tAS Addresses tAHT tASO CS# tCSPH tOEH WE# tOEPH OE# tDH DQ6/DQ2 tOE Valid Data Valid Status Valid Status Valid Status (first read) (second read) (stops toggling) Valid Data RY/BY# Note: 1. A = Valid address; Not required for DQ6. Illustration shows first two status cycle after command sequence, last status read cycle, and array data read cycle 2. CE# does not need to go high between status bit reads. FIG 25: DQ2 VS. DQ6 Enter Embedded Erasing WE# Erase Suspend Erase Enter Erase Suspend Program Erase Suspend Read Erase Resume Erase Suspend Program Erase Suspend Read Erase Erase Complete DQ6 DQ2 NOTE: DQ2 toggles only when read at an address within an erase-suspended sector. The system may use OE# or CS# to toggle DQ2 and DQ6. White Electronic Designs Corp. reserves the right to change products or specifications without notice. November 2009 Rev. 10 (c) 2010 White Electronic Designs Corp. All rights reserved 44 White Electronic Designs Corporation * (602) 437-1520 * www.whiteedc.com White Electronic Designs W78M64VP-XSBX FIG 26: SECTOR/SECTOR BLOCK PROTECT AND UNPROTECT TIMING DIAGRAM VID VIH RESET # SA, A6 , A1, A 0 Valid* Valid* Sector Group Protect/Unprotec t Data 60h Valid* Verify 60h 40h Status 1 s CS# Sector Group Protect: 150 s Sector Group Unprotect: 15 m s WE# OE# NOTES: For sector protect, A6 = 0, A1 = 1, A0 = 0. For sector unprotect, A6 = 1, A1 = 1, A0 = 0. White Electronic Designs Corp. reserves the right to change products or specifications without notice. November 2009 Rev. 10 (c) 2010 White Electronic Designs Corp. All rights reserved 45 White Electronic Designs Corporation * (602) 437-1520 * www.whiteedc.com White Electronic Designs W78M64VP-XSBX FIG 27: ALTERNATE CS# CONTROLLED WRITE (ERASE/PROGRAM) OPERATION TIMINGS 555 for program 2AA for erase PA for program SA for sector erase 555 for chip erase Data# Polling Addresses PA tWC tAS tAH tWH WE# tGHEL OE# tWHWH1 or 2 tCP CS# tWS tCPH t BUSY tDS tDH DQ7# Data tRH A0 for program 55 for erase DOUT PD for program 30 for sector erase 10 for chip erase RESET# RY/BY# NOTES: 1. FIG: Indicated last two bus cycles of a program or erase operation. 2. PA = program address. SA = sector address, PD = program data. 3. DQ7 is the complement of the data written to the device. DOUT is the data written to the device. White Electronic Designs Corp. reserves the right to change products or specifications without notice. November 2009 Rev. 10 (c) 2010 White Electronic Designs Corp. All rights reserved 46 White Electronic Designs Corporation * (602) 437-1520 * www.whiteedc.com White Electronic Designs W78M64VP-XSBX PACKAGE: 159 PBGA (PLASTIC BALL GRID ARRAY) BOTTOM VIEW 159 X O 0.762 (0.030) NOM A B C D E F G H J K L M N P R T 1.27 (0.050) NOM 19.05 (0.750) NOM 22.15 (0.872) MAX 10 9 8 7 6 5 4 3 2 1 0.61 (0.024) NOM 1.27 (0.050) NOM 11.43 (0.450) NOM 2.34 (0.092) MAX 13.15 (0.518) MAX ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES ORDERING INFORMATION W 7 8M64 VP XXX SB X White Electronic Designs Corp. Flash: Organization, 8M x 64: User configurable as 2 x 8M x 32, or 4 x 8M x16 3.3V Power Supply: Access Time (ns): 110 = 110ns 120 = 120ns Package Type: SB = 159 PBGA, 13mm x 22mm Devise Grade: M = Military I = Industrial C = Commercial -55C to +125C -40C to +85C 0C to +70C White Electronic Designs Corp. reserves the right to change products or specifications without notice. November 2009 Rev. 10 (c) 2010 White Electronic Designs Corp. All rights reserved 47 White Electronic Designs Corporation * (602) 437-1520 * www.whiteedc.com White Electronic Designs W78M64VP-XSBX Document Title 8Mx64 Flash 3.3V Page Mode Multi-Chip Package Revision History Rev # History Release Date Status Rev 0 Initial Release June 2008 Advanced Rev 1 Change (Pg. All) July 2008 Advanced October 2008 Advanced December 2008 Advanced December 2008 Advanced 1.1 Add detail to DC, AC and programming sections Rev 2 Change (Pg. 1, 3, 25, 27, 47) 2.1 Removed 90 and 100ns access times 2.2 Added 110ns access time Rev 3 Change (Pg. 2) 3.1 Correct ball B6; change from "NC" to "DQ57" Rev 4 Change (Pg. 2, 25, 26, 28) 4.1 Remove "TBD" from pin configuration and block diagram 4.2 In Table 30; ICC5 is 2mA 4.3 In Table 30; Add Note 3 to ILI (WP/ACC), ILIT, ILOZ, ICC6, IACC, VHH, VID, VLKO 4.4 In Table 30; Remove VIL = VSS + 0.3V/-1.0V from ICC6 and ICC5 4.5 In Table 32; Remove Note 1 from read cycle time, page access time and output enable hold time 4.6 In Table 32; Change page access time to 25ns on both -100 and -120 4.7 In Table 35; Change output enable to output valid symbol to tGLQV 4.8 In Table 35; Remove Note 1 from duration of byte programming operation 4.9 In Table 35; Remove Note 3 from write cycle time 4.10 Change 100 to 110 in Table 35 4.11 In Table 36; Remove Note 1 from write cycle time and correct JEDEC symbol tAVAV 4.12 Add new page; Test Conditions - Figure 11 - Test Setup Diagram and Table 40 - Test Specifications 4.13 Update all figures and tables following addition of Figure 11 and Table 40 White Electronic Designs Corp. reserves the right to change products or specifications without notice. November 2009 Rev. 10 (c) 2010 White Electronic Designs Corp. All rights reserved 48 White Electronic Designs Corporation * (602) 437-1520 * www.whiteedc.com White Electronic Designs W78M64VP-XSBX Document Title 8Mx64 Flash 3.3V Page Mode Multi-Chip Package Revision History Continued Rev # History Release Date Status Rev 4 Change (Pg. 48) March 2009 Advanced March 2009 Advanced June 2009 Advanced August 2009 Advanced 4.14 Change dimension thickness to 2.70 (0.106) max due to typo Rev 5 Change (Pg. 1, 2, 3, 16 ,23, 26, 30, 39, 41, 44) 5.1 Delete VIO range is 1.65 to VCC 5.2 Remove (*) astrisk from pin H10, A-1 from Fig 3, correct spelling of versatile in Fig. 2 5.3 Delete versatile IO (VIO) control pargraph 5.4 Remove paragraph on customer programming services 5.5 Remove all reference to Fig. 8.1 5.6 Change output hold from address in Table 32 to 0 for both speeds grades, change output enable hold time - Read to 0 for both speed grades 5.7 Table 38, note 1 is Table 2, note 8 is Table3 5.8 Table 39 note 1 is Table 2 5.9 Correct Fig. 12; Maximum negative overshoot wave form, Fig. 13; maximum positive overshoot waveform 5.10 Add Table 40; Power-up sequence timings and notes Rev 6 Change (Pg. 29) 6.1 Table 37 notes: change notes 1-5 Rev 7 Change (Pg. 4, 7,25, 26, 27, 28, 29, 30, 39, 40, 41, 43, 45, 46) 7.1 Change Table 38 to 39 7.2 Add new Table 32 - Test Specifications 7.3 Re-number table sequence from Table 32 7.4 Add Note #1 to Figure 16 7.5 Remove Table 41, duplicate to Table 35 7.6 Add Note #4 to Figure 21 7.7 Add Note #2 to Figure 24 White Electronic Designs Corp. reserves the right to change products or specifications without notice. November 2009 Rev. 10 (c) 2010 White Electronic Designs Corp. All rights reserved 49 White Electronic Designs Corporation * (602) 437-1520 * www.whiteedc.com White Electronic Designs W78M64VP-XSBX Document Title 8Mx64 Flash 3.3V Page Mode Multi-Chip Package Revision History Continued Rev # History Release Date Status Rev 8 Change (Pg. 1, 2, 17, 18, 19, 20, 21, 22, 23, 24, 25, 27) September 2009 Advanced October 2009 Final November 2009 Final 8.1 Remove "/128KB sectors" from uniform sector architecture - No Byte mode 8.2 Remove "/256 byte and /16 byte" from secured silicon sector region. 8.3 Remove "under development, is not qualified or characterized and is" or cancellation. 8.4 Remove "Pin A-1" from block diagram 8.5 Remove "Byte# = VIL" in device operations 8.6 Remove "AMax:A-1 in byte mode," from Notes in device operations 8.7 Remove all reference to "Byte Address" from pages 17 through 23 8.8 Change ILI to 10A for WP/ACC and 8A for others, ILIT = 70A, ILO = 2A, ICC1 = 440A, IIO2 = 20A, ICC2 = 20A, ICC3 = 180A, ICC4 = 10A, ICC5 = 1mA, ICC6 = 10A, IACC = 40mA for WP#/ACC Pin and 160mA for VCC Pin 8.9 Add Note (1) to AC Characteristics: tOE for data polling is 45ns when VIO = 1.65V to 2.7V and 32ns when VIO = 2.7V to 3.6V. Rev 9 Change (Pg. 1, 23) 9.1 Remove "Advanced," "under development, is not qualified or characterized and is," "or cancellation." 9.2 Add capacitance values to table 27. CWE = 13pf, CCS = 25pf, CI/O = 15, CAD = 30pf, CRB = 40pf and COE = 35pf. 9.3 Change status of data sheet to Final. 9.4 Change "max" to "22" 9.5 Remove "Note" in Fig. 16 Rev 10 Change (Pg. 26, 27) 10.1 Corrected Table 35 10.2 Add "tCH" to Table 37 White Electronic Designs Corp. reserves the right to change products or specifications without notice. November 2009 Rev. 10 (c) 2010 White Electronic Designs Corp. All rights reserved 50 White Electronic Designs Corporation * (602) 437-1520 * www.whiteedc.com