1
2005 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. DSC-5903/10
©
IDT72V71623
3.3 VOLT TIME SLOT INTERCHANGE
DIGITAL SWITCH WITH RATE
MATCHING
2,048 x 2,048
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. The ST-BUS® is a trademark of Zarlink Semiconductor, Inc..
FUNCTIONAL BLOCK DIAGRAM
FEATURES:
••
••
•Up to 16 serial input and output streams
••
••
•Maximum 2,048 x 2,048 channel non-blocking switching
••
••
•Accepts data streams at 2.048 Mb/s, 4.096 Mb/s, 8.192 Mb/s or
16.384 Mb/s
••
••
•Rate matching capability: Mux/Demux mode
••
••
•Output Enable Indication pins provided by dedicated pins
••
••
•Per-channel Variable Delay mode for low-latency applications
••
••
•Per-channel Constant Delay mode for frame integrity applica-
tions
••
••
•Automatic identification of ST-BUS® and GCI serial streams
••
••
•Automatic frame offset delay measurement
••
••
•Per-stream frame delay offset programming
••
••
•Per-channel high-impedance output control
••
••
•Per-channel Processor mode to allow microprocessor writes to
TX streams
••
••
•Direct microprocessor access to all internal memories
••
••
•Memory block programming for quick setup
••
••
•IEEE-1149.1 (JTAG) Test Port
••
••
•Internal Loopback for testing
••
••
•Available in 144-pin Thin Quad Flatpack (TQFP) and
144-pin Ball Grid Array (BGA) packages
••
••
•Operating Temperature Range -40°°
°°
°C to +85°°
°°
°C
••
••
•3.3V I/O with 5V tolerant inputs and TTL compatible outputs
DESCRIPTION:
The IDT72V71623 has a maximum non-blocking switch capacity of
2,048 x 2,048 channels with data rates at 2.048 Mb/s, 4.096 Mb/s, 8.192 Mb/s
or 16.384 Mb/s. With 16 inputs and 16 outputs, a variety of rate combinations
is supported under Mux/Demux mode, to allow for switching between streams
of different data rates.
Output
MUX
Receive
Serial Data
Streams
RX0
RX1
RX2
RX3
RX4
RX5
RX6
RX7
ODE
F0i
Vcc
CSDS R/WA0-A13
GND
DTA
5903 drw01
RX8
RX9
RX10
RX11
RX12
RX13
RX14
RX15
Loopback
Test Port
Data Memory
Internal
Registers
Microprocessor InterfaceTiming Unit
TX0
TX1
TX2
TX3
TX4
TX5
TX6
TX7
TX8
TX9
TX10
TX11
TX12
TX13
TX14
TX15
CLK FE/
HCLK
WFPS
TDITMS TCK
TDO TRST
RESET
OEI0
OEI1
OEI2
OEI3
OEI4
OEI5
OEI6
OEI7
OEI8
OEI9
OEI10
OEI11
OEI12
OEI13
OEI14
OEI15
Connection
Memory
Transmit
Serial Data
Streams
D0-D15
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COMMERCIAL TEMPERATURE RANGE
IDT72V71623 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 2,048 x 2,048
PIN CONFIGURATIONS
BGA: 1mm pitch, 13mm x 13mm (Order Code: BC, BCG)
TOP VIEW
NOTES:
1. IC - Internal Connection, tie to Ground for normal operation.
2. All I/O pins are 5V tolerant except for TMS, TDI and TRST.
RX0 RX1 RX3 RX6 TX1 TX4 TX7 RX10 RX12 RX15 TX10 TX11
CLK ODE RX2 RX5 TX0 TX3 TX6 RX9 RX13 RX14 TX9 TX12
F0i FE/HCLK RESET RX4 RX7 TX2 TX5 RX8 RX11 TX8 TX13 TX14
TMS WFPS TDI VCC VCC VCC VCC VCC VCC TX15 IC IC
TD0 TCK TRST VCC IC IC IC
DS CS R/WVCC IC IC IC
A0 A1 A2 VCC OEI0 OEI1 OEI2
A3 A4 A5 A13 OEI3 OEI4 OEI5
A6 A7 A8 D15 OEI6 IC OEI7
A9 A10 DTA D9 D6 D3 D0 OEI13 OEI10 IC IC IC
A11 IC D12 D11 D7 D4 D1 OEI14 OEI11 OEI8 IC IC
A12 D14 D13 D10 D8 D5 D2 OEI15 OEI12 OEI9 IC IC
A1 BALL PAD CORNER
A
B
C
D
E
F
G
H
J
K
L
M
12 3 4 5 6 7 8 9 101112
5903 drw02
GND GND GND GND VCC
GND GND GND GND VCC
VCC
GND GND GND GND VCC
VCC VCC VCC VCC GND
GND GND GND GND
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COMMERCIAL TEMPERATURE RANGE
IDT72V71623 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 2,048 x 2,048
TQFP: 0.50mm pitch, 20mm x 20mm (Order Code: DA, DAG)
TOP VIEW
PIN CONFIGURATIONS (CONTINUED)
NOTES:
1. IC - Internal Connection, tie to Ground for normal operation.
2. All I/O pins are 5V tolerant except for TMS, TDI and TRST.
TX11
TX10
GND
TX9
TX8
VCC
RX15
RX14
RX13
RX12
RX11
RX10
RX9
RX8
GND
TX7
TX6
TX5
TX4
GND
TX3
TX2
TX1
TX0
GND
RX7
RX6
RX5
RX4
RX3
RX2
RX1
RX0
IC
IC
IC
IC
IC
IC
IC
IC
GND
OEI7
OEI6
OEI5
OEI4
GND
OEI3
OEI2
OEI1
OEI0
GND
IC
IC
IC
IC
IC
IC
IC
IC
TX15
TX14
GND
TX13
TX12
VCC
OEI8
OEI9
GND
OEI10
OEI11
OEI12
OEI13
GND
OEI14
OEI15
D0
D1
GND
D2
D3
D4
D5
GND
D6
D7
VCC
D08
D09
GND
D10
D11
VCC
D12
D13
GND
D14
D15
DTA
A13
A12
IC
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A0
R/W
CS
DS
GND
TRST
TCK
TDO
TD
I
TMS
VCC
WFPS
FE/HCLK
F0i
CLK
GND
RESET
ODE
GND
A1
5903 drw03
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
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COMMERCIAL TEMPERATURE RANGE
IDT72V71623 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 2,048 x 2,048
PIN DESCRIPTION
SYMBOL NAME I/O DESCRIPTION
GND Ground. Ground Rail.
Vcc Vcc +3.3 Volt Power Supply.
TX0-15 TX Output 0 to 15 O Serial data output stream. These streams may have a data rate of 2.048 Mb/s, 4.096 Mb/s, 8.192 Mb/s,
(Three-state Outputs) or 16.384 Mb/s.
OEI0-15 Output Enable O These pins reflect the active or three-state status for the corresponding, (TX0-15) output streams.
Indication 0 to 15
(Three-state Outputs)
RX0-15 RX Input 0 to 15 I Serial data input stream. These streams may have a data rate of 2.048 Mb/s, 4.096 Mb/s, 8.192 Mb/s,
or 16.384 Mb/s.
F0i Frame Pulse I This input accepts and automatically identifies frame synchronization signals formatted according to
ST-BUS® and GCI specifications.
FE/HCLK Frame Evaluation/ I When the WFPS pin is LOW, this pin is the frame measurement input. When the WFPS pin is HIGH, the HCLK
HCLK Clock (4.096 MHZ clock) is required for frame alignment in the wide frame pulse (WFP) mode.
C LK Clock I Serial clock for shifting data in/out on the serial streams (RX/TX 0-15).
TMS Test Mode Select I JTAG signal that controls the state transitions of the TAP controller. This pin is pulled HIGH by an internal
pull-up when not driven.
TDI Test Serial Data In I JTAG serial test instructions and data are shifted in on this pin. This pin is pulled HIGH by an internal pull-up
when not driven.
TDO Test Serial Data Out O JTAG serial data is output on this pin on the falling edge of TCK. This pin is held in high-impedance state when
JTAG scan is not enabled.
TCK Test Clock I Provides the clock to the JTAG test logic.
TRST Test Reset I Asynchronously initializes the JTAG TAP controller by putting it in the Test-Logic-reset state. This pin is pulled
by an internal pull-up when not driven. This pin should be pulsed LOW on power-up, or held LOW, to ensure
that the IDT72V71623 is in the normal functional mode.
RESET Device Reset I This input (active LOW) puts the IDT72V71623 in its reset state that clears the device internal counters, registers
and brings TX0-15 and microport data outputs to a high-impedance state. In normal operation, the RESET
pin must be held LOW for a minimum of 100ns to reset the device. After reset state, RESET must be held HIGH
for minimum 100ns before beginning operation.
WFPS Wide Frame Pulse Select I When 1, enables the wide frame pulse (WFP) Frame Alignment interface. When 0, the device operates in
ST-BUS® /GCI mode.
DS Data Strobe I This active LOW input works in conjunction with CS to enable the read and write operations.
R/WRead/Write I This input controls the direction of the data bus lines during a microprocessor access.
CS Chip Select I Active LOW input used by a microprocessor to activate the microprocessor port of IDT72V71623.
A0-13 Address Bus 0 to 13 I These pins allow direct access to Connection Memory, Data Memory and internal control registers.
D0-15 Data Bus 0-15 I/O These pins are the data bits of the microprocessor port.
DTA Data Transfer O This active LOW signal indicates that a data bus transfer is complete. When the bus cycle ends, this pin drives
Acknowledgment HIGH and then goes high-impedance, allowing for faster bus cycles with a weaker pull-up resistor. A pull-up
resistor is required to hold a HIGH level when the pin is in high-impedance.
ODE Output Drive Enable I This is the output enable control for the TX0-15 serial outputs. When ODE input is LOW and the OSB bit of
the IMS register is LOW, TX0-15 are in a high-impedance state. If this input is HIGH, the TX0-15 output
drivers are enabled. However, each channel may still be put into a high-impedance state by using the per
channel control bit in the Connection Memory.
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IDT72V71623 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 2,048 x 2,048
DESCRIPTION (CONTINUED)
Output enable indications are provided through dedicated pins (one pin per
output stream) to facilitate external data bus control.
The IDT72V71623 is capable of switching up to 2,048 x 2,048 channels
without blocking. Designed to switch 64 Kbit/s PCM or N x 64 Kbit/s data, the
device maintains frame integrity in data applications and minimizes throughput
delay for voice applications on a per channel basis.
The serial input streams (RX) and serial output streams (TX) of the
IDT72V71623 can be run up to 16.384 Mb/s allowing 256 channels per 125µs
frame. Depending on the input and output data rates the device can support
up to 16 serial streams.
With two main operating modes, Processor mode and Connection Mode,
the IDT72V71623 can easily switch data from incoming serial streams (Data
Memory) or from the controlling microprocessor (Connection Memory). As
control and status information is critical in data transmission, the Processor mode
is especially useful when there are multiple devices sharing the input and output
streams.
With two main configuration modes, Regular and Mux/Demux mode the
IDT72V71623 is designed to work in a mixed data-rate environment. In Mux/
Demux mode, all of the input streams work at one data rate and the output streams
at another. Depending on the configuration, more or less serial streams will be
available on the inputs or outputs to maintain a non-blocking switch.
With data coming from multiple sources and through different paths, data
entering the device is often delayed. To handle this problem, the IDT72V71623
has a frame evaluation feature to allow individual streams to be offset from the
frame pulse in half clock-cycle intervals up to +4.5 clock cycles for speeds up
to 8 Mb/s or +2.5 clock cycles for 16 Mb/s. (See Table 8 for maximum allowable
skew).
The IDT72V71623 also provides a JTAG test access port, an internal
loopback feature, memory block programming, a simple microprocessor
interface and automatic ST-BUS®/GCI sensing to shorten setup time, aid in
debugging and ease use of the device without sacrificing capabilities.
FUNCTIONAL DESCRIPTION
DATA AND CONNECTION MEMORY
All data that comes in through the RX inputs go through a serial-to-parallel
conversion before being stored into internal Data Memory. The 8 KHz frame
pulse (F0i) is used to mark the 125µs frame boundaries and to sequentially
address the input channels in Data Memory. The Data Memory is only written
by the device from the RX streams and can be read from either the TX streams
or the microprocessor.
Data output on the TX streams may come from either the Serial Input Streams
(Data Memory) or from the microprocessor (Connection Memory). In the case
that RX input data is to be output, the addresses in Connection Memory are used
to specify a stream and channel of the input. The Connection Memory is setup
in such a way that each location corresponds to an output channel for each
particular stream. In that way, more than one channel can output the same data.
In Processor mode, the microprocessor writes data to the Connection Memory
locations corresponding to the stream and channel that is to be output. The lower
byte (8 least significant bits) of the Connection Memory is output every frame
until the microprocessor changes the data or mode of the channel. By using this
Processor mode capability, the microprocessor can access input and output
time-slots on a per channel basis.
The most significant bits of the Connection Memory are used to control per
channel functions such as Processor mode, Constant or Variable Delay mode,
three-state of output drivers, and the Loopback function.
OPERATING MODES
In addition to Regular mode where input and output streams are operating
at the same rate, the IDT72V71623 incorporates a rate matching function,
Mux/Demux mode. In Mux/Demux mode, all input streams are operating at
the same rate, while output streams are operating at a different rate. All
configurations are non-blocking. These modes can be entered by setting the
DR3-0 bits in the Control Register, see Table 5.
OUTPUT IMPEDANCE CONTROL
In order to put all streams in three-state, all per-channel three-state control
bits in the Connection Memory are set (MOD0 and MOD1 = 1) or both the ODE
pin and the OSB bit of the Control Register must be zero. If any combination
other than 0-0, for the ODE pin and the OSB bit, is used, the three-state control
of the streams will be left to the state of the MOD1 and MOD0 bits of the Connection
Memory. The IDT72V71623 incorporates a memory block programming
feature to facilitate three-state control after reset. See Table 1 for Output High-
Impedance Control.
SERIAL DATA INTERFACE TIMING
When a 16Mb/s serial data rate is required, the master clock frequency
will be running at 16.384MHz resulting in a single-bit per clock. For all other
cases, 2Mb/s, 4Mb/s, and 8Mb/s, the master clock frequency will be twice the
fastest data rate on the serial streams. Use Table 5 to determine clock speed
and DR3-0 bits in the Control Register to setup the device. The IDT72V71623
provides two different interface timing modes, ST-BUS® or GCI. The
IDT72V71623 automatically detects the presence of an input frame pulse and
identifies it as either ST-BUS® or GCI.
In ST-BUS®, when running at 16.384MHz, data is clocked out on the
falling edge and is clocked in on the subsquent rising-edge. At all other data
rates, there are two clock cycles per bit and every second falling edge of the
master clock marks a bit boundary and the data is clocked in on the rising edge
of CLK, three quarters of the way into the bit cell. See Figure 15 for timing.
In GCI format, when running at 16.384MHz, data is clocked out on the
rising edge and is clocked in on the subsquent falling edge. At all other data
rates, there are two clock cycles per bit and every second rising edge of the
master clock marks the bit boundary and data is clocked in on the falling edge
of CLK at three quarters of the way into the bit cell. See Figure 16 for timing.
INPUT FRAME OFFSET SELECTION
Input frame offset selection allows the channel alignment of individual input
streams to be offset with respect to the output stream channel alignment (i.e. F0i).
Although input data is synchronous, delays can be caused by variable path
serial backplanes and variable path lengths, which may be implemented in large
centralized and distributed switching systems. Because data is often delayed
this feature is useful in compensating for the skew between clocks.
Each input stream can have its own delay offset value by programming the
frame input offset registers (FOR, Table 7). The frame offset shown is a function
of the data rate, and can be as large as +4.5 master clock (CLK) periods forward
with a resolution of ½ clock period. To determine the maximum offset allowed
see Table 8.
SERIAL INPUT FRAME ALIGNMENT EVALUATION
The IDT72V71623 provides the frame evaluation (FE) input to determine
different data input delays with respect to the frame pulse F0i. Setting the start
frame evaluation (SFE) bit low for at least one frame starts a measurement cycle.
When the SFE bit in the Control Register is changed from low to high, the
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COMMERCIAL TEMPERATURE RANGE
IDT72V71623 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 2,048 x 2,048
evaluation starts. Two frames later, the complete frame evaluation (CFE) bit of
the frame alignment register (FAR) changes from low to high to signal that a valid
offset measurement is ready to be read from bits 0 to 11 of the FAR register. The
SFE bit must be set to zero before a new measurement cycle is started.
In ST-BUS ® mode, the falling edge of the frame measurement signal (FE)
is evaluated against the falling edge of the ST-BUS ® frame pulse. In GCI mode,
the rising edge of FE is evaluated against the rising edge of the GCI frame pulse.
See Table 6 and Figure 5 for the description of the frame alignment register.
MEMORY BLOCK PROGRAMMING
The IDT72V71623 provides users with the capability of initializing the entire
Connection Memory block in two frames. To set bits 15 to 13 of every Connection
Memory location, first program the desired pattern in bits 9 to 7 of the Control
Register.
Setting the memory block program (MBP) bit of the control register high
enables the block programming mode. When the block programming enable
(BPE) bit of the Control Register is set to high, the block programming data will
be loaded into the bits 15 to 13 of every Connection Memory location. The other
Connection Memory bits (bit 12 to bit 0) are loaded with zeros. When the memory
block programming is complete, the device resets the BPE bit to zero.
LOOPBACK CONTROL
The loopback control (LPBK) bit of each Connection Memory location allows
the TX output data to be looped backed internally to the RX input for diagnostic
purposes.
If the LPBK bit is high, the associated TX output channel data is internally
looped back to the RX input channel (i.e., data from TXn channel m routes to
the RXn channel m internally); if the LPBK bit is low, the loopback feature is
disabled. For proper per-channel loopback operation, the contents of frame
delay offset registers must be set to zero and the device must be in regular switch
mode (DR3-0 = 0x0, 0x1 or 0x2).
DELAY THROUGH THE IDT72V71623
The switching of information from the input serial streams to the output serial
streams results in a throughput delay. The device can be programmed to
perform time-slot interchange functions with different throughput delay capabili-
ties on a per-channel basis. For voice applications, Variable throughput delay
is best as it ensures minimum delay between input and output data. In wideband
data applications, Constant throughput delay is best as the frame integrity of the
information is maintained through the switch.
The delay through the device varies according to the type of throughput
delay selected in the MOD1 and MOD0 bits of the Connection Memory.
VARIABLE DELAY MODE (MOD1-0 = 0x0)
In this mode, the delay is dependent only on the combination of source and
destination serial stream speed. Although the minimum delay achievable is
dependent on the input and output serial stream speed, if data is switched
out +3 channels of the slowest data rate, the data will be switched out in the same
frame except if the input and output data rates are both 16 Mb/s (DR3-0 = 0x3).
(See Figure 2 for example).
For example, given the input data rate is 2 Mb/s and the output data rate is
8 Mb/s, input channel CH0 can be switch out by output channel CH12. In the
above example the input streams are slower than the output streams. Also, for
every 2 Mb/s time slot there are four 8 Mb/s time slots, thus a three 2 Mb/s channel
delay equates to 12 output channel time slots. See Figure 2 for this example and
other examples of minimum delay to guarantee transmission in the same frame.
CONSTANT DELAY MODE (MOD1-0 = 0x1)
In this mode, frame integrity is maintained in all switching configurations by
making use of a multiple Data Memory buffer. Input channel data is written into
the Data Memory buffers during frame n will be read out during frame n+2.
Figure 1 shows examples of Constant Delay mode.
MICROPROCESSOR INTERFACE
The IDT72V71623’s microprocessor interface looks like a standard RAM
interface to improve integration into a system. With a 14-bit address bus and a
16-bit data bus, read and writes are mapped directly into Data and Connection
memories and require only one Master Clock cycle to access. By allowing the
internal memories to be randomly accessed in one cycle, the controlling
microprocessor has more time to manage other peripheral devices and can
more easily and quickly gather information and setup the switch paths.
Table 2 shows the mapping of the addresses into internal memory blocks,
Table 3 shows the Control Register information and Figure 11 and Figure 12
shows asynchronous and synchronous microprocessor accesses.
MEMORY MAPPING
The address bus on the microprocessor interface selects the internal
registers and memories of the IDT72V71623. The two most significant bits of the
address select between the registers, Data Memory, and Connection Memory.
If A13 and A12 are HIGH, A11-A0 are used to address the Data Memory (Read
Only) where data output is read from the 8 least significant bits on the data bus.
If A13 is HIGH and A12 is LOW, A11-A0 are used to address Connection
Memory (Read/Write). If A13 is LOW and A12 is HIGH A11-A9 are used to select
the Control Register, Frame Alignment Register, and Frame Offset Registers.
See Table 2 for mappings..
CONTROL REGISTER
As explained in the Serial Data Interface Timing and Switching Configura-
tions sections, after system power-up, the Control Register should be pro-
grammed immediately to establish the desired switching configuration.
The data in the Control Register consists of the Memory Block Programming
bit (MBP), the Block Programming Data (BPD) bits, the Begin Block Program-
ming Enable (BPE), the Output Stand By (OSB), Start Frame Evaluation (SFE),
and Data Rate Select bits (DR 3-0). As explained in the Memory Block
Programming section, the BPE begins the programming if the MBP bit is enabled.
This allows the entire Connection Memory block to be programmed with the
Block Programming Data bits.
CONNECTION MEMORY CONTROL
If the ODE pin or the OSB bit is high, the MOD1-0 bits of each Connection
Memory location controls the output drivers. See Table 1 for detail. The
Processor Channel (PC) mode is entered by a 1-0 of the MOD1-0 of the
Connection Memory. In Processor Channel Mode, this allows the microproces-
sor to access TX output channels. Once the MOD1-0 bits are set the lower 8
bits of the Connection Memory will be output on the TX serial streams. Also
controlled in the Connection Memory is the Variable Delay mode or Constant
Delay mode. Each Connection Memory location allows the per-channel
selection between Variable and Constant throughput Delay modes and
Processor mode.
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COMMERCIAL TEMPERATURE RANGE
IDT72V71623 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 2,048 x 2,048
If the LPBK bit is high, the associated TX output channel data is internally
looped back to the RX input channel (i.e., RXn channel m data comes from the
TXn channel m). If the LPBK bit is low, the loopback feature is disabled. For
proper per-channel loopback operation, the contents of the frame delay offset
registers must be set to zero and the device must be in regular switch mode
(DR3-0 = 0x0, 0x1 or 0x2).
OUTPUT ENABLE INDICATION
The IDT72V71623 has dedicated pins to indicate the state of the outputs
(active or three-state). See Figure 13 for timing.
INITIALIZATION OF THE IDT72V71623
After power up, the IDT72V71623 should be reset. During reset, the internal
registers are put into their default state and all TX outputs are put into three-state.
After reset however, the state of Connection Memory is unknown. As such, the
outputs should be put in high-impedance by holding the ODE low. While the ODE
is low, the microprocessor can initialize the device, program the active paths,
and disable unused outputs by programming the OE bit in Connection Memory.
Once the device is configured, the ODE pin (or OSB bit depending on
initialization) can be switched. See Figure 8.
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COMMERCIAL TEMPERATURE RANGE
IDT72V71623 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 2,048 x 2,048
TABLE 2 — INTERNAL REGISTER AND ADDRESS MEMORY MAPPING
TABLE 1 — OUTPUT HIGH-IMPEDANCE CONTROL
MOD1-0 BITS IN ODE PIN OSB BIT IN CONTROL OUTPUT DRIVER
CONNECTION MEMORY REGISTER STATUS
1 and 1 Don’t Care Don’t Care Per Channel High-Impedance
Don’t Care 0 0 High-Impedance
Any, other than 1 and 1 0 1 Enable
Any, other than 1 and 1 1 0 Enable
Any, other than 1 and 1 1 1 Enable
A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 R/W Location
1 1 STA3 STA2 STA1 STA0 CH7 CH6 CH5 CH4 CH3 CH2 CH1 CH0 R Data Memory
1 0 STA3 STA2 STA1 STA0 CH7 CH6 CH5 CH4 CH3 CH2 CH1 CH0 R/W Connection Memory
0 100 0xxxxx xxxxR/WControl Register
0 100 1xxxxx xxxxRFrame Align Register
0 101 0xxxxx xxxxR/W FOR0
0 101 1xxxxx xxxxR/W FOR1
0 110 0xxxxx xxxxR/W FOR2
0 110 1xxxxx xxxxR/W FOR3
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COMMERCIAL TEMPERATURE RANGE
IDT72V71623 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 2,048 x 2,048
Figure 1. Constant Delay Mode Examples
1 Frame (125µsec) 1 Frame (125µsec) 1 Frame (125µsec)
• • • •
RX 2 Mb/s A• • • • Q
TX 16 Mb/s Q(1) • • • • A(2)
DR3-0 = 9H
NOTES:
1. Timeslot Q ⎯ 2 Frames ⎯ minimum delay.
2. Timeslot A ⎯ 3 Frames - 1 output channel period ⎯ maximum delay.
1 Channel @ 2 Mb/s
ABCDEF
RX 2 Mb/s
Figure 2. Variable Delay Mode Examples
TX 8 Mb/s
RX 16 Mb/s
TX 8 Mb/s A or B(1,2) C or D
DR3-0 = 4H(3)
NOTES:
1 . If data is switched at least +3 channel periods of the slower data rate, the data will transmit out in the same frames except if the input and output data rates are both 16 Mb/s
(DR3-0 = 0x3).
2. Delay is a function of input channel and output channel combinations, and input and output stream data rate.
3. See switching mode table for input and output speed combinations.
4. When the input and output data rates are both 16 Mb/s, the minimum delay achievable is 6 time slots.
2 Mb/s → 8 Mb/s
1 Channel @ 8 Mb/s
A(1,2)
DR3-0 = AH(3)
ABC DEF GH I J
1 Channel @ 8 Mb/s
1 Channel @ 16 Mb/s
2 Mb/s → 16 Mb/s
16 Mb/s → 8 Mb/s
RX 16 Mb/s
DR3-0 = 3H(3,4)
ABCDEFGHI JKLMNO PQR
TX 16 Mb/s ABBBA
16 Mb/s → 16 Mb/s
10
COMMERCIAL TEMPERATURE RANGE
IDT72V71623 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 2,048 x 2,048
TABLE 3 — CONTROL REGISTER (CR) BITS
TABLE 4 — CONNECTION MEMORY BITS
Reset Value: 4000H.
Bit Name Description
15 Reset (Software Reset) A one will reset the device and have the same effect as of the RESET pin. Must be zero for normal operation. Before beginning
operation, this bit must be held zero for minimum 100ns.
14 Unused Must be one for proper operation.
13 OEPOL When 1, a one on OEI pin denotes an active state on the output data stream; zero on OEI pin denotes high-impedance state.
(Output Enable Polarity) When 0, a one denotes high-impedance and a zero denotes an active state.
12 Unused Must be zero for normal operation.
11 MBP When 1, the Connection Memory block programming feature is ready for the programming of Connection Memory high bits,
(Memory Block Program) bit 13 to bit 15. When 0, this feature is disabled.
10 Unused Must be zero for normal operation.
9-7 BPD2-0 These bits carry the value to be loaded into the Connection Memory block whenever the memory block programming feature is
(Block Programming Data) activated. After the MBP bit in the control register is set to 1 and the BPE bit is set to 1, the contents of the bits BPD2-0 are
loaded into bit 15 and 13 of the Connection Memory. Bit 12 to bit 0 of the Connection Memory are set to 0.
6 BPE A zero to one transition of this bit enables the memory block programming function. The BPE and BPD2-0 bits in the CR register
(Begin Block Programming have to be defined in the same write operation. Once the BPE bit is set HIGH, the device requires two frames to complete the
Enable) block programming. After the programming function has finished, the BPE bit returns to zero to indicate the operation is completed.
When the BPE=1, the other bit in the control register must not be changed for two frames to ensure proper operation.
5 OSB When ODE=0 and OSB=0, the output drivers of transmit serial streams are in high-impedance mode. When ODE=1 or OSB=1,
(Output Stand By) Connection Memory Mod 1 - 0 ≠ 1 and 1, the output serial stream drivers function normally. When both Connection Memory Mod
1 - 0 = 1 and 1, the output drivers of the transmit serial streams are in high impedance mode. Please refer to Table 1.
4 SFE A zero to one transition in this bit starts the frame evaluation procedure. When the CFE bit in the FAR register changes from zero
(Start Frame Evaluation) to one, the evaluation procedure stops. To start another frame evaluation cycle, set this bit to zero for at least one frame.
3-0 DR3-0 Input/Output data rate selection. See Table 5 for detailed programming.
1514131211109876543210
SRS 1 OEP 0 MBP 0 BPD2 BPD1 BPD0 BPE OSB SFE DR3 DR2 DR1 DR0
Bit Name Description
15 LPBK When 1, the RX n channel m data comes from the TX n channel m. For proper per channel loopback operations, set the delay
(Per Channel Loopback) offset register bits OFn[2:0] to zero for the streams which are in the loopback mode. This feature is offered only when
DR3-0 = 0000, 0001 or 0010 is selected via the control register.
14,13 MOD1-0 MOD1 MOD0 MODE
(Switching Mode Selection) 0 0 Variable Delay mode
0 1 Constant Delay mode
1 0 Processor mode
1 1 Output High-Impedance
12 Unused Must be zero for normal operation.
11-8 SAB3-0 The binary value is the number of the data stream for the source of the connection. Unused SAB bits must be zero for proper
(Source Stream Address Bits) operation.
7-0 CAB7-0 The binary value is the number of the channel for the source of the connection. Unused CAB bits must be zero for proper
(Source Channel Address Bits) operation.
1514131211109876543210
LPBK MOD1 MOD0 0 SAB3 SAB2 SAB1 SAB0 CAB7 CAB6 CAB5 CAB4 CAB3 CAB2 CAB1 CAB0
11
COMMERCIAL TEMPERATURE RANGE
IDT72V71623 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 2,048 x 2,048
Figure 3. Regular Switch Mode
Figure 4. Mux/Demux Mode
TABLE 5 — SWITCH MODES
Switching Control Bits Data Rate bits/s Clock Rate
Mode DR3 DR2 DR1 DR0 Receive Streams Transmit Streams MHz
0 0 0 0 2 M on RX0-15 2 M on TX0-15 4
Regular 0 0 0 1 4 M on RX0-15 4 M on TX0-15 8
0 0 1 0 8 M on RX0-15 8 M on TX0-15 1 6
0 0 1 1 16 M on RX0-7 16 M on TX0-7 1 6
0 1 0 0 2 M on RX0-15 8 M on TX0-3 1 6
0 1 0 1 8 M on RX0-3 2 M on TX0-15 16
0 1 1 0 4 M on RX0-15 8 M on TX0-7 1 6
Mux/Demux 0 1 1 1 8 M on RX0-7 4 M on TX0-15 1 6
1 0 0 0 16 M on RX0-1 2 M on TX0-15 1 6
1 0 0 1 2 M on RX0-15 16 M on TX0-3 1 6
1 0 1 0 16 M on RX0-7 8 M on TX0-15 1 6
1 0 1 1 8 M on RX0-15 16 M on TX0-7 1 6
RX0
RX15
TX0
TX15
5903 drw04
2, 4, 8 Mb/s 2, 4, 8 Mb/s
DR3-0 = 0H, 1H, 2H
RX0
RX7
RX8
RX15
16 Mb/s
DR3-0 = 3H
TX0
TX7
TX8
TX15
16 Mb/s
OPEN
16 Mb/s → 16 Mb/s
2 Mb/s → 2 Mb/s, 4 Mb/s → 4 Mb/s, 8 Mb/s → 8 Mb/s
TX0
TX3
TX4
TX15
5903 drw05
2 Mb/s
8 Mb/s
DR3-0 = 4H
16 Mb/s
DR3-0 = 8H
TX0
TX15
2 Mb/s
OPEN
RX4
RX15
RX0
RX3
RX0
RX15
16 Mb/s → 2 Mb/s
2 Mb/s → 8 Mb/s
12
COMMERCIAL TEMPERATURE RANGE
IDT72V71623 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 2,048 x 2,048
TABLE 6 — FRAME ALIGNMENT REGISTER (FAR) BITS
Figure 5. Example for Frame Alignment Measurement
Reset Value: 0000H.
Bit Name Description
15-13 Unused Must be zero for normal operation
1 2 CFE (Complete When CFE = 1, the frame evaluation is completed and bits FD10 to FD0 bits contains a valid frame alignment offset. This bit is reset to
Frame Evaluation) zero, when SFE bit in the CR register is changed from 1 to 0.
11 FD11 The falling edge of FE (or rising edge for GCI mode) is sampled during the CLK-high phase (FD11 = 1) or during the CLK-low phase
(Frame Delay Bit 11) (FD11 = 0). This bit allows the measurement resolution to ½ CLK cycle.
10-0 FD10-0 The binary value expressed in these bits refers to the measured input offset value. These bits are rest to zero when the SFE bit of the
(Frame Delay Bits) CR register changes from 1 to 0. (FD10 – MSB, FD0 – LSB)
1514131211109876543210
0 0 0 CFE FD11 FD10 FD9 FD8 FD7 FD6 FD5 FD4 FD3 FD2 FD1 FD0
0 1 2 3 4 5 6 7 8 910111213141516
ST-BUS® Frame
CLK
Offset Value
FE Input
0123456789101112131415
GCI Frame
CLK
Offset Value
FE Input
(FD[10:0] = 06H)
(FD11 = 0, sample at CLK LOW phase)
(FD[10:0] = 09H)
(FD11 = 1, sample at CLK HIGH phase)
5903 drw06
13
COMMERCIAL TEMPERATURE RANGE
IDT72V71623 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 2,048 x 2,048
TABLE 7 — FRAME INPUT OFFSET REGISTER (FOR) BITS
NOTE:
1. n denotes an input stream number from 0 to 31.
Reset Value: 0000H for all FOR registers.
1514131211109876543210
OF32 OF31 OF30 DLE3 OF22 OF21 OF20 DLE2 OF12 OF11 OF10 DLE1 OF02 OF01 OF00 DLE0
FOR0 Register
1514131211109876543210
OF72 OF71 OF70 DLE7 OF62 OF61 OF60 DLE6 OF52 OF51 OF50 DLE5 OF42 OF41 OF40 DLE4
FOR1 Register
1514131211109876543210
OF112 OF111 OF110 DLE11 OF102 OF101 OF100 DLE10 OF92 OF91 OF90 DLE9 OF82 OF81 OF80 DLE8
FOR2 Register
1514131211109876543210
OF152 OF151 OF150 DLE15 OF142 OF141 OF140 DLE14 OF132 OF131 OF130 DLE13 OF122 OF121 OF120 DLE12
FOR3 Register
Name(1) Description
OFn2, OFn1, OFn0 These three bits define how long the serial interface receiver takes to recognize and store bit 0 from the RX input pin: i.e., to start a new frame.
(Offset Bits 2, 1 & 0) The input frame offset can be selected to +4.5 clock periods from the point where the external frame pulse input signal is applied to the F0i
input of the device. See Figure 6.
DLEn ST-BUS® mode: DLEn = 0, if clock rising edge is at the ¾ point of the bit cell.
(Data Latch Edge) DLEn = 1, if when clock falling edge is at the ¾ of the bit cell.
GCI mode: DLEn = 0, if clock falling edge is at the ¾ point of the bit cell.
DLEn = 1, if when clock rising edge is at the ¾ of the bit cell.
14
COMMERCIAL TEMPERATURE RANGE
IDT72V71623 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 2,048 x 2,048
TABLE 8 — MAXIMUM ALLOWABLE SKEW
Switching Control Bits Data Rate bits/s Maximum
Mode DR3 DR2 DR1 DR0 Receive Streams Transmit Streams allowable skew
0 0 0 0 2 M on RX0-15 2 M on TX0-15 +4.5
Regular 0 0 0 1 4 M on RX0-15 4 M on TX0-15 +4.5
0 0 1 0 8 M on RX0-15 8 M on TX0-15 +4.5
0 0 1 1 16 M on RX0-7 16 M on TX0-7 +2.5
0 1 0 0 2 M on RX0-15 8 M on TX0-3 +1.5
0 1 0 1 8 M on RX0-3 2 M on TX0-15 +4.5
0 1 1 0 4 M on RX0-15 8 M on TX0-7 +1.5
Mux/Demux 0 1 1 1 8 M on RX0-7 4 M on TX0-15 +4.5
1 0 0 0 16 M on RX0-3 2 M on TX0-15 +2.5
1 0 0 1 2 M on RX0-15 16 M on TX0-3 +1.5
1 0 1 0 16 M on RX0-7 8 M on TX0-15 +4.5
1 0 1 1 8 M on RX0-15 16 M on TX0-7 +4.5
15
COMMERCIAL TEMPERATURE RANGE
IDT72V71623 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 2,048 x 2,048
Figure 6. Examples for Input Offset Delay Timing in 16 Mb/s mode
NOTE:
1. See Table 8 for maximum allowable offsets.
TABLE 9 — OFFSET BITS (OFN2, OFN1, OFN0, DLEN) & FRAME DELA Y BITS
(FD11, FD2-0) Measurement Result from Corresponding
Input Stream Frame Delay Bits Offset Bits
Offset FD11 FD2 FD1 FD0 OFn2 OFn1 OFn0 DLEn
No clock period shift (Default) 10000000
+ 0.5 clock period shift 00000001
+ 1.0 clock period shift 10010010
+ 1.5 clock period shift 00010011
+ 2.0 clock period shift 10100100
+ 2.5 clock period shift 00100101
+ 3.0 clock period shift 10110110
+ 3.5 clock period shift 00110111
+ 4.0 clock period shift 11001000
+ 4.5 clock period shift 01001001
ST-BUS® F0i
RX Stream
(16.384 Mb/s)
5903 drw07
Bit 7
Bit 7
Bit 6
Bit 0
Bit 0
Bit 1
Bit 0 Bit 2
Bit 1 Bit 2
Bit 1 Bit 2
Bit 6 Bit 5 Bit 4
Bit 5Bit 6
Bit 7 Bit 5 Bit 4
16.384 MHz
CLK
offset = 0, DLE = 0
offset = 1, DLE = 0
offset = 0, DLE = 1
GCI F0i
offset = 0, DLE = 0
offset = 1, DLE = 0
offset = 0, DLE = 1
RX Stream
(16.384 Mb/s)
16.384 MHz
CLK
RX Stream
(16.384 Mb/s)
RX Stream
(16.384 Mb/s)
RX Stream
(16.384 Mb/s)
RX Stream
(16.384 Mb/s)
16
COMMERCIAL TEMPERATURE RANGE
IDT72V71623 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 2,048 x 2,048
Figure 6. Examples for Input Offset Delay Timing in 8 Mb/s, 4 Mb/s and 2 Mb/s mode (Continued)
ST-BUS® F0i
RX Stream
5903 drw08
Bit 7
Bit 7
CLK
Bit 7
Bit 7
denotes the 3/4 point of the bit cell
offset = 0, DLE = 0
offset = 1, DLE = 0
offset = 0, DLE = 1
offset = 1, DLE = 1
GCI F0i
Bit 0
Bit 0
CLK
Bit 0
Bit 0
denotes the 3/4 point of the bit cell
offset = 0, DLE = 0
offset = 1, DLE = 0
offset = 0, DLE = 1
offset = 1, DLE = 1
RX Stream
RX Stream
RX Stream
RX Stream
RX Stream
RX Stream
RX Stream
17
COMMERCIAL TEMPERATURE RANGE
IDT72V71623 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 2,048 x 2,048
JTAG SUPPORT
The IDT72V71623 JTAG interface conforms to the Boundary-Scan stan-
dard IEEE-1149.1. This standard specifies a design-for-testability technique
called Boundary-Scan test (BST). The operation of the boundary-scan
circuitry is controlled by an external test access port (TAP) Controller.
TEST ACCESS PORT (TAP)
The Test Access Port (TAP) provides access to the test functions of the
IDT72V71623. It consists of three input pins and one output pin.
•Test Clock Input (TCK)
TCK provides the clock for the test logic. The TCK does not interfere with
any on-chip clock and thus remain independent. The TCK permits shifting of
test data into or out of the Boundary-Scan register cells concurrently with the
operation of the device and without interfering with the on-chip logic.
•Test Mode Select Input (TMS)
The logic signals received at the TMS input are interpreted by the TAP
Controller to control the test operations. The TMS signals are sampled at the
rising edge of the TCK pulse. This pin is internally pulled to VCC when it is not
driven from an external source.
•Test Data Input (TDI)
Serial input data applied to this port is fed either into the instruction register
or into a test data register, depending on the sequence previously applied to
the TMS input. Both registers are described in a subsequent section. The
received input data is sampled at the rising edge of TCK pulses. This pin is
internally pulled to VCC when it is not driven from an external source.
•Test Data Output (TDO)
Depending on the sequence previously applied to the TMS input, the
contents of either the instruction register or data register are serially shifted out
towards the TDO. The data out of the TDO is clocked on the falling edge of the
TCK pulses. When no data is shifted through the boundary scan cells, the TDO
driver is set to a high-impedance state.
•Test Reset (TRST)
Reset the JTAG scan structure. This pin is internally pulled to VCC.
INSTRUCTION REGISTER
In accordance with the IEEE-1149.1 standard, the IDT72V71623 uses
public instructions. The IDT72V71623 JTAG Interface contains a two-bit
instruction register. Instructions are serially loaded into the instruction register
from the TDI when the TAP Controller is in its shifted-IR state. Subsequently,
the instructions are decoded to achieve two basic functions: to select the test data
register that may operate while the instruction is current, and to define the serial
test data register path, which is used to shift data between TDI and TDO during
data register scanning.
Value Instruction
00 EXTEST
11 BYPASS
01 or 10 SAMPLE/PRELOAD
TEST DATA REGISTER
As specified in IEEE-1149.1, the IDT72V71623 JTAG Interface contains
two test data registers:
•The Boundary-Scan register
The Boundary-Scan register consists of a series of Boundary-Scan cells
arranged to form a scan path around the boundary of the IDT72V71623 core
logic.
•The Bypass Register
The Bypass register is a single stage shift register that provides a one-bit
path from TDI to its TDO. The IDT72V71623 boundary scan register bits are
shown in Table 10. Bit 0 is the first bit clocked out. All three-state enable bits are
active high.
JTAG Instruction Register Decoding
18
COMMERCIAL TEMPERATURE RANGE
IDT72V71623 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 2,048 x 2,048
TABLE 10 — BOUNDARY SCAN REGISTER BITS
Boundry Scan Bit 0 to bit 168
Device Pin Three-State Output Input
Control Scan Cell Scan Cell
IC 93
IC 94
IC 95
IC 96
OEI7 97 98
OEI6 99 100
OEI5 101 102
OEI4 103 104
OEI3 105 106
OEI2 107 108
OEI1 109 110
OEI0 111 112
IC 113
IC 114
IC 115
IC 116
IC 117
IC 118
IC 119
IC 120
TX15 121 122
TX14 123 124
TX13 125 126
TX12 127 128
TX11 129 130
TX10 131 132
TX9 133 134
TX8 135 136
RX15 137
RX14 138
RX13 139
RX12 140
RX11 141
RX10 142
RX9 143
RX8 144
TX7 145 146
TX6 147 148
TX5 149 150
TX4 151 152
TX3 153 154
TX2 155 156
TX1 157 158
TX0 159 160
RX7 161
RX6 162
RX5 163
RX4 164
RX3 165
RX2 166
RX1 167
RX0 168
Boundary Scan Bit 0 to bit 168
Device Pin Three-State Output Input
Control Scan Cell Scan Cell
ODE 0
RESET 1
CLK 2
F0i 3
FE/HCLK 4
WFPS 5
DS 6
CS 7
R/W8
A0 9
A1 10
A2 11
A3 12
A4 13
A5 14
A6 15
A7 16
A8 17
A9 18
A10 19
A11 20
IC 21
A12 22
A13 23
DTA 24
D15 25 26 27
D14 28 29 30
D13 31 32 33
D12 34 35 36
D11 37 38 39
D10 40 41 42
D9 43 44 45
D8 46 47 48
D7 49 50 51
D6 52 53 54
D5 55 56 57
D4 58 59 60
D3 61 62 63
D2 64 65 66
D1 67 68 69
D0 70 71 72
OEI15 73 74
OEI14 75 76
OEI13 77 78
OEI12 79 80
OEI11 81 82
OEI10 83 84
OEI9 85 86
OEI8 87 88
IC 89
IC 90
IC 91
IC 92
19
COMMERCIAL TEMPERATURE RANGE
IDT72V71623 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 2,048 x 2,048
Symbol Parameter Min. Typ. Max. Units
ICC (2) Supply Current - - 75 mA
IIL(3,4) Input Leakage (input pins) - - 60 µA
IOZ(3,4) High-impedance Leakage - - 60 µA
VOH(5) Output HIGH Voltage 2.4 - - V
VOL(6) Output LOW Voltage - - 0.4 V
Symbol Rating Level Unit
VTT TTL Threshold 1.5 V
VHM TTL Rise/Fall Threshold Voltage HIGH 2.0 V
VLM TTL Rise/Fall Threshold Voltage LOW 0.8 V
DC ELECTRICAL CHARACTERISTICS
AC ELECTRICAL CHARACTERISTICS - TIMING PARAMETER
MEASUREMENT VOLTAGE LEVELS
NOTES:
1. Voltages are with respect to ground (GND) unless otherwise stated.
2. Outputs unloaded.
3. 0 ≤ V ≤ VCC.
4. Maximum leakage on pins (output or I/O pins in high-impedance state) is over an applied voltage (V).
5. IOH = 10 mA.
6. IOL = 10 mA.
S1 is open circuit except when testing output
levels or high-impedance states.
S2 is switched to VCC or GND when testing
output levels or high-impedance states.
Figure 7. Output Load
Symbol Parameter Min. Max. Unit
VCC Supply Voltage 3.0 3.6 V
Vi Voltage on Digital Inputs GND -0.3 5.3 V
IOCurrent at Digital Outputs -50 50 mA
TSStorage Temperature -55 +125 °C
PDPackage Power Dissapation ⎯2W
NOTE:
1. Exceeding these values may cause permanent damage. Functional operation under
these conditions is not implied.
ABSOLUTE MAXIMUM RATINGS(1) RECOMMENDED OPERATING
CONDITIONS(1)
NOTE:
1. Voltages are with respect to Ground unless otherwise stated.
Symbol Parameter Min. Typ. Max. Unit
VCC Positive Supply 3. 0 3.3 3. 6 V
VIH Input HIGH Voltage 2. 0 ⎯5.3 V
VIL Input LOW Voltage ⎯⎯0.8 V
TOP Operating Temperature -40 25 +85 °C
Commercial
Test Point
Output
Pin
CL
GND
S1
RL
VCC
GND
5903 drw09
S2
20
COMMERCIAL TEMPERATURE RANGE
IDT72V71623 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 2,048 x 2,048
AC ELECTRICAL CHARACTERISTICS - FRAME PULSE AND CLK
Symbol Parameter Min. Typ. Max. Units
tFPW(1) Frame Pulse Width (ST-BUS®, GCI)
Bit rate = 2.048 Mb/s 26 ⎯295 ns
Bit rate = 4.096 Mb/s 26 ⎯145 ns
Bit rate = 8.192 Mb/s or 16.384 Mb/s 26 ⎯65 ns
tFPS(1) Frame Pulse Setup time before CLK falling (ST-BUS® or GCI) 5 ⎯⎯ns
tFPH(1) Frame Pulse Hold Time from CLK falling (ST-BUS® or GCI) 10 ⎯⎯ns
tCP(1) CLK Period
Bit rate = 2.048 Mb/s 1 90 ⎯300 ns
Bit rate = 4.096 Mb/s 1 10 ⎯150 ns
Bit rate = 8.192 Mb/s or 16.384 Mb/s 58 ⎯70 ns
tCH(1) CLK Pulse Width HIGH
Bit rate = 2.048 Mb/s 85 ⎯150 ns
Bit rate = 4.096 Mb/s 50 ⎯75 ns
Bit rate = 8.192 Mb/s or 16.384 Mb/s 20 ⎯40 ns
tCL(1) CLK Pulse Width LOW
Bit rate = 2.048 Mb/s 85 ⎯150 ns
Bit rate = 4.096 Mb/s 50 ⎯75 ns
Bit rate = 8.192 Mb/s or 16.384 Mb/s 20 ⎯40 ns
tr, tfClock Rise/Fall Time ⎯⎯10 ns
tHFPW(2) Wide Frame Pulse Width
HCLK = 4.096 MHz 244 ns
HCLK = 8.192 MHz 122 ns
tHFPS(2) Frame Pulse Setup Time before HCLK 4 MHz falling 5 0 ⎯150 ns
tHFPH(2) Frame Pulse Hold Time from HCLK 4 MHz falling 50 ⎯150 ns
tHFPS(2) Frame Pulse Setup Time before HCLK 8 MHz rising 45 ⎯90 ns
tHFPH(2) Frame Pulse Hold Time from HCLK 8 MHz rising 45 ⎯90 ns
tHCP(2) HCLK Period
@ 4.096 MHz 244 ns
@ 8.192 MHz 122 ns
tHr, tHf HCLK Rise/Fall Time ⎯⎯10 ns
tDIF(3) Delay between falling edge of HCLK and falling edge of CLK -1 0 ⎯10 ns
NOTES:
1. WFPS Pin = 0.
2. WFPS Pin = 1.
3 . WFPS Pin = 0 or 1.
21
COMMERCIAL TEMPERATURE RANGE
IDT72V71623 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 2,048 x 2,048
Figure 8. Reset and ODE Timing
Figure 9. Serial Output and External Control Figure 10. Output Driver Enable (ODE)
RESET
TX
ODE
tRS
tZR tRZ
tRZ
tODE
5903
drw10
CLK
(ST-BUS® or
WFPS mode)
TX
TX VALID DATA
VALID DATA
tZD
CLK
(GCI mode)
590 3 drw11
tDZ ODE
TX VALID DATA
5903
drw 12
tODE tODE
22
COMMERCIAL TEMPERATURE RANGE
IDT72V71623 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 2,048 x 2,048
AC ELECTRICAL CHARACTERISTICS - MICROPROCESSOR INTERFACE TIMING
NOTES:
1. CL= 150pF
2. RL = 1K
3. High-Impedance is measured by pulling to the appropriate rail with RL, with timing corrected to cancel time taken to discharge CL.
4. To achieve one clock cycle fast memory access, this setup time, tDSS should be met. Otherwise, worst case memory access operation is determined by tAKD.
Symbol Parameter Min. Typ. Max. Units
tCSS CS Setup from DS falling 0 ns
tRWS R/W Setup from DS falling 3 ns
tADS Address Setup from DS falling 2 ns
tCSH CS Hold after DS rising 0 ns
tRWH R/W Hold after DS Rising 3 ns
tADH Address Hold after DS Rising 2 ns
tDDR(1) Data Setup from DTA LOW on Read 2 ns
tDHR(1,2,3) Data Hold on Read 1 0 1 5 25 ns
tDSW Data Setup on Write (Register Write) 10 ns
tSWD Valid Data Delay on Write (Connection Memory Write) - 0ns
tDHW Data Hold on Write 5 ns
tDSPW DS Pulse Width 5 ns
tCKAK Clock to ACK 35 ns
tAKD (1) Acknowledgment Delay:
Reading/Writing Registers 30 ns
Reading/Writing Memory @ 2.048 Mb/s 3 4 5 n s
@ 4.096 Mb/s 2 0 0 n s
@ 8.192 Mb/s or 16.384 Mb/s 1 20 ns
tAKH (1,2,3) Acknowledgment Hold Time 15 ns
tDSS (4) Data Strobe Setup Time 2 ns
23
COMMERCIAL TEMPERATURE RANGE
IDT72V71623 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 2,048 x 2,048
Figure 11. Asyncronous Bus Timing
Figure 12. Syncronous Bus Timing
DS
CS
VALID WRITE ADDRESS
A0-A13
t
CSS
t
CSH
R/W
t
RWS
t
RWH
t
ADS
t
ADH
VALID WRITE
DATA
D0-D15
t
DSW
t
DHW
DTA
t
AKD
t
AKH
t
CSS
t
CSH
t
RWS
t
RWH
VALID READ ADDRESS
t
ADS
t
ADH
VALID READ DATA
t
DDR
t
DHR
t
AKD
t
AKH
5903 drw13
5903 drw14
D0-D15
CS
DTA
VALID WRITE
ADDRESS
R/W
A0-A13
DS
CLK GCI
CLK ST-BUS
tDSS
tCSS tCSH
tRWS tRWH
VALID READ
ADDRESS
tADS tADH
VALID READ
DATA
tDHR
tCKAK tAKH
tDDR
tDSPW
tDSS
tCSS tCSH
tRWS tRWH
tADS tADH
VALID WRITE
DATA
tSWD tDHW
tCKAK tAKH
24
COMMERCIAL TEMPERATURE RANGE
IDT72V71623 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 2,048 x 2,048
Figure 13. Output Enable Indicator Timing (8 Mb/s ST-BUS® )
tCP tCH tCL trtf
tFPW
tFPH
tFPS
F0i
CLK
16.384 MHz
5903 drw15
Bit 5Bit 6Bit 7 Bit 4
tSOD
Bit 1Bit 2
Bit 3 Bit 0
tZD
TX 8 Mb/s
tOEIE
tOEIE
OEI(1)
tOEID
tOEID
tDZ
OEI(2)
NOTES:
1. When OEPOL = 1, OEI is HIGH when TX is active and LOW when TX is in three-state.
2. When OEPOL = 0, OEI is LOW when TX is active and HIGH when TX is in three-state.
25
COMMERCIAL TEMPERATURE RANGE
IDT72V71623 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 2,048 x 2,048
Figure 14. WFPS Timing
t
CP
t
CH
t
r
t
f
t
CL
t
HCH
t
HCL
t
Hf
t
Hr
Bit 0 Bit 7 Bit 6 Bit 5 Bit 4
t
SIS
Bit 3 Bit 2 Bit 1 Bit 0
t
SIH
RX 8 Mb/s
Bit 1
5903 drw16
RX 16 Mb/s
Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7Bit 2 Bit 1
t
SIH
t
SIS
Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Bit 1
t
SOD
TX 16 Mb/s
Bit 2
Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
HCLK-
4.096 MHz
TX 8 Mb/s
t
DIF
t
Hf
t
Hr
HCLK-
8.192 MHz
t
DIF
CLK-
16.384 MHz
t
HFPH
F0i
t
HFPS
t
HFPW
Bit 1
t
SOD
t
HCL
t
HCH
t
HCP
t
HCP
26
COMMERCIAL TEMPERATURE RANGE
IDT72V71623 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 2,048 x 2,048
Symbol Parameter Min. Typ. Max. Units
tSIS RX Setup Time 2 ⎯⎯ns
tSIH RX Hold Time 1 0 ⎯⎯ns
tSOD TX Delay – Active to Active ⎯⎯22 ns
tDZ(1) TX Delay – Active to High-Z ⎯⎯22 ns
tZD(1) TX Delay – High-Z to Active ⎯⎯22 ns
tODE(1) Output Driver Enable (ODE) Delay ⎯⎯30 ns
tOEIE Output Enable Indicator (OEI) Enable ⎯⎯40 ns
tOEID Output Enable Indicator (OEI) Disable ⎯⎯25 ns
tRZ Active to High-Z on Master Reset ⎯⎯30 ns
tZR High-Z to Active on Master Reset ⎯⎯30 ns
tRs Reset pulse width 100 ⎯⎯ns
AC ELECTRICAL CHARACTERISTICS(1) ⎯ SERIAL STREAM (ST-BUS® and GCI)
NOTE:
1. High-Impedance is measured by pulling to the appropriate rail with RL (1KΩ), with timing corrected to cancel time taken to discharge CL (150 pF).
27
COMMERCIAL TEMPERATURE RANGE
IDT72V71623 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 2,048 x 2,048
tSIS tSIH
5903 drw17
TX 8 Mb/s
RX 8 Mb/s
TX 4 Mb/s
RX 4 Mb/s
Bit 7
tSOD
Bit 0 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7
Bit 0Bit 1 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1
tSOD
Bit 7
Bit 0 Bit 6 Bit 5 Bit 4 Bit 3
tSIS tSIH
Bit 7 Bit 6 Bit 5 Bit 4Bit 0
TX 2 Mb/s
RX 2 Mb/s
tSOD
Bit 7Bit 0 Bit 6 Bit 5
tSIS tSIH
Bit 7 Bit 6Bit 0
Bit 1
Bit 0
tFPW
tFPHtFPS
F0i
CLK-
16.384 MHz
TX 16 Mb/s
RX 16 Mb/s
Bit 7
Bit 0
tSIS tSIH
Bit 7
tSOD
Bit 1
Bit 2 Bit 5
Bit 6 Bit 3
Bit 4 Bit 1
Bit 2 Bit 7
Bit 0 Bit 5
Bit 6 Bit 3
Bit 4 Bit 1
Bit 2 Bit 7
Bit 0
Bit 0
Bit 1
Bit 2 Bit 5
Bit 6 Bit 3
Bit 4 Bit 1
Bit 2 Bit 7
Bit 0 Bit 5
Bit 6 Bit 3
Bit 4 Bit 1
Bit 2 Bit 7
Bit 0
tCP
tCH tCL
trtf
Figure 15. ST-BUS® Timing
Figure 16. GCI Timing
t
SIS
t
SIH
Bit 7
Bit 6 Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7
t
SIS
t
SIH
Bit 0 Bit 1 Bit 2 Bit 3Bit 7
5903 drw18
Bit 0 Bit 1Bit 7
t
SIS
t
SIH
TX 8 Mb/s
RX 8 Mb/s
TX 4 Mb/s
RX 4 Mb/s
Bit 0Bit 7 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7
Bit 6
t
SOD
Bit 0
Bit 7 Bit 1 Bit 2 Bit 3
t
SOD
Bit 0Bit 7 Bit 1
t
SOD
TX 2 Mb/s
RX 2 Mb/s
TX 16 Mb/s
RX 16 Mb/s
t
FPW
t
FPH
t
CP
t
r
t
f
t
FPS
t
CH
t
CL
F0i
CLK-
16.384 MHz
t
SIS
t
SIH
Bit 0
Bit 0
t
SOD
Bit 7Bit 6Bit 5 Bit 3Bit 2Bit 1 Bit 6Bit 5Bit 4 Bit 1Bit 0Bit 7 Bit 4Bit 3Bit 2 Bit 7Bit 6Bit 5
Bit 7Bit 6 Bit 3Bit 2Bit 1 Bit 6Bit 5Bit 4 Bit 1Bit 0Bit 7 Bit 4Bit 3Bit 2 Bit 7Bit 6Bit 5
28
CORPORATE HEADQUARTERS for SALES: for Tech Support:
2975 Stender Way 800-345-7015 or 408-727-6116 408-330-1552
Santa Clara, CA 95054 fax: 408-492-8674 email: telecomhelp@idt.com
www.idt.com
ORDERING INFORMATION
DATASHEET DOCUMENT HISTORY
6/07/2000 pgs. 3 and 4.
10/10/2000 pgs. 1 through 28.
11/20/2000 pgs. 10 and 11.
03/09/2001 pg. 19
08/20/2001 pg. 22.
10/22/2001 pg. 1.
1/04/2002 pgs. 1 and 19.
5/17/2002 pg. 26
3/10/2005 pgs. 1, 4, 6, 10, and 26
3/22/2005 pgs. 1-3, 26, 28
3/23/2005 pgs. 4, 5, 13, 28
2/09/2009 pg. 28 removed IDT from orderable part number
5903 drw19
XXXXXX
Device Type
X
Package Process/
Temperature
Range
XX
BLANK Commercial (-40°C to +85°C)
72V71623 2,048 x 2,048 ⎯ 3.3V Time Slot Interchange Digital Switch with Rate Matching
BC
BCG
DA
DAG
Ball Grid Array (BGA, BC144)
Green - Ball Grid Array (BGA, BCG144)
Thin Quad Flatpacks (TQFP, DA144)
Green - Thin Quad Flatpacks (TQFP, DAG144)
