Trusted Platform Module TPM SLB 9660 TCG Rev. 116 SLB 9660VQ1.2 SLB 9660TT1.2 SLB 9660XT1.2 SLB 9660XQ1.2 Data Sheet Revision 1.0, 2014-12-12 Chip Card and Security ICs SLB 9660 TPM1.2 Trusted Platform Module Revision History Page or Item Subjects (major changes since previous revision) Revision 1.0, 2014-12-12 Initial version. Data Sheet 2 Revision 1.0 2014-12-12 SLB 9660 TPM1.2 Trusted Platform Module Table of Contents Table of Contents Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 2.1 2.2 2.3 2.4 LPC Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SYNC Field Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Localities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LPC Access Rights . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Device Types / Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4 4.1 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Typical Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5 5.1 5.2 5.3 5.4 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 13 13 14 15 6 6.1 6.2 6.3 Package Dimensions (TSSOP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Packing Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Recommended Footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Chip Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 16 17 17 7 7.1 7.2 7.3 Package Dimensions (VQFN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Packing Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Recommended Footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Chip Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 18 18 19 6 6 6 7 7 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Data Sheet 3 Revision 1.0 2014-12-12 SLB 9660 TPM1.2 Trusted Platform Module List of Figures List of Figures Figure 4-1 Figure 4-2 Figure 4-3 Figure 6-1 Figure 6-2 Figure 6-3 Figure 6-4 Figure 7-1 Figure 7-2 Figure 7-3 Figure 7-4 Data Sheet Pinout of the SLB 9660TT1.2 / SLB 9660XT1.2 (PG-TSSOP-28-2 Package, Top View) . . . . . . . . . . . 8 Pinout of the SLB 9660VQ1.2 / SLB 9660XQ1.2 (PG-VQFN-32-13 Package, Top View) . . . . . . . . . . . 9 Typical Schematic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Package Dimensions PG-TSSOP-28-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Tape & Reel Dimensions PG-TSSOP-28-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Recommended Footprint PG-TSSOP-28-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Chip Marking PG-TSSOP-28-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Package Dimensions PG-VQFN-32-13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Tape & Reel Dimensions PG-VQFN-32-13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Recommended Footprint PG-VQFN-32-13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Chip Marking PG-VQFN-32-13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4-4 Revision 1.0 2014-12-12 SLB 9660 TPM1.2 Trusted Platform Module List of Tables List of Tables Table 2-1 Table 3-1 Table 4-1 Table 4-2 Table 4-3 Table 4-4 Table 5-1 Table 5-2 Table 5-3 Table 5-4 Table 5-5 Data Sheet LT Register Access Matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Device Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Buffer Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Not Connected . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Functional Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Current Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 DC Characteristics for non-LPC Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 DC Characteristics for LPC Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5-5 Revision 1.0 2014-12-12 SLB 9660 TPM1.2 Trusted Platform Module Overview 1 Overview The SLB 9660 is a Trusted Platform Module and is based on advanced hardware security technology. This TPM implementation has achieved CC EAL4+ certification and serves as a basis for other TPM 1.2 products and firmware upgrades. It is available in different packages, see Table 3-1. It supports the LPC interface and interrupts are communicated with the serial interrupt (SERIRQ) protocol. Features * Compliant to TPM Main Specification, Version 1.2, Rev. 116 * LPC interface * Approved for Google Chromebook/Chromebox * Standard (-20..+85C) and wide temperature range (-40..+85C) * TSSOP-28 and VQFN-32 package * Optimized for battery operated devices: low standby power consumption (typ.150 A) * 24 PCRs * 6 kBytes free NV memory * Up to 10 concurrent sessions * Up to eight 2048-bit keys can be loaded into volatile storage * 16 slots for keys of up to 2048-bit * 8 monotonic counters * 1280 Bytes IO buffer * Built-in support by LinuxTM kernel version 3.10 and higher 2 LPC Interface The SLB 9660 features the Low Pin Count (LPC) interface (for a specification, please refer to [1]). From the cycle types defined in the mentioned specification, only the TPM-type cycles (read and write) are supported. All accesses with different cycle types are ignored by the device. 2.1 SYNC Field Usage Since the legacy interface is not supported anymore, the SLB 9660 will never generate SYNC ERRORs on the LPC. It will either acknowledge a cycle with SYNC OK or use a "Long Wait" SYNC field to enlarge a cycle (that means, inserting wait states on the bus). 2.2 Localities The interface explicitly does not support standard IO cycles (read and write). This implies that IO-mapped addressing of the device is not possible; only accesses via the locality-based TPM-type cycles are possible which also means that "locality none" as defined in [4] is not supported as well. For a detailed description of the locality addressing scheme and the registers located in each locality, please refer to [4] as well. Data Sheet 6 Revision 1.0 2014-12-12 SLB 9660 TPM1.2 Trusted Platform Module LPC Interface 2.3 Power Management The SLB 9660 does not support the LPC power down signal (signal LPCPD) or the clock run protocol (signal CLKRUN). Power management is handled internally; no explicit power-down or standby mode is available. The device automatically enters a low-power state after each successful command/response transaction. If a transaction is started on the LPC bus from the host platform, the device will wake immediately and will return to the low-power mode after the transaction has been finished. 2.4 LPC Access Rights The registers located in the address space of the SLB 9660 are described in the respective TCG document (please refer to [4]). The registers READFIFO and WRITEFIFO mentioned in Table 2-1 below refer to the DATAFIFO register, the names are used to state whether this register is read or written. Each register has its own access rights which describe if the register is updated on a write or can be read if the associated ACTIVE.LOCALITY is set respectively not set. If the access cycle is not accepted by the TPM, it will be master aborted (no LPC SYNC cycle will be generated and no action is done on the internal registers). Table 2-1 shows which operation is done by the TPM on each register depending on the ACTIVE.LOCALITY bit. Note: In Table 2-1, "abort" means that no valid SYNC is generated when a cycle is seen by the interface which shall be aborted. The data present in an aborted write access cycle does not change the addressed register. Table 2-1 LT Register Access Matrix ACTIVE.LOCALITY set for this locality ACTIVE.LOCALITY set for different LOCALITY ACTIVE.LOCALITY not set READ WRITE READ WRITE READ WRITE STS read write abort abort abort abort INT.ENABLE read write read abort read abort INT.VECTOR read write read abort read abort INT.STATUS read reset interrupt read abort read abort INT.CAPABILITY read - (abort) read - (abort) read - (abort) ACCESS read write read write read write READFIFO read 1) abort abort abort abort abort WRITEFIFO abort write abort abort abort abort Configuration Registers read write read abort read abort HASH.START abort write abort abort abort write2) HASH.DATA abort write abort abort abort abort HASH.END abort write3) abort abort abort abort 1) If STS.DATA.AVAIL is not set, this access is `abort'. 2) The write to HASH.START sets ACCESS.ACTIVE.LOCALITY of locality 4. 3) The write to HASH.END is an implicit release of the TPM (like a `1'-write to the ACCESS.ACTIVE.LOCALITY bit of locality 4). Data Sheet 7 Revision 1.0 2014-12-12 SLB 9660 TPM1.2 Trusted Platform Module Device Types / Ordering Information 3 Device Types / Ordering Information The SLB 9660 product family features devices with different packages. Table 3-1 shows the different versions. Table 3-1 Device Configuration Device Name Package Remarks SLB 9660TT1.2 PG-TSSOP-28-2 Standard temperature range SLB 9660VQ1.2 PG-VQFN-32-13 Standard temperature range SLB 9660XT1.2 PG-TSSOP-28-2 Enhanced temperature range SLB 9660XQ1.2 PG-VQFN-32-13 Enhanced temperature range Pin Description 18 NC LRESE T# GND 22 LA D3 VDD LA D2 LCLK LA D1 25 LFRAME# VDD GND LA D0 SERIRQ NC 28 15 Pinning_TSSOP-28-2_SLB9660.vsd 4 TPM SLB 9660TT1.2 PG-TSSOP-28-2 1 4 8 11 14 NC NC NC G ND V DD NC NC PP G PIO V DD G ND NC NC NC Figure 4-1 Pinout of the SLB 9660TT1.2 / SLB 9660XT1.2 (PG-TSSOP-28-2 Package, Top View) Data Sheet 8 Revision 1.0 2014-12-12 SLB 9660 TPM1.2 Trusted Platform Module Pin Description 26 LAD1 1 GPIO LFRAME# TPM SLB 9660VQ1.2 NC NC 22 LAD2 NC VDD PG-VQFN-32-13 NC NC LCLK 7 LAD3 18 NC LRESET# NC 10 15 Pinning_VQFN-32-13_SLB9660.vsd VDD 30 GND LAD0 SERIRQ NC NC PP GND VDD GND NC NC NC NC NC VDD VDD Figure 4-2 Pinout of the SLB 9660VQ1.2 / SLB 9660XQ1.2 (PG-VQFN-32-13 Package, Top View) Table 4-1 Buffer Types Buffer Type Description TS Tri-State pin ST Schmitt-Trigger pin OD Open-Drain pin Table 4-2 I/O Signals Pin Number Name Pin Type Buffer Type Function PG-TSSOP- PG-VQFN28-2 32-13 26 27 LAD0 I/O TS LPC Address/Data Bit 0 Multiplexed LPC command, address and data bus. Connect these pins to the LAD[3:0] pins of the LPC host. 23 24 LAD1 I/O TS LPC Address/Data Bit 1 see description of LAD0 above. 20 21 LAD2 I/O TS LPC Address/Data Bit 2 see description of LAD0 above. 17 19 LAD3 I/O TS LPC Address/Data Bit 3 see description of LAD0 above. 22 23 LFRAME# I ST LPC Framing Signal LPC framing signal. This pin is connected to the LPC LFRAME# signal and indicates the start of a new cycle on the LPC bus or the termination of a broken cycle. The signal is active low. Data Sheet 9 Revision 1.0 2014-12-12 SLB 9660 TPM1.2 Trusted Platform Module Pin Description Table 4-2 I/O Signals (continued) Pin Number Name Pin Type Buffer Type Function PG-TSSOP- PG-VQFN28-2 32-13 21 22 LCLK I ST Clock Input This pin provides the external clock for the chip and is typically connected to the PCI clock of the host. The clock frequency range is 1 MHz - 33 MHz (nominal). 16 18 LRESET# I ST Reset External reset signal. Asserting this pin unconditionally resets the device. The signal is active low and is typically connected to the PCIRST# signal of the host. 6 2 GPIO I/O OD General Purpose I/O This pin is a general purpose I/O pin. It is defined as GPIO-Express-00, please refer to [4] and the PCI-SIG ECN "Trusted Configuration Space for PCI Express". This pin may be left unconnected; however, to minimize power consumption, it shall be connected to a fixed level (either GND or VDD) via an external resistor (4.7 k..10 k). 7 31 PP I ST Physical Presence This pin should be connected to a jumper. The standard position of the jumper should connect the pin to GND. If the pin is connected to VDD, some special commands are enabled (for instance, the command TPM_ForceClear, also refer to [3]). This pin does not have an internal pull-up or pulldown resistor and must not be left floating. 27 28 SERIRQ I/O TS Serial Interrupt Request Interrupt request signal, uses the serial interrupt request protocol (see [2]). Connect to the LPC host. Data Sheet 10 Revision 1.0 2014-12-12 SLB 9660 TPM1.2 Trusted Platform Module Pin Description Table 4-3 Power Supply Pin Number Name Pin Type Buffer Type Function 5, 10, 19, 24 1, 9, 10, 20, VDD 25 PWR -- Power Supply All VDD pins must be connected externally and should be bypassed to GND via 100 nF capacitors. 4, 11, 18, 25 16, 26, 32 GND -- Ground All GND pins must be connected externally. Pin Type Buffer Type Function 1, 2, 3, 8, 12, 3, 4, 5, 6, 7, NC 13, 14, 15, 11, 12, 13, 28 14, 15, 17, 29, 30 NU -- Not Connected All pins must not be connected externally (must be left floating). 9 NU -- Not Connected This pin may be connected to the Reset signal (for backward compatibility) or may be left floating. PG-TSSOP- PG-VQFN28-2 32-13 Table 4-4 GND Not Connected Pin Number Name PG-TSSOP- PG-VQFN28-2 32-13 Data Sheet 8 NC 11 Revision 1.0 2014-12-12 SLB 9660 TPM1.2 Trusted Platform Module Pin Description 4.1 Typical Schematic Figure 4-3 shows the typical schematic for the SLB 9660. The power supply pins should be bypassed to GND with capacitors located close to the device. The physical presence input may be connected to a jumper as shown in the schematic; or it may be driven by other devices (this is application- or platform-dependent). 3.3V LAD[3:0] LCLK LAD[3:0] VDD LCLK LFRAME# LFRAME# LRESET# LRESET# SERIRQ SERIRQ 1 F GND 4x 100 nF (place close to device VDD/GND pins) J1 3.3V PP GPIO GPIO NC SLB 9660 Schematic _SLB9660 .vsd Figure 4-3 Typical Schematic Data Sheet 12 Revision 1.0 2014-12-12 SLB 9660 TPM1.2 Trusted Platform Module Electrical Characteristics 5 Electrical Characteristics This chapter lists the maximum and operating ranges for various electrical and timing parameters. 5.1 Absolute Maximum Ratings Table 5-1 Absolute Maximum Ratings Parameter Symbol Values Min. Typ. Max. Unit Note or Test Condition Supply Voltage VDD -0.3 - 3.6 V - Voltage on any pin Vmax -0.3 - VDD+0.3 V - Ambient temperature TA -20 - 85 C Standard temperature devices Ambient temperature TA -40 - 85 C Enhanced temperature devices Storage temperature TS -40 - 125 C - ESD robustness HBM: 1.5 k, 100 pF VESD,HBM - - 2000 V According to EIA/JESD22-A114-B ESD robustness VESD,CDM - - 500 V According to ESD Association Standard STM5.3.1 - 1999 Latchup immunity Ilatch 100 mA According to EIA/JESD78 Attention: Stresses above the max. values listed here may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Maximum ratings are absolute ratings; exceeding only one of these values may cause irreversible damage to the integrated circuit. 5.2 Functional Operating Range Table 5-2 Functional Operating Range Parameter Symbol Values Min. Typ. Max. Unit Note or Test Condition Supply Voltage VDD 3.0 3.3 3.6 V - Ambient temperature TA -20 - 85 C Standard temperature devices Ambient temperature TA -40 - 85 C Enhanced temperature devices - - 5 y Operating lifetime - - 5 y Average TA over lifetime - 55 - C Useful lifetime1) 1) 1) The useful lifetime of the device is 5 (five) years with a duty cycle (that means, a power-on time) of 100%. An useful lifetime of 7 (seven) years can be guaranteed for a duty cycle of 70%. For both scenarios, it is assumed that the device will be used for calculations for approximately 5% of the maximum useful lifetime. Data Sheet 13 Revision 1.0 2014-12-12 SLB 9660 TPM1.2 Trusted Platform Module Electrical Characteristics 5.3 DC Characteristics TA = 25C, VDD = 3.3V 0.3V unless otherwise noted Table 5-3 Current Consumption Parameter Symbol Values Min. Unit Note or Test Condition mA Assuming operating state S0, that means active. Note that since the device is mostly in an internal sleep state in a "typical" application, the typical average current consumption is far less than the maximum value. It is assumed that in a normal environment, the device is in an internal sleep state for approximately 90% of the operating time of the platform. Typ. Max. Current Consumption in IVDD_Active Active Mode 2.5 25 Current Consumption in IVDD_Sleep Sleep Mode 0.9 mA Pins LRESET#, LFRAME#, LADn, SERIRQ = VDD. Assuming operating state S0 with active clock. No ongoing internal TPM operation. The device is in an internal sleep state. Current Consumption in IVDD_Sleep_CS Sleep Mode with Stopped Clock 150 A Pins LRESET#, LFRAME#, LADn, SERIRQ = VDD and LCLK = GND. Assuming operating state S3 with clock stopped. Obviously, this value is zero if the TPM is not powered in S3 state (this is platform dependent). Note: Current consumption does not include any currents flowing through resistive loads on output pins! For the definition of power/operating states, please refer to the ACPI standard. Note: Device sleep mode will be entered after 30 seconds of inactivity after the last TPM command was executed. Table 5-4 DC Characteristics for non-LPC Pins Parameter Symbol Values Min. Typ. Unit Note or Test Condition Max. Input voltage high VIH 0.7 VDD VDD V GPIO and PP pins Input voltage low VIL 0 0.3 VDD V GPIO and PP pins Input high leakage current IIH -15 15 VIN = VDD, GPIO and PP pins Data Sheet 14 A Revision 1.0 2014-12-12 SLB 9660 TPM1.2 Trusted Platform Module Electrical Characteristics Table 5-4 DC Characteristics for non-LPC Pins (continued) Parameter Symbol Values Min. Input low leakage current IIL -15 Output high voltage VOH VDD-0.3 Output low voltage VOL Table 5-5 Typ. Unit Note or Test Condition A VIN = 0V, GPIO and PP pins V IOH = 1mA, Pin GPIO V IOL = 1mA, Pin GPIO Unit Note or Test Condition Max. 15 0.3 DC Characteristics for LPC Pins Parameter Symbol Values Min. Typ. Max. Input voltage high VIH 0.5 VDD VDD+0.3 V All signal pins except GPIO and PP Input voltage low VIL -0.3 0.28 VDD V All signal pins except GPIO and PP Input high leakage current IIH -10 10 A VIN = VDD, all signal pins except GPIO and PP Input low leakage current IIL -10 10 A VIN = 0V, all signal pins except GPIO and PP Output high voltage VOH 0.9 VDD V IOH = -500A, pins LAD[3:0] and SERIRQ Output low voltage VOL V IOL = 1.5mA, pins LAD[3:0] and SERIRQ 5.4 0.1 VDD Timing Some pads are disabled after deassertion of the reset signal for up to 500 s. This is especially important for the SERIRQ signal; after deassertion of the reset signal, this signal is only valid after that time has expired. Data Sheet 15 Revision 1.0 2014-12-12 SLB 9660 TPM1.2 Trusted Platform Module Package Dimensions (TSSOP) 6 Package Dimensions (TSSOP) H B 0.65 C 0.1 C 28x SEATING COPLANARITY PLANE 0.6 0.1 6.4 13 x 0.65 = 8.45 2) 0.22 +0.08 -0.03 28 0... 8 4.4 0.13) +0.073 0.127 -0. 037 1.1 MAX. 0.9 0.05 0.1 0.05 STAND OFF All dimensions are given in millimeters (mm) unless otherwise noted. The packages are "green" and RoHS compliant. 0.2 A-B, H C 2x 14 TIPS 0.1 M A B C 28x 15 1 14 9.7 0.11) A Index Marking 1) Does not include plastic or metal protrusion of 0.15 max. per side 2) Does not include dambar protrusion of 0.08 max. per side 3) Does not include interlead flash or protrusion of 0.25 max. per side PG-TSSOP-28-2, -16-PO V07 Figure 6-1 Package Dimensions PG-TSSOP-28-2 6.1 Packing Type PG-TSSOP-28-2: Tape & Reel (reel diameter 330mm), 3000 pcs. per reel 0.3 8 6.8 16 10.2 Index Marking 1.2 1.6 PG-TSSOP-28-2, -16-TP V01 Figure 6-2 Tape & Reel Dimensions PG-TSSOP-28-2 Data Sheet 16 Revision 1.0 2014-12-12 SLB 9660 TPM1.2 Trusted Platform Module Package Dimensions (TSSOP) Recommended Footprint 1.31 0.25 5.85 1.35 0.29 0.65 Copper 5.85 6.2 0.65 Solder mask Stencil apertures PG-TSSOP-28-2, -16-FP V01 Figure 6-3 Recommended Footprint PG-TSSOP-28-2 6.3 Chip Marking Line 1: SLB9660TT12 or SLB9660XT12, see Table 3-1 Line 2: G <datecode> KMC, <K> indicates assembly site code, <MC> indicates mold compound code Line 3: 00 <Lot number>, the 00 is an internal FW indication (only at manufacturing due to field upgrade option) Assembly Site Code 12345678901 G KMC 12XXXXXXXXXXX Softwarecode Mold Compound Code Lot Code ChipMarking.vsd Figure 6-4 Chip Marking PG-TSSOP-28-2 Data Sheet 17 Revision 1.0 2014-12-12 SLB 9660 TPM1.2 Trusted Platform Module Package Dimensions (VQFN) 7 Package Dimensions (VQFN) All dimensions are given in millimeters (mm) unless otherwise noted. The packages are "green" and RoHS compliant. 5 7 x 0.5 = 3.5 A 0.5 0.9 MAX. 0.1 A 2x B 17 32x 0.05 C 0.1 C 24 25 0.1 B 2x SEATING PLANE 5 3.6 0.1 16 Index Marking 9 32 8 1 3.6 0.1 C (0.2) Index Marking 32x 0.25 +0.05 -0.07 0.1 M A B C 0.05 M C (4.2) 0.4 0.05 0.05 MAX. PG-VQFN-32-13-PO V01 Figure 7-1 Package Dimensions PG-VQFN-32-13 7.1 Packing Type PG-VQFN-32-13: Tape & Reel (reel diameter 330mm), 5000 pcs. per reel 0.3 5.25 12 8 5.25 Index Marking 1.1 PG-VQFN-32-13-TP V01 Figure 7-2 Tape & Reel Dimensions PG-VQFN-32-13 7.2 Recommended Footprint Figure 7-3 shows the recommended footprint for the PG-VQFN-32-13 package. The exposed pad of the package is internally connected to GND. It shall be connect to GND externally as well. 4.1 3.6 0.5 4.1 3.6 0.7 Package outline 5 x 5 0.25 PG-VQFN-32-13-FP V01 Figure 7-3 Recommended Footprint PG-VQFN-32-13 Data Sheet 18 Revision 1.0 2014-12-12 SLB 9660 TPM1.2 Trusted Platform Module Package Dimensions (VQFN) 7.3 Chip Marking Line 1: SLB 9660 Line 2: VQ12 yy or XQ12 yy (see Table 3-1), the <yy> is an internal FW indication (only at manufacturing due to field upgrade option) Line 3: <Lot number> H <datecode> Infineon 1234567 VQ12 YY XXH Softwarecode Lot Code ChipMarking_VQFN.vsd Figure 7-4 Chip Marking PG-VQFN-32-13 Data Sheet 19 Revision 1.0 2014-12-12 SLB 9660 TPM1.2 Trusted Platform Module References References [1] --, "Low Pin Count (LPC) Interface Specification", Version 1.1, Intel [2] --, "Serialized IRQ Support for PCI Systems", Version 6.0, September 1, 1995, Cirrus Logic et al. [3] --, "TPM Main Specification", Version 1.2, Rev. 116, 2011-03-01, TCG (parts 1-3) [4] --, "TCG PC Client TPM Interface Specification (TIS)", Version 1.3, 2013-03-21, TCG Data Sheet 20 Revision 1.0 2014-12-12 SLB 9660 TPM1.2 Trusted Platform Module Terminology Terminology ESW Embedded Software HMAC Hashed Message Authentication Code LPC Low Pin Count (bus) PCR Platform Configuration Register PUBEK Public Endorsement Key SCP Symmetric Crypto Processor TCG Trusted Computing Group TPM Trusted Platform Module TSS TCG Software Stack Data Sheet 21 Revision 1.0 2014-12-12 Trademarks of Infineon Technologies AG AURIXTM, C166TM, CanPAKTM, CIPOSTM, CoolGaNTM, CoolMOSTM, CoolSETTM, CoolSiCTM, CORECONTROLTM, CROSSAVETM, DAVETM, DI-POLTM, DrBLADETM, EasyPIMTM, EconoBRIDGETM, EconoDUALTM, EconoPACKTM, EconoPIMTM, EiceDRIVERTM, eupecTM, FCOSTM, HITFETTM, HybridPACKTM, ISOFACETM, IsoPACKTM, MIPAQTM, ModSTACKTM, my-dTM, NovalithICTM, OmniTuneTM, OPTIGATM, OptiMOSTM, ORIGATM, POWERCODETM, PRIMARIONTM, PrimePACKTM, PrimeSTACKTM, PROFETTM, PROSILTM, RASICTM, REAL3TM, ReverSaveTM, SatRICTM, SIEGETTM, SIPMOSTM, SmartLEWISTM, SOLID FLASHTM, SPOCTM, TEMPFETTM, thinQ!TM, TRENCHSTOPTM, TriCoreTM. Other Trademarks VisionTM, AMBATM, ARMTM, KEILTM, MULTI-ICETM, THUMBTM of ARM Limited, UK. AUTOSARTM of AUTOSAR development partnership. CIPURSETM of OSPT Alliance. EMVTM of EMVCo, LLC (Visa Holdings Inc.). FLEXGOTM of Microsoft Corporation. HYPERTERMINALTM of Hilgraeve Incorporated. IrDATM of Infrared Data Association Corporation. MCSTM of Intel Corp. MICROWAVE OFFICETM (MWO) of Applied Wave Research Inc. TEAKLITETM of CEVA, Inc. VXWORKSTM of WIND RIVER SYSTEMS, INC. Chrome OSTM of Google, Inc. Trademarks Update 2014-07-17 www.infineon.com Edition 2014-12-12 Published by Infineon Technologies AG 81726 Munich, Germany (c) 2014 Infineon Technologies AG. All Rights Reserved. Do you have a question about any aspect of this document? Email: erratum@infineon.com Document reference Legal Disclaimer The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. 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