Preliminary MT9V032: 1/3-Inch Wide-VGA Digital Image Sensor Features 1/3-Inch Wide-VGA CMOS Digital Image Sensor MT9V032C12STM (Monochrome, Pb-Free) MT9V032C12STC (Color, Pb-Free) Features Table 1: * Micron(R) DigitalClarity(R) CMOS imaging technology * Array format: Wide-VGA, active 752H x 480V (360,960 pixels) * Global shutter photodiode pixels; simultaneous integration and readout * Monochrome or color: Near_IR enhanced performance for use with non-visible NIR illumination * Readout modes: Progressive or interlaced * Shutter efficiency: >99% * Simple two-wire serial interface * Register lock capability * Window size: User programmable to any smaller format (QVGA, CIF, QCIF, and so on). Data rate can be maintained independent of window size * Binning: 2 x 2 and 4 x 4 of the full resolution * ADC: On-chip, 10-bit column-parallel (option to operate in 12-bit to 10-bit companding mode) * Automatic controls: Auto exposure control (AEC) and auto gain control (AGC); variable regional and variable weight AEC/AGC * Support for four unique serial control register IDs to control multiple imagers on the same bus * Data output formats: * Single sensor mode: 10-bit parallel/stand-alone Parameter 1/3-inch 4.51mm(H) x 2.88mm(V) 5.35mm diagonal Active pixels 752H x 480V Pixel size 6.0m x 6.0m Color filter array Monochrome or color RGB Bayer pattern Shutter type Global shutter--TrueSNAPTM Maximum data rate 26.6 Mp/s master clock 26.6 MHz Full resolution 752 x 480 Frame rate 60 fps (at full resolution) ADC resolution 10-bit column-parallel Responsivity 4.8 V/lux-sec (550nm) Dynamic range >55dB linear; >80-100dB in HiDy mode Supply voltage 3.3V +0.3V (all supplies) Power consumption <320mW at maximum data rate; 100W standby current Operating temperature -30C to +70C Packaging 48-pin CLCC Output gain 15.3 e-/LSB Read noise 25 e-PRMS at 1X Dark current 9,042 e-/pix/s at 55C Ordering Information * Stereo sensor mode: Interspersed 8-bit serial LVDS Table 2: Applications Security High dynamic range imaging Unattended surveillance Stereo vision Video as input Machine vision Automation Traffic camera PDF: 09005aef824c9998/Source: 09005aef824c999c MT9V032_LDS_1.fm - Rev. B 3/07 EN Value Optical format Active imager size 8-bit or 10-bit serial LVDS * * * * * * * * Key Performance Parameters Available Part Numbers Part Number Description MT9V032C12STM ES MT9V032C12STC ES MT9V032C12STMD ES MT9V032C12STMH ES 48-pin CLCC (mono) 48-pin CLCC (color) Demo kit (mono) Demo kit headboard only (mono) Demo kit (color) Demo kit headboard only (color) MT9V032C12STCD ES MT9V032C12STCH ES 1 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. Preliminary MT9V032: 1/3-Inch Wide-VGA Digital Image Sensor General Description General Description The Micron Imaging MT9V032 is a 1/3-inch wide-VGA format CMOS active-pixel digital image sensor with global shutter and high dynamic range (HDR) operation. The sensor has specifically been designed to support the demanding interior and exterior unattended surveillance imaging needs, which makes this part ideal for a wide variety of imaging applications in real-world environments. This wide-VGA CMOS image sensor features DigitalClarityMicron's breakthrough low-noise CMOS imaging technology that achieves CCD image quality (based on signalto-noise ratio and low-light sensitivity) while maintaining the inherent size, cost, and integration advantages of CMOS. The active imaging pixel array is 752H x 480V. It incorporates sophisticated camera functions on-chip--such as binning 2 x 2 and 4 x 4, to improve sensitivity when operating in smaller resolutions--as well as windowing, column and row mirroring. It is programmable through a simple two-wire serial interface. The MT9V032 can be operated in its default mode or be programmed for frame size, exposure, gain setting, and other parameters. The default mode outputs a wide-VGAsize image at 60 frames per second (fps). An on-chip analog-to-digital converter (ADC) provides 10 bits per pixel. A 12-bit resolution companded for 10-bits for small signals can be alternatively enabled, allowing more accurate digitization for darker areas in the image. In addition to a traditional, parallel logic output the MT9V032 also features a serial lowvoltage differential signaling (LVDS) output. The sensor can be operated in a stereocamera mode, and the sensor, designated as a stereo-master, is able to merge the data from itself and the stereo-slave sensor into one serial LVDS stream. Figure 1: Block Diagram Serial Register I/O Control Register Active-Pixel Sensor (APS) Array 752H x 480V Timing and Control Analog Processing ADCs Digital Processing Parallel Video Data Out Serial Video LVDS Out Slave Video LVDS In (for stereo applications only) PDF: 09005aef824c9998/Source: 09005aef824c999c MT9V032_LDS_2.fm - Rev. B 3/07 EN 2 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. Preliminary MT9V032: 1/3-Inch Wide-VGA Digital Image Sensor General Description Figure 2: MT9V032 Quantum Efficiency vs. Wavelength Blue Green (B) Green (R) Red 40 35 Quantum E ffic ienc y (%) 30 25 20 15 10 5 0 350 450 550 650 750 850 950 1050 Wavelength (nm) PDF: 09005aef824c9998/Source: 09005aef824c999c MT9V032_LDS_2.fm - Rev. B 3/07 EN 3 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. Preliminary MT9V032: 1/3-Inch Wide-VGA Digital Image Sensor Pin Descriptions Pin Descriptions Figure 3 shows the package pinout for the MT9V032. Table 3 on page 5 provides the pin descriptions. DOUT2 1 48 47 46 45 44 43 SER_DATAIN_N 10 39 VAA SER_DATAIN_P 11 38 AGND LVDSGND 12 37 NC DGND 13 36 NC VDD 14 35 VAA DOUT5 15 34 AGND DOUT6 16 33 STANDBY DOUT7 17 32 RESET# 18 31 S_CTRL_ADR1 20 LINE_VALID DOUT9 19 21 22 23 24 4 25 26 27 28 29 30 S_CTRL_ADR0 VAAPIX RSVD 40 OE 9 LED_OUT BYPASS_CLKIN_P SCLK DOUT4 STFRM_OUT 41 SDATA DOUT3 8 EXPOSURE 42 BYPASS_CLKIN_N STLN_OUT 7 FRAME_VALID LVDSGND DOUT8 PDF: 09005aef824c9998/Source: 09005aef824c999c MT9V032_LDS_2.fm - Rev. B 3/07 EN DOUT1 2 DOUT0 3 PIXCLK SHFT_CLKOUT_P 4 SYSCLK SHFT_CLKOUT_N 5 VDD SER_DATAOUT_P 6 DGND SER_DATAOUT_N 48-Pin CLCC Package Pinout Diagram VDDLVDS Figure 3: Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. Preliminary MT9V032: 1/3-Inch Wide-VGA Digital Image Sensor Pin Descriptions Table 3: Pin Descriptions Only pins DOUT0 through DOUT9 may be tri-stated Pin Number Symbol Type Description Notes 29 10 RSVD SER_DATAIN_N Input Input 1 11 SER_DATAIN_P Input 8 BYPASS_CLKIN_N Input 9 BYPASS_CLKIN_P Input 23 25 EXPOSURE SCLK Input Input 28 30 31 32 33 47 24 OE S_CTRL_ADR0 S_CTRL_ADR1 RESET# STANDBY SYSCLK SDATA Input Input Input Input Input Input I/O 22 STLN_OUT I/O 26 STFRM_OUT I/O 20 21 15 16 17 18 19 27 41 42 43 44 45 46 2 3 4 5 LINE_VALID FRAME_VALID DOUT5 DOUT6 DOUT7 DOUT8 DOUT9 LED_OUT DOUT4 DOUT3 DOUT2 DOUT1 DOUT0 PIXCLK SHFT_CLKOUT_N SHFT_CLKOUT_P SER_DATAOUT_N SER_DATAOUT_P Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Connect to DGND. Serial data in for stereoscopy (differential negative). Tie to 1k pull-up (to 3.3V) in non-stereoscopy mode. Serial data in for stereoscopy (differential positive). Tie to DGND in non-stereoscopy mode. Input bypass shift-CLK (differential negative). Tie to 1K pull-up (to 3.3V) in non-stereoscopy mode. Input bypass shift-CLK (differential positive). Tie to DGND in non-stereoscopy mode. Rising edge starts exposure in slave mode. Two-wire serial interface clock. Connect to VDD with 1.5K resistor even when no other two-wire serial interface peripheral is attached. DOUT enable pad, active HIGH. Two-wire serial interface slave address bit 3. Two-wire serial interface slave address bit 5. Asynchronous reset. All registers assume defaults. Shut down sensor operation for power saving. Master clock (26.6 MHz). Two-wire serial interface data. Connect to VDD with 1.5K resistor even when no other two-wire serial interface peripheral is attached. Output in master mode--start line sync to drive slave chip in-phase; input in slave mode. Output in master mode--start frame sync to drive a slave chip in-phase; input in slave mode. Asserted when DOUT data is valid. Asserted when DOUT data is valid. Parallel pixel data output 5. Parallel pixel data output 6. Parallel pixel data output 7. Parallel pixel data output 8 Parallel pixel data output 9. LED strobe output. Parallel pixel data output 4. Parallel pixel data output 3. Parallel pixel data output 2. Parallel pixel data output 1. Parallel pixel data output 0. Pixel clock out. DOUT is valid on rising edge of this clock. Output shift CLK (differential negative). Output shift CLK (differential positive). Serial data out (differential negative). Serial data out (differential positive). PDF: 09005aef824c9998/Source: 09005aef824c999c MT9V032_LDS_2.fm - Rev. B 3/07 EN 5 2 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. Preliminary MT9V032: 1/3-Inch Wide-VGA Digital Image Sensor Pin Descriptions Table 3: Pin Descriptions (continued) Only pins DOUT0 through DOUT9 may be tri-stated Pin Number Symbol Type 1, 14 35, 39 40 6 7, 12 13, 48 34, 38 36, 37 VDD VAA VAAPIX VDDLVDS LVDSGND DGND AGND NC Supply Supply Supply Supply Ground Ground Ground NC Notes: Figure 4: Description Notes Digital power 3.3V. Analog power 3.3V. Pixel power 3.3V. Dedicated power for LVDS pads. Dedicated GND for LVDS pads. Digital GND. Analog GND. No connect. 3 1. Pin 29 (RSVD) must be tied to GND. 2. Output Enable (OE) tri-states signals DOUT0-DOUT9. No other signals are tri-stated with OE. 3. No connect. These pins must be left floating for proper operation. Typical Configuration (Connection)--Parallel Output Mode 10k 1.5k Master Clock VDDLVDS VDD VAA VAAPIX VDD VAA VAAPIX DOUT(9:0) LINE_VALID FRAME_VALID PIXCLK SYSCLK OE RESET# EXPOSURE STANDBY S_CTRL_ADR0 S_CTRL_ADR1 SCLK SDATA STANDBY from Controller or Digital GND Two-Wire Serial Interface RSVD LED_OUT DGND LVDSGND To Controller To LED output AGND 0.1F Note: PDF: 09005aef824c9998/Source: 09005aef824c999c MT9V032_LDS_2.fm - Rev. B 3/07 EN LVDS signals are to be left floating. 6 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. Preliminary MT9V032: 1/3-Inch Wide-VGA Digital Image Sensor Electrical Specifications Electrical Specifications Table 4: DC Electrical Characteristics VPWR = 3.3V 0.3V; TA = Ambient = 25C Symbol Definition VIH VIL IIN Input high voltage Input low voltage Input leakage current VOH VOL IOH IOL VAA IPWRA VDD IPWRD VAAPIX IPIX VLVDS ILVDS IPWRA Standby IPWRD Standby Clock Off IPWRD Standby Clock On Output high voltage Output low voltage Output high current Output low current Analog power supply Analog supply current Digital power supply Digital supply current Pixel array power supply Pixel supply current LVDS power supply LVDS supply current Analog standby supply current Table 5: Condition No pull-up resistor; VIN = VPWR or VGND IOH = -4.0mA IOL = 4.0mA VOH = VDD - 0.7 VOL = 0.7 Default settings Default settings Default settings Default settings, CLOAD= 10pF Default settings Default settings Default settings Default settings STDBY = VDD Min Typ Max Unit VPWR -0.5 -0.3 -15.0 - - - VPWR +0.3 0.8 15.0 V V A VPWR -0.7 - -9.0 - 3.0 - 3.0 - 3.0 0.5 3.0 11.0 2 - - - - 3.3 35.0 3.3 35.0 3.3 1.4 3.3 13.0 3 - 0.3 - 9.0 3.6 60.0 3.6 60 3.6 3.0 3.6 15.0 4 V V mA mA V mA V mA V m V mA A Digital standby supply current with clock off STDBY = VDD, CLKIN = 0 MHz 1 2 4 A Digital standby supply current with clock on STDBY= VDD, CLKIN = 27 MHz - 1.05 - mA Min Typ Max Unit 250 - - - 400 50 mV mV 1.0 - 1.2 - 1.4 35 mV mV 10 12 mA 1 10 A LVDS Driver DC Specifications VPWR = 3.3V 0.3V; TA = Ambient = 25C Symbol |VOD| |DVOD| VOS DVOS IOS IOZ Definition Output differential voltage Change in VOD between complementary output states Output offset voltage Change in VOS between complementary output states Output current when driver shorted to ground Output current when driver is tri-state PDF: 09005aef824c9998/Source: 09005aef824c999c MT9V032_LDS_2.fm - Rev. B 3/07 EN Condition RLOAD = 100 1% 7 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. Preliminary MT9V032: 1/3-Inch Wide-VGA Digital Image Sensor Electrical Specifications Table 6: LVDS Receiver DC Specifications VPWR = 3.3V 0.3V; TA = Ambient = 25C Symbol VIDTH+ Iin Definition Input differential Input current Caution Table 7: Condition Min Typ Max Unit | VGPD| <925mV -100 - - - 100 20 mV A Stresses greater than those listed in Table 7 may cause permanent damage to the device. Absolute Maximum Ratings Symbol Parameter VSUPPLY ISUPPLY IGND VIN VOUT TSTG Power supply voltage (all supplies) Total power supply current Total ground current DC input voltage DC output voltage Storage temperature Note: PDF: 09005aef824c9998/Source: 09005aef824c999c MT9V032_LDS_2.fm - Rev. B 3/07 EN Min Max Unit -0.3 - - -0.3 -0.3 -40 4.5 200 200 VDDQ + 0.3 VDDQ + 0.3 +125 V mA mA V V C These are stress ratings only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 8 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. Preliminary MT9V032: 1/3-Inch Wide-VGA Digital Image Sensor Package Dimensions Package Dimensions Figure 5: 48-Pin CLCC Package Outline Drawing 2.3 0.2 D 1.7 Seating plane Substrate material: alumina ceramic 0.7 thickness Wall material: alumina ceramic A Lid material: borosilicate glass 0.55 thickness 8.8 47X 1.0 0.2 0.8 TYP 4.4 48 48X 0.40 0.05 48X R 0.15 H CTR 1.75 O0.20 A B C 1 First clear pixel 5.215 4.84 4.4 O0.20 A B C 5.715 0.8 TYP 4X 10.9 0.1 CTR V CTR 11.43 8.8 Image sensor die: 0.675 thickness 0.2 5.215 5.715 11.43 Lead finish: Au plating, 0.50 microns minimum thickness over Ni plating, 1.27 microns minimum thickness Notes: PDF: 09005aef824c9998/Source: 09005aef824c999c MT9V032_LDS_2.fm - Rev. B 3/07 EN C Optical area A B 0.05 1.400 0.125 0.90 for reference only 0.35 for reference only 0.10 A 10.9 0.1 CTR Optical center1 Optical area: Maximum rotation of optical area relative to package edges: 1 Maximum tilt of optical area relative to seating plane A : 50 microns Maximum tilt of optical area relative to top of cover glass D : 100 microns 1. Optical center = package center. 2. All dimensions are in millimeters. 9 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. Preliminary MT9V032: 1/3-Inch Wide-VGA Digital Image Sensor Appendix A - Serial Configurations Appendix A - Serial Configurations With the LVDS serial video output, the deserializer can be up to 8 meters from the sensor. The serial link can save on the cabling cost of 14 wires (DOUT[9:0], LINE_VALID, FRAME_VALID, PIXCLK, GND). Instead, just three wires (two serial LVDS, one GND) are sufficient to carry the video signal. Configuration of Sensor for Stand-Alone Serial Output with Internal PLL In this configuration, the internal PLL generates the shift-clk (x12). The LVDS pins SER_DATAOUT_P and SER_DATAOUT_N must be connected to a deserializer (clocked at approximately the same system clock frequency). Figure 6 shows how a standard off-the-shelf deserializer (National Semiconductor DS92LV1212A) can be used to retrieve the standard parallel video signals of DOUT[9:0], LINE_VALID and FRAME_VALID. Figure 6: Stand-Alone Topology CLK 26.6 MHz Osc. LVDS SER_DATAIN Sensor LVDS BYPASS_CLKIN LVDS SER_DATAOUT LVDS SHIFT_CLKOUT DS92LV1212A 8 8 meters (maximum) 26.6 MHz Osc. 2 PIXEL LINE_VALID FRAME_VALID 8-bit configuration shown Typical configuration of the sensor: 1. Power up sensor. 2. Enable LVDS driver (set R0xB3[4]= 0). 3. De-assert LVDS power-down (set R0xB1[1] = 0. 4. Issue a soft reset (set R0x0C[0] = 1 followed by R0x0C[0] = 0. If necessary: 5. Force sync patterns for the deserializer to lock (set R0xB5[0] = 1). 6. Stop applying sync patterns (set R0xB5[0] = 0). PDF: 09005aef824c9998/Source: 09005aef824c999c MT9V032_LDS_2.fm - Rev. B 3/07 EN 10 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. Preliminary MT9V032: 1/3-Inch Wide-VGA Digital Image Sensor Appendix A - Serial Configurations Configuration of Sensor for Stereoscopic Serial Output with Internal PLL In this configuration the internal PLL generates the shift-clk (x18) in phase with the system-clock. The LVDS pins SER_DATAOUT_P and SER_DATAOUT_N must be connected to a deserializer (clocked at approximately the same system clock frequency). Figure 7 shows how a standard off-the-shelf deserializer can be used to retrieve back DOUT(9:2) for both the master and slave sensors. Additional logic is required to extract out LINE_VALID and FRAME_VALID embedded within the pixel data stream. Figure 7: Stereoscopic Topology SLAVE MASTER 26.6 MHz Osc. LVDS SER_DATAIN LVDS SER_DATAIN SENSOR SENSOR SENSOR LVDS BYPASS_CLKIN LVDS BYPASS_CLKIN X 1 8/X 1 2 PL L LVDS SER_DATAOUT LVDS SHIFT_CLKOUT LVDS SER_DATAOUT LVDS SHIFT_CLKOUT 5 meters (maximum) 1. PLL in non-bypass mode 2. PLL in x 18 mode (stereoscopy) 1. PLL in bypass mode DS92LV16 8 PIXEL FROM SLAVE 26.6 MHz Osc. 8 PIXEL FROM MASTER LV and FV are embedded in the data stream Typical configuration of the master and slave sensors: 1. Power up the sensors. 2. Broadcast WRITE to de-assert LVDS power-down (set R0xB1[1] = 0). 3. Individual WRITE to master sensor putting its internal PLL into bypass mode (set R0xB1[0] = 1). 4. Broadcast WRITE to both sensors to set the stereoscopy bit (set R0x07[5] = 1). 5. Make sure all resolution, vertical blanking, horizontal blanking, window size, and AEC/AGC configurations are done through broadcast WRITE to maintain lockstep. 6. Broadcast WRITE to enable LVDS driver (set R0xB3[4] = 0). 7. Broadcast WRITE to enable LVDS receiver (set R0xB2[4] = 0). 8. Individual WRITE to master sensor, putting its internal PLL into bypass mode (set R0xB1[0] = 1). 9. Individual WRITE to slave sensor, enabling its internal PLL (set R0xB1[0] = 0). 10. Individual WRITE to slave sensor, setting it as a stereo slave (set R0x07[6] = 1). 11. Individual WRITEs to master sensor to minimize the inter-sensor skew (set R0xB2[2:0], R0xB3[2:0], and R0xB4[1:0] appropriately). Use R0xB7 and R0xB8 to get lockstep feedback from stereo_error_flag. 12. Broadcast WRITE to issue a soft reset (set R0x0C[0] = 1 followed by R0x0C[0] = 0). Note: PDF: 09005aef824c9998/Source: 09005aef824c999c MT9V032_LDS_2.fm - Rev. B 3/07 EN The stereo_error_flag is set if a mismatch has occurred at a reserved byte (slave and master sensor's codes at this reserved byte must match). If the flag is set, steps 11 and 12 are repeated until the stereo_error_flag remains cleared. 11 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. Preliminary MT9V032: 1/3-Inch Wide-VGA Digital Image Sensor Appendix A - Serial Configurations Broadcast and Individual Writes for Stereoscopic Topology In stereoscopic mode, the two sensors are required to run in lockstep. This implies that control logic in each sensor is in exactly the same state as its pair on every clock. To ensure this, all inputs that affect control logic must be identical and arrive at the same time at each sensor. These inputs include: * system clock * system reset * two-wire serial interface clk - SCL * two-wire serial interface data - SDA Figure 8: Two-Wire Serial Interface Configuration in Stereoscopic Mode L 26.6 MHz Osc. L L S_CTRL_ADR[0] CLK S_CTRL_ADR[0] MASTER SENSOR SLAVE SENSOR CLK SCL HOST CLK SDA SCL SDA SCL SDA Host launches SCL and SDA on positive edge of SYSCLK. All system clock lengths (L) must be equal. SCL and SDA lengths to each sensor (from the host) must also be equal. The setup in Figure 8 shows how the two sensors can maintain lockstep when their configuration registers are written through the two-wire serial interface. A WRITE to configuration registers would either be broadcast (simultaneous WRITES to both sensors) or individual (WRITE to just one sensor at a time). READs from configuration registers would be individual (READs from just one sensor at a time). One of the two serial interface slave address bits of the sensor is hardwired. The other is controlled by the host. This allows the host to perform either a broadcast or a one-toone access. Broadcast WRITES are performed by setting the same S_CTRL_ADR input bit for both slave and master sensor. Individual WRITES are performed by setting opposite S_CTRL_ADR input bit for both slave and master sensor. Similarly, individual READs are performed by setting opposite S_CTRL_ADR input bit for both slave and master sensor. PDF: 09005aef824c9998/Source: 09005aef824c999c MT9V032_LDS_2.fm - Rev. B 3/07 EN 12 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. Preliminary MT9V032: 1/3-Inch Wide-VGA Digital Image Sensor Revision History Revision History Rev. B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3/28/2007 * Updated package drawing PDF: 09005aef824c9998/Source: 09005aef824c999c MT9V032_LDS_2.fm - Rev. B 3/07 EN 13 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved.