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IDT74FCT166244AT/CT
FAST CMOS 16-BIT BUFFER/LINE DRIVER INDUSTRIAL TEMPERATURE RANGE
JUNE 2002INDUSTRIAL TEMPERATURE RANGE
FEATURES:
0.5 MICRON CMOS Technology
High-speed, low-power CMOS replacement for ABT functions
Typical tSK(o) (Output Skew) < 250ps
Low input and output leakage
1µA (max.)
Light drive balanced output of ±8mA
Minimal system switching noise
Typical VOLP (Output Ground Bounce) < 0.25V at VCC = 5V,
TA = 25°C
Power off disable outputs permit “live insertion”
Available in SSOP and TSSOP packages
FUNCTIONAL BLOCK DIAGRAM
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
2002 Integrated Device Technology, Inc. DSC-5462/2
IDT74FCT166244AT/CT
FAST CMOS 16-BIT
BUFFER/LINE DRIVER
DESCRIPTION:
The FCT166244T 16-Bit Buffer/Line Driver is for bus interface or signal
buffering applications requiring high speed and low power dissipation. These
devices have a flow through pin organization, and shrink packaging to simplify
board layout. All inputs are designed with hysteresis for improved noise
margin. The three-state controls allow independent 4-bit, 8-bit or combined 16-
bit operation. These parts are plug in replacements for ABT16244 where
higher speed, lower noise or lower power dissipation levels are desired.
The FCT166244T is suited for very low noise, point-to-point driving
where there is a single receiver, or a very light lumped load (<100pF). The
buffers are designed to limit the output current to levels which will avoid noise
and ringing on the signal lines without using external series terminating
resistors.
3OE
3A1
3A2
3A3
3A4
3Y1
3Y2
3Y3
3Y4
1Y1
1Y2
1Y3
1Y4
1A1
1A2
1A3
1A4
1OE
4OE
4A1
4A2
4A3
4A4
4Y1
4Y2
4Y3
4Y4
2OE
2A1
2A2
2A3
2A4
2Y1
2Y2
2Y3
2Y4
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INDUSTRIAL TEMPERATURE RANGE
IDT74FCT166244AT/CT
FAST CMOS 16-BIT BUFFER/LINE DRIVER
SSOP/ TSSOP
TOP VIEW
PIN CONFIGURATION Symbol Description Max Unit
VTERM(2) Terminal Voltage with Respect to GND –0.5 to +7 V
VTERM(3) Terminal Voltage with Respect to GND –0.5 to VCC+0.5 V
TSTG Storage Temperature –65 to +150 °C
IOUT DC Output Current –60 to +120 mA
ABSOLUTE MAXIMUM RATINGS(1)(1)
(1)(1)
(1)
NOTES:
1 . Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. All device terminals except FCT162XXX Output and I/O terminals.
3. Output and I/O terminals for FCT162XXX.
Symbol Parameter(1) Conditions Typ. Max. Unit
CIN Input Capacitance VIN = 0V 3.5 6 pF
COUT Output Capacitance VOUT = 0V 3.5 8 pF
CAPACITANCE (TA = +25°C, F = 1.0MHz)
NOTE:
1. This parameter is measured at characterization but not tested.
FUNCTION TABLE(1)
NOTE:
1 . H = HIGH Voltage Level
L = LOW Voltage Level
X = Don't Care
Z = High-Impedance
1Y1
GND
1Y3
VCC
GND
3Y2
GND
VCC
GND
1Y2
1Y4
2Y1
2Y2
2Y3
2Y4
3Y1
3Y3
3Y4
4Y1
4Y3
4Y4
4Y2
4OE
1A1
1A2
GND
1A3
1A4
VCC
2A1
2A2
2A3
2A4
3A1
3A2
3A3
3A4
VCC
4A1
4A3
4A4
4A2
GND
GND
GND
2OE
3OE
39
29
30
31
32
33
34
35
36
37
38
25
26
27
28
48
47
41
42
43
44
45
46
40
1
2
3
4
5
6
7
8
9
10
12
13
14
15
16
17
18
19
20
11
21
22
23
24
1OE
Inputs Outputs
xOE xAx xYx
LL L
LH H
HX Z
Pin Names Description
xOE 3-State Output Enable Inputs (Active LOW)
xAx Data Inputs
xYx 3-State Outputs
PIN DESCRIPTION
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IDT74FCT166244AT/CT
FAST CMOS 16-BIT BUFFER/LINE DRIVER INDUSTRIAL TEMPERATURE RANGE
Symbol Parameter Test Conditions(1) Min. Typ.(2) Max. Unit
IODL Output LOW Current VCC = 5V, VIN = VIH or VIL, VO = 1.5V(3) 16 48 96 mA
IODL Output HIGH Current VCC = 5V, VIN = VIH or VIL, VO = 1.5V(3) –16 –48 –96 mA
VOH Output HIGH Voltage VCC = Min. IOH = –8mA 2 .4 3.3 V
VIN = VIH or VIL
VOH Output LOW Voltage VCC = Min. IOL = 8 m A 0.3 0.55 V
VIN = VIH or VIL
Symbol Parameter Test Conditions(1) Min. Typ.(2) Max. Unit
VIH Input HIGH Level Guaranteed Logic HIGH Level 2 V
VIL Input LOW Level Guaranteed Logic LOW Level 0.8 V
IIH Input HIGH Current (Input pins)(5) VCC = Max. VI = VCC ——±1µA
Input HIGH Current (I/O pins)(5) ——±1
IIL Input LOW Current (Input pins)(5) VI = GND ±1
Input LOW Current (I/O pins)(5) ——±1
IOZH High Impedance Output Current VCC = Max. VO = 2.7V ±1 µA
IOZL (3-State Output pins)(5) VO = 0.5V ±1
VIK Clamp Diode Voltage VCC = Min., IIN = –18mA –0.7 –1.2 V
IOS Short Circuit Current VCC = Max., VO = GND(3) –80 –140 –250 mA
VHInput Hysteresis 100 m V
ICCL Quiescent Power Supply Current VCC = Max. 5 500 µA
ICCH VIN = GND or VCC
ICCZ
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Industrial: TA = –40°C to +85°C, VCC = 5.0V ±10%
NOTES:
1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at VCC = 5.0V, +25°C ambient.
3. Not more than one output should be shorted at one time. Duration of the test should not exceed one second.
4. Duration of the condition can not exceed one second.
5 . The test limit for this parameter is ±5µA at TA = -55°C.
OUTPUT DRIVE CHARACTERISTICS
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INDUSTRIAL TEMPERATURE RANGE
IDT74FCT166244AT/CT
FAST CMOS 16-BIT BUFFER/LINE DRIVER
Symbol Parameter Test Conditions(1) Min. Typ.(2) Max. Unit
ICC Quiescent Power Supply VCC = Max. 0.5 1.5 mA
Current TTL Inputs HIGH VIN = 3.4V(3)
ICCD Dynamic Power Supply Current(4) VCC = Max., VIN = VCC 60 100 µA/
Outputs Open VIN = GND M H z
xOE = GND
One Input Toggling
50% Duty Cycle
ICTotal Power Supply Current(6) VCC = Max., VIN = VCC 0.6 1.5 mA
Outputs Open VIN = GND
fCP = 10MHz (CLKBA)
50% Duty Cycle VIN = 3.4V 0.9 2.3
xOE = GND VIN = GND
One Bit Toggling
VCC = Max., VIN = VCC 2.4 4.5(5)
Outputs Open VIN = GND
fi = 2.5MHz
50% Duty Cycle VIN = 3.4V 6.4 16.5(5)
xOE = GND VIN = GND
Sixteen Bits Toggling
POWER SUPPLY CHARACTERISTICS
NOTES:
1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at VCC = 5.0V, +25°C ambient.
3. Per TTL driven input (VIN = 3.4V). All other inputs at VCC or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
5. Values for these conditions are examples of the ICC formula. These limits are guaranteed but not tested.
6. IC = IQUIESCENT + IINPUTS + IDYNAMIC
IC = ICC + ICC DHNT + ICCD (fCPNCP/2 + fiNi)
ICC = Quiescent Current (ICCL, ICCH and ICCZ)
ICC = Power Supply Current for a TTL High Input (VIN = 3.4V)
DH = Duty Cycle for TTL Inputs High
NT = Number of TTL Inputs at DH
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fCP = Clock Frequency for Register Devices (Zero for Non-Register Devices)
NCP = Number of Clock Inputs at fCP
fi = Input Frequency
Ni = Number of Inputs at fi
74FCT166244AT 74FCT166422CT
Symbol Parameter Condition(1) Min.(2) Max. Min.(2) Max. Unit
tPLH Propagation Delay CL = 50pF 1.5 4.8 1.5 4.1 ns
tPHL xAx to xYx RL = 500
tPZH Output Enable Time 1.5 6.2 1.5 5.8 ns
tPZL
tPHZ Output Disable Time 1.5 5.6 1.5 5.2 ns
tPLZ
tSK(o) Output Skew(3) 0.5 0.5 ns
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
NOTES:
1. See test circuits and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design.
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IDT74FCT166244AT/CT
FAST CMOS 16-BIT BUFFER/LINE DRIVER INDUSTRIAL TEMPERATURE RANGE
Pulse
Generator
RT
D.U.T.
VCC
VIN
CL
VOUT
50pF 500
500
7.0V
3V
1.5V
0V
3V
1.5V
0V
3V
1.5V
0V
3V
1.5V
0V
DATA
INPUT
TIMING
INPUT
ASYNCHRONO US CONTROL
PRESET
CLEAR
ETC.
SYNCHRONOUS CO NTROL
tSU tH
tREM
tSU tH
PRESET
CLEAR
CLO CK ENAB LE
ETC.
HIGH-LOW-HIGH
PULSE
LOW-HIGH-LOW
PULSE
tW
1.5V
1.5V
SAME PHASE
INPUT TRANSITION
3V
1.5V
0V
1.5V
VOH
tPLH
OUTPUT
OPPOSITE PHASE
INPUT TRANSITION
3V
1.5V
0V
tPLH tPHL
tPHL
VOL
CONTROL
INPUT
3V
1.5V
0V
3.5V
0V
OUTPUT
NORMALLY
LOW
OUTPUT
NORMALLY
HIGH
SWITCH
CLOSED
SWITCH
OPEN
VOL
0.3V
0.3V
tPLZtPZL
tPZH tPHZ
3.5V
0V
1.5V
1.5V
ENABLE DISABLE
VOH
TEST CIRCUITS AND WAVEFORMS
Propagation Delay
Test Circuits for All Outputs
Enable and Disable Times
Set-up, Hold, and Release Times
Pulse Width
NOTES:
1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.
2. Pulse Generator for All Pulses: Rate 1.0MHz; tF 2.5ns; tR 2.5ns.
Test Switch
Open Drain
Disable Low Closed
Enable Low
All Other Tests Open
SWITCH POSITION
DEFINITIONS:
CL = Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.
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INDUSTRIAL TEMPERATURE RANGE
IDT74FCT166244AT/CT
FAST CMOS 16-BIT BUFFER/LINE DRIVER
ORDERING INFORMATION
IDT XX
Temp. Range XXXX
Device Type XX
Package
PV
PA
244AT
244CT
Shrink Small Outl ine Package
Thin Shrink Small Outline Package
16-Bit Buffer/Line Driver
74 40°C to +85°C
166 16-Bit, 5 Volt, Light Drive
FCT XXX
Family
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2975 Stender Way 800-345-7015 or 408-727-6116 logichelp@idt.com
Santa Clara, CA 95054 fax: 408-492-8674 (408) 654-6459
www.idt.com
6/21/2002 Updated according to PDNs Logic-00-07 and Logic-01-04
DATA SHEET DOCUMENT HISTORY