®
Mono and Colour Digital Video CMOS Image Sensors
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VV5410 & VV6410
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The VV5410/VV6410 are multi format digital output imaging
devices based on STMicroelectronics’s unique CMOS
sensor technology. Both sensors require minimal support
circuitry.
VV5410 (monochrome) and VV6410 (colourised) produce
digital video output. The video streams from both devices
contain embedded control data that can be used to enable
frame grabbing applications as well as providing input data
for the external exposure controller.
The pixel array in VV6410 is coated with a Bayer colour
pattern. This colourised sensor can interface to a range of
STMicroelectronics co-processors. A chipset comprising
VV6410 and STV0657 will output 8bit YUV or RGB digital
video. A USB camera can be realised by partnering VV6410
with STV0672. Finally a high quality digital stills camera can
be produced by operating VV6410 with STV0680B-001.
Please contact STMicroelectronics for ordering information
on all of these products.
Both VV5410 and VV6410 are initialised in a power saving
mode and must be enabled via I2C control before they can
produce video. The I2C allows the master coprocessor to
reconfigure the device and control exposure and gain
settings.
USB systems are catered for with an ultra low power, pin
driven, suspend mode.
The on board regulator can supply sufficient current drive to
power external components, (e.g. the video coprocessor).
Functional block diagram
Key Features
• 3.3V operation
• Multiple video formats available
• Pan tilt image feature
• Sub sampled image full FOV feature
• On board 10 bit ADC
• On board voltage regulator
• Low power suspend mode for USB systems
• Automatic black and dark calibration
• On board audio amplifier
• I2C communications
Applications
• PC camera
• Personal digital assistant
• Mobile video phones
• Digital stills cameras
Specifications
VOLTAGE REFERENCES,VOLTAGE REGULATORS AND AUDIO AMP CIRCUITRY
DIGITAL
CONTROL
LOGIC
SDA
SCL
DATA
FST
LST
QCK
SUSPEND
OEB
PIXEL ARRAY
COLUMN ADC
X-DECODER
SRAM LINE STORE
READOUT
STRUCTURE
Y-
DECODER
Effective image sizes after
colour processing 352 x 288 (CIF,PAL)
176 x 144 (QCIF)
Pixel resolution up to 356 x 292
Pixel size 7.5µm x 6.9µm
Array size 2.73mm x 2.04mm
Exposure control +81dB
Analogue gain +12dB (recommended max)
SNR c.56dB
Random Noise 1.17mV
Sensitivity (Green channel) 2.1V/lux.sec
Dark Current 46mV/sec
VFPN 1.2mV
Supply voltage 3.0V- 6.0V DC +/− 10%
Supply current 26.2mA (max,CIF@30fps)
85µA (suspend mode)
Operating temperature
(ambient) 0oC - 40oC
Package type 36pin CLCC
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Table of Contents
1. Document Revision History ............................................................................................ 4
2. Introduction ...................................................................................................................... 5
2.1 Overview ........................................................................................................................................5
2.2 Exposure Control............................................................................................................................5
2.3 Digital Interface ..............................................................................................................................5
2.4 Other Features ...............................................................................................................................7
3. Operating Modes.............................................................................................................. 9
3.1 Video Timing ..................................................................................................................................9
3.2 Pixel Array....................................................................................................................................10
3.3 X-offset and Y-offset.....................................................................................................................11
3.4 QCIF Output Modes .....................................................................................................................16
4. Black Offset Cancellation.............................................................................................. 18
5. Dark Offset Cancellation................................................................................................ 20
6. Exposure Control........................................................................................................... 21
7. Timed Serial Interface Parameters ............................................................................... 24
8. Digital Video Interface Format ...................................................................................... 27
8.1 General description ......................................................................................................................27
8.2 Embedded control data ................................................................................................................28
8.3 Video timing reference and status/configuration data ..................................................................31
8.4 Detection of sensor using data bus state .....................................................................................48
8.5 Resetting the Sensor Via the Serial Interface ..............................................................................48
8.6 Resetting the Sensor Via the RESETB pin ..................................................................................48
8.7 Resynchronising the Sensor Via the RESETB pin configured as SINB.......................................48
8.8 Power-up, Low-power and Sleep modes .....................................................................................50
8.9 Suspend mode .............................................................................................................................52
8.10 Data Qualification Clock, QCK .....................................................................................................52
9. Serial Control Bus.......................................................................................................... 60
9.1 General Description......................................................................................................................60
9.2 Serial Communication Protocol....................................................................................................60
9.3 Data Format .................................................................................................................................60
9.4 Message Interpretation.................................................................................................................61
9.5 The Programmers Model..............................................................................................................61
9.6 Types of messages ......................................................................................................................82
9.6 Types of messages ......................................................................................................................82
9.7 Serial Interface Timing .................................................................................................................85
10. Clock Signal.................................................................................................................... 86
11. Other Features................................................................................................................ 87
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11.1 Audio Amplifier .............................................................................................................................87
11.2 Voltage Regulators.......................................................................................................................89
11.3 Valid Supply Voltage Configurations............................................................................................89
11.4 Programmable Pins......................................................................................................................91
12. Characterisation Details................................................................................................ 92
12.1 VV5410/VV6410 AC/DC Specification .........................................................................................92
12.2 VV5410/VV6410 Optical Characterisation Data...........................................................................92
12.3 VV5410/VV6410 Power Consumption .........................................................................................94
12.4 Digital Input Pad Pull-up and Pull-down Strengths.......................................................................94
13. Pixel Defect Specification.............................................................................................. 95
13.1 Pixel Fault Definitions...................................................................................................................95
13.2 Stuck at White Pixel Fault ............................................................................................................95
13.3 Stuck at Black Pixel Fault.............................................................................................................95
13.4 Column / Row Faults....................................................................................................................95
13.5 Image Array Blemishes ................................................................................................................96
14. Pinout and pin descriptions.......................................................................................... 98
14.1 36pin CLCC Pinout Map...............................................................................................................98
15. Package Details (36pin CLCC).................................................................................... 101
16. Recommended VV5410/6410 support circuit............................................................. 102
17. Evaluation kits (EVK’s)................................................................................................ 103
18. Ordering details............................................................................................................ 104
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1. Document Revision History
Revision Date Comments
1.0 13/06/2000 • Original release
2.0 06/07/2000 • Package drawing and pin description updated
• Optical characterisation data added
• Audio description extended
• Pixel defect specification added
• Product numbering updated
• Reference design for BGA packaged 410 added
• Gain ceiling recommendation
2.1 04/09/2000 • Remove all reference to BGA package option
3.0 28/09/2000 • Product maturity moves to Mat29 therefore d/s moves to Release3.0
Table 1 : Document Revision History
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2. Introduction
2.1 Overview
VV5410/VV6410 is a CIF format CMOS image sensor. The VV5410 sensor is the basic monochrome device and VV6410 is the
colourised variant. The operation of VV5410 and VV6410 is very similar but any differences will be identified and explained.
VV6410 can output digital colourised pixel data at frame and line rates compatible with either NTSC or PAL video standards.
VV5410 and VV6410 contain the same basic video timing modes. Table 2 summarises these video modes.
The various operating modes are detailed in Section 3.
Important: VV5410 and VV6410’s output video data stream only contains raw data. A master co-processor is required to
generate a video waveform that can be displayed on a VDU
Note: The user can also provide a 24 MHz clock, rather than a 16 MHz clock, for the QCIF-60fps, CIF-25fps and CIF-30fps
modes, which the sensor then internally divides by 1.5, (see data_format[22]), to give an effective input clock frequency of 16
MHz.
2.2 Exposure Control
VV5410/VV6410 does not include any form of automatic exposure and/or gain control. Thus to produce a correctly exposed
image the integration period for the pixels, in the sensor array, an exposure control algorithm must be implemented externally.
The new exposure values are written to the sensor via the serial interface.
2.3 Digital Interface
The sensor’s offers a very flexible digital interface, the main components of which are listed below:
1. A tri-stateable 5-wire data bus (D[4:0]) for sending both video data and embedded timing references.
2. 4-wire and 8-wire data bus alternatives available. If the 8-wire option is selected then the FST/LST pins are reconfigured to
output data information.
3. A data qualification clock, QCK, which can be programmable via the serial interface to behave in a number of different ways
(Tri-stateable).
4. A line start signal, LST (Tri-stateable).
5. A frame start signal, FST (Tri-stateable).
6. OEB tri-states all 5 data bus lines, D[4:0], the qualification clock, QCK, LST, FST and D[7].
7. A 2-wire serial interface (SDA,SCL) for controlling and setting up the device.
Mode Input Clock
(MHz)Note
System
Clock
Divisor Image Size Line Time
(µs)
Lines
per
Frame
FrameRate
(fps)
QCIF - 25 fps 8.00 8 180 x 148 250.00 160 25.00000
QCIF - 30 fps 8.00 8 180 x 148 208.00 160 30.04807
QCIF - 60 fps 16.00 8 180 x 148 104.00 160 60.09614
CIF - 25 fps 16.00 4 356 x 292 125.00 320 25.00000
CIF - 30 fps 16.00 4 356 x 292 104.00 320 30.04807
NTSC (3.2 fsc) 28.636360 / 2.5 2 306 x 244 63.555564 525 29.97003
PAL (3.2 fsc) 35.46895 / 2.5 2 356 x 292 63.999639 625 25.00014
Table 2 : Video Modes
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2.3.1 Digital Data Bus
Along with the pixel data, codes representing the start and end of fields and the start and end of lines are embedded within the
video data stream to allow a co-processor to synchronise with video data the camera module is generating. Section 8. defines the
format for the output video data stream.
2.3.2 Frame Grabber Control Signals
To complement the embedded control sequences the data qualification clock (QCK), the line start signal (LST) and the field start
signal (FST) signals can be independently set-up as follows:
1. Disabled
2. Free-running.
3. Qualify only the control sequences and the pixel data.
4. Qualify the pixel data only
There is also the choice of two different QCK frequencies where one is twice the frequency of the other.
1. Fast QCK: the falling edge of the clock qualifies every 8, 5 or 4 bit blocks of data that makes up a pixel value.
2. Slow QCK: the rising edge qualifies 1st, 3rd, 5th, etc. blocks of data that make up a pixel value while the falling edge quali-
fies the 2nd, 4th, 6th etc. blocks of data. For example in 4-wire mode the rising edge of the clock qualifies the most signifi-
cant nibbles while the falling edge of the clock qualifies the least significant nibbles.
2.3.3 2-wire Serial Interface
The 2-wire serial interface provides complete control over sensor setup and operation. Two serial interface broadcast addresses
are supported. One allows all sensors to be written to in parallel while the other allows all sensors and co-processors to be written
to in parallel.
Section 9. defines the serial interface communications protocol and the register map of all the locations which can be accessed
via the serial interface.
Figure 1 : Block Diagram of VV5410/VV6410 Image Sensor (5-wire output)
OUTPUT
FORMAT
D[4:0]
QCK
LST
FST
SDA
SCL
OEB
CLKI
RESETB
IMAGE
FORMAT EXPOSURE
CONTROL SERIAL
INTERFACE
OFFSET
CANCELLATION
Digital Logic
Y-
DECODER
VREGS,
AUDIO AMP.,
& REFS
PHOTO DIODE
ARRAY
Column ADC Readout
Analogue Core
Structure
X-Decoder
SRAM line store
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2.3.4 Sensor/Co-processor Interface Options
There are 3 main ways of interfacing to the VV5410/VV6410 sensor based on the above signals:
1. The colour co-processor supplies the sensor clock, CLKI, and uses the embedded control sequences to synchronise with
the frame and line level timings. Thus the host and sensor are running off derivatives of the same fundamental clock. To
allow the co-processor to determine the best sampling position of the video data, during its power-up sequence the sensor
outputs a 101010... sequence on each of its data bus lines for the host to lock on to.
2. The colour co-processor supplies the sensor clock, CLKI, and uses a free-running QCK supplied by the sensor to sample
the incoming video data stream. The embedded control sequences are used to synchronise the frame and line level timings.
3. The colour co-processor supplies the sensor clock, CLKI, and uses FST, LST and the data only mode for QCK to synchro-
nise to the incoming video data. Primarily intended for interfacing to frame grabbers.
2.4 Other Features
2.4.1 Audio Amplifier
Pins AIN and AOUTP & AOUTN are the input and outputs respectively for an audio amplifier.
2.4.2 Voltage Regulator
The on-chip voltage regulator requires only a few external components to form a fully functional voltage regulator to 3.3V.
SDA
SCL
D[4:0]
CLKI
1.
VV5410/
VV6410
Sensor Co-processor
SDA
SCL
D[4:0]
QCK
CLKI
2.
VV5410/
VV6410
Sensor Co-processor
SDA
SCL
D[4:0]
QCK
CLKI
3.
VV5410/
VV6410
Sensor
Co-processor
LST
FST
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2.4.3 Serial Interface Programmable Pins
The FST and QCK pins are re-configurable to follow the state of 2-bits in a serial register. The user could then use these control
bits to control a peripheral device, a motor or shutter mechanism for example.
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3. Operating Modes
3.1 Video Timing
The video format mode on power-up is CIF 30fps by default. After power-up the mode can be changed by a serial interface to
write to the
video_timing
register. The frame/field rate is also programmable via the serial interface. Bit [3] of serial register [16]
selects between 30 and 25 frames per second for the CIF modes and 60/50 fields per second for the Digital and Analog Timing
modes. Please note that the sensor can exit low power in ANY of the available video modes.
The number of video lines in each frame is the same (320) for both the CIF modes. The slower frame rate (25 fps) is implemented
by simply extending the line period from 416 pixel periods to 500 pixel periods.
Table 3 details the setup for each of the video timing modes. A serial write to serial register [16] will force the contents of other
registers in the serial interface to change to the appropriate values, regardless of their present state. If for example a different
data output mode is required than the default for a particular video mode, a write to the appropriate register after the mode has
changed will restore the desired value.
3.1.1 Arbitration registers
When the operating video mode is changed a number of serial registers are forced into new states. The complete list is as
follows:
Video Mode Clock (MHz) System
Clock
Divisor
Video Data Line
Length Field Length DataOutput
Mode
PAL (3.2 fsc) 28.636360 / 2.5 2 356 x 292 454 312/313 5-wire
NTSC (3.2 fsc) 35.46895 / 2.5 2 306 x 244 364 262/263 5-wire
CIF - 25 fps 16.0 4 356 x 292 500 320 5-wire
CIF - 30 fps 16.0 4 356 x 292 416 320 5-wire
QCIF - 25 fps 8.0 8 180 x 148 250 160 5-wire
QCIF - 30 fps 8.0 8 180 x 148 208 160 5-wire
QCIF - 60 fps 16.0 8 180 x 148 208 160 5-wire
Table 3 : Video Timing Modes
Arbitrated
feature
Video mode selected/value automatically programmed
PAL NTSC CIF 25fps CIF 30fps PTQCIF
25fps PTQCIF
30fps SSQCIF
25fps SSQCIF
30fps
line length 453 363 499 415 249 207 249 207
field length 311 261 319 319 159 159 159 159
system clock divi-
sion 22448888
free running
qcknote1
yes yes no no no no no no
extra black
linesnote2
yes yes no no no no no no
Table 4 : Arbitration registers
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note1: The free running qck, slow by default, is enabled by writing 8’h04 to serial register [20].
note2: The contents of the extra black lines are enabled on to the data bus by setting bit [5] of serial register [17]. If bit [0] of serial
register [24] is reset, indicating that the preferred coprocessor device is not the VP3 device, (a STMicroelectronics coprocessor),
then the extra black lines are enabled by default regardless of the basic video mode selected.
The registers that control the image position within the pixel array and also the order in which the pixels are read out have not
been included in the table as their values are subject to a secondary series of registers. We will discuss the former in sections 2.2
and 2.3.
3.1.2 Input Clock Frequencies
It is recommended that a 16 MHz clock is used to generate CIF-25fps,CIF-30fps and QCIF-60fps and that an 8 MHz clock is used
to generate QCIF-25fps and QCIF-30fps, however the sensor can adapt to a range of other input frequencies and still generate
the required frame rates. For example, a 24 MHz clock can be used to generate CIF-30fps. By setting bit [7] of serial register [22]
the sensor can automatically divide the incoming clock by 1.5 by setting bit [7] of serial register [22], such that the internal clock
generator logic will still receive a 16 MHz clock.
Note that the clock division register is internally an 8 bit value, although the user may only program the lower nibble. The upper
nibble is reserved for setting the clock divisor as we change between primary video modes. The lower nibble can be programmed
to reduce the effective frame rate within each video mode.
The system clock divisor column in Table 5 assumes that the programmable pixel clock divisor is set to the default of 0,
implementing a divide by 1 of the internal pixel clock. Consider the following scenario where a user requires 15 fps CIF resolution
image. As can be seen there are a wide range of options to achieve the same result.
3.2 Pixel Array
The physical pixel array is 364 x 296 pixels. The pixel size is 7.5 µmby6.9µm. The image size for NTSC is 306 x 244 pixels, for
PAL and CIF it is 356 x 292 pixels, while for the QCIF modes the image size is 180 x 148 pixels. The remaining 4 physical
columns on each side of the PAL image size prevent columns 1 and 2 in PAL/CIF modes from being distorted by the edge effects
which occur when a pixel is close to the outer edge of the physical pixel array. Please note that these columns can be enabled as
part of the visible image if the user is operating the sensor in the pantilt QCIF mode.
Figure 3 shows how the 306 x 244 and 180 x 148 sub-arrays are aligned within the bigger 364 x 296 pixel array. The Bayer
colourisation pattern requires that the top-left corner of the pixel sub-array is always a Green 1 pixel. To preserve this Bayer
colour pattern the NTSC sub-array has been offset relative to the centre of the array. The QCIF size images are centrally
orientated.
Image read-out is very flexible. Sections 3.3.2 - describe the options available to the user. By default the sensor read out is
configured to be horizontally ‘shuffled’ non-interlaced raster scan. The horizontally ‘shuffled’ raster scan order differs from a
conventional raster in that the pixels of individual rows are re-ordered, with the odd pixels within a row read-out first, followed by
the even pixels. This ‘shuffled’ read-out within a line, groups pixels of the same colour (according to the Bayer pattern - Figure 2)
together, reducing cross talk between the colour channels. This option is on by default and is controllable via the serial interface.
The horizontal shuffle option would normally only be selected with the colour sensor variant, VV6410.
clk in
(MHz) Divide by 3/2
enabled? Systemclock
divisor Pixel clock
divisor pclk (MHz) Field Rate
8no 4 1 2 15
12 yes 4 1 2 15
16 no 4 2 2 15
24 yes 4 2 2 15
Table 5 : System clock divisor options
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3.3 X-offset and Y-offset
The image information is retrieved from the pixel array via a 2 dimensional address. The x and y address busses count from a
starting point described by x-offset, y-offset up to a maximum count in x and y that is determined by the image size. The order of
this count and the count step size is dependent upon the special image format parameters described below. The detailed control
of the x and y address counters is entirely handled by the sensor logic
As can be seen in Figure 3 the visible array size is 364 columns by 296 rows. The PAL and CIF images are sized, 356 columns
by 292 rows, thus we have a “border” of visible pixels that we do not read out if either of these modes are selected.
The images that are read out of the sensor are always “centred” on the array, therefore we allow a border of 4 columns at either
end of the image in the x-direction and a border of 2 rows at the top and bottom of the image in the y-direction. The pantilt QCIF
and NTSC video modes are similarly centred within the full size array.
For all the modes except the pantilt QCIF the x and y offset coordinates are fixed. If the user selects the pantilt QCIF mode then
they may specify x and y-offsets in the range:
• (xoffset >= 1) and (xoffset <= 185)
• (yoffset >= 5) and (yoffset <= 149)
The sensor will automatically clip values outwith the specified ranges. The y addresses less than 5 are reserved for the sensor
black lines and the y address greater than 296 are reserved for the sensor dark lines. Neither the black lines nor the dark lines
contain visible image data
Figure 2 : Bayer Colourisation Pattern (VV6410 only)
Green 1
Blue Green 2
Red
Odd Rows
(5, 7, 9,...)
Even Rows
(4, 6, 8,...)
Odd
Columns
(1,3,5,...)
Even
Columns
(2, 4, 6,...)
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Blue Green
Green Red
Blue Green
Green Red
356 Pixels
306 Pixels
244 Pixels
292 Pixels
4321
6
8
7
5
65
1, 2, 3, 4, 5, 6,... ..., 361, 362, 363, 364
5, 6, 7, 8, 9, 10,... ..., 297, 298, 299, 300
26 Pixels24 Pixels
22 Pixels22 Pixels
Blue Green
Green Red
10
9
87
360359358357 362361 364363
296 Pixels
364 Pixels
Blue Green
Green Red
Blue Green
Green Red
Blue Green
Green Red
Blue Green
Green Red
Blue Green
Green Red
Blue Green
Green Red
Blue Green
Green Red
Blue Green
Green Red
Blue Green
Green Red
Blue Green
Green Red
Blue Green
Green Red
Blue Green
Green Red
Blue Green
Green Red
Blue Green
Green Red
Blue Green
Green Red
Blue Green
Green Red
Blue Green
Green Red
Blue Green
Green Red
Blue Green
Green Red
Blue Green
Green Red
Blue Green
Green Red
180 Pixels
148 Pixels
88 Pixels
72 Pixels
The colour dyes included in this
diagram are only applicable to
VV6100. The monochrome device
VV5410 has exactly the same
readout structure and array size as
VV6410 - but no colourised pixels
296
298
297
295
300
299
Figure 3 : Image Readout Formats
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3.3.1 Image readout parameters
The following parameters are available to process the sensor readout:
• Shuffle horizontal readout, enabled by setting bit [7] of serial register [17]
• Mirror horizontal readout, enabled by setting bit [3] of serial register [22]
• Shuffle vertical readout, enabled by setting [2] or serial register [22]
• Flip vertical readout, enabled by setting [4] of serial register [22]
The effect of each of these parameters is probably best described via a series of diagrams, see sections 3.3.2 - below.
Although all the above features may be used in conjunction with one another we will only display one special image readout
parameter at any one time.
3.3.2 Horizontal shuffle
Figure 5 is the reference figure that shows the image readout without any of the optional image parameters, shuffle or mirror,
selected. Figure 5 shows how the image will appear if the horizontal shuffle bit has been selected. Note that the even columns,
(column 2,4,6 etc), are read out first followed by the odd columns, (1,3,5,7 etc).‘
GRGRGRGRGRGR GRGRGRGRGRGR
Where G - Green and R - Red
Figure 4 : Standard Image Readout
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3.3.3 Horizontal mirror
Figure 6 shows the output image with the horizontal mirror feature enabled. Note that the columns are read out in reverse order.
3.3.4 Vertical Flip
Figure 7 shows the output image with the vertical flip feature enabled. Note that the even rows (rows 2,4,6 etc), are read out first
RRRRRRGGGGGGGRGRGRGRGRGR
Where G - Green and R - Red
Figure 5 : Horizontal Shuffle Enabled
GRGRGRGRGRGR RGRGRGRGRGRG
Where G - Green and R - Red
Figure 6 : Horizontal mirror enabled
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followed by the odd rows, (rows 1,3,5 etc)
3.3.5 Vertical Flip
Figure 3.4 shows the output image with the vertical flip feature enabled. Note that the rows are read out in reverse order.
B
G
B
G
B
G
B
G
B
G
G
G
G
G
G
B
B
B
B
B
Where G - Green and B - Blue Figure 7 : Vertical Shuffle enabled
B
G
B
G
B
G
B
G
B
G
G
B
G
B
G
B
G
B
G
B
Where G - Green and B - Blue
Figure 8 : Vertical Flip enabled
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3.4 QCIF Output Modes
VV5410/VV6410 has two QCIF output modes, pan/tilt QCIF (ptQCIF) and sub sampled QCIF (ssQCIF), both of which have the
same output format. The data contained within the active QCIF image differs between the sub sampled and pan tilt modes. As
the QCIF mode contains a quarter of the data of the CIF mode, the effective pixel clock can be run at a quarter of the rate. This
means that in CIF mode a system clock of 16MHz will produce a field rate of 30fps, whereas in QCIF mode a system clock of only
8MHz is required to produce the same field rate. Note that the sensor divides the system clock internally by 4 for CIF mode and 8
for QCIF mode. If the user supplied the sensor with a 16Mhz system clock and selected QCIF mode then a field rate of 60fps is
possible.
3.4.1 Pan/Tilt QCIF
In this mode the QCIF image is generated by outputting a cropped portion of the CIF image as illustrated in Figure 9. When the
pan-tilt QCIF video mode is initially selected the image will be horizontally and vertically justified in the within the full size array
(364 pixels by 292 pixels). The coordinates which define the top left corner of the QCIF portion of the array to be output are
defined by the x-offset & y-offset parameters in serial registers [88 - 91] inclusive.
The x-offset and y-offset parameters are subject to minimum and maximum values which are set according to the video output
mode (horizontal shuffle etc). Any clipping (against a maximum) or clamping (against a minimum) will be automatically controlled
by the sensor logic. Regardless of whether any of the shuffle/mirror modes have been selected the user should always identify
the top left corner coordinates as the x-offset and y-offset. To preserve the Bayer pattern at the sensor output the first pixel image
of the image should always be green followed by red. If the x or y offsets are adjusted by a single step, i.e. adjust the x-offset from
n to n+1, then this pattern will be corrupted. The user should always write an odd number to the x and y offset registers and this
will preserve the Bayer pattern. The 5410, monochrome sensor is unaffected by such an adjustment to the x-offset coordinate, as
the pixels do not contain any colour information.
Figure 9 : Pan/Tilt QCIF Image Format
180 pixels
148 pixels
y-offset
x-offset
364 pixels
292 pixels
QCIF Image
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3.4.2 Sub-Sampled QCIF
In this mode the QCIF image is generated by sub-sampling the CIF image in groups of 4 to preserve the Bayer pattern with every
second group of pixels & lines skipped as illustrated in Figure 10. Although the former would not necessarily apply to a
monochrome sensor the same address sequence is preserved. VV5410 users should ignore the colour references in Figure 10.
Due to the crude nature of the sub-sampling, the resultant output image will be of inferior quality but contains full field of view and
is intended for use in gesture recognition applications or perhaps as a preview option before switching to pan tilt QCIF mode to
view the required scene region in more detail.
Figure 10 : Sub-Sampled QCIF Image Format
Blue Green
Green Red
Blue Green
Green Red
Blue Green
Green Red
Blue Green
Green Red
Blue Green
Green Red
Blue Green
Green Red
Blue Green
Green Red
Blue Green
Green Red
Blue Green
Green Red
Blue Green
Green Red
Blue Green
Green Red
Blue Green
Green Red
Blue Green
Green Red
Blue Green
Green Red
Blue Green
Green Red
Blue Green
Green Red
Blue Green
Green Red
Blue Green
Green Red
Blue Green
Green Red
Blue Green
Green Red
Blue Green
Green Red
Blue Green
Green Red
Blue Green
Green Red
Blue Green
Green Red
Blue Green
Green Red
Blue Green
Green Red
Blue Green
Green Red
Blue Green
Green Red
Blue Green
Green Red
Blue Green
Green Red
Bayer Colourised Pixel Array
Sub-Sampled Bayer Colourised Pixel Array
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4. Black Offset Cancellation
In order to produce a high quality output image from VV6410 it is important to maximise the dynamic range of the video output.
This can be achieved by accurately controlling the video signal black level. Within the sensor array of VV6410 there are a number
of lines that are specified to be black, that is they are exposed to the incident light but they are always held in minimum exposure.
VV6410 also has a number of dark lines, that is lines that are integrated for the same length of time as the visible lines but the
pixels within these dark lines are shielded from incident light by an opaque material (e.g. metal 3). The diagram below shows
where the different types of lines that appear within the full array.
VV5410/VV6410 can perform automatic black offset cancellation. VV5410/VV6410 contains an algorithm that monitors the level
of the designated black pixels and applies a correction factor, if required, to provide an ideal black level for the video stream.
The user can control the application of the offset cancellation parameter. The internally calculated offset can be applied to the
video stream or alternatively an externally calculated offset can be applied or finally there is the option of applying no offset at all.
Details of how to select the aforementioned modes can be found in subsubsection 9.5.5.
The black offset cancellation algorithm accumulates data from the centre 2 of the 4 physical black lines. The internal cancellation
algorithm uses a leaky integrator model to control the size of the calculated offset. The leaky integrator model takes as input the
current offset plus a shifted version of the error between the ideal black level and the current offset. The magnitude of the shift in
the error is programmable. It is also possible to control the range of pixel values that will inhibit a change in the calculated offset.
A narrow band (128 +/- 2 codes) or a wide band (128 +/- 4 codes) can be selected. If the latter is selected and the pixel average
Figure 11 : Physical position of Black and Dark Lines
364 pixels
296 pixels
Dark Lines
8 pixels
4 pixels
Black Lines
Visible Pixel Array
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returned in the current field lies between 124 and 132 then the offset cancellation will remain unchanged.
Following a gain change, or when exitting low-power, sleep or suspend modes, the internal (19bit) offset register will be reset to
the default resulting in an automatic black offset of -64.
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5. Dark Offset Cancellation
VV5410/VV6410 performs dark line offset cancellation as well as black line offset cancellation. A dark line is shielded from
incident light by an opaque material such as metal 3 (as an example) but these lines will be exposed to incident light for the same
length of time as the visible pixels. If the dark pixels are completely shielded from light then no incident light should reach the
pixels and the pixels will produce the same digital code as the black pixels, i.e. 128 internally (therefore 64 externally). The
algorithm used to calculate the dark offset cancellation is identical to that used to calculate the black offset cancellation, however
the dark algorithm does assume that the dark pixels have already been black corrected therefore the target dark average is 64
thus the dark offset cancellation is 0 by default.
The dark offset cancellation algorithm is configured by the dark offset cancellation setup register, [46], see subsubsection 9.5.3.
The only parameter in this that is different from the corresponding table that configures the black offset cancellation algorithm is
the control bit, [bit2], that determines the number of dark lines that are to be used by the cancellation algorithm. It is possible to
select half of the total number of available dark lines to be used to calculate the dark offset cancellation setting. When the former
is selected the dark lines used by the algorithm are always preceeded by another dark line, thereby giving extra immunity from
damaging edge effects that may occur on lines close to the edge of the shield material.
It should be noted that the black and dark offset cancellation are completely independent. For example it is possible for the user
to select internal automatic black offset cancellation but to opt for no dark offset cancellation or indeed choose to perform the dark
offset cancellation externally.
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6. Exposure Control
6.1 Calculating Exposure Period
The exposure time, comprising coarse and fine components, for a pixel and the analogue gain are programmable via the serial
interface.
The coarse exposure value sets the number of complete lines a pixel exposes for, while the fine exposure sets the number of
additional pixel clock cycles a pixel integrates for. The sum of the two gives the overall exposure time for the pixel array.
Exposure Time = ((Coarse setting x Line Period) + (Fine setting)) x (CLKI clock period) x Clock Divider Rationote1
note1: Clock Divider Ratio = 1/(Basic Clock Division * Optional Pixel Clock Divisor)
Default Clock Divider Ratio as follows: (Optional Pixel Clock Divisor = 1)
• PAL/NTSC - 1/2
• CIF - 1/4
• QCIF - 1/8
The maximum coarse and fine exposure settings are a function of the field and line lengths respectively. The maximum coarse
exposure is current field length - 1 and the maximum fine exposure is current line length - fixed offset, see below. If an exposure
value is requested that is beyond the maximum then the applied exposure setting will be clipped to the current maximum.
6.2 Gain Components
The analogue gain in VV5410/VV6410 is programmed via the 8 bit gain register[36]. The analogue gain comprises 2
components, capacitive gain, (set by the ms nibble), and current gain, (set by the ls nibble). It is strongly recommended that the
capacitive gain setting is left at the default value of 4’b1111. Table 7 details the available gain settings in 9bit, (PAL or NTSC),
and 10bit, (CIF or QCIF), modes. We assume that mode_select[24], bit1 is 0. gain[7:0] is the value programmed in register[36].
The ls nibble of the gain value is limited to 4’he, with 4’hf not permitted.
Video Mode Fine Exposure Offset (pck’s)
NTSC 51
PAL 86
CIF 51
QCIF 23
Table 6 : Fine Exposure Offset
The current revision of VV5410/VV6410 in the following modes of operation:
VP3 mode (OFF), QCIF and PAL (Video mode)
has an error in the application of coarse exposure. Please contact STMicroelectronics for more details.
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note: The relationship between the programmed gain value as written to register[36] and the igain (current gain) and
cgain (capacitive gain) is as follows:
igain
If mode_select[24], bit 1 is set then igain[3:0] is the inverse of gain[3:0], i.e. if gain[3:0] = 6, igain[3:0] = 9.
If mode_select[24], bit 1 is reset then igain[3:0] is the inverse of the mirror of gain[3:0], i.e. bit 3 of igain is the inverse of bit 0 of
gain, i.e. gain = 4 and igain = 13.
cgain
cgain is a 6 bit value therefore we have to pad the 4 bits of the gain register. In 10bit modes cgain[1:0] is fixed at 2’b11 and
cgain[5:2] is set to gain[7:4]. In the 9bit modes cgain[1:0] is also set to 2’b11, however cgain[5:2] is set to gain[7:4] divided by 2,
thus gain[7:4] = 4’b1111 gives cgain[5:0] = 6’b011111.
6.2.1 Recommended Gain Settings
To ensure optimum sensor performance it is recommended that the igain setting, controlled by the ls nibble of serial
register[3610], be limited to 12.
6.3 Clock Division
Although the clock divisor register is an 8 bit register the user only has write access to the lower 4 bits as described above. The
upper 4 bits of the register are altered automatically when the video mode is changed by writing to Setup0[16] register. The upper
4 bits are pre-programmed as follows:
10bit ADC mode 9bit ADC mode
gain[7:0] igain[3:0] cgain[5:0] Overall
Gain gain[7:0] igain[3:0] cgain[5:0] Overall
Gain
8’hfe 1 (00012) 63 8.000 8’hfe 1 (00012) 31 8.000
8’hfd 2 (00102) 63 5.333 8’hfd 2 (00102) 31 5.333
8’fc 3 (00112) 63 4.000 8’fc 3 (00112) 31 4.000
8’hfb 4 (01002) 63 3.200 8’hfb 4 (01002) 31 3.200
8’hfa 5 (01012) 63 2.667 8’hfa 5 (01012) 31 2.667
8’hf9 6 (01102) 63 2.2857 8’hf9 6 (01102) 31 2.2857
8’hf8 7 (01112) 63 2.0000 8’hf8 7 (01112) 31 2.0000
8’hf7 8 (10002) 63 1.7778 8’hf7 8 (10002) 31 1.7778
8’hf6 9 (10012) 63 1.6000 8’hf6 9 (10012) 31 1.6000
8’hf5 10 (10102) 63 1.4545 8’hf5 10 (10102) 31 1.4545
8’hf4 11 (10112) 63 1.3333 8’hf4 11 (10112) 31 1.3333
8’hf3 12 (11002) 63 1.2308 8’hf3 12 (11002) 31 1.2308
8’hf2 13 (11012) 63 1.1429 8’hf2 13 (11012) 31 1.1429
8’hf1 14 (11102) 63 1.0667 8’hf1 14 (11102) 31 1.0667
8’hf0 15 (11112) 63 1.0000 8’hf0 15 (11112) 31 1.0000
Table 7 : Analogue Gain Settings
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6.4 Updating Exposure, Gain and Clock Division Settings
Although the user can write a new exposure, gain or clock division parameter at any point within the field the sensor will only
consume these new external values at a certain point. The exceptions to this behaviour are when the user has selected
immediate update of gain and clock division. If the user has selected the former then the new gain or clock division value will be
applied as soon as the serial interface message has completed. The fine and coarse exposure values are always written in a
“timed” manner. There are a number of “update pending” flags available to the user (see Status0 reg[2] for details) that allows the
user to detect when the sensor has consumed one of the timed parameters. In the next section of this document we will detail all
the timed parameters and describe when they are updated.
It is important to realise that there is a 1 frame latency between a new exposure value being applied to the sensor array and the
results of this new exposure value being read-out. The same latency does not exist for the gain value. To ensure that the effect of
the new exposure and gain values are coincident the sensor delays the application of the new gain value by approximately one
frame relative to the application of the new exposure value.
If the user is using the autoincrement option in the serial interface when writing a new series of exposure/gain and clock division
parameters then it is important to ensure that the sensor receives the complete message bunch before updating any of the
parameters. It is also important that the timed parameters are updated in the correct order, we will discuss this fully in the next
section. If an autoincrement message sequence is in progress but we have reached the point in the field timing where the gain
value would normally be updated, we actually inhibit the update. We inhibit the update to ensure that the gain change is not
passed to the sensor while a change in the exposure is still pending.
Video mode Register[37], bits[7:4] Effective system clock divisor
CIF 4’b0001 Divide CLKI/CLKIP by 4
QCIF 4’b0011 Divide CLKI/CLKIP by 8
PAL/NTSC 4’b0000 Divide CLKI/CLKIP by 2
Table 8 : System Clock Divisor Options
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7. Timed Serial Interface Parameters
The previous section, Exposure Control, introduced the concept of a “timed parameter”, that is information that is written via the
serial interface but will not be used immediately by the sensor, rather there will be a delay before the information is passed to the
internal registers (referred to as the working registers) from the serial interface registers (referred to as the shadow registers). It is
the contents of the working registers that will determine sensor behaviour.
The architecture of VV5410/6410 requires that many of the programmable registers are handled in such a manner. This section
will identify all these registers, describe what they are all used for and then go on to explain when they are all updated.
7.1 Listing and Categorizing the Parameters
The timed parameters are split into 6 categories as follows:
• fine exposure
• coarse exposure
• clock division
• gain
• pan parameter
• tilt parameter
• video timing
There is a “pending” flag for each of the above categories. These flags are stored in Status0 Register[2]. If one of the flags is high
this indicates that the working register/s controlled by that flag have yet to be updated from the according shadow register/s. This
feedback information could be useful if a user is, for example, attempting to write an exposure controller. The status of the
pending flags allows accurate timing of the serial interface communications.
7.1.1 Fine Exposure
The fine exposure category simply comprises registers[32,33].
7.1.2 Coarse Exposure
The coarse exposure category simply comprises registers[34,35].
7.1.3 Clock Division
The clock division category simply comprises register[37].
7.1.4 Gain
The gain category simply comprises register[36].
7.1.5 Pan Parameter
The pan parameter category comprises the following registers:
• Setup0[16] (The “pan_pend” flag will only be set if the subsampled QCIF mode is entered or exited)
• Setup1[17] (The “pan_pend” flag will only be set if the hshuffle control bit is changing state)
• Data_format[22] (The “pan_pend” flag will only be set if the hmirror control bit is changing state)
• X-offset[87,88] (The “pan_pend” flag set unconditionally)
7.1.6 Tilt Parameter
The tilt parameter category comprises the following registers:
• Setup0[16] (The “tilt_pend” flag will only be set if the subsampled QCIF mode is entered or exited)
• data_format[22] (The “tilt_pend” flag will be set if the hshuffle control bit or the hmirror control bit is changing state)
• Y-offset[89,90] (The “tilt_pend” flag set unconditionally)
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7.1.7 Video Timing Parameter
The video timing parameter category comprises all the other shadow/working register pairs. The video timing parameter update
pending flag will be unconditionally set if any of the following registers are written to:
• Setup0[16]
• Setup1[17]
• fg_mode[20]
• data_format[22]
• op_format[23]
• mode_select[24]
• Dark Pixel Offset[44,45]
• Dark Pixel Cancellation Setup Register
• Black Pixel Offset[44,45]
• Black Pixel Cancellation Setup Register
• Line Length[82,83]
• Field Length[97,98]
7.2 Timed Parameter Update Points
The timed parameter categories are updated as follows:
note: We refer to odd and even fields in the Table 9 below. In a video mode like CIF or QCIF the fields are all identical in length,
we still have to be able to differentiate between fields to enable correct updating of register parameters.
The order that the above timed parameters are updated is critical. Let us assume that all the pending flags are set, i.e. we have
written to at least one register in each category. The working registers will be updated in the following order:
1. Coarse exposure
2. Tilt parameters
Timed parameter category Updated point
fine exposure Conditional on a change pending in the line length register.
Line length change pending
: update fine exposure at the odd to even field
transition
Line length change not pending
: update fine exposure during the start of
active video (SAV) region of the end of frame (EOF) line (the line that follows
the last line of active video) in the odd field.
coarse exposure Updated during the SAV region of the first dark line in an odd field
clock division Updated at the odd to even field transition
gain Updated during the SAV region of the EOF line in the odd field
pan parameter Updated during the SAV region of the EOF line in the odd field
tilt parameter Updated during the SAV region of the first visible line in an odd field
video timing Updated at the odd to even field transition
Table 9 : Timed Parameter Update Points
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8. Digital Video Interface Format
8.1 General description
The video interface consists of a bidirectional, tri-stateable 5-wire data bus. The nibble transmission is synchronised to the rising
edge of the system clock (Figure 31).
Digital video data may be either 8 or 10 bits per sample, and can be transmitted in one of the following ways:
10-bit data
1. A series pair of 5-bit nibbles, most significant nibble first, on 5 wires.
2. An 8-bit number e.g. line code. line numbers and status line data is padded with 00 in the least significant two bits to make
up a 10-bit value.
8-bit data
1. A single 8 bit byte over 8 output wiresnote.
2. A series pair of 4-bit nibbles, most significant nibble first, on 4 wires.
3. The top 8-bits of a 10-bit value e.g. pixel data or line averages is used as the 8-bit equivalent.
note: if the 8-wire output mode has been selected then the normal FST/LST pin function is sacrificed as these pins are required
to output data information
In the following description the 4-wire mode is used as an example. The 5-wire mode can be viewed as a variant of the 4-wire
mode. Data is output on the least significant data wires available. e.g. in 4-wire mode, data is output on data wires D[3:0] while in
Read-out Order Progressive Scan (Non-interlaced)
Form of encoding Uniformly quantised, PCM, 8/10 bits per sample
Correspondence between video signal
levels and quantisation levels: The internal10-bit pixel data is clipped to ensure that 0Hand 3FFH(5
Wire) or FFH(4/8 Wire) values do not occur when pixel data is being
output on the data bus.
10-Bit Data 8-Bit Data
Pixel Values 1 to 1022 Pixel Values 1 to 254
Black Level 64 Black Level 16
Table 10 : Video encoding parameters
Figure 12 : Possible Output Modes
4 - wire Output Mode D9,D8,D7,D6D5,D4,D3,D2
D5,D4,D3,D2D9,D8,D7,D6
8-bit Pixel Data
10-bit Pixel Data
5 - wire Output Mode D9,D8,D7,D6,D5D4,D3,D2,D1,D0
D4,D3,D2,D1,D0D9,D8,D7,D6,D5
8- wire Output Mode D9,D8,D7,D6,D5,D4,D3,D2D9,D8,D7.............D2,D1,D0
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5-wire mode data is output on D[4:0].
Multiplexed with the sampled pixel data is control information including both video timing references, sensor status/configuration
data and the pixel average from the current line.
Video timing reference information takes the form of field start characters, line start characters, end of line characters and a line
counter.
Where hexadecimal values are used, they are indicated by a subscript H, such as FFH; other values are decimal.
8.2 Embedded control data
To distinguish the control data from the sampled video data all control data is encapsulated in embedded control sequences.
These are 6 bytes long and include a combined escape/sync character sequence, 1 control byte (the ‘command byte’) and 2
bytes of supplementary data.
To minimise the susceptibility of the embedded control data to random bit errors redundant coding techniques have been used to
allow single bit errors in the embedded control words to be corrected. However, more serious corruption of control words or the
corruption of escape/sync characters cannot be tolerated without loss of sync to the data stream. To ensure that a loss of sync is
detected a simple set of rules has been devised. The four exceptions to the rules are outlined below:
1. Data containing a command word that has two bit errors.
2. Data containing two ‘end of line’ codes that are not separated by a ‘start of line’ code.
3. Data preceding an ‘end of field’ code before a start of frame’ code has been received.
4. Data containing line that do not have sequential line numbers (excluding the ‘end of field’ line).
If the host detects one of these violations then it should abandon the current field of video
8.2.1 The combined escape and sync character
Each embedded control sequence begins with a combined escape and sync character that is made up of three words. The first
two of these are FFH FFH- constituting two words that are illegal in normal data. The next word is 00H - guaranteeing a clear
signal transition that allows a host to determine the position of the word boundaries in the serial stream of nibbles. Combined
escape and sync characters are always followed by a command byte - making up the four byte minimum embedded control
sequence.
8.2.2 The command word
The byte that follows the combined escape/sync characters defines the type of embedded control data. Three of the 8 bits are
used to carry the control information, four are ‘parity bits’ that allow the host to detect and correct a certain level of errors in the
transmission of the command words, the remaining bit is always set to 1 to ensure that the command word never has the value
00H. The coding scheme used allows the correction of single bit errors (in the 8-bit sequence) and the detection of 2 bit errors
The three data bits of the command word are interpreted as shown in Figure 13.The even parity bits are based on the following
relationships:
1. An even number of ones in the 4-bit sequence (C2, C1, C0 and P0).
2. An even number of ones in the 3-bit sequence (C2, C1, P1).
3. An even number of ones in the 3-bit sequence (C2, C0, P2).
4. An even number of ones in the 3-bit sequence (C1, C0, P3).
Table 13 shows how the parity bits maybe used to detect and correct 1-bit errors and detect 2-bit errors.
8.2.3 Supplementary Data
The last 2 bytes of the embedded control sequence contains supplementary data. The are two options:
1. The last 2 bytes of the SAV 6 byte sequence contain the current 12-bit line number. The 12-bit line number is packaged up
by splitting it into two 6-bit values. Each 6-bit value is then converted into an 8-bit value by adding a zero to the start and an
odd word parity bit at the end.
2. The 5th byte of the EAV sequence contains a pixel average for that line either based upon the middle 256 pixels if the
CIF,PAL or NTSC video modes are selected or the middle 128 pixels if the QCIF video mode is selected. The final byte is
FFH.
Note: in 5-wire mode, the embedded control data is calculated as detailed above and output as the most significant 8-bits. The
least significant 2-bits are padded with zero.
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note1: This code is only generated in the PAL or NTSC video modes
note2: This code is only generated in the PAL or NTSC video modes
We include Table 12 to show how the 8 bit control codes are mapped onto the output data bits in the 5 wire mode.
Table 12 : Mapping 8bit control codes to 5 wire output mode
Line Code Nibble XH(1 C2 C1C0) Nibble YH(P3 P2 P1 P0)
End of Line 10002(8H) 00002 (0H)
Blank Line (BL) 10012(9H) 11012 (DH)
Black line (BK) 10102(AH) 10112 (BH)
Visible Line (VL) 10112(BH) 01102 (6H)
Start of Even Field (SOEF) 11002(CH) 01112 (7H)
End of Even Field (EOEF) 11012(DH) 10102 (AH)
Start of Odd Field (SOOF)note1 11102(EH) 11002 (CH)
End of Odd Field (EOOF)note2 11112(FH) 00012 (1H)
Table 11 : Embedded Line Codes
Line Code Most significant nibble
Data[4:0] Least significant nibble
Data[4:0]
End of Line 1_00002(10H) 0_00002 (00H)
Blank Line (BL) 1_00112(13H) 1_01002 (14H)
Black line (BK) 1_01012(15H) 0_11002 (0CH)
Visible Line (VL) 1_01102(16H) 1_10002 (18H)
Start of Even Field (SOEF) 1_10002(18H) 1_11002 (1CH)
End of Even Field (EOEF) 1_10112(1BH) 0_10002 (08H)
Start of Odd Field (SOOF) 1_11012(1DH) 1_00002 (10H)
End of Odd Field (EOOF) 1_11102(1EH) 0_01002 (04H)
Parity Checks Comment
P3P2P1P0
✔✔✔✔Code word un-corrupted
✔✔✔✘P0 corrupted, line code OK
✔✔✘✔P1 corrupted, line code OK
✔✘✔✔P2 corrupted, line code OK
Table 13 : Parity Checking
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✘✔✔✔P3 corrupted, line code OK
✘✘✔✘C0 corrupted, invert sense of C0
✘✔✘✘C1 corrupted, invert sense of C1
✔✘✘✘C2 corrupted, invert sense of C2
All other codes 2-bit error in code word.
Parity Checks Comment
P3P2P1P0
Table 13 : Parity Checking
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8.3 Video timing reference and status/configuration data
Each frame of video sequence comprises 2 fields. Each field of data is constructed of the following sequence of data lines.
Figure 13 : Embedded Control Sequence
Command (Line Code)
Supplementary Data
(i) Line Number (L11 MSB) output in SAV
or (ii) Pixel average output in EAV (4-wire used as example, P7MSB)
Odd
word
parity
01234567Bit
Nibble D0 = FH
Nibble D1 = FH
P6
P7P5P4
L11
0 L10 L9L7
L8L6P
P2
P3P1P011 1 1 11 1 1
Nibble D2
Nibble D3
01234567Bit
L5
0 L4L3L1
L2L0P
Nibble D0
Nibble D1
01234567Bit
C2
1 C1C0P2
P3P1P0
Nibble YH
Nibble XH
4-wireoutput
mode
8-bit Data
Escape/Sync Sequence
D0
D1
D2
D3
YH
XH
0H
0H
FH
FH
FH
FH
FFHFFH00HXYHD3D2D1D0
5-wireoutput
mode 00H
00H
1FH
1FH
1FH
1FH
Nibble D3Nibble D2
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1. A start of field line
2. A number of black lines
3. A number of blank (or dark) lines
4. A number active video lines
5. An end of field line
6. A number of blank or black lines
Table 14 details the number of each type of data lines for NTSC, PAL, CIF and QCIF output formats. Each line of data starts with
an embedded control sequence that identifies the line type (as outlined in Table 14). The control sequence is then followed by
two bytes that contain a coded line number. The line number sequences starts with the start-of-frame line at 00Hand increments
one per line up until the end-of-frame line. Each line is terminated with an end-of-line embedded control sequence. The line start
embedded sequences must be used to recognise visible video lines as a number of null bytes may be inserted between
successive data lines.
There are a series of figures (Figure 14 - Figure 25) on the following pages that show line type construction of the fields in each
Video Format NTSC PAL CIF QCIF
VP3 mode On Off On Off On Off On Off
Extra Black Lines On Off N/A On Off N/A On Off N/A On Off N/A
1st Field
Start of Field Line 1 1 1 1 1 1 1 1 1 1 1 1
Black Lines 8 2 8 8 2 16 8 2 16 8 2 8
Blanking Lines 1 7 0 1 7 0 1 7 0 1 7 0
Dark Lines 0 0 8 0 0 2 0 0 10 0 0 2
Active Video lines 244 244 244 292 292 292 292 292 292 148 148 148
End of Field Line 1 1 1 1 1 1 1 1 1 1 1 1
Blanking Lines 0 7 0 0 9 0 0 17 0 0 1 0
Black Lines 7 0 0 9 0 0 17 0 0 1 0 0
Total 262 262 262 312 312 312 320 320 320 160 160 160
2nd Field
Start of Field Line 1 1 1 1 1 1 1 1 1 1 1 1
Black Lines 8 2 8 8 2 16 8 2 16 8 2 8
Blanking Lines 1 7 0 1 7 0 1 7 0 1 7 0
Dark Lines 0 0 8 0 0 2 0 0 10 0 0 2
Active Video lines 244 244 244 292 292 292 292 292 292 148 148 148
End of Field Line 1 1 1 1 1 1 1 1 1 1 1 1
Blanking Lines 0 8 0 0 10 0 0 17 0 0 1 0
Black Lines 8 0 1 10 0 1 17 0 0 1 0 0
Total 263 263 263 313 313 313 320 320 320 160 160 160
Table 14 : Field and Frame Formats
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of the available video modes in VV5410/VV6410.
8.3.1 Blank lines
In addition to padding between data lines, actual blank data lines may appear in the positions indicated above. These lines begin
with start-of-blank-line embedded control sequences and are constructed identically to active video lines except that they will
contain only blank bytes, 07H, (expressed as 01CH in 10bit form).
8.3.2 Black line timing
The black lines (which are used for black offset calculation) are identical in structure to valid video lines except that they begin
with a start-of-black line code and contain either information from the sensor black lines or blanking data.
By default VP3 mode (see mode_select[24] for details) is selected. It is an option in any of the VP3 modes to select the additional
black lines to be output (line 3-8). If the VP3 mode is not selected then all the black lines are enabled - no blank lines are output.
Internally there is the concept of dark lines - to be used for dark offset cancellation (see following diagrams to identify their
position within the frame timing model), however externally the dark lines share the same line type code as the black lines.
8.3.3 Padding Lines and Fields
The user may choose to extend the inter-field period by increasing the field length by writing to serial registers 97 & 98. In this
event, the appropriate number of additional black or blank lines is inserted between the End Of Field (EOF) line and the Start Of
Field (SOF) line. This means that the distance between SOF and EOF will remain constant.
The user can also extend the line length by writing to serial registers 82 and 83. The line length padding is inserted after the EAV
sequence, ensuring that the distance between the SAV and EAV sequences will remain constant.
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Figure 14 : NTSC Field and Frame Formats - VP3 Mode On, Extra Black Lines Off
8 Blanking Lines
262
2 Black Lines
Start Of 2nd Field Line
End Of 2nd Field Line
7 Blanking Lines
244 Visible Lines
8 Blanking Lines
0
2nd Field = 263 Lines
Frame = 525 Lines
1
0
2
3
9
10
11
253
251
252
12
254
262
255
2 Black Lines
Start Of 1st Field Line
End Of 1st Field Line
7 Blanking Lines
244 Visible Lines
7 Blanking Lines
1st Field = 262 Lines
1
0
2
3
9
10
11
253
251
252
12
254
261
255
Start Of 1st Field Line
8
8
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Figure 15 : NTSC Field and Frame Formats - VP3 Mode On, Extra Black Lines On
8 Blanking Lines
262
8 Black Lines
Start Of 2nd Field Line
End Of 2nd Field Line
Blanking Line
244 Visible Lines
8 Black Lines
0
2nd Field = 263 Lines
Frame = 525 Lines
1
0
2
3
9
10
11
253
251
252
12
254
262
255
8 Black Lines
Start Of 1st Field Line
End Of 1st Field Line
Blanking Line
244 Visible Lines
7 Black Lines
1st Field = 262 Lines
1
0
2
3
9
10
11
253
251
252
12
254
261
255
Start Of 1st Field Line
8
8
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End Of 2nd Field Line261
End Of 2nd Field Line
8 Dark Lines
244 Visible Lines
17
18
260
258
259
19
261
16
9
262 1 Black Line
Figure 16 : NTSC Field and Frame Formats - VP3 Mode Off
8 Black Lines
Start Of 2nd Field Line
0
2nd Field = 263 Lines
Frame = 525 Lines
1
0
2
3
8 Black Lines
Start Of 1st Field Line
End Of 1st Field Line
8 Dark Lines
244 Visible Lines
1st Field = 262 Lines
1
0
2
3
9
17
18
260
258
259
19
261
Start Of 1st Field Line
8
16
10
262 1 Black Line
8
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Figure 17 : PAL Field and Frame Formats - VP3 Mode On, Extra Black Lines Off
10 Blanking Lines
312
2 Black Lines
Start Of 2nd Field Line
End Of 2nd Field Line
7 Blanking Lines
292 Visible Lines
10 Blanking Lines
0
2nd Field = 313 Lines
Frame = 625 Lines
1
0
2
3
9
10
11
301
299
300
12
302
312
303
2 Black Lines
Start Of 1st Field Line
End Of 1st Field Line
7 Blanking Lines
292 Visible Lines
9 Blanking Lines
1st Field = 312 Lines
1
0
2
3
9
10
11
301
299
300
12
302
311
303
Start Of 1st Field Line
8
8
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Figure 18 : PAL Field and Frame Formats - VP3 Mode On, Extra Black Lines On
10 Black Lines
312
8 Black Lines
Start Of 2nd Field Line
End Of 2nd Field Line
Blanking Line
292 Visible Lines
10 Black Lines
0
2nd Field = 313 Lines
Frame = 625 Lines
1
0
2
3
9
10
11
301
299
300
12
302
312
303
8 Black Lines
Start Of 1st Field Line
End Of 1st Field Line
Blanking Line
292 Visible Lines
9 Black Lines
1st Field = 312 Lines
1
0
2
3
9
10
11
301
299
300
12
302
311
303
Start Of 1st Field Line
8
8
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Figure 19 : PAL Field and Frame Formats - VP3 Mode Off
312
Start Of 2nd Field Line
0
2nd Field = 313 Lines
Frame = 625 Lines
0
16 Black Lines
Start Of 1st Field Line
End Of 1st Field Line
2 Dark Lines
292 Visible Lines
1st Field = 312 Lines
1
0
2
3
17
19
20
310
308
309
21
311
Start Of 1st Field Line
16
1 Black Line
18
15
14
16 Black Lines
End Of 2nd Field Line
2 Dark Lines
292 Visible Lines
1
2
3
17
19
20
310
308
309
21
311
16
18
15
312 1 Black Line
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Figure 20 : CIF Field and Frame Formats - VP3 Mode On, Extra Black Lines Off
17 Blanking Lines
319
2 Black Lines
Start Of 2nd Field Line
End Of 2nd Field Line
7 Blanking Lines
292 Visible Lines
17 Blanking Lines
0
2nd Field = 320 Lines
Frame = 640 Lines
1
0
2
3
9
10
11
301
299
300
12
302
319
303
2 Black Lines
Start Of 1st Field Line
End Of 1st Field Line
7 Blanking Lines
292 Visible Lines
17 Blanking Lines
1st Field = 320 Lines
1
0
2
3
9
10
11
301
299
300
12
302
319
303
Start Of 1st Field Line
8
8
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Figure 21 : CIF Field and Frame Formats - VP3 Mode On, Extra Black Lines On
17 Black Lines
319
8 Black Lines
Start Of 2nd Field Line
End Of 2nd Field Line
Blanking Line
292 Visible Lines
17 Black Lines
0
2nd Field = 320 Lines
Frame = 640 Lines
1
0
2
3
9
10
11
301
299
300
12
302
319
303
8 Black Lines
Start Of 1st Field Line
End Of 1st Field Line
Blanking Line
292 Visible Lines
17 Black Lines
1st Field = 320 Lines
1
0
2
3
9
10
11
301
299
300
12
302
319
303
Start Of 1st Field Line
8
8
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Figure 22 : CIF Field and Frame Formats - VP3 Mode Off
319
16 Black Lines
Start Of 2nd Field Line
End Of 2nd Field Line
0
2nd Field = 320 Lines
Frame = 640 Lines
1
0
2
3
319
16 Black Lines
Start Of 1st Field Line
End Of 2nd Field Line
10 Dark Lines
292 Visible Lines
1st Field = 320 Lines
1
0
2
3
17
18
30
28
29
26
317
319
318
Start Of 1st Field Line
16
16
27
10 Dark Lines
292 Visible Lines
17
18
317
318
End Of 1st Field Line
30
28
29
26
27
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Figure 23 : QCIF Field and Frame Formats - VP3 Mode On, Extra Black Lines Off
0
Frame = 320 Lines
Start Of 1st Field Line
2 Black Lines
Start Of 1st Field Line
End Of 1st Field Line
7 Blanking Lines
148 Visible Lines
Blanking Line
1st Field = 160 Lines
1
0
2
3
9
10
11
157
155
156
12
158
159
8
End Of 2nd Field Line
Blanking Line
158
159
2 Black Lines
Start Of 2nd Field Line
End Of 2nd Field Line
7 Blanking Lines
148 Visible Lines
Blanking Line
2nd Field = 160 Lines
1
0
2
3
9
10
11
157
155
156
12
158
159
8
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Figure 24 : QCIF Field and Frame Formats - VP3 Mode On, Extra Black Lines On
0
Frame = 320 Lines
Start Of 1st Field Line
8 Black Lines
Start Of 2nd Field Line
End Of 2nd Field Line
Blanking Line
148 Visible Lines
Black Line
2nd Field = 160 Lines
1
0
2
3
9
10
11
157
155
156
12
158
159
8
8 Black Lines
Start Of 1st Field Line
End Of 1st Field Line
Blanking Line
148 Visible Lines
Black Line
1st Field = 160 Lines
1
0
2
3
9
10
11
157
155
156
12
158
159
8
End Of 2nd Field Line
Black Line
158
159
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Figure 25 : QCIF Field and Frame Formats - VP3 Mode Off
0
Frame = 320 Lines
Start Of 1st Field Line
8 Black Lines
Start Of 2nd Field Line
End Of 2nd Field Line
2 Dark Lines
148 Visible Lines
2nd Field = 160 Lines
1
0
2
3
9
11
157
155
156
12
159
8
8 Black Lines
Start Of 1st Field Line
End Of 1st Field Line
2 Dark Lines
148 Visible Lines
1st Field = 160 Lines
1
0
2
3
9
10
11
157
155
156
12
159
8
End Of 2nd Field Line159
158
158
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Start of Active Video (SAV)
Line
Figure 26 : Line Data Format.
End of Active Video (EAV)
Video Data
YHD1D0
D3D2PMPLPMPL
PMPLPMPLPMPL
PMPL
Number
SAV
8H0H
XH
Line
Code
Escape/Sync
Sequence Line
Code
Escape/Sync
Sequence
(i)
(ii)
(iii)
(iv)
(v)
Blanking Line (BL)
Black Line (BK)
Visible Line (VL)
Start of Frame (SOF)
End of Frame (EOF)
P = Blanking Level (07H)
P = Valid Black Pixel Data
P = Valid Pixel Data
P = Sensor Status Data, data at pixel position 0 and 1 set to blanking level, 07H.
P = Blanking Level (07H)
N/2 Even PixelsN/2 Odd Pixels
N Pixels
0 1 N/2 -1 N/2 N -1 N -2
0 1 N -1 1 N-4 N-2
Pixel Number (Unshuffled Pixel Data)
Pixel Number (Shuffled Pixel Data)
4-wire Output Mode
Line Format
8-wire Output Mode
FFH00HXH YHD3 D2D1 D0P P P P P P FFH00H80HFFH
0HFH0H
FH
Line Period
FH
D1D0
D3D2
D3 D2D1 D0
Null
Chars
Pixel
Avg
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Start of Active Video
Figure 27 : Status Line Data Format and FST Signals
End of Active Video
Serial Interface Register Values
0H1H
0H1H0H7H
FHFH
1H9H
(SAV) (EAV)
CH7H0H7H0H7HAH0H0H7H
0H7H
0H7H8H0H
0H
0H
Start of Frame
Line Code
DeviceL
(Register 1)
Padding
Characters
FFH00H80HFFH
07H07H
07H07H19H07HA0H07H
00HC7H01H01H
FFH
8-wire Output Mode
4-wire Output Mode
D1D0
D3D2
D3 D2D1 D0
FH
FST Pin:
00H04H
00H04H00H1CH
3FH3FH
18H1CH00H1CH00H1CH14H00H00H1CH
00H1CH
00H1CH10H00H
00H
Line
Number 0 DeviceH
(Register 0) DeviceL
(Register 1)
5-wire Output Mode
D1D0
D3D23FH
DeviceH
(Register 0)
Line
Number 0
14H00H
Padding
Characters
Padding
Characters
00H
(i) Frame start pulse - qualifies status line information - selected by writing 2’b01 to fg_mode register[7:6], see Table 32 for details
(ii) Flash synchronisation mode for FST - high in line following EOF, falls at start of EAV in Status line - selected by writing 2’b1x to serial register, 14(hex)
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8.3.4 Valid video line timing
All valid video data is contained on active video lines. The pixel data appears as a continuous stream of bytes within the active
lines. The pixel data may be separated from the line header and end-of-line control sequence by a number of ‘blank’ bytes (07H).
8.3.5 Start of frame line timing
The start of frame line which begins each video field contains no video data but instead contains the contents of the serial
interface register map. Immediately following the SAV sequence there are 2 padding pixels, (see Figure 27), output as blanking
levels, (07H). There will be more blanking codes output after all the serial interface registers have been output . The padding
pixels continue to be output until terminated by an end-of-line control sequence. To ensure that no escape/sync characters, (the
reserved FF,FF,00 sequence), appear in the sensor status/configuration information the code 07H is output after each serial
interface value.
If a serial interface register location is unused then a default value, the DeviceH register, is output. The read-out order of the
registers is independent of whether the pixel read-out order is shuffled or un-shuffled.
8.3.6 End of frame line timing
The end of frame line contains no video data. Its sole purpose is to indicate the end of a frame.
8.4 Detection of sensor using data bus state
On power-up a sensor will pull all data lines high and these lines will remain high while the device is in the power up default, low
power state. The device is removed from this low power mode by the I2C host writing to sensor register, setup0 [address 1016].
When the device exits the low power mode it will follow a defined power up sequence, please see Figure 30 for more details.
Upon completion of the power up sequence the sensor will begin streaming video.
8.5 Resetting the Sensor Via the Serial Interface
Bit 2 of setup0 register allows the VV5500/VV6500 sensor to be reset to its power-on state via the serial interface. Setting this
“Soft Reset” bit causes all of the serial interface registers including the “Soft Reset” bit to be reset to their default values. This
“Soft Reset” leaves the sensor in low-power mode.
8.6 Resetting the Sensor Via the RESETB pin
On power-up the RESETB pin is configured as an active low system reset which has the same effect as a soft reset issued via
the serial interface as described above.
8.7 Resynchronising the Sensor Via the RESETB pin configured as SINB
Bit 5 of the pin mapping register [21] allows the RESETB pin to be re-configured as an active low (edge triggered) system
synchronisation signal which will reset the video timing to the beginning of a field but will NOT reset the serial registers therefore
the host does not have to reconfigure the sensor following a resynchronisation.
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Figure 28 : Reseting the Sensor via the Serial Interface (example shown is 4wire output mode)
FH
9H,6H,9H,6H...
N 0 1
D[3:0]
CLKI
Frame
Number
SDA
SCL
2345
Start of Frame Line for the 1st
frame of valid video data. Valid Video data.
SR0
SR1
SR2
SR6
SR7
setup0[2]
SR0-SR1 “Soft-Reset” Command. At the end of the command the sensor is reset and enters low-power mode.
SR2 The sensor enters low-power mode.
SR3-SR4 “Exit Low Power Mode” Command. Powers-up analogue circuits and initates the sensor’s 4-frame start-up sequence
SR5-SR6 1 Frame of alternating 9H & 6H data on D[3:0] for the host to determine the best sampling phase for the nibble data (D[3:0]).
SR7-SR8 4 Frames after the “Exit Low-Power mode” command, the sensor starts outputing valid video data.
One frame of 9H&6
Hdata.
FH
SR3
SR4
SR5
SR8
setup0[0]
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8.8 Power-up, Low-power and Sleep modes
Please note that the following descriptions of low power and sleep modes assumes that the user has selected the optional 4 wire
output mode, that is D[3:0] will transmit the digital video data. If the 5-wire or 8-wire modes are selected the same basic behaviour
is followed however the contents of the data bus will differ slightly.
8.8.1 Power-Up/Down (Figure 29)
The sensor enters low-power mode on power-up. On power-up all of the data bus lines are driven high immediately and the
device is in low-power mode (Section 8.8.2).
The sensor will remain in the low power mode until the external host sends the appropriate message over I2C to clear the low
power bit - bit0 of serial reguister, setup0, index 1016.
After the “Exit Low-Power Mode” command has been sent the sensor will output for one frame, a continuous stream of alternating
9H and 6H values on D[3:0] The patterns generated in 5 and 8 wire modes are given in Table 16 below. By locking onto the
resulting 0101/1010 patterns appearing on the data bus lines the host can determine the best sampling position for the nibble
data. After the last 9H6Hpair has been output the data bus returns to FH,(1FHin 5 wire mode), until the start of fifth frame. At this
point the first active video frame will be output. After the host has determined the correct sampling position for the data, it should
then wait for the next start of frame line (SOF).
PU0 System Power Up
PU1 Sensor enters low power mode and databus bits driven high.
PU2 Host enables the sensor clock, CLKI.
PU3-PU4 The host sends a “Soft-Reset” command to the sensor via the serial interface. This ensures that
the sensor is in low-power mode.
PU5 Host issues command to remove sensor from low-power mode.
PU6-PU7 Sensors begins execution 4 frame start sequence.
PU8-PU9 One frame of alternating 9H & 6H data on D[3:0] for the host to determine the best sampling
phase for video data.
PU10-PU11 4 Frames after the “Exit Low-Power Mode” serial comms, the sensor starts outputing valid video
data.
Table 15 : Typical System Power-Up
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Figure 29 : Typical System Power-Up Procedure
43
2
10
FH
FH
3V3
0V
9H,6H,9H,6H...
Regulated
Sensor
Power
D[3:0]
CLKI
Frame
Number
SDA
SCL
PU0
PU1
PU2
PU3
PU4
PU5
Start of Frame Line for the
1st frame of valid video data.
One frame of 9H & 6H data.
PU6
PU7
PU8
PU9
PU10
PU11
setup0[2]
setup0[0]
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8.8.2 Low-Power Mode (Figure 30)
Under the control of the serial interface the sensor analog circuitry can be powered down and then repowered. When the low-
power bit is set via the serial interface, all the data bus lines will go high at the end of the end of frame line of the current frame.
At this point the analog circuits in the sensor will power down. The system clock must remain active for the duration of low power
mode.
During low power mode only the analog circuits are powered down, the values of the serial interface registers e.g. exposure and
gain are preserved. The internal frame timing is reset to the start of a video frame on exiting low-power mode. In a similar manner
to the previous section, the first frame after the serial comms contains a continuous stream of alternating 9H and 6H - or
equivalent for the alternative ouput databus widths - to allow the host to re-confirm its sampling position. Then three frames later
the first start of frame line is generated.
8.8.3 Sleep Mode
Sleep mode is similar to the low-power mode, except that analog circuitry remains powered. When the sleep command is
received via the serial interface the pixel array will be put into reset and the data lines all will go high at the end of the current
frame. Again the system clock must remain active for the duration of sleep mode.
When sleep mode is disabled, the CMOS sensor’s frame timing is reset to the start of a frame. During the first frame after exiting
from sleep mode the data bus will remain high, while the exposure value propagates through the pixel array. At the start of the
second frame the first start of field line will be generated.
8.8.4 System clock status during sensor low-power modes
To allow the sensor to enter and exit the low power and sleep modes the system clock, CLKI, must be active.
8.9 Suspend mode
Under the control of the SUSPEND pin VV5410/VV6410 can be forced into an ultra low power mode. The sensor will consume
less than 80uA of current while suspended. While the sensor is in this mode video output is turned off and no serial
communications can occur.
The SUSPEND mode is effectively identical to a power on reset - all the video timing blocks within the sensor are reset as are the
contents of the serial interface, therefore the user will have to perform a compete reconfiguration of the device on exitting
SUSPEND. The sensor will also repeat the full 4 field power up sequence.
8.10 Data Qualification Clock, QCK
VV5410/VV6410 provides a data qualification clock, (see Figure 31), to qualify the information output on data bus. The sensor
can generate two styles of qualification clock:
• Fast QCK, clocks at nibble rate. The falling edge of this clock qualifies data
Mode 10-bit Value Output Data Bus Pattern
4-Wire 258H 9H/6H(10012/01102)
5-Wire 136H 09H/16H(010012/101102)
8-Wire 096H / 069H 25H/1AH(001001012/000110102)
Table 16 : Output Data Bus Patterns for determination of Best Sampling Position
Mode Description Approx. Sensor Current
Suspend Sensor in lowest power state. Suspend has been
asserted by host. c.80uA
Table 17 : VV5410/VV6410 suspend mode power consumption
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.
Figure 30 : Entering and Exiting Low Power Mode (example is 4wire mode).
N 0 1
D[3:0]
CLKI
Frame
Number
SDA
SCL
2 3 4 5
Start of Frame Line for the 1st
frame of valid video data. Valid Video data.
LP0
LP1
LP3
LP2
LP7
LP8
setup0[0]
LP0-LP1 “Enter Low Power Mode” Command.
LP2 At end of current frame, the sensor will enter the low power mode and the databus will be driven high.
LP3-LP4 “Exit Low Power Mode” Command sent to sensor - sensor begins power up sequence.
LP5-LP6 1 Frame of alternating 9H & 6H data on D[3:0] for the host to determine the best sampling phase for the nibble data (D[3:0]).
LP7-LP8 4 Frames after the “Exit low Power Mode” command, the sensor starts outputing valid video data.
One frame of 9H&6
Hdata.
FHFH
9H,6H,9H,6H...
LP4
LP5
LP6
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• The slow QCK, clocks at pixel rate. Both the falling and rising edge of this clock are used to qualify data. The most significant
data nibble is qualified by the rising edge of the slow QCK and the least significant nibble is qualified by the falling edge of
the slow QCK.
There are 4 modes of operation of QCK.
1. Disabled (Always low - default mode of operation)
2. Free running - qualifies the entire output data stream.
3. Qualify embedded control sequences, status data, (from the SOF line), and pixel data.
4. Qualify pixel data only, (this will include data from the black lines).
The operating mode for QCK is set via the serial interface. The QCK output can be tri-stated either when OEB is driven high or
via the appropriate control bit in the serial interface, (see data_format register[22]).
The QCK pin can also be configured to output the state of a serial interface register bit. This feature allows the sensor to control
external devices, e.g. stepper motors, shutter mechanisms.
Full details of how to configure the QCK output pin can be found in 2 registers, fg_mode[20] and pin_mapping[21].
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End of Active Video
(EAV)
Start of Active Video
(SAV)
Pixel Data
Figure 31 : Qualification of Output Data (Border Rows and Columns Enabled).
Video Data
FH
Line Format
4-wire Nibble Output Mode - D[3:0]
D1D0
FHFHFH
PMPLPMPLPMPLPMPL
Crystal Clock or external clock applied to CKI
Slow Qualification Clock, QCK
(i) Free running
(ii) Control sequences and Pixel Data
(iii) Pixel Data only
PM = Pixel Value - Most Significant Nibble, PL = Pixel Value - Least Significant Nibble, P = 8-bit Pixel Value
Fast Qualification Clock, QCK
(i) Free running
(ii) Control sequences and Pixel Data
(iii) Pixel Data only
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Figure 32 : Frame/Field Level Timings for FST and LST.
Start of Field
Black Lines
Blanking Lines
Visible Lines
End of Field
Blanking Lines
Blanking Lines
Start of Field
2nd Field
1 Frame
Start of Field
Black Lines
Blanking Lines
Visible Lines
End of Field
Blanking Lines
1st Field
Frame/Field Format:
LST:
(iii) Data Only
(ii) Control plus Data
(i) Free Running
(ii) Shutter mode
FST Pin:
(i) FST
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8.10.5 Line Start Signal, LST
There are 4 modes of operation for the LST pin programmable via the serial interface, (see fg_mode[20]):
1. Disabled (Always Low- Default).
2. Free running - LST signal occurs once at the beginning of every line.
3. All lines except blanking lines are qualified by LST.
4. Only Black and Visible Lines are qualified by LST.
The LST is tri-stated either when OEB is driven high or via the appropriate control bit in the serial interface, (see data_format
register[22]). Table 18below details the LST timing for the different video modes, (see Figure 33 for specification of t1 and t2).
8.10.6 Frame Start Signal, FST
There are 3 modes of operation for the FST pin programmable via the serial interface:
1. Disabled (Always Low- Default).
2. Frame start signal. The FST signal occurs once frame, is high for 356 pixel periods (712 system clock periods) and qualifies
the data in the start of frame line.
3. Shutter/Electronic Flash Synchronisation Signal - FST rises a the start of the video data in the first black/blank line after the
EOF line and falls at the end of data in the SOF line.
The FST output is tri-stated either when OEB is driven high or via the appropriate control bit in the serial interface, (see
data_format register[22]).
The configuration details for FST can be found in fg_mode register[20].
Video Mode t1 t2
pck’s us pck’s us
CIF 21 5.25 16 4.000
QCIF (both pan tilt and sub sampled,
16Mhz clock) 6 6.00 15 15.00
QCIF (both pan tilt and sub sampled,
8Mhz clock) 6 6.00 15 15.00
PAL 33 4.652 42 5.962
NTSC 27 4.714 12 2.095
Table 18 : LST Timing
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Figure 33 : Line Level Timings for FST and LST.
Video
Data Start of Active
Video (SAV) EAV
Inter-line Period (DataBus = FH)
End of Active Video
(EAV)
FST Pin:
Frame start pulse - qualifies status line information
End of Active Video
(EAV)
LST Pin:
6 Pixels 180/306/356 Pixels6 Pixels
1 Line
t1 t2
Video Data
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Figure 34 : Frame/Field Level Timings for FST and QCK.
Start of Field
Black Lines
Blanking Lines
Visible Lines
End of Field
Blanking Lines
Blanking Lines
Start of Field
2nd Field
1 Frame
Start of Field
Black Lines
Blanking Lines
Visible Lines
End of Field
Blanking Lines
1st Field
Frame/Field Format:
QCK:
(iii) Data Only
(ii) Control plus Data
(i) Free Running
(ii) Shutter mode
FST Pin:
(i) FST
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9. Serial Control Bus
9.1 General Description
Writing configuration information to the video sensor and reading both sensor status and configuration information back from the
sensor is performed via the 2-wire serial interface.
Communication using the serial bus centres around a number of registers internal to the video sensor. These registers store
sensor status, set-up, exposure and system information. Most of the registers are read/write allowing the receiving equipment to
change their contents. Others (such as the chip id) are read only.
The main features of the serial interface include:
• Variable length read/write messages.
• Indexed addressing of information source or destination within the sensor.
• Automatic update of the index after a read or write message.
• Message abort with negative acknowledge from the master.
• Byte oriented messages.
The contents of all internal registers accessible via the serial control bus are encapsulated in each start-of-field line - see Section
8.3.5.
9.2 Serial Communication Protocol
The co- processor or host must perform the role of a communications master and the camera acts as either a slave receiver or
transmitter.The communication from host to camera takes the form of 8-bit data with a maximum serial clock host frequency of up
to 100 kHz. Since the serial clock is generated by the bus master it determines the data transfer rate. Data transfer protocol on
the bus is illustrated in Figure 35.
9.3 Data Format
Information is packed in 8-bit packets (bytes) always followed by an acknowledge bit. The internal data is produced by sampling
sda
at a rising edge of
scl
. The external data must be stable during the high period of
scl
. The exceptions to this are
start
(S) or
stop
(P) conditions when
sda
falls or rises respectively, while
scl
is high.
A message contains at least two bytes preceded by a
start
condition and followed by either a
stop
or
repeated start, (Sr)
followed
by another message.
The first byte contains the device address byte which includes the data direction
read,
(r)
, ~write
, (~w), bit. The lsb of the address
byte indicates the direction of the message. If the lsb is set high then the master will read data from the slave and if the lsb is reset
low then the master will write data to the slave. After the
r, ~w
bit is sampled, the data direction cannot be changed, until the next
address byte with a new
r, ~w
bit is received.
12 78A
Start condition
Stop condition
SDA
SCL
Acknowledge
P
S3 4 56
Address or data byte
MSB LSB
Figure 35 : Serial Interface Data Transfer Protocol
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The byte following the address byte contains the address of the first data byte (also referred to as the
index
). The serial interface
can address up to 128, byte registers. If the msb of the second byte is set the automatic increment feature of the address index is
selected.
9.4 Message Interpretation
All serial interface communications with the sensor must begin with a
start
condition. If the
start
condition is followed by a valid
address byte then further communications can take place. The sensor will acknowledge the receipt of a valid address by driving
the
sda
wire low. The state of the
read/~write
bit (lsb of the address byte) is stored and the next byte of data, sampled from
sda,
can be interpreted.
During a write sequence the second byte received is an address index and is used to point to one of the internal registers. The
msbit of the following byte is the
index auto increment
flag. If this flag is set then the serial interface will automatically increment
the index address by one location after each slave acknowledge. The master can therefore send data bytes continuously to the
slave until the slave fails to provide an acknowledge or the master terminates the write communication with a
stop
condition or
sends a
repeated start
,
(Sr)
. If the auto increment feature is used the master does
not
have to send indexes to accompany the
data bytes.
As data is received by the slave it is written bit by bit to a serial/parallel register. After each data byte has been received by the
slave, an acknowledge is generated, the data is then stored in the internal register addressed by the current index.
During a read message, the current index is read out in the byte following the device address byte. The next byte read from the
slave device are the contents of the register addressed by the current index. The contents of this register are then parallel loaded
into the serial/parallel register and clocked out of the device by
scl.
At the end of each byte, in both read and write message sequences, an acknowledge is issued by the receiving device. Although
VV5410/VV6410 is always considered to be a slave device, it acts as a transmitter when the bus master requests a read from the
sensor.
At the end of a sequence of incremental reads or writes, the terminal index value in the register will be one
greater
the last
location read from or written to. A subsequent read will use this index to begin retrieving data from the internal registers.
A message can only be terminated by the bus master, either by issuing a stop condition, a repeated start condition or by a
negative acknowledge after reading a complete byte during a read operation.
9.5 The Programmers Model
There may be up to 128, 8-bit registers within the camera, accessible by the user via the serial interface. They are grouped
0010000
Figure 36 : VV5410/VV6410’s Serial Interface Address
R/W
Saddress[7:1]
R/Wbit
ADATA[7:0]
A
Sensor acknowledges valid address Acknowledge from slave
INDEX[6:0]INC
P
A
A
DATA[7:0]
[0]
address
Auto increment
Index bit
Figure 37 : Serial Interface Data Format
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according to function with each group occupying a 16-byte page of the location address space. There may be up to eight such
groups, although this scheme is purely a conceptual feature and not related to the actual hardware implementation, The primary
categories are given below:
• Status Registers (Read Only).
• Setup registers with bit significant functions.
• Exposure parameters that influence output image brightness.
• System functions and analog test bit significant registers.
Any internal register that can be written to can also be read from. There are a number of read only registers that contain device
status information, (e.g. design revision details).
Names that end with H or L denote the most or least significant part of the internal register. Note that unused locations in the H
byte are packed with zeroes.
STMicroelectronics sensors that include a 2-wire serial interface are designed with a common address space. If a register
parameter is unused in a design, but has been allocated an address in the generic design model, the location is referred to as
reserved
. If the user attempts to read from any of these
reserved or unused
locations a default byte will be read back. In
VV5410/VV6410 this data is 19H. A write instruction to a reserved (but unused) location is illegal and would not be successful as
the device would not allocate an internal register to the data word contained in the instruction.
A detailed description of each register follows. The address indexes are shown as decimal numbers in brackets [....] and are
expressed in decimal and
hexadecimal
respectively.
Index10 Index16 Name Length R/W Default Comments
Status Registers - [0-15]
0 0 deviceH 8 RO 0001_10012Chip identification number including
revision indicator
1 1 deviceL 8 RO 1010_00002
2 2 status0 8 RO 0001_00002User can determine whether timed
serial interface data has been
consumed by interrogating flag states
3 3 line_countH 8 RO n/a Current line counter value
4 4 line_countL 8 RO n/a
5 5 xendH 1 RO 359 End x coordinate of image size
6 6 xendL 8 RO
7 7 yendH 1 RO 293 End y coordinate of image size
8 8 yendL 8 RO
9 9 dark_avgH 4 RO 0 This is the average pixel value
returned from the dark line offset
cancellation algorithm
(2’s complement notation)
10 A dark_avgL 8 RO 0
11 B black_avgH 4 RO 0 This is the average pixel value
returned from the black line offset
cancellation algorithm
(2’s complement notation)
12 C black_avgL 8 RO 0
13 D status1 2 RO 00 Flags to indicate whether the x or y
image coordinates have been clipped
14-15 E-F unused Setup Registers - [16-31]
Table 19 : Serial Interface Address Map.
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16 10 setup0 8 R/W 0000_10012Low-power/sleep modes & video
timing
17 11 setup1 8 R/W 1100_00002Various parameters
18 12 sync_value 8 R/W 0001_11112Contains pixel counter reset value
used by external sync
19 13 reserved
20 14 fg_modes 8 R/W 0000_00002Frame grabbing modes
(FST, LST and QCK)
21 15 pin_mapping 7 R/W 000_10002FST and QCK mapping modes.
22 16 data_format 8 R/W 0000_00012Data resolution
23 17 op_format 7 R/W 001_10002Output coding formats
24 18 mode_select 2 R/W 012Various mode select bits
25 - 31 19-1F unused Exposure Registers - [32-47]
32 20 fineH 2 R/W 0 Fine exposure.
33 21 fineL 8 R/W
34 22 coarseH 2 R/W 302 Coarse exposure
35 23 coarseL 8 R/W
36 24 analog gain 8 R/W 1111_0000 Analog gain setting
37 25 clk_div 4 R/W 0 Clock division
38-43 26-2B reserved
44 2C dark offsetH 3 R/W 0 dark line offset cancellation value
(2’s complement notation)
45 2D dark offsetL 8 R/W
46 2E dark offset
setup 7 R/W 0110 00012dark line offset cancellation enable
47 2F reserved Colour Registers - [48-79]
48 - 79 30-4F reserved 8 R/W
Video Timing Registers - [80-103]
80-81 50-51 reserved
82 52 line_lengthH 2 R/W 415 Line Length (Pixel Clocks)
83 53 line_lengthL 8 R/W
84 - 86 54-56 reserved
87 57 x-offsetH 1 R/W 5 x-co-ordinate of top left corner of
region of interest (x-offset)
88 58 x-offsetL 8 R/W
89 59 y-offsetH 1 R/W 3 y-co-ordinate of top left corner of
region of interest (y-offset)
90 5A y-offsetL 8 R/W
91 - 96 5B-60 reserved
97 61 field_lengthH 2 R/W 319 Field length (Lines)
98 62 field_lengthL 8 R/W
99-102 63-66 reserved
103 67 unused R/W
Text Overlay Registers - [104-107]
104 - 105 68-69 reserved
106 - 107 6A-6B unused
Index10 Index16 Name Length R/W Default Comments
Table 19 : Serial Interface Address Map.
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9.5.1 Status Registers - [0 - 15],
[0-F]
[0-1],
[0-1]
- DeviceH and DeviceL
These registers provide read only information that identifies the sensor type that has been coded as a 12bit number and a 4bit
mask set revision identifier. The device identification number for VV5410/VV6410 is 410 i.e. 0001 1001 10102. The initial mask
revision identifier is 0 i.e. 00002.
[2]
,[2]
- Status0
Serial Interface Autoload Registers - [108-111]
108 - 109 6C-6D reserved
110 - 111 6E-6F unused System Registers - [112-127]
112 70 black offsetH 3 R/W - 64 black offset cancellation default value
(2’s complement notation)
113 71 black offsetL 8 R/W
114 72 black offset
setup 6 R/W 0011 00012black offset cancellation setup
115 73 unused
116 74 reserved
117 75 cr0 8 R/W 0000 00002Analog Control Register 0
118 76 cr1 8 R/W 0000 00002Analog Control Register 1
119 77 as0 8 R/W 0101 10102ADC Setup Register
120 78 at0 8 R/W 0000 00002Analog Test Register
121 79 at1 8 R/W 0000 00012Audio Amplifier Setup Register
122 - 125 7A-7D unused
126 7E reserved
127 7F reserved
Bits Function Default Comment
7:0 Device type identifier 0001 10012Most significant 8 bits of the 12 bit code identifying the
chip type.
Table 20 : [0],
[0]
- DeviceH
Bits Function Default Comment
7:4 Device type identifier 10102Least significant 4 bits of the 12 bit code identifying the
chip type.
3:0 Mask set revision identifier 00002
Table 21 : [1]
,[1]
- DeviceL
Bit Function Default Comment
0 Fine exposure value update
pending 0 Fine exposure value sent but not yet consumed by the
sensor
Table 22 : [2],
[2]
- Status0
Index10 Index16 Name Length R/W Default Comments
Table 19 : Serial Interface Address Map.
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[3-4],
[3-4]
- Line_countH & Line_countL
[5-6],
[5-6]
- XendH & XendL
[7-8],
[7-8]
- YendH & YendL
1 Coarse exposure value update
pending 0 Coarse exposure value sent but not yet consumed by
the sensor
2 Gain value update pending 0 Gain value sent but not yet consumed by the sensor
3 Clock division update pending 0 Clock divisor sent but not yet consumed by the sensor
4 Odd/even frame 1 The flag will toggle state on alternate frames
5 Pan image parameters pending 0 Pan image parameters sent but not yet consumed by
the sensor
6 Tilt image parameters pending 0 Tilt image parameters sent but not yet consumed by
the sensor
7 Video timing parameter update
pending flag 0 Video timing parameters sent but not yet consumed
by sensor
Register
Index Bits Function Default Comment
3 0 Current line count MSB - Displays current line count
4 7:0 Current line count LSB -
Table 23 : [3-4],
[3-4] -
Current Line Counter Value.
Register
Index Bits Function Default Comment
5 0 Xend msb’s 359 These registers contain the end x
coordinate of the read out image size,
(the x offset register contains the start x
coordinate)
6 7:0 Xend ls byte
Table 24 : [5-6],
[5-6] -
Xend
Register
Index Bits Function Default Comment
5 0 Yend ms bits 293 These registers contain the end y
coordinate of the read out image size,
(the y offset register contains the start y
coordinate)
6 7:0 Yend ls byte
Table 25 : [7-8],
[7-8] -
Yend
Bit Function Default Comment
Table 22 : [2],
[2]
- Status0
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[9-12],
[9-C]
- Black_Avg & Dark_Avg
[13],
[D]
- Status1 Register
[14-15],
[E-F]
- unused
9.5.2 Setup Registers - [16 - 31]
,[10-1F]
[16]
,[10]
- Setup0
[
Register
Index Bits Function Default Comment
9 3:0 Dark avg ms bits 0 The calculated pixel average over a
series of dark lines (1,2 or 4 lines). The
pixel sample size from each dark line
will be image size dependent up to a
maximum of 256
The average value is a signed 12 bit
number
10 7:0 Dark avg ls byte 0
11 3:0 Black avg ms bits 0 The calculated pixel average over a
series of black lines (4 or 8 lines). The
pixel sample size from each black line
will be image size dependent up to a
maximum of 256
The average value is a signed 12 bit
number
12 7:0 Black avg ls byte 0
Table 26 : [9-12],
[9-C] -
Black & Dark Averages
Bit Function Default Comment
0 X image parameters clipped 0 If this bit is set then the current x offset parameter
requested has caused the x coordinates to be
clipped
1 Y image parameters clipped 0 If this bit is set then the current y offset parameter
requested has caused the y coordinates to be
clipped
7:2 unused 000000
Table 27 : [13],
[D] -
Status1
Bit Function Default Comment
0 Low Power Mode:
Off / On
1 Powers down the sensor array. The output data bus
goes to FH. On power-up the sensor enters low power
mode.
1 Sleep Mode:
Off / On
0 Puts the sensor array into reset. The output data bus
goes to FH.
Table 28 : [16],
[10]
- Setup0
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[17],
[11]
- Setup1
2 Soft Reset
Off / On
0 Setting this bit resets the sensor to its power-up
defaults. This bit is also reset.
3 Frame/Field Rate select:
25 fps (PAL) / 30 fps (NTSC)
1
5:4 reserved 00
7:6 Video Timing Mode Select 00 00 - CIF Timing Modes
01 - PAL/NTSC 3.2 fsc Timing Modes
10 - pan/tilt/QCIF Timing Modes
If this mode is selected a QCIF size image will be
output. The coordinates which define the top left
corner of the QCIF portion of the array to be output
are defined by the parameters in registers 88 - 91
inclusive. By default the x- and y-sizes of the output
image are180 & 148 respectively.
11 - sub-sampled QCIF Timing Modes
If this mode is selected a QCIF size image will be
output. The CIF image is sub-sampled in groups of 4
to preserve the Bayer pattern with every second group
of pixels & lines skipped.
Video
Mode setup0
[7:6] setup0
[3] System
Clock
Divisor
Video
Data Line
Length Field
Length Data
Format
(default)
Comment
1000 4 356 x 292 500 320 5-wire CIF 25fps
21
4 356 x 292 416 320 5-wire CIF 30fps
3010 2 356 x 292 454 312/313 5-wire PAL (3.2 fsc)
41
2 306 x 244 364 262/263 5-wire NTSC (3.2 fsc)
5100 8 180 x 148 250 160 5-wire pan/tilt QCIF 25fps
61
8 180 x 148 208 160 5-wire pan/tilt QCIF 30fps
7110 8 180 x 148 250 160 5-wire sub-sampled QCIF 25fps
81
8 180 x 148 208 160 5-wire sub-sampled QCIF 30fps
Table 29 : Video Timing Modes
Bit Function Default Comment
2:0 reserved 000
3 Enable immediate clock division
update. Off/On 0 Allow manual change to clock division to be
applied immediately
4 Enable immediate gain update.
Off/On
0 Allow manual change to gain to be applied
immediately
Table 30 : [17],
[11]
- Setup1
Bit Function Default Comment
Table 28 : [16],
[10]
- Setup0
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[18],
[12]
- sync_reset
[19],
[13]
- reserved
[20],
[14]
- fg_modes
Bits [3:2] of the fg_mode register are mode dependent. If the NTSC or PAL video modes are selected then the free running QCK
mode will be selected. The slow QCK is selected by default, regardless of the video mode.
note1: The FST pin will always output the free running version of QCK (either inverted or normal)
5 Enable additional black lines (lines 3-8)
Off/On
0 If enabled this bit will also enable the lines
immediately following the end of frame line. This
bit can only set/reset if the VP3 mode (ON) has
been selected. In VP3 mode (OFF) operation all
possible black lines are always output.
6 reserved 1
7 Pixel read-out order (hshuffle)
Unshuffled or Shuffled
1 It is strongly recommended to use shuffled
horizontal read-out with VV6410 sensor.
Bit Function Default Comment
7:0 Pixel counter reset value 31 During synchronisation the pixel counter can be
reset to the known value or offset by up to 255
pck’s into the pixel count sequence.
Table 31 : [18],
[12]
- sync_reset
Bit Function Default Comment
1:0 FST/QCK pin modes 00 Selection of FST, QCK pin data
3:2 QCK modes 00 00 - if CIF & QCIF mode selected
01 - if NTSC and PAL mode selected
5:4 LST modes 00 See Table 35 below for details
7:6 FST modes 00 See Table 36 below for details
Table 32 : [20],
[14]
- fg_modes
fg_mode[1:0] FST pin QCK pin
0 0 FST Slow QCK
0 1 FST Fast QCK
1 0 Fast QCKnote1 Slow QCK
1 1 Invert of Fast QCKnote1 Fast QCK
Table 33 : FST/QCK Pin Selection
Bit Function Default Comment
Table 30 : [17],
[11]
- Setup1
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.
The option to enable the qclk during the data and control period of the line
must not be selected if monochrome (shuffled or
unshuffled) video has been selected.
[21],
[15]
- pin_mapping
fg_mode[3:2] QCK state
0 0 Off
0 1 Free Running
1 0 Valid during data and control period of line
1 1 Valid only during data period of line
Table 34 : QCK Modes
fg_mode[5:4] LST pin
0 0 Off
0 1 Free Running
1 0 Output for black, video data and status lines
1 1 Output only for black and video data lines.
Table 35 : LST Modes
fg_mode[7:6] FST pin
0 0 Off
0 1 Normal behaviour, FST will qualify the visible pixels in
the status line
1 x Special digital stills mode. FST will be asserted at the
beginning of valid data on the line following the EOF
line. FST will be cleared at the end of the visible pix-
els in the following status line.
Table 36 : FST Modes
Bit Function Default Comment
0 Map serial interface register bits values
on to the QCK and FST pins
Off/On
0
1 Serial Interface Bit for QCK pin 0
2 Serial Interface Bit for FST pin 0
4:3 Output driver strength select 00 Default setting selects 2mA driver
Table 37 : [21],
[15]
- pin_mapping
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[22],
[16]
- data_format
5 Enable RESETB pin as SIN
Off / On
0 On power up the RESETB pin is configured as an
active low system reset which will synchronise the
video timing logic and reset all serial registers to
their default state. Setting this bit configures the
RESETB pin as an active high system
synchronisation signal (SIN) which will
synchronise the video timing but will NOT reset the
serial registers.
7:6 unused 0
Mapping Enable FST pin QCK pin
0 FST QCK
1 pin_mapping[2] pin_mapping[1]
Table 38 : FST/QCK Pin Selection
oeb_composite pin_map[4] pin_map[3] Comments
0 0 0 Drive strength = 2mA (Default)
0 0 1 Drive strength = 4mA
0 1 0 Drive strength = 6mA
0 1 1 unallocated
1 x x Outputs are not being driven therefore
driver strength is irrelevant
Table 39 : Output driver strength selection
Bit Function Default Comment
1:0 Unused 1
2 Line read-out order (vertical)
Unshuffled or Shuffled
0 If the line read out is shuffled then all the even address
rows will be read out first followed by all the odd
address rows
3 Pixel read-out order (hmirror)
Normal or Mirrored
0 If the pixel read out is horizontally mirrored then the
columns are read out in reverse order, that is the
column on the right of the sensor array will appear on
the left of the displayed image and vice versa
4 Line read-out order (vertical flip)
Normal or Mirrored
0 If the line read out is vertically mirrored then the rows
are read out in reverse order, that is the row at the
bottom of the array will appear at the top of the
displayed image and vice versa.
Table 40 : [22],
[16]
- data_format
Bit Function Default Comment
Table 37 : [21],
[15]
- pin_mapping
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5 FST/LST Enable/Tri-state 0 The FST/LST digital outputs can be tri-stated but are
enabled as outputs by default. The enabling/disabling
of FST/LST can be retimed to a field boundary. The
state of this control bit is always available via a serial
interface read, i.e. it does not have to wait to change
state at a field boundary
6 QCK Enable/Tri-state 0 The QCK output can be tri-stated independently. The
enabling/disabling of QCK can be retimed to a field
boundary. The state of this control bit is always availa-
ble via a serial interface read, i.e. it does not have to
wait to change state at a field boundary.
7 Pre clock generator divide
On/Off 0 The CIF and QCIF video modes expect a recom-
mended set of input clock frequencies, however the
acceptable range of clock frequencies can be extended
if this bit is set. If this bit is set then the primary input
clock will be divided down by 1.5 prior to the clock gen-
erator, thus if the expected clock input is 16 MHz, we
can set this bit and accept 24 MHz and achieve the
same final frame rate.
OEB pin data_format[5] oeb_composite Comments
0 0 0 FST/LST outputs enabled.
0 1 1 FST/LST outputs are tri-stated by
data_format[5]
1 0 1 FST/LST outputs are tri-stated by OEB pin.
1 1 1 FST/LST outputs are tri-stated.
Table 41 : FST/LST output control
OEB pin data_format[6] oeb_composite Comments
0 0 0 QCK output enabled.
0 1 1 QCK output is tri-stated by op_format[6]
1 0 1 QCK output is tri-stated by OEB pin.
1 1 1 QCK output is tri-stated.
Table 42 : QCK output control
Bit Function Default Comment
Table 40 : [22],
[16]
- data_format
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[23],
[17]
- op_format
Note: oeb_composite is the logical OR of op_format[5] and the OEB pin.
[24],
[18]
- mode_select
This register allows the user to configure the sensor to operate with the present generation of coprocessors as well as anticipated
future devices.
Bit Function Default Comment
1:0 Data format select. 0 00 - 5 wire parallel output
01 - 4 wire parallel output
1x - 8 wire parallel output
Note: If the 8 wire output option has been selected then
the FST and LST pins will output data bits 5 and 6
respectively, normal FST and LST function is not
available
2 Embedded SAV/EAV Escape
Sequences1
On / Off
1. Please note that if the embedded coding sequences are disabled then the FST signal is also disabled. The QCK
output will continue to function IF the free running option has been selected. The LST functionality is unaffected
by the state of this bit.
00 - Insert Embedded Control Sequences e.g Start
and End of Active Video into Output Video data
1 - Pass-through mode. Output Video data equals ADC
data.
4:3 reserved 11
5 Tri-state output data bus
Enabled / Tri-state
0 On power up the data bus pads are enabled by default.
This bit is OR’ed with the OEB pin to generate the
enable signal for the data pins as detailed in Table 44
6 Re-time tri-state update.
Off / On
0 Re-time new tri-state value to a field boundary. This bit
affects the updating of the op_format[5] as well as
data_format[6:5]
7 unused 0
Table 43 : [23],
[17]
- op_format
OEB pin op_format[5] oeb_composite Comments
0 0 0 Data outputs enabled.
0 1 1 Data outputs are tri-stated by op_format[5]
1 0 1 Data outputs are tri-stated by OEB pin.
1 1 1 Data outputs are tri-stated.
Table 44 : Data bus output control
Bit Function Default Comment
0 Coprocessor device is VP3
No/Yes 1 By default the sensor expects the coprocessor to be a
VP3 device. If the sensor is not being used with a VP3
device then this bit should be reset. This bit controls
the arrangement of black/dark/visible lines within the
field. It does not alter timing. Please see
Table 45 : [24],
[18]
- Mode Select
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[25-31],
[19-1F]
- unused
9.5.3 Exposure Control Registers [32 - 47],
[20-2F]
There is a set of programmable registers which controls the sensitivity of the sensor. The registers are as follows:
1. Fine exposure.
2. Coarse exposure.
3. Analog gain.
4. Clock division
Note
:
As we know from an explanation earlier in this document (see Section 6. for further details) the exposure control
registers are not updated immediately, rather they are timed to be updated at a precise point in the field timing.
The range of some parameter values is limited and any value programmed out-with this range will be clipped to the maximum
currently permitted, (the fine and coarse maximum allowable settings are set by the current line and field length respectively).
1 Retro mode for gain application
Off/On 0 The gain passed to the CAB comprises 2 components,
IDAC[3:0] and CDAC[5:0]. If the user selects the retro
mode then the IDAC value will be the inverse of the ls
gain nibble. The user is barred from writing to the ms
gain nibble. In the non retro mode all 8 bits are availa-
ble to program. The 2 ls bits of CDAC[5:0] are fixed at
2’b11.
2 Select log CDAC ramp
Off/On 0 By default the same CDAC value is applied for the
duration of every line of every field. Setting this bit
causes the CDAC value to be varied during the line.
7:3
Index10 Index16 Bits Function Default Comment
32 20 0 Fine MSB exposure value 0 The maximum fine exposure is line
length dependent. The expressions
used to calculate the maximum fine
exposure for each of the default
video modes, that can be selected
via Setup0 register, are as follows
NTSC = line length - 51
PAL = line length - 86
CIF = line length - 51
QCIF = line length - 23
33 21 7:0 Fine LSB exposure value
Bit Function Default Comment
Table 45 : [24],
[18]
- Mode Select
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Table 46 : Exposure Related Registers
34 22 0 Coarse MSB exposure value 302 The maximum allowable coarse
exposure setting is filed length
dependent. We provide the
maximum coarse exposure settings
for each of the standard video
modes.
NTSC = 260
PAL = 310
CIF (25 & 30 fps) = 318
QCIF (25 & 30 fps) = 158
35 23 7:0 Coarse LSB exposure value
36 24 7:0 Analog gain value 1111_0000 Bits [7:4] CDAC gain control
CDAC default = 63 (10-bit modes)
CDAC default = 31 (9-bit modes)
Bits[3:0] IDAC maximum
recommended IDAC value = 12.
37 25 3:0 Clock divisor value 0 The user can opt to slow the internal
clocks down form their default
settings. Table 47 describes the
range of clock divisors that may be
selected.
Clock Divisor Setting Pixel Clock Divisor
0000 1
0001 2
0010 3
0011 4
0100 5
0101 6
0110 7
0111 8
1000 9
1001 10
1010 11
1011 12
1100 13
1101 14
1110 15
Table 47 : Clock Divisor Values
Index10 Index16 Bits Function Default Comment
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1111 16
Clock Divisor Setting Pixel Clock Divisor
Table 47 : Clock Divisor Values
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[38-43],
[26-3B]
- reserved
[44 - 45],
[3C-3D]
- Dark Pixel Offset
[46],
[3E]
- Dark Pixel Cancellation Setup Register
[47],
[3F] -
reserved
[48-79],
[30-4F] -
reserved
9.5.4 Video Timing Registers [80 - 103],
[50-67]
Indexes in the range [80 - 103] control the generically named video timing registers, including the image pan/tilt parameters and
line & field length of the sensor. The registers are as follows:
1. line length.
2. x-offset of region of interest.
Bit Function Default Comment
2:0 MS Dark line pixel offset 0 This register contains a fixed offset that can
be applied to the digitised pixels in the dig-
ital output coding block. The offset is a 2’s
complement number, giving an offset range
-1024,+1023.
If this external offset cancellation is to be
applied then it register[46], bits[1:0] should
be reprogrammed to 2’b1x.
7:0 LS Dark line pixel offset
Table 48 : [44 - 45],
[3C-3D]
- Dark Pixel Offset
Bit Function Default Comment
1:0 Dark line offset cancellation 01 x0 - Accumulate dark pixels, calculate dark
pixel average and report, but don’t apply
anything to data stream
01 - Accumulate dark pixels, calculate dark
pixel average and report and apply
internally calculated offset to data stream
11 - Accumulate dark pixels, calculate dark
pixel average and report, but apply an
externally calculated offset
2 Number of dark lines used
All dark lines/Use half the number of
dark lines.
0 The dark line offset cancellation algorithm
can opt to only use pixels from dark lines
that are preceeded by another dark line, i.e
line choose only line 306 from line 305 and
line 306.
5:3 reserved
6 Use narrow dark offset deadband
Yes/No
1 The deadband describes a range of dark
pixel averages that will force the leaky
integrator algorithm to hold it’s current
value.
0 - Target +/- 4 codes
1 - Target +/- 2 codes
7 unused 0
Table 49 : [46],
[3E]
- Dark Pixel Cancellation Setup Register
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3. y-offset of region of interest.
4. frame length.
The length of a line is specified in a number of pixel clocks, whereas the length of a field is specified in a number of lines.
The range of some parameter values is limited and any value programmed out-with this range will be clipped to the maximum
allowed. The x-offset and y-offset are only programmable if the user has selected the pan tilt QCIF mode. If the other video
modes are selected then the x-offset and y-offset registers will have pre-programmed values applied, but they cannot be
changed. The x-offset and y-offset default values are chosen such that the output image, regardless of video mode selected, will
be centered within the pixel array, (see Section 3.2 for details).
[103],
[67]
- unused
[104-105],
[68-69]
- reserved
[106-107],
[6A-6B] -
unused
[108-109],
[6C-6D]
- reserved
[110-111],
[6E-6F]
- unused
9.5.5 System Registers -Addresses [112 - 127],
[70-7F]
This page of the serial interface I2C address space comprises a wide range of registers including the registers required to control
the black offset cancellation algorithm, enable test modes and also control various aspects of the analogue behavior of the
sensor.
Index10 Index16 Bit Function Default Comment
80-81 50-51 reserved
82 52 1:0 Line Length MSB value 415 Minimum mode dependent
Maximum = 1023
Actual line duration in pixel periods is
line length programmed +1.
83 53 7:0 Line Length LSB value
84 - 86 54-56 reserved
87 57 0 x-offset MSB value 5 Minimum (positive) value = 1
88 58 7:0 x-offset LSB value
89 59 0 y-offset MSB value 3 Minimum (positive) value = 1
90 5A 7:0 y-offset LSB value
91 - 96 5B-60 reserved
97 61 1:0 Field Length MSB value 319 Minimum mode dependent
Maximum = 1023
Actual field duration in line periods is
field length programmed +1.
98 62 7:0 Field Length LSB value
99-102 63-66 reserved
Table 50 : Video Timing Registers
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[112 - 113],
[70-71]
- Black Pixel Offset
[114],
[72]
- Black Pixel Cancellation Setup Register
[115],
[73]
- unused
[116],
[74]
- reserved
[117 - 118],
[75-76]
- Control Registers 0 and 1- CR0 and CR1
Although we give the user access to the following 5registers it is not anticipated that the contents of these registers will have to be
altered. If the user does wish to alter any of the register bits then they are strongly advised to contact VIBU before doing so.
Bit Function Default Comment
2:0 MS Black line pixel offset - 64 This register contains a fixed offset that can be applied to
the digitised pixels in the digital output coding block.The
offset is a 2’s complement number, giving an offset range
-1024,+1023.
If this external offset cancellation is to be applied then it
register[114], bits[1:0] should be reprogrammed to 2’b1x.
7:0 LS Black line pixel offset
Table 51 : [112 - 113],
[70-71]
- Black Pixel Offset
Bit Function Default Comment
1:0 Black line offset cancellation 01 x0 - Accumulate black pixels, calculate
black pixel average and report, but don’t
apply anything to data stream
01 - Accumulate black pixels, calculate
black pixel average and report and apply
internally calculated offset to data stream
11 - Accumulate black pixels, calculate
black pixel average and report, but apply an
externally calculated offset
4:2 reserved 100 The time constant controls the rate at which
a change in the black level is corrected for.
5 Use narrow black offset deadband
Yes/No
1 The deadband describes a range of pixel
averages that will cause the leaky integrator
algorithm to hold it’s current value.
0 - Target +/- 4 codes
1 - Target +/- 2 codes
7:6 unused 00
Table 52 : [114],
[72] -
Black offset cancellation setup
Bit Function Default Comment
0 Enable bit line clamp
Off/On
0
1 Enable bit line test
Off/On
0
Table 53 : [117],
[75]
- Control Register CR0
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[119]
[77]
- ADC Setup Register AS0
3:2 Bit line white reference
0.7 V / 1.1 V / 1.5V / Ext.
00 00 - 0.7V
01 - 1.1V
10 - 1.5V
11 - External
4 Enable anti blooming
Off/On
0
5 Power Down - LVDS input comparator
Off/On
0 Powers down LVDS input. CMOS clock
input may still be used.
6 Power Down - SRAM
Off/On
0 Powers down SRAM comparator
7 Power Down - VCCS
Off/On
0 Powers down voltage controlled current
source
Bit Function Default Comment
0 Stand-by
Off/On
0 Powers down ALL analog circuitry with the
exception of the band gap
1 Power Down - Internal Ramp Generator
Off/On
0
2 Power Down - Column ADC
Off/On
0 Powers down preamp and comparators
3 Power Down - CAB regulator
Off/On
0 Referred to in figures as pd_creg
4 Power Down - Audio Amplifier regulator
Off/On
0 Referred to in figures as pd_areg
5 Power Down - VRT Amplifier
Off/On
0 Allows external VRT to be applied
6 Ramp common mode voltage
VRT-vtn/1.5V
0 0 - VRT-vtn ramp common mode voltage
1- 1.5V ramp common mode voltage
7 Current boost to column comparator
75uA/50uA
0 0 - 75uA
1- 50uA
Table 54 : [118],
[76]
- Control Register CR1
Bit Function Default Comment
1:0 reserved 10
Table 55 : [119],
[77]
- ADC Setup Register AS0
Bit Function Default Comment
Table 53 : [117],
[75]
- Control Register CR0
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2 Enable voltage doubler
Off/On
0 It is recommended that this bit is set if the sensor
is being used in a 3.3V supply environment
3 Differential ramp enable
Off//On
1 Ramp generator signal bpramp
4 view column/view vcmtcas
vcmtcas/column
1 0 - view column voltage Vx[363]
1- view vcmtcas
5 ramp viewing/column comparator test
ramps/test comparator
0 0 -view ramps on CPOS/CNEG
1- input to test comparator 364
6 Stepped Ramp Enable
Off/On
1 Setting this bit enables a stepped ramp.
Clearing this bit enables a continuous ramp.
7
Bit Function Default Comment
Table 55 : [119],
[77]
- ADC Setup Register AS0
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[120],
[78] -
Analog Test Register AT0
[121],
[79]
- Audio Amplifier Setup Register AT1
[122-125]
,[7A-7D]
- unused
[126-127]
,[7E-7F]
- reserved
Bit Function Default Comment
0 SRAM test enable
Off/On
0
2:1 VRT Voltage
2.2V / 2.5V / 2.8V / Ext.
00 00 - VRT = 2.2V
01 - VRT = 2.5V
10 - VRT = 2.8V
11 - reserved
4:3 LineInt & ReadInt phasing 00 00- 0 degree phase delay
01 - 90 degree phase delay
10 - 180 degree phase delay
11 - 270 degree phase delay
7:5 unused 000
Table 56 : [120],
[78]
- Analog Test Register AT0
Bit Function Default Comments
0 First stage gain 1 0 - 0dB
1 - 30dB
1 Second stage gain[1] 0 gain[1] gain[0] - gain(dB)
0 0 - 0dB
0 1 - 6dB
1 0 - 12dB
1 1 - 18dB
2 Second stage gain[0] 0
3 Power Down 1 0 - Powered up
1 - Power down
4 Output Select 0 0 - Single ended
1 - Differential
5 Current Boost 0 0 - 1mA output drive in output buffers
1 - 2mA output drive in output buffers
7:6 Unused 00
Table 57 : [121],
[79]
- Audio Amplifier Setup Register AT1
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9.6 Types of messages
This section gives guidelines on the basic operations to read data from and write data to the serial interface.
The serial interface supports variable length messages. A message may contain no data bytes, one data byte or many data
bytes. This data can be written to or read from common or different locations within the sensor. The range of instructions
available are detailed below.
• Write no data byte, only sets the index for a subsequent read message.
• Single location data write or read for monitoring (real time control)
• Multiple location read or write for fast information transfers.
Examples of these operations are given below. A full description of the internal registers is given in the previous section. For all
examples the slave address used is 3210 for writing and 3310 for reading. The write address includes the read/write bit (the lsb)
set to zero while this bit is set in the read address.
9.6.1 Single location, single data write.
When a random value is written to the sensor, the message will look like this:
In this example, the
fineH
exposure register (index = 3210) is set to 8510. The r/w bit is set to zero for writing and the
inc
bit (msbit
of the index byte) is set to zero to disable automatic increment of the index after writing the value. The address index is preserved
and may be used by a subsequent read. The write message is terminated with a stop condition from the master.
9.6.2 Single location, single data read.
A read message always contains the index used to get the first byte.
This example assumes that a write message has already taken place and the residual index value is 3210. A value of 8510 is read
from the
fineH
exposure register. Note that the read message is terminated with a negative acknowledge (A) from the master: it is
not guaranteed that the master will be able to issue a stop condition at any other time during a read message. This is because if
the data sent by the slave is all zeros, the
sda
line cannot rise, which is part of the stop condition.
Figure 38 : Single location, single write.
S 32
10 A0 32
10 A85
10 A P
Start Device Ack
address Index Data Stop
Inc
Figure 39 : Single location, single read.
S 33
10 A0 32
10 A85
10 A P
Start Device Ack
address Index Data Stop
Master reads from slave, acknowledging
each byte
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9.6.3 No data write followed by same location read.
When a location is to be read, but the value of the stored index is not known, a write message with no data byte must be written
first, specifying the index. The read message then completes the message sequence. To avoid relinquishing the serial to bus to
another master a repeated start condition is asserted between the write and read messages, i.e. no stop condition is asserted. In
this example, the
gain
value (index = 3610) is read as 1510:
As mentioned in the previous example, the read message is terminated with a negative acknowledge (A) from the master.
9.6.4 Same location multiple data write.
It may be desirable to write a succession of data to a common location. This is useful when the status of a bit (e.g. auto-load)
must be toggled.
The message sequence indexes
sf_setup
register 108. If bit 0 is toggled high, low this will initiate a fresh auto-load. This is
achieved by writing two consecutive data bytes to the sensor. There is no requirement to re-send the register index before each
data byte.
9.6.5 Same location multiple data read
When an exposure related value (
fineH, fineL, coarseH, coarse L
,
gain or clk_div
) is written, it takes effect on the output at the
beginning of the next video frame, (remember that the application of the
gain
value is a frame later than the other exposure
parameters). To signal the consumption of the written value, a flag is set when any of the exposure or gain registers are written
and is reset at the start of the next frame. This flag appears in
status0
register and may be monitored by the bus master. To
speed up reading from this location, the sensor will repeatedly transmit the current value of the register, as long as the master
acknowledges each byte read.
In the below example, a
fineH
exposure value of 0 is written, the status register is addressed (no data byte) and then constantly
read until the master terminates the read message.
Figure 40 : No data write followed by same location read.
SASr A
AAP
3310 3610 3310 3610 1510 A
00
No data write Read index and data
SA A A
3210 2110 410 010 A
0
Write to
pin_mapping
Figure 41 : Same location multiple data write.
410 P
Toggle control bit
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9.6.6 Multiple location write
If the automatic increment bit is set (msb of the index byte), then it is possible to write data bytes to consecutive adjacent internal
registers, (i.e. 23,24,25,26 etc), without having to send explicit indexes prior to sending each data byte. An auto-increment write to
the exposure registers with their default values is shown in the following example, where we write 1710 to the pin_mapping
register[21] and 19310 to the data format register[22].
.
9.6.7 Multiple location read
In the same manner, multiple locations can be read with a single read message. In this example the index is written first, to
ensure the exposure related registers are addressed and then all six are read.
Note: a stop condition is not required after the final negative acknowledge from the master, the sensor will terminate the
communication upon receipt of the negative acknowledge from the master.
SA 0
10 AA A3210 3310 3210 010 A0
Sr A AA A3310 010 110 110 110 A0
Sr
Write
fineL
with zero Address the status0 register
A
110 010 A
Read continuously...
...until flag reset
P
Figure 42 : Same location multiple data read.
SA 17
10 AAA3210 2110 19310
1
Incremental write
P
Figure 43 : Multiple location write.
Incremental read
SAA3210 3210
1 Sr 3310 AA3210
1
fineH
A
AP
fineL coarseH coarseL gain clk_div
AAAA
No data write
Incremental read
Figure 44 : Multiple location read.
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9.7 Serial Interface Timing
Parameter Symbol Min. Max. Unit
SCL clock frequency fscl 0 100 kHz
Bus free time between a
stop
and a
start
tbuf 2 - us
Hold time for a repeated
start
thd;sta 80 - ns
LOW period of SCL tlow 320 - ns
HIGH period of SCL thigh 160 - ns
Set-up time for a repeated
start
tsu;sta 80 - ns
Data hold time thd;dat 0 - ns
Data Set-up time tsu;dat 0 - ns
Rise time of SCL, SDA tr - 300 ns
Fall time of SCL, SDA tf - 300 ns
Set-up time for a
stop
tsu;sto 80 - ns
Capacitive load of each bus line (SCL,
SDA) Cb - 200 pF
Table 58 : Serial Interface Timing Characteristics
SDA
SCL
thd;sta
tr
thigh
tf
tsu;datthd;dat tsu;sta tsu;sto
...
...
thd;statlowtbuf
stopstartstop start
Figure 45 : Serial Interface Timing Characteristics
VV5410 & VV6410 Clock Signal
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10. Clock Signal
VV5410/VV6410 system clock is supplied from an external clock source directly driving the CLKI pin. The clock pad has an
integral Schmitt buffer to filter noise from the clock source. Please note that there is no support for an external resonator circuit.
The clock signal must be a square wave with, ideally a 50% ( 10%) mark:space ratio, although a non-ideal mark:space ratio can
be tolerated, please contact STMicroelectronics for details. The maximum input clock frequency for the module is 24.0 MHz. If
the 24MHz crystal is preferred then the user must select the pre-clock divide by 1.5 option such that the bulk of the internal logic
is driven by a 16MHz clock, see serial interface, register 1610, data_format.
VV5410/VV6410
CLK
Figure 46 : CMOS Clock Source
CLKI
Clock
Source CLOCK
DIVISION
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11. Other Features
11.1 Audio Amplifier
VV5410/VV6410 contains an on-chip audio amplifier which can be configured via the serial interface. The amplifier may also be
powered down via the serial interface.
The following document outlines the implementation of audio circuitry on the VV5410/VV6410 sensor.
11.1.1 Audio Amplifier Configuration
The audio circuit is controlled through a single eight bit register on the VV5410/VV6410. This includes bits for power down, output
select, first and second stage gains and current boosting. Table 59 describes the functionality of the control register bits.
The first stage provides a gain of 0dB or 30dB using a low noise amplifier design.
The reference is provided from the on-chip bandgap voltage. This is buffered by a cut down version of the low-noise amplifier
used in the first gain stage.
The output of the first gain stage is fed to two output amplifiers. These can be configured with a 1mA or 2mA output drive current.
The inverting gain stage provides an additional gain between 0dB and 18dB.
The output of the inverting gain stage may be routed through the other output buffer to provide two single ended outputs.
Otherwise, the inverted and non-inverted outputs provide a fully differential output signal.
Some more circuit specifications may be found in Table 60.
Bit Function Default Comments
0 First stage gain 1 0 - 0dB
1 - 30dB
1 Second stage gain[1] 0 gain[1] gain[0] - gain(dB)
0 0 - 0dB
0 1 - 6dB
1 0 - 12dB
1 1 - 18dB
2 Second stage gain[0] 0
3 Power Down 0 0 - Powered up
1 - Power down
4 Output Select 0 0 - Single ended
1 - Differential
5 Current Boost 0 0 - 1mA output drive in output buffers
1 - 2mA output drive in output buffers
7:6 Unused
Table 59 : Control register summary for VV5410/VV6410 audio circuit.
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11.1.2 AUD3V3 (Audio Supply Regulator)
11.1.3 Audio Amplifier Parameters
Symbol Parameter Min Typical Max Units
AUD3V3 Regulated supply
(No external load)
3.13 3.3 3.46 V
AUD3V3_Ld Regulated supply Vdrop
(Current Load 20mA)
-50 mV
AUD3V3_sus Regulated supply
(Suspend mode)
Off V
ZAUD3V3_sus Output impedance in
Suspend mode TBC KΩ
PSRR Power Supply Rejection
versus Vin -48 dB
Table 60 : Audio Circuit Specification
Symbol Parameter Min Typical Max Units
VAin Audio Regulator Input Voltage Vbg V
RIN Input impedance 100 kΩ
Gain1 Ist stage (28dB) gain accuracy +/-0.5 dB
Gain2 2nd stage (0,6,12,18dB) gain accuracy1
1. 2nd stage gain is only available on AoutN with the audio amplifier in differential mode
+/-0.2 dB
Gmatch Differential output mode gain matching
(0dB)
(28dB)( 0.2
0.5
dB
Out_max Output Clipping Level21.6 2.2 Vpp
OUT_DC Output DC Voltage 1.1 1.22 1.3 V
D-OUT_DC Differential DC Offset (AoutN-AoutP) 20 100 mV
Rout Output Impedance 2 kΩ
THD THD (includes noise)
Vin = 20mVpp, f-1KHz, Gain =28dB 0.2 %
SNR Signal to Noise ratio
(1KHz)
(10KHz)365
75
dB
PSRR Power supply rejection ratio from Vin -55 dB
LFc Low frequency cutoff (Cin=100nF) 15 Hz
Xtalk Video crosstalk to audio outputs (gain = 28dB) -56 dB
Table 61 : Audio Amplifier Parameters
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11.1.4 Audio Amplifier Bandwidth1
The audio circuit can be bandwidth limited to a first order, through the use of minimum external circuitry. The two outputs, AoutP
and AoutN, require compensation capacitors that may also be used to define the bandwidth of the circuit.
In addition, the inclusion of a resistor (microphone biasing) and decoupling capacitor at the input allows a first order high pass
filter to be realised. This can easily be designed to remove frequencies below 50Hz/60Hz (mains electricity noise).
11.2 Voltage Regulators
VV5410/VV6410 contains three on-chip voltage regulators, two of which are capable of being powered-down via the serial
interface. The third regulator, controlling the band gap references is never powered down. The band gap circuitry is extremely low
power consuming only 30µA.
11.2.1 Regulator for Digital System
The output of the regulator, Reg3V3, powers the digital logic and can power an external co-processor. The regulator is powered
up by default. The regulator has its own discrete power supply and can source a load of 300µA -> 150mA and will regulate to
3.0V 10% from an input range of 4-6V. When VV5410/VV6410 is in the USB compatible suspend mode, the clocks to the digital
logic are removed to limit power consumption to approximately 80µA. If an external 3.3V supply is available, this regulator may
be overdriven by an external 3.3V supply to directly power the logic. This voltage regulator is never powered down.
11.2.2 Regulator for Audio Amplifier
The output of the regulator for the audio amplifier, Aud3V3, drives the load resistor for the microphone and the audio pre-
amplifier. As this regulator is capable of being powered-down via the serial interface, all control signals from the digital logic are
low during low power/standby. This regulator will be powered up by default.
11.2.3 Regulator for Video Supply/Analogue Core
The output of the regulator for the video supply,Vid3V3, powers the analog core. This regulator is capable of being powered-
down via the serial interface but will be powered up by default. Note that the sensor will be in low power mode initially and
therefore
11.3 Valid Supply Voltage Configurations
The power supplies to the VV5410 and VV6410 sensors can be configured such that the sensor will operate in a number of
systems:
• USBsystem (sensorwill regulatethe nominal5V supplyto 3V3internally) withoptional BJTto providepower fora companion
chip.
• Direct drive the sensor with 3V3 (internal voltage regulators will be powered down in this mode).
The next 2figures will detail the options described above:
2. Minimum dynamic range includes dcout (i.e. Vclip- OUT_DC is greater than Vppmin/2)
3. Assumes 10µF bypass capacitors on all supplies and well separated supplies and grounds
1. Each audio output must have a capacitor (Ccomp) connected to ground to avoid any oscillation
Compensation Capacitor (nF) 3dB Bandwidth Units
1 175 kHz
10 41 kHz
100 4.2 kHz
Table 62 : Compensation capacitor values
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Digital
Regulator
5V
Vout
Audio
Regulator
5V Vout
Analog
Regulator
5V Vout
Audio Amp
Analog Core
Digital
Logic
VVL410
pd_areg
pd_creg
pd
Vbus Reg3v3
Vddcore
Aud3v3
Vid3v3
Vbase
220nF
220nF
Bandgap
Vbg
Vbg
Vbg
100nF
Voltage
Doubler 100nF
Vddhi
Vbg
Vddio
VIN
(5V)
(powered up)
(powered up)
Figure 47 : USB Power Setup
27uF
390
Key: 5V0 supply
from USB cable
Regulated 3V3
Digital
Regulator
5V
Vout
Audio
Regulator
5V Vout
Analog
Regulator
5V Vout
Audio Amp
Analog Core
Digital
Logic
VVL410
pd_areg
pd_creg
pd
Vbus Reg3v3
Vddcore
Aud3v3
Vid3v3
DVDD
Vbase
220nF
220nF
Bandgap
Vbg
Vbg
Vbg
100nF
Voltage
Doubler 100nF
Vddhi
Vbg
(3.3V)
Vddio
AVDD
(3.3V)
N/C
N/C
(powered down)
(powered down)
Figure 48 : Direct drive @3V3 Setup
Key: Analogue 3V3
supply
Digital 3V3
supply
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11.4 Programmable Pins
The FST and QCK pins can be re-configured to follow the values of bits 1 and 2 in the serial interface.register
pin_mapping
. This
is to allow remote control of a electro-mechanical system, maybe two different crop settings, in a remote camera head via the
serial interface.
Supply USB System 3.3V-only System
Vbus Supply from USB cable 3.3V direct drive
Vddio connect to Vreg3v3 3.3V direct drive
Vddcore connect to Vreg3v3 3.3V direct drive
Vreg3v3 optionally populate external BJT for
added drive BJT not populated
Vid3v3 generated by internal regulator internal regulator powered down
Aud3v3 generated by internal regulator internal regulator powered down
Table 63 : Sensor Voltage Supply summary
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12. Characterisation Details
12.1 VV5410/VV6410 AC/DC Specification
Table 64 : VV5410/6410 DC specification
12.2 VV5410/VV6410 Optical Characterisation Data
Parameter Comment Units
Image Format 356 x 292 pixels (PAL/CIF)
306 x 244 pixels (NTSC)
180 x 148 pixels (QCIF)
-
Pixel Size 7.5 x 6.9 µm
Technology 0.5µm 3 level metal CMOS -
Array Format CIF -
Exposure control range 81
(minimum exposure period 3µs and maximum exposure
period is 33ms)1
1. We assume CIF (30fps) mode, input clock of 16MHz and internal clock divisor of 1.
db
Supply Voltage 3.0-6.0 DC +/-10% V
Operating Temp. range 0 - 40 oC
VOL_max2
2. This is worst case reading. Device outputs had significant capacitive loading and supply voltage reduced to 2V7
0.512 V
VOH_min3
3. This is worst case reading. Device outputs had significant capacitive loading and supply voltage reduced to 2V7
2.054 V
VI_maxL4
4. This is worst case reading. Device outputs had significant capacitive loading and supply voltage reduced to 2V7
0.683 V
VIH_min5
5. This is worst case reading. Device outputs had significant capacitive loading and supply voltage reduced to 2V7
2.237 V
Serial interface frequency
range 0-100kHz
Optical Parameter Min Typical Max Units
Dark Current - 46 - mV/sec
Average Sensitivity - 2.1 - V/lux.sec
Fixed Pattern Noise (FPN) - 1.74 - mV
Vertical Fixed Pattern Noise (VFPN) - 1.2 - mV
Random Noise - 1.17 - mV
Sensor SNR - c.56 - dB
Shading (Gross) - 0.9 - mV
Table 65 : VV5410/VV6410 Optical Characterisation Data
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12.2.1 Noise Parameters and Dark Current
Various noise parameters are measured on the 410 device as follows:
• Fixed Pattern Noise (FPN)
• Vertical Fixed Pattern Noise (VFPN)
• Random Noise
• Fine Shading
• Gross Shading
The parameters will be described in more detail below along with the data produced by the characterisation programme.
12.2.2 Blooming
Blooming is a phenomenon that does not affect CMOS sensors in the same way as CCD imagers are afflicted. With a CCD
blooming can cause an entire column/columns to flood and saturate.
CMOS imagers are however affected by a different type of saturation. If an intense light source, (e.g. Maglite torch), is shone at
very close proximity to the image sensor the pixel sampling mechanism will break down and rather than displaying a saturated
white light a black image will occur.
The 410 pixel architecture uses Correlated Double Sampling (CDS) to help reduce noise in the system. The pixel is read normally
first, yielding the true integrated signal information, then the pixel is reset and very quickly read for a second time. This normally
yields black information - as the pixel has had no exposure time - that can be subtracted from the signal from the first read. This
subtraction will remove much of the noise from the pixel leaving only the useful signal information.
In an example where a pixel has saturated in both the first and the second reads due to an intense light source. When the noise
cancellation subtraction operation is then performed the result is close to zero signal from the pixel therefore resulting in the
displayed black image.
We do not perform any test measurements for this phenomenon.
12.2.3 Dark Current
This is defined as the rate at which the average pixel voltage increases over time with the device not illuminated. The dark current
will be measured at a gain setting of 4 and a clock divisor of 16 at a fixed temperature and will be expressed in mV.
12.2.4 Fixed Pattern Noise
The FPN of an image sensor is the average pixel non-temporal noise divided by the average pixel voltage. The illumination
source will be white light that has been IR filtered, producing a diffuse uniform illumination at the surface of the sensor package.
The FPN will be calculated at coarse exposure settings of 0,10,150,250 and 302 with gain set to 1. 10 frames are grabbed and
averaged to produce a temporally independent frame before each calculation. FPN will be expressed in mV.
12.2.5 Vertical Fixed Pattern Noise
VFPN describes the spatial noise in an image sensor related to patterns with a vertical orientation. The VFPN is defined as the
standard deviation over all columns of the average pixel voltage for each column determined at zero exposure and zero
illumination. VFPN will be expressed in mV.
12.2.6 Random Noise
Random noise is the temporal noise component within the image. Random noise will be expressed in mV.
12.2.7 Shading
This describes how average pixel values per “block” change across the image sensor array. For fine shading calculations the
image sensor array is split into 30 pixel by 30 pixel blocks. An average value is then calculated for each block and the averages
are then compared across the whole device. The blocks are increased in size to 60 pixels by 60 pixels for the gross shading
calculation. Shading will be expressed in mV.
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12.3 VV5410/VV6410 Power Consumption
Table 66 : VV5410/6410 Current consumption in different modes
12.4 Digital Input Pad Pull-up and Pull-down Strengths
Operating Condition Current Consumption
Low power mode current consumption 5.6mA
Sleep mode current consumption1
1. Estimated figures - this parameter was not measured during final characterisation
18mA
Suspend mode current consumption
(with CLKIP disabled) 85uA
Normal operating mode current consumption2
2. Measured while device is clocked at 16MHz and streaming CIF video at 30fps
26.2mA
Pad Type Pads Min current Max Current
Library pulldown suspend 35uA 52uA
Library pullup scl, sda, oeb 25uA 42uA
Custom pullup resetb 66uA 250uA
Table 67 : Pad Pull-up/Pull-down Strengths
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13. Pixel Defect Specification
13.1 Pixel Fault Definitions
Please find the pixel notation described in Figure 49 below. For the purposes of the test the 3x3 array describes 9 bayer pixels of
a common colour, i.e. ALL the pixels will either be Red, Green or Blue. The pixel under test is X.
Figure 49 : Pixel Numbering Notation
13.2 Stuck at White Pixel Fault
A pixel is said to be “stuck at white” - it can also be referred to as “hot” - if it is saturated (pixel output at maximum) even with no
incident light and exposure set to zero.
13.3 Stuck at Black Pixel Fault
A pixel is said to be “stuck at black” - it can also be referred to as “dead” - if the pixel output is zero even if the pixel is fully
exposed to incident light.
13.4 Column / Row Faults
A line of continuous pixel fails of length > 3 will be described as a row fault in the x-direction and a column fault in the y-direction.
If the array contains more than 1 row or column fault and the defective pixels overlap as shown in Figure 50 then this fault is
described as a double row or double column fault respectively. The minimum overlap is 1 pixel. A defective pixel is indicated by X
and a good pixel by ‘p’.
Figure 50 : Double Column Fault
In Figure 51 there are 2 column faults however there is no overlap between the 2 columns therefore there are 2 single column
faults but no double column faults.
[0] [1] [2]
[7] X[3]
[6] [5] [4]
n n+1
X‘p’
X‘p’
Xp
XX
‘p’ X
‘p’ X
‘p’ X
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Figure 51 : Single Column Faults
13.5 Image Array Blemishes
The automatic test programme rejects any sensors that contain blemishes referred to as blobs and clusters (please see below for
definitions of these terms) as they cannot be successfully defect corrected by ST coprocessor devices. Up to 120 single pixel
faults can be corrected and sensors meeting this criteria will PASS this part of the test programme.
13.5.1 Cluster Definition
A failing pixel at X with a failing pixel at position [0] or [1] or [2] or [3] or [4] or [5] or [6] or [7] or any combination of these 8
positions except the case where all positions are defective. This is a special case and is described below. In the example in
Figure 52 there are additional pixel fails in positions [3] and [7].
Figure 52 : Cluster Example
Blob (special case of cluster):- a failing pixel at position Xwith failing pixels at position [0],[1],[2],[3],[4],[5],[6] and [7] as in Figure
53 below:
Figure 53 : Blob Example
n n+1
X‘p’
X‘p’
Xp
X‘p’
‘p’ X
‘p’ X
‘p’ X
‘p’ X
[0] [1] [2]
[X]X[X]
[6] [5] [4]
[X][X][X]
[X]X[X]
[X][X][X]
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Single pixel:- a failing pixel with no immediate failing same colour neighbours. Pixels at position [0],[1],[2],[3],[4],[5],[6] and [7] are
all valid pixels. Please see Figure 54 below.
Figure 54 : Isolated pixel fail
13.5.2 Summary Pass Criteria
Clusters Blobs Row Fails (inc doubles) Column Fails (inc doubles) Single pixel fails Notes1
1. If there is a non-zero number of clusters, blobs or row/column faults and greater than 120 single pixel defects then the
device will be rejected and classed as a fail.
0 0 0 0 <=120 Pass
Table 68 : Sensor Pixel Defect Pass Criteria
[0] [1] [2]
[7] X[3]
[6] [5] [4]
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14. Pinout and pin descriptions
14.1 36pin CLCC Pinout Map
Figure 55 : 36 pin CLCC package pin assignment
Name Pin Number Type Description
POWER SUPPLIES
AVSS 10 GND Core analog ground and reference supplies.
RESETB
D[0]
LST/D[5]
FST/D[6]
VDDcore/
Vbus
VBG
VRT
AoutP
VDDhi
OEB
CLKI
7
8
6
54
3
2
1
9
10
11
12
13
14
15
16
17
19
20
21
22
23
24
25
26
27
28
29
32 33 34 35 36
D[3]
D[4]
Aud3V3
AoutN
Vbase
AVSS
18
30
31 Vbltw
D[1]
Vid3V3
AIN
VSScore
VSSio
SRAMVSS
D[2]
QCK
SDA
SUSPEND
VDDio
D[7]
Vbloom
Reg3V3
SCL
PORB
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SRAMVSS 17 GND In-column SRAM analog ground.
VDDcore/
Reg3V3 34 PWR Digital logic power.
VDDio 33 PWR Digital pad ring power.
VSScore 22 GND Digital logic ground.
VSSio 23 GND Digital pad ring ground.
Vid3V3 11 PWR On-chip Video Supply Voltage Regulator Output
Aud3V3 3 PWR On-chip Audio Amplifier Voltage Regulator Output
ANALOG SIGNALS
VBG 1 OA Internally generated bandgap reference voltage 1.22V
VDDHI 9 IA Voltage doubler output, 4.6V -> 4.8V
VBase 35 OA Drive for base of external bipolar
Vbus 36 IA Incoming power supply 3.3 -> 6V
AIN 4 IA Analog input to Audio Amplifier
AOutP 5 OA Analog output of Audio Amplifier (positive)
AOutN 6 OA Analog output of Audio Amplifier (negative)
PORB 13 OD Power-on Reset (Bar) Output.
DIGITAL VIDEO INTERFACE
D[4]
D[3]
D[2]
D[1]
D[0]
27
26
25
24
20
ODT Tri-stateable 5-wire output data bus.
- D[4] is the most significant bit.
- D[4:0] have programmable drive strengths 2, 4 and 6 mA
QCK 32 ODT Tri-stateable data qualification clock.
LST/D[5] 28 ODT Tri-stateable Line start output
May be configured as tri-stateable output data bit 5 D[5].
FST/D[6] 29 ODT Tri-stateable Frame start signal.
May be configured as tri-stateable output data bit 6 D[6].
D[7] 31 ODT Tri-stateable Data wire (ms data bit).
May be configured as tri-stateable output data bit 6 D[6].
OEB 16 ID↓Digital output (tri-state) enable.
DIGITAL CONTROL SIGNALS
Name Pin Number Type Description
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RESETB 21 ID↑System Reset. Active Low.
May be configured as System Sync. Active Low.
SUSPEND 12 ID↑USB Suspend Mode Control signal. Active High
If this feature is not required then the support circuit must pull the pin to
ground. The combination of an active high signal and pull up pad was
chosen to limit current drawn by the device while in suspend mode.
SERIAL INTERFACE
SCL 15 BI↑Serial bus clock (input only).
SDA 14 BI↑Serial bus data (bidirectional, open drain).
SYSTEM CLOCKS
CLKI 30 ID↓Schmitt Buffered Clock input or LVDS positive Clock input
Key
A Analog Input D Digital Input
OA Analog Output ID↑Digital input with internal pull-up
BI Bidirectional ID↓Digital input with internal pull-down
BI↑Bidirectional with internal pull-up OD Digital Output
BI↓Bidirectional with internal pull-down ODT Tri-stateable Digital Output
Name Pin Type Description
ANALOG SIGNALS
Vbloom 8 OA Anti-blooming pixel reset voltage1
1. This pin has been removed from the production bonding diagram
VBLTW 7 OA Bitline test white level reference 2
2. This pin has been removed from the production bonding diagram
VRT 2 IA Pixel reset voltage3
3. This pin has been removed from the production bonding diagram
Name Pin Number Type Description
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15. Package Details (36pin CLCC)
RevNo Revision note Date
2
1345678
ECN No.
10.67 -0.13
+0.30
2.67
2.02
8.13 0.13
1.02 0.13
40 Places
R0.15
Notes.
1. Die is optically centred.
2. Refractive index of glass is ~1.52.
3. Distance to optical surface of Die.
4. Pixel area of sensor.
Pin 1 Pin 5
Pin 6
A
A
1.16 0.09 (note 3)
2.15 -0.26
+0.16
0.60 -0.10
0.00
1.55 0.16
A-A (8 : 1)
A Pin Locations changed, tolerance added to O/all dims 14/7/99
B Package now 36 Pin 20/7/99
C 1.03 0.13 was 1.03 0.08 2/8/99
D 1.16 dim tolerance revised 15/10/99
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16. Recommended VV5410/6410 support circuit
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17. Evaluation kits (EVK’s)
It is highly recommended that an Evaluation Kit (EVK) is used for initial evaluation and design-in of the VV5410/6410. A VV5410/
VV6410 evaluation kit can now be ordered. Please contact STMicroelectronics for details.
VV5410 & VV6410 Ordering details
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18. Ordering details
Part Number Description
VV5410C036 36pin CLCC packaged, microlensed CIF monochrome sensor
VV6410C036 36pin CLCC packaged, microlensed CIF ColourMOS sensor
STV0657 YUV/RGB CoProcessor
STV0672 USB companion CoProcessor
STV0680B-001 Digital stills companion CoProcessor
STV-5410-R01 Reference design board for VV6410C036
STV-6410-R01 Reference design board for VV6410C036
STV-USB/CIF-R01 Reference design board for VV6410C036 & STV0672
STV-YUV/CIF-R02 Reference design board for VV6410C036 & STV0657-001
STV-DCA/CIF-R01 Reference design board for VV6410C036 & STV0680B-001
STV-5410/5500-E01 Sensor only evaluation kit for VV6410C036 & VV6500-C048
STV-6410/6500-E01 Sensor only evaluation kit for VV6410C036 & VV6500-C048
Table 69 : VV6410/VV5410 Ordering Details
Commercial in confidence
105/105
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Imaging Division
cd5410-6410f-3-0.fm
CMOS Sensor; Customer Datasheet, Rev 3.0,28 September 2000 cd5410-6410f
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