HD74AC174 Hex D-Type Flip-Flop with Master Reset REJ03D0256-0200Z (Previous ADE-205-376 (Z)) Rev.2.00 Jul.16.2004 Description The HD74AC174 is a high-speed hex D flip-flop. The device is used primarily as a 6-bit edge-triggered storage register. The information on the D inputs is transferred to storage during the Low-to-High clock transition. The device has a Master Reset to simultaneously clear all flip-flops. Features * Outputs Source/Sink 24 mA * Ordering Information Part Name Package Type Package Code Package Abbreviation Taping Abbreviation (Quantity) HD74AC174FPEL SOP-16 pin (JEITA) FP-16DAV FP EL (2,000 pcs/reel) HD74AC174RPEL SOP-16 pin (JEDEC) FP-16DNV RP EL (2,500 pcs/reel) Notes: 1. Please consult the sales office for the above package availability. 2. The packages with lead-free pins are distinguished from the conventional products by adding V at the end of the package code. Pin Arrangement MR 1 16 VCC Q0 2 15 Q5 D0 3 14 D5 D1 4 13 D4 Q1 5 12 Q4 D2 6 11 D3 Q2 7 10 Q3 GND 8 9 CP (Top view) Rev.2.00, Jul.16.2004, page 1 of 7 HD74AC174 Logic Symbol D0 D1 D2 D3 D4 D5 CP MR Q0 Q1 Q2 Q3 Q4 Q5 Pin Names D0 to D5 CP MR Q0 to Q5 Data Inputs Clock Pulse Input Master Reset Input Outputs Functional Description The HD74AC174 consists of six edge-triggered D flip-flops with individual D inputs and Q outputs. The Clock (CP) and Master Reset (MR) are common to all flip-flops. Each D input's state is transferred to the corresponding flipflops's output following the Low-to-High Clock (CP) transition. A Low input to the Master Reset (MR) will force all outputs Low independent of Clock or Data inputs. The HD74AC174 is useful for applications where the true output only is required and the Clock and Master Reset are common to all storage elements. Truth Table Inputs CP MR L H H H X L H : L : X : : High Voltage Level Low Voltage Level Immaterial Low-to-High Transition of Clock Rev.2.00, Jul.16.2004, page 2 of 7 Output Q D X H L X L H L Q HD74AC174 Logic Diagram MR CP D5 D4 D Q D3 D CP CD Q D CP CD Q5 D2 Q D CP CD Q4 D1 D0 Q D CP CD Q3 Q D CP CD Q2 Q CP CD Q1 Q0 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. Absolute Maximum Ratings Item Symbol Ratings Unit Condition Supply voltage DC input diode current VCC IIK -0.5 to 7 -20 V mA VI 20 -0.5 to Vcc+0.5 mA V VI = Vcc+0.5V DC input voltage DC output diode current IOK -50 50 mA mA VO = -0.5V VO = Vcc+0.5V DC output voltage DC output source or sink current VO IO -0.5 to Vcc+0.5 50 V mA DC VCC or ground current per output pin Storage temperature ICC, IGND Tstg 50 -65 to +150 mA C VI = -0.5V Recommended Operating Conditions Supply voltage Item Symbol VCC 2 to 6 V Input and output voltage Operating temperature VI, VO Ta 0 to VCC -40 to +85 V C Input rise and fall time (except Schmitt inputs) VIN 30% to 70% VCC tr, tf 8 ns/V Rev.2.00, Jul.16.2004, page 3 of 7 Ratings Unit Condition VCC = 3.0V VCC = 4.5 V VCC = 5.5 V HD74AC174 DC Characteristics Item Input Voltage Symbol VIH VIL Output voltage VOH VOL Ta = 25C Vcc (V) 3.0 min. 2.1 typ. 1.5 max. -- Ta = -40 to +85C min. max. 2.1 -- 4.5 5.5 3.15 3.85 2.25 2.75 -- -- 3.15 3.85 -- -- 3.0 4.5 -- -- 1.50 2.25 0.9 1.35 -- -- 0.9 1.35 5.5 3.0 -- 2.9 2.75 2.99 1.65 -- -- 2.9 1.65 -- 4.5 5.5 4.4 5.4 4.49 5.49 -- -- 4.4 5.4 -- -- 3.0 4.5 2.58 3.94 -- -- -- -- 2.48 3.80 -- -- 5.5 3.0 4.94 -- -- 0.002 -- 0.1 4.80 -- -- 0.1 4.5 5.5 -- -- 0.001 0.001 0.1 0.1 -- -- 0.1 0.1 3.0 4.5 -- -- -- -- 0.32 0.32 -- -- 0.37 0.37 Unit V Condition VOUT = 0.1 V or VCC -0.1 V VOUT = 0.1 V or VCC -0.1 V V VIN = VIL or VIH IOUT = -50 A VIN = VIL or VIH IOH = -12 mA IOH = -24 mA IOH = -24 mA VIN = VIL or VIH IOUT = 50 A VIN = VIL or VIH IOL = 12 mA IOL = 24 mA Input leakage current IIN 5.5 5.5 -- -- -- -- 0.32 0.1 -- -- 0.37 1.0 A VIN = VCC or GND IOL = 24 mA Dynamic output current* IOLD IOHD 5.5 5.5 -- -- -- -- -- -- 86 -75 -- -- mA mA VOLD = 1.1 V VOHD = 3.85 V Quiescent supply current ICC 5.5 -- -- 8.0 -- 80 A VIN = VCC or ground *Maximum test duration 2.0 ms, one output loaded at a time. AC Characteristics: HD74AC174 Item Symbol VCC (V)*1 Ta = +25C CL = 50 pF Min Typ Max Ta = -40C to +85C CL = 50 pF Min Max Unit Maximum clock frequency fmax 3.3 5.0 90 100 100 125 -- -- 70 100 -- -- MHz Propagation delay CP to Qn tPLH 3.3 5.0 1.0 1.0 9.0 6.0 11.5 8.5 1.0 1.0 12.5 9.5 ns Propagation delay CP to Qn tPHL 3.3 5.0 1.0 1.0 8.5 6.0 11.0 8.0 1.0 1.0 12.0 9.0 ns Propagation delay MR to Qn tPHL 3.3 5.0 1.0 1.0 9.0 7.0 11.5 9.0 1.0 1.0 12.5 10.5 ns Note: 1. Voltage Range 3.3 is 3.3 V 0.3 V Voltage Range 5.0 is 5.0 V 0.5 V Rev.2.00, Jul.16.2004, page 4 of 7 HD74AC174 AC Operating Requirements: HD74AC174 Ta = +25C CL = 50 pF Item Setup time, HIGH or LOW Symbol VCC (V)*1 Typ tsu 3.3 2.5 Dn to CP Hold time, HIGH or LOW th 5.0 3.3 Ta = -40C to +85C CL = 50 pF Guaranteed Minimum 6.5 7.0 ns 2.0 1.0 5.0 3.0 5.5 3.0 ns tw 5.0 3.3 0.5 1.0 3.0 5.5 3.0 7.0 ns CP pulse width tw 5.0 3.3 1.0 1.0 5.0 5.5 5.0 7.0 ns Recovery time trec 5.0 3.3 1.0 0 5.0 2.5 5.0 2.5 ns 5.0 0 2.0 2.0 Dn to CP MR pulse width, LOW MR to CP Note: Unit 1. Voltage Range 3.3 is 3.3 V 0.3 V Voltage Range 5.0 is 5.0 V 0.5 V Capacitance Item Input capacitance Power dissipation capacitance Rev.2.00, Jul.16.2004, page 5 of 7 Symbol CIN CPD Typ 4.5 85.0 Unit pF pF Condition VCC = 5.5 V VCC = 5.0 V HD74AC174 Package Dimensions As of January, 2003 Unit: mm 10.06 10.5 Max 9 1 8 1.27 *0.40 0.06 0.20 7.80 +- 0.30 1.15 0 - 8 0.10 0.10 0.80 Max *0.20 0.05 2.20 Max 5.5 16 0.70 0.20 0.15 0.12 M Package Code JEDEC JEITA Mass (reference value) *Ni/Pd/Au plating FP-16DAV -- Conforms 0.24 g As of January, 2003 Unit: mm 9.9 10.3 Max 9 1 8 0.635 Max *0.40 0.06 0.15 *0.20 0.05 1.27 0.11 0.14 +- 0.04 1.75 Max 3.95 16 0.10 6.10 +- 0.30 1.08 0 - 8 + 0.67 0.60 - 0.20 0.25 M *Ni/Pd/Au plating Rev.2.00, Jul.16.2004, page 6 of 7 Package Code JEDEC JEITA Mass (reference value) FP-16DNV Conforms Conforms 0.15 g HD74AC174 As of January, 2003 Unit: mm 4.40 5.00 5.30 Max 16 9 1 8 0.65 *0.20 0.05 1.0 0.13 M Rev.2.00, Jul.16.2004, page 7 of 7 *0.15 0.05 1.10 Max *Ni/Pd/Au plating 0.10 0.07 +0.03 -0.04 6.40 0.20 0.65 Max 0 - 8 0.50 0.10 Package Code JEDEC JEITA Mass (reference value) TTP-16DAV -- -- 0.05 g Sales Strategic Planning Div. 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