Rev.2.00, Jul.16.2004, page 1 of 7
HD74AC174
Hex D-Type Flip-Flop with Master Reset REJ03D0256–0200Z
(Previous ADE-205-3 76 (Z))
Rev.2.00
Jul.16.2004
Description
The HD74AC174 is a high-speed hex D flip-flop. The device is used primarily as a 6-bit edge-triggered storage register.
The information on the D inputs is transferred to sto r age during the Low-to-High clock transition. The device has a
Master Reset to simultaneo u sly c lear all flip-flops.
Features
Outputs Source/Sink 24 mA
Ordering Information
Part Name Package Type Package Code Package Abbreviation Taping Abbreviation (Quantity)
HD74AC174FPEL SOP-16 pin (JEITA) FP-16DAV FP EL (2,000 pcs/reel)
HD74AC174RPEL SOP-16 pin (JEDEC) FP-16DNV RP EL (2,500 pcs/reel)
Notes: 1. Please consult the sales office for the above package availability.
2. The packages with lead-free pins are distinguished from the conventional products by adding V at the end of
the package code.
Pin Arrangement
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
MR
Q
0
D
0
D
1
Q
1
Q
2
D
2
GND
V
CC
Q
5
D
5
D
4
Q
4
D
3
Q
3
CP
(Top view)
HD74AC174
Rev.2.00, Jul.16.2004, page 2 of 7
Logic Symbol
D
0
D
1
D
2
D
3
D
4
D
5
Q
0
CP
MR
Q
1
Q
2
Q
3
Q
4
Q
5
Pin Names
D0 to D5Data Inputs
CP Clock Pulse I nput
MR Master Re se t Input
Q0 to Q5Outputs
Functional Description
The HD74AC174 consists of six edge-triggered D flip-flops with individual D inputs and Q outputs. The Clock (CP)
and Master Reset (MR) are common to all flip-flops. Each D input’s state is transferred to the corresponding flip-
flops’s output following the Low-to-High Clock (CP) transition. A Low input to the Master Re set (MR) will force all
outputs Low independent of Clock or Data inputs. The HD74AC174 is useful for applications where the true output
only is required and the Clock and Master Reset are common to all storage elements.
Truth Table
Inputs Output
MR
MRMR
MR CP D Q
LXXL
HHH
HLL
HLXQ
H : High Voltage Level
L : Low Voltage Level
X : Immaterial
: Low-to-High Transition of Clock
HD74AC174
Rev.2.00, Jul.16.2004, page 3 of 7
Logic Diagram
CP
CD
CP
M
RD5
Q5Q4Q3Q2Q1Q0
D4D3D2D1D0
DQ
CP
CD
DQ
CP
CD
DQ
CP
CD
DQ
CP
CD
DQ
CP
CD
DQ
Please note that this diagram is provided only for the understanding of logic operations and should not be
used to estimate propagation delays.
Absolute Maximum Ratings
Item Symbol Ratings Unit Condition
Supply voltage VCC –0.5 to 7 V
–20 mA VI = –0.5VDC input diode current IIK 20 mA VI = Vcc+0.5V
DC input voltage VI–0.5 to Vcc+0.5 V
–50 mA VO = –0.5VDC output diode current IOK 50 mA VO = Vcc+0.5V
DC output voltage VO–0.5 to Vcc+0.5 V
DC output source or sink current IO±50 mA
DC VCC or ground current per output pin ICC, IGND ±50 mA
Storage temperature Tstg –65 to +150 °C
Recommended Operating Conditions
Item Symbol Ratings Unit Condition
Supply voltage VCC 2 to 6 V
Input and output voltage VI, VO0 to VCC V
Operating temperature Ta –40 to +85 °CVCC = 3.0V
VCC = 4.5 V
Input rise and fall time
(except Schmitt inputs)
VIN 30% to 70% VCC
tr, tf 8 ns/V
VCC = 5.5 V
HD74AC174
Rev.2.00, Jul.16.2004, page 4 of 7
DC Characteristics
Ta = 25°
°°
°C Ta = –40 to
+85°
°°
°C
Item Sym-
bol Vcc
(V) min. typ. max. min. max.
Unit Condition
3.0 2.1 1.5 2.1
4.5 3.15 2.25 3.15
VIH
5.5 3.85 2.75 3.85
VOUT = 0.1 V or VCC0.1 V
3.0 1.50 0.9 0.9
4.5 2.25 1.35 1.35
Input Voltage
VIL
5.5 2.75 1.65 1.65
V
VOUT = 0.1 V or VCC0.1 V
3.0 2.9 2.99 2.9
4.5 4.4 4.49 4.4
5.5 5.4 5.49 5.4
VIN = VIL or VIH
IOUT = –50 µA
3.0 2.58 2.48 IOH = –12 mA
4.5 3.94 3.80 IOH = –24 mA
VOH
5.5 4.94 4.80
VIN = VIL or VIH
IOH = –24 mA
3.0 0.002 0.1 0.1
4.5 0.001 0.1 0.1
5.5 0.001 0.1 0.1
VIN = VIL or VIH
IOUT = 50 µA
3.0 0.32 0.37 IOL = 12 mA
4.5 0.32 0.37 IOL = 24 mA
Output voltage
VOL
5.5 0.32 0.37
V
VIN = VIL or VIH
IOL = 24 mA
Input leakage
current IIN 5.5 ±0.1 ±1.0 µAV
IN = VCC or GND
IOLD 5.5———86—mAV
OLD = 1.1 VDynamic outp ut
current*IOHD 5.5 –75 mA VOHD = 3.85 V
Quiescent su pply
current ICC 5.5 8.0 80 µAV
IN = VCC or ground
*Maximum test duration 2.0 ms, one output loaded at a time.
AC Characteristics: HD74AC174
Ta = +25°C
CL = 50 pF Ta = –40°C to +85°C
CL = 50 pF
Item Symbol VCC (V)*1Min Typ Max Min Max Unit
Maximum clock fmax 3.3 90 100 70 MHz
frequency 5.0 100 125 100
Propagation delay tPLH 3.3 1.0 9.0 11.5 1.0 12.5 ns
CP to Qn5.0 1.0 6.0 8.5 1.0 9.5
Propagation delay tPHL 3.3 1.0 8.5 11.0 1.0 12.0 ns
CP to Qn5.0 1.0 6.0 8.0 1.0 9.0
Propagation delay tPHL 3.3 1.0 9.0 11.5 1.0 12.5 ns
MR to Qn5.0 1.0 7.0 9.0 1.0 10.5
Note: 1. Voltage Range 3.3 is 3.3 V ± 0.3 V
Voltage Range 5.0 is 5.0 V ± 0.5 V
HD74AC174
Rev.2.00, Jul.16.2004, page 5 of 7
AC Operating Requirements: HD74AC174
Ta = +25°C
CL = 50 pF
Ta = –40°C
to +85°C
CL = 50 pF
Item Symbol VCC (V)*1Ty p Guaranteed Minimum Unit
Setup time, HIGH or LOW tsu 3.3 2.5 6.5 7.0 ns
Dn to CP 5.0 2.0 5.0 5.5
Hold time, HIGH or LOW th3.3 1.0 3.0 3.0 ns
Dn to CP 5.0 0.5 3.0 3.0
MR pulse width, LOW tw3.3 1.0 5.5 7.0 ns
5.0 1.0 5.0 5.0
CP pulse width tw3.3 1.0 5.5 7.0 ns
5.0 1.0 5.0 5.0
Recovery time trec 3.3 0 2.5 2.5 ns
MR to CP 5.0 0 2.0 2.0
Note: 1. Voltage Range 3.3 is 3.3 V ± 0.3 V
Voltage Range 5.0 is 5.0 V ± 0.5 V
Capacitance
Item Symbol Typ Unit Condition
Input capacitan ce CIN 4.5 pF VCC = 5.5 V
Power dissipation capacitance CPD 85.0 pF VCC = 5.0 V
HD74AC174
Rev.2.00, Jul.16.2004, page 6 of 7
Package Dimensions
Package Code
JEDEC
JEITA
Mass
(reference value)
FP-16DAV
Conforms
0.24 g
*Ni/Pd/Au plating
*0.20 ± 0.05
*0.40 ± 0.06
0.12
0.15
M
2.20 Max
5.5
10.06
0.80 Max
16 9
18
10.5 Max
+ 0.20
0.30
7.80
0.70 ± 0.20
0˚ – 8˚
0.10 ± 0.10
1.15
1.27
As of January, 2003
Unit: mm
Package Code
JEDEC
JEITA
Mass
(reference value)
FP-16DNV
Conforms
Conforms
0.15 g
*Ni/Pd/Au plating
1.27
16 9
18
0.15
0.25
M
1.75 Max 3.95
*0.20 ± 0.05
9.9
0˚ 8˚
10.3 Max
+ 0.10
0.30
6.10
+ 0.67
0.20
0.60
+ 0.11
0.04
0.14
*0.40 ± 0.06
0.635 Max
1.08
As of January, 2003
Unit: mm
HD74AC174
Rev.2.00, Jul.16.2004, page 7 of 7
Package Code
JEDEC
JEITA
Mass
(reference value)
TTP-16DAV
0.05 g
*Ni/Pd/Au plating
0.50 ± 0.10
0˚ 8˚
*0.15 ± 0.05
6.40 ± 0.20
0.10
1.10 Max
0.13 M
0.65
18
16 9
4.40
5.00
5.30 Max
0.07+0.03
0.04
0.65 Max
1.0
*0.20 ± 0.05
As of January, 2003
Unit: mm
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