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SOCS062B – JANUARY 2001 – REVISED MAY 2002
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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DVery Low Noise, High Sensitivity,
Electronically Variable
DHigh Resolution, 1/3-in Format, Solid State
Charge-Coupled Device (CCD) Frame
Transfer Image Sensor for Black and White
National Television and Standard
Committee (NTSC) and Computer
Applications
D340,000 Pixels per Field
DFrame Memory
D656 (H) × 496 (V) Active Pixels in Image
Sensing Area Compatible With Electronic
Centering
DMultimode Readout Capability
– Progressive Scan
– Interlace Scan
– Line Summing
DFast Single-Pulse Clear Capability
DContinuous Electronic Exposure Control
from 1/60 s to 1/5,000 s
D7.4 µm Square Pixels
DAdvanced Lateral Overflow Drain
DLow Dark Current
DSolid State Reliability With No Image
Burn-In, Residual Imaging, Image
Distortion, Image Lag, or Microphonics
DHigh Photoresponse Uniformity from
Deep Ultraviolet (DUV) to Near Infrared
(NIR)
description
The TC253SPD device is a frame-transfer, CCD image sensor designed for use in black and white NTSC TV,
computer, and special-purpose applications that require high sensitivity, low noise, and small size.
The TC253SPD sensor is a new device of the IMPACTRONt family of very low noise, high sensitivity image
sensors that multiply charge directly in the charge domain before conversion to voltage. The charge carrier
multiplication (CCM) is achieved by using a low-noise, single-carrier, impact ionization process that occurs
during repeated carrier transfers through high field regions. Applying multiplication pulses to specially designed
gates activates the CCM. The amount of multiplication is adjustable, depending on the amplitude of the
multiplication pulses. The device function resembles the function of image intensifiers implemented in solid
state.
This MOS device contains limited built-in gate protection. During storage or handling, the device leads should be shorted together
or the device should be placed in conductive foam. In a circuit, unused inputs should always be connected to VSS. Under no
circumstances should pin voltages exceed absolute maximum ratings. Avoid shorting OUT to VSS during operation to prevent
damage to the amplifier. The device can also be damaged if the output terminals are reverse-biased and an excessive current is
allowed to flow. Specific guidelines for handling devices of this type are contained in the publication Guidelines for Handling
Electrostatic-Discharge-Sensitive (ESDS) Devices and Assemblies available from Texas Instruments.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
ADVANCE INFORMATION
Copyright 2002, Texas Instruments Incorporated
IMPACTRON is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
1
2
3
4
5
67
8
9
10
11
12
DUAL-IN-LINE PACKAGE
(TOP VIEW)
ODB
IAG2
SAG2
SRG1
SRG2
CMG
NC
IAG1
SAG1
SUB
ADB
Vout
×
SOCS062B – JANUARY 2001 – REVISED MAY 2002
2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
description (continued)
The image-sensing area of the TC253SPD sensor is configured into 500 lines with 680 pixels in each line.
Twenty-two pixels are reserved in each line for dark reference. The blooming protection is based on an
advanced lateral overflow drain concept that does not reduce NIR response. The sensor can be operated in
the interlaced or progressive scan modes and can capture full 340,000 pixels in one image field. The frame
transfer from the image-sensing area to the memory area is accomplished at a very high rate that minimizes
image smear. The electronic exposure control is achieved by clearing unwanted charge from the image area
using a short positive pulse applied to the antiblooming drain. This pulse marks the beginning of the integration
time, which can be arbitrarily shortened from its nominal length. After charge is integrated and stored in the
memory it is available for readout in the next cycle. This is accomplished using a unique serial register design
that includes special charge multiplication pixels.
The TC253SPD sensor is built using TI-proprietary advanced split-gate virtual-phase CCD (SGVPCCD)
technology, which provides devices with wide spectral response, ranging from DUV to NIR, high quantum
efficiency (QE), low dark current, and high response uniformity. The TC253SPD sensor is characterized over
an operating free-air temperature range of TA= –10°C to 45°C.
ADVANCE INFORMATION
×
SOCS062B – JANUARY 2001 – REVISED MAY 2002
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
functional block diagram
ODB
IAG2 IAG1
SAG2 SAG1
SRG1
SRG2
CMG
SUB
2
3
4
5
6
9
10
11
12
7
1
Dark Reference Pixels
Image Sensing Area
with Blooming Protection
Image Storage Area
Serial Readout Register
Charge Multiplier
Output Amplifier
VO
Clearing Drain ADB
ADVANCE INFORMATION
×
SOCS062B – JANUARY 2001 – REVISED MAY 2002
4POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
sensor topology diagram
400 Multiplication Pixels
Dark Reference Pixels
Image Sensing Area
with Blooming Protection
Image Storage Area
24 656 Active Pixels
98
188
Optical Black Pixels (OPB)
Dummy Pixels
24 Dark
Reference
Pixels
4 Dark
Isolation Lines
496 Active Lines
500 Lines
656 Active Pixels
ADVANCE INFORMATION
×
SOCS062B – JANUARY 2001 – REVISED MAY 2002
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Terminal Functions
TERMINAL
I/O
DESCRIPTION
NAME NO. I/O DESCRIPTION
ADB 9 I Supply voltage for amplifiers and clearing drain
CMG 6 I Charge multiplication gate
IAG1 12 I Image area gate 1
IAG2 2 I Image area gate 2
NC 8 –No connection
ODB 1 I Supply voltage for antiblooming drain
VOUT 7 O Output signal, multiplier channel
SAG1 11 IStorage area gate 1
SAG2 3 I Storage area gate 2
SRG1 4 I Serial register gate 1
SRG2 5 I Serial register gate 2
SUB 10 Chip substrate
detailed description
The TC253SPD sensor consists of four basic functional blocks: the image-sensing area, the image storage
area, the serial register, and the charge multiplier. The location of each of these blocks is identified in the
functional block diagram.
image-sensing and storage areas
Figure 1 and Figure 2 show cross sections with potential-well diagrams and top views of the pixels in the
image-sensing and storage areas. As light enters silicon in the image-sensing area, electrons are generated
and collected in potential wells of the pixels. Applying a suitable dc bias to the antiblooming drain provides
blooming protection. Electrons that exceed a specified level, determined by the ODB bias, are drained away
from the pixels. If it is necessary to remove all previously accumulated charge from the wells, a short positive
pulse must be applied to the drain. This marks the beginning of the new integration period. After the integration
cycle is completed, charge is quickly transferred into the memory where it waits for readout. The lines can be
read out from the memory in a sequential order to implement progressive scan, or two lines can be summed
together to implement the pseudo-interlace scan.
Twenty-two columns at the left edge of the image-sensing area are shielded from incident light. These pixels
provide the dark reference used in subsequent video-processing circuits to restore the video black level. An
additional four dark lines located between the image-sensing area and the image storage area were added for
isolation.
ADVANCE INFORMATION
×
SOCS062B – JANUARY 2001 – REVISED MAY 2002
6POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ÎÎÎÎÎÎÎÎÎ
+ + + + + + + + + + + + + + + + + + + + + + + + +
n – Buried Channel
p – Substrate
p+
Virtual Phase
X
Ø
Pixel Cross Section
Channel Potential
Integrated
Charge
IAG2/SAG2
IAG1/SAG1
Polysilicon Gates
Figure 1. Image Area and Storage Area Pixel Cross Section with Channel Potential
ADVANCE INFORMATION
×
SOCS062B – JANUARY 2001 – REVISED MAY 2002
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Antiblooming
Drain
Channel Stops
IAG1
IAG2
SAG1
SAG2
Image Area Pixel
Storage Area Pixel
7.4 µm
7.4 µm
7.0 µm
7.4 µm
Figure 2. Image Area and Memory Area Pixel Topologies
ADVANCE INFORMATION
×
SOCS062B – JANUARY 2001 – REVISED MAY 2002
8POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
advanced lateral overflow drain
The advanced lateral overflow drain structure is shared by two neighboring pixels in each line. Varying the dc
bias of the antiblooming drain can control the blooming protection level and trade it for well capacity. Applying
a pulse (approximately 10 V above the nominal level for a minimum of 1 µs) to the drain removes all charge from
the pixels. This feature permits a precise control of the integration time on a frame-by-frame basis. The
single-pulse clearing capability also reduces smear by eliminating accumulated charge in the pixels before the
start of the integration period (single-sided smear). The application of a negative 1-V pulse to the antiblooming
drain during the parallel transfer is recommended. This pulse prevents creation of undesirable artifacts caused
by the on-chip crosstalk between the image area gate clock lines and the antiblooming drain bias lines.
serial register and charge multiplier
The serial register is used to transport charge stored in the pixels of the memory to the output amplifier . However ,
the TC253SPD device has a serial register with twice the standard length. The first half has a conventional
design that interfaces with the memory and the clearing drain as it would in any other CCD sensor (for example
the TC237 sensor). The second half, however, is unique and includes 400 charge multiplication stages with a
number of dummy pixels that are needed to transport charge between the active register blocks and the output
amplifier. Charge is multiplied as it progresses from stage to stage in the multiplier toward the charge detection
node. The charge multiplication level depends on the amplitude of multiplication pulses (approximately 11 V ~
17 V) applied to the multiplication gates. Due to the double length of the registers, the first line in the field or frame
scan does not contain valid data and must be discarded.
readout and video processing
The last element of the charge readout and detection chain is the charge detection node. Charge detection
nodes use standard floating diffusion (FD) concepts followed by dual-stage source followers as buffer
amplifiers. The reset gate is internally connected to SRG1. This connection results in a simultaneous FD reset
when the SRG1 gate is clocked high. To achieve the ultimate sensor performance, it is necessary to eliminate
the detection node kTC noise using CDS processing techniques. The IMPACTRONt devices can detect single
photons when cooling or when sufficiently short integration times are used.
ADVANCE INFORMATION
×
SOCS062B – JANUARY 2001 – REVISED MAY 2002
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature (unless otherwise noted)†
Supply voltage range, VSS: ADB (see Note 1) SUB to SUB + 15 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Supply voltage range, VSS: ODB SUB to SUB + 22 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, VI: IAG1, IAG2, SAG, SRG –10 V to 10 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, VI: IAG1, SAG, SRG2 –8 V to 8 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, VI: SRG1 –5 V to 8 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, VI: CMG –5 V to 15 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature range, TA –10°C to 45°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg –30°C to 85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating case temperature range, TC –10°C to 55°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to SUB.
recommended operating conditions
MIN NOM MAX UNIT
Substrate bias, VSS 0 V
ADB 12
S ppl oltage V
For blooming control 6
V
Supply voltage, VDD ODB For clearing 13 V
ODB
For transfer 5.5
IAG1
High 2.4
IAG1 Low –3.2
IAG2
High 4.5
IAG2 Low –6.2
SAG1
High 2.4
SAG1 Low –2.4
Input voltage V †
SAG2
High 3.1
V
Input voltage, VI
†
SAG2 Low –4.2 V
SRG1
High 4.2
SRG1 Low –4.6
SRG2
High 5.7
SRG2 Low –3.4
CMG
High 7 13.6
CMG Low –2
IAG1, IAG2 3.125
Clock freq enc f
SAG1, SAG2 3.125
MH
Clock frequency, fclock SRG1, SRG2 12.5 MHz
CMG 12.5
Load capacitance OUT 6 pF
Operating free-air temperature, TA–10 45 °C
†Fine tuning of input voltages is required in order to obtain good charge transfer.
ADVANCE INFORMATION
×
SOCS062B – JANUARY 2001 – REVISED MAY 2002
10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
PARAMETER MIN TYP†MAX UNIT
Charge multiplication gain 1 30 (100)‡
Charge multiplication gain temperature coefficient %/°C
Excess noise factor for typical CCM gain (see Note 2) 1 1.2 1.4
Dynamic range without CCM gain 58 dB
Dynamic range with typical CCM gain (see Note 3) 50 dB
Charge conversion gain without CCM (see Note 4) 10 µV/e
τSignal-response delay time (see Note 5) 9 ns
Output resistance 320 Ω
Amplifier noise-equivalent signal without CCM gain §42 e
Amplifier noise-equivalent signal with typical CCM gain §1.5 e
Response linearity with no CCM gain 1
Response linearity with typical CCM gain 1
Charge-transfer efficiency (see Note 6) 0.9998 0.9999
Supply current 2 3 4 mA
IAG-1 2.95
IAG-2 3.22
IAG-1–IAG2 1.98
nF
SAG-1 3.04 nF
SAG-2 3.62
C
Inp t capacitance
SAG-1–SAG2 2.22
CiInput capacitance SRG-1 40
SRG-2 40
SRG-1–SRG2
pF
CMG 30 pF
CMG–SRG1
ODB 1,000
ADB high (see Note 7) 20
SRG-1, 2 high (see Note 7) 45
Pulse amplitude rejection ratio
SRG-1, 2 low (see Note 7) 45
dB
Pulse amplitude rejection ratio CMG high (see Note 7) 45 dB
CMG low (see Note 7) 45
ODB low (see Note 7) 45
†All typical values are at TA = 25°C.
‡Maximum CCM gain is not ensured.
§The values in this table are quoted using correlated double sampling (CDS), which is a signal processing technique that improves performance
by minimizing undesirable effects of reset noise.
NOTES: 2. Excess noise factor F is defined as the ratio of noise sigma after multiplication divided by M times the noise sigma before
multiplication where M is the charge multiplication gain.
3. Dynamic range is –20 times the logarithm of the mean noise sigma divided by the saturation output signal amplitude.
4. Charge conversion factor is defined as the ratio of output signal to input number of electrons.
5. Signal-response delay time is the time between the falling edge of the SRG2 pulse and the output signal valid state.
6. Charge transfer efficiency is 1 minus the charge loss per transfer in the CCD register. The test is performed in the dark using either
electrical or optical input.
7. Rejection ratio is –20 times the logarithm of the output referenced to the reset level divided by the 1 V of amplitude change of the
corresponding gate or terminal signal.
ADVANCE INFORMATION
×
SOCS062B – JANUARY 2001 – REVISED MAY 2002
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
optical characteristics, TA = 40°C (unless otherwise noted)
PARAMETER MIN TYP MAX UNIT
Sensitivity with typical CCM gain (see Note 8)
No IR filter 240
V/Lux
Sensitivity with typical CCM gain (see Note 8) With IR filter 33 V/Lux
Sensiti it itho t CCM gain (see Note 8)
No IR filter 8
V/L
Sensitivity without CCM gain (see Note 8) With IR filter 1.1 V/Lux
Vsat Saturation signal output no CCM gain (see Note 9) 260 mV
Vsat Saturation signal output with typical CCM gain (see Note 9) 440 mV
Voff Zero input offset output (see Note 10) 200 mV
Blooming overload ratio (see Note 11) 1000:1
Image area well capacity 26k
Smear (see Note 12) 66 dB
Dark current (see Note 13) 0.15 0.90 nA/cm2
Dark signal (see Note 14) 0.08 0.50 mV
Dark-signal uniformity (see Note 15) 0.3 mV
Dark-signal shading (see Note 16) 0.4 mV
Spurious nonuniformity
Dark 0.8 mV
Spurious nonuniformity Illuminated –20% 20%
Column uniformity (see Note 17) 0.2 mV
Electronic-shutter capability 1/5000 1/60 s
NOTES: 8. Light source temperature is 2856°K. The IR filter used is CM500 1 mm thick.
9. Saturation is the condition in which further increase in exposure does not lead to further increases in output signal.
10. Zero-input offset is the residual output signal measured from the reset level with no input charge present. This level is not caused
by the dark current and remains approximately constant, independent of temperature. This level can vary with the amplitude of
SRG2.
11. Blooming is the condition in which charge induced by light in one element spills over to the neighboring elements.
12. Smear is the measure of error signal introduced into the pixels by transferring them through the illuminated region into the memory.
The illuminated region is 1/10 of the image area height. The value in the table is obtained for the integration time of 16.66 ms and
3.125 MHz vertical clock transfer frequency.
13. Dark current depends on temperature and approximately doubles every 8°C. Dark current is also multiplied by the CCM operation.
The value given in the table is with the multiplier turned off, and it is a calculated value.
14. Dark signal is actual device output measured in darkness.
15. Dark signal uniformity is the sigma of difference of two neighboring pixels taken from all the image area pixels.
16. Dark signal shading is the difference between maximum and minimum of a 5-pixel median taken anywhere in the array.
17. Column uniformity is obtained by summing all the lines in the array, finding the maximum of the difference of two neighboring columns
anywhere in the array, and dividing the result by the number of lines.
ADVANCE INFORMATION
×
SOCS062B – JANUARY 2001 – REVISED MAY 2002
12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CMG
Clear Integrate Transfer to Memory Readout
ODB
IAG1
IAG2
SAG1
SAG2
SRG1
SRG2
IAG1
IAG2
SAG1
SAG2
SRG1
SRG2
CMG
Expanded Section of Parallel Transfer
500 Pulses
Expanded Section of Serial Transfer
501 Cycles
685 Pulses Line 500
Pulse Position
Determines Exposure
685 Pulses Line 0 {
{ Line 0 does not contain valid data.
686 Pulses Line 500
686 Pulses Line 500
SRG1
SRG2
CMG
Expanded Section of Serial Transfer
686 Pulses Line 0 {
686 Pulses Line 0 {
Figure 3. Progressive Scan Timing
ADVANCE INFORMATION
×
SOCS062B – JANUARY 2001 – REVISED MAY 2002
13
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CMG
Clear Integrate Transfer to Memory Readout
ODB
IAG1
IAG2
SAG1
SAG2
SRG1
SRG2
IAG1
IAG2
SAG1
SAG2
SRG1
SRG2
CMG
Expanded Section of Parallel Transfer
500 Pulses Even Field, 501 Pulses Odd Field
Expanded Section of Serial Transfer
251 Cycles
685 Pulses Line 250
Pulse Position
Determines Exposure
685 Pulses Line 0 {
{ Line 0 does not contain valid data.
686 Pulses Line 250
686 Pulses Line 250
SRG1
SRG2
CMG
Expanded Section of Serial Transfer
686 Pulses Line 0 {
686 Pulses Line 0 {
Figure 4. Interlace Timing for Line Summing Mode
ADVANCE INFORMATION
×
SOCS062B – JANUARY 2001 – REVISED MAY 2002
14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SRG1
SRG2
V
S/H
Clamp
CMG
Reset Level
OUT1,2
{ Output signal may not be zero for zero-input charge. Offset level up to 100 mV may be present.
Output Signal{
Figure 5. Detail Serial Register Clock Timing for CDS Implementation
ADVANCE INFORMATION
×
SOCS062B – JANUARY 2001 – REVISED MAY 2002
15
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Input Light Intensity [Lux]
V
V
10*M V/e
Zero Offset
O
SAT
µ
[mV]
Built-In Threshold Level
Ith
Figure 6. Photon Transfer Characteristic of CCD Outputs
ADVANCE INFORMATION
×
SOCS062B – JANUARY 2001 – REVISED MAY 2002
16 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
Vcl
Vodb
Vcmdh Vcmdl
+Vsag1
–Vsag1
+Vsag2
–Vsag2
+Viag1
–Viag1
+Viag2
–Viag2
+Vsrg1
–Vsrg1
+Vsrg2
–Vsrg2
Vcc
DC Voltages (Typ.)
Vcl
Vodb
Vcc
+Vsag1
–Vsag1
+Vsag2
–Vsag2
12 V
15 V
5 V
2.5 V
–2.5 V
3.5 V
–4.0 V
–Viag1
+Viag2
+Viag1
–Viag2
2.4 V
–3.2 V
4.5 V
–6.2 V
–Vsrg2
+Vsrg1
+Vsrg2
–Vsrg1
4.2 V
–4.6 V
5.7 V
–3.4 V
1.5 V
Vcmgh
Vcmgl
13.6 V
SAG1 –Vsag1
+Vsag1
IAG1
Vcc +Viag1
+Vsrg2
Vcc
SRG2
+Vsrg1
–Vsrg1
Vcc
SRG1
–Vsrg2
–Viag1
+Viag2
Vcc
IAG2
+Vsag2
–Vsag2
Vcc
SAG2
–Viag2
ODB1
ODB2
CMG
Vcc
Vcc
Oscillator
–Viag2
10 k
EL7156CS
VS+
1
OE
2
IN
3
GND
4
VH 8
OUT 7
VL 6
VS–5
TC253
ODB
1
IAG2
2
SAG2
3
SRG1
4
NC 8
Vout 7
CMG
6SRG2
5ADB 9
SUB 10
SAG1 11
IAG1 12
EL7156CS
VS+
1
OE
2
IN
3
GND
4
VH 8
OUT 7
VL 6
VS–50.1
10
10 k
0.10.1
10 k
ODB Driver
Vodb
ODBout
ODB1
GND
ODB2
EL7156CS
VS+
1
OE
2
IN
3
GND
4
VH 8
OUT 7
VL 6
VS–5
EL7156CS
VS+
1
OE
2
IN
3
GND
4
VH 8
OUT 7
VL 6
VS–5
EL7156CS
VS+
1
OE
2
IN
3
GND
4
VH 8
OUT 7
VL 6
VS–5
CMG Driver
Vcmgh
CMGout
CMG
GND
Vcmgl
0.1 0.1
0.1 0.1
EL7156CS
VS+
1
OE
2
IN
3
GND
4
VH 8
OUT 7
VL 6
VS–5
10 k
10 k
10 k
0.1 0.1
0.1 0.1
0.1 0.1
10
10
10
10
User Defined Timer
ODB2
IAG2
SAG2
SRG1
CLMP
ODB1
CMG
SRG2
Vcc
GND
SAG1
IAG1
CLK
S/H
SYNC
LCLMP
CLEAR
0.1 33
+
0.1
10
10
OUT
–Vsag2
0.1 0.1
–Vsag1
0.1
0.1
–Viag1
0.1
NOTES: A. All values are in Ω and µF unless otherwise noted.
B. TI recommends ac coupled system for coupling to the next video processing circuits.
C. IAG and SAG signal from user defined timer must be shifted its GND level to –V before the driver IC (EL7156CS) input.
D. The value of the CCD external capacitors (on IAG and SAG) were recommended with 2000 pF ~ 5000 pF.
Figure 7. Typical Application Circuit
ADVANCE INFORMATION
×
SOCS062B – JANUARY 2001 – REVISED MAY 2002
17
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
ODB Driver Circuit
CMG Driver Circuit
ODB2
Vcmgl
CMGout
Vcmgh
Vodb = 24 V
ODB1
CMG
ODBout
Q3
1SS193
10
Q1
VR
2.0 k
0.1
1.5 k
2200p
0.1
0.1
3.3 k
TN2106N3
1.5 k
0.1
10 k
1SS193
1SS226
2.7 k
0.1
2200p
10 k
5.6 k
Q2
3.3 k
10 k
1SS226
2.7 k
3.3 k
TP2104N3
NOTE A: All values are in Ω and µF unless otherwise noted.
Figure 8. Example of CMG Driver Circuit
ADVANCE INFORMATION
×
SOCS062B – JANUARY 2001 – REVISED MAY 2002
18 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
The package for the TC253SPD image sensor consists of a ceramic base, a glass window, and a 12-lead frame.
The glass window is sealed to the package by an epoxy adhesive. The package leads are configured in a
dual-in-line arrangement and fit into mounting holes with 1,78 mm center-to-center spacing.
12 pin
7 pin
1.78
0.33
4.45
0.51
11.68
12.40
2.08
3.298
3.998
5.94
11.50 3.65
5.64
4.15
Package Center
Opticle Center
1 pin
6 pin
11.10
12.00
11.75
1 pin Index Mark
11.85
0.76
0.41
3.35
11.05
10.95
3.398
2.798
0.17
1.48
Focal Plane
11.18
ALL LINEAR DIMENSIONS ARE IN MILLIMETERS
TC253 (12 pin)
10/00
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