1
LTC1543
sn1534 1543fas
Software-Selectable
Multiprotocol Transceiver
, LTC and LT are registered trademarks of Linear Technology Corporation.
D2 D1
LTC1544
RTS
DTRDSR DCDCTS
D3
R2 R1R4 R3 D2
LTC1543
LL TXDSCTETXC
RXCRXD
21424111512179314192062322513 81018 7 16
1543 TA01
LTC1344A
D3
R2 R1R3 D1
TXD A (103)
TXD B
SCTE A (113)
SCTE B
RXC A (115)
RXC B
RXD A (104)
RXD B
RTS A (105)
RTS B
DTR A (108)
DTR B
CTS A (106)
CTS B
LL A (141)
SG (102)
SHIELD (101)
DB-25 CONNECTOR
TXC A (114)
TXC B
DCD A (109)
DCD B
DSR A (107)
DSR B
D4
DTE or DCE Multiprotocol Serial Interface with DB-25 Connector
■
Data Networking
■
CSU and DSU
■
Data Routers
■
Software-Selectable Transceiver Supports:
RS232, RS449, EIA530, EIA530-A, V.35, V.36, X.21
■
TUV/Detecon Inc. Certified NET1 and NET2
Compliant (Test Report No. NET2/102201/97)
■
TBR2 Compliant (Test Report No. CTR2/022701/98)
■
Software-Selectable Cable Termination Using
the LTC1344A
■
Complete DTE or DCE Port with LTC1544, LTC1344A
■
Operates from Single 5V Supply
DESCRIPTIO
U
FEATURES
APPLICATIO S
U
TYPICAL APPLICATIO
U
The LTC
®
1543 is a 3-driver/3-receiver multiprotocol
transceiver that operates from a single 5V supply. The
LTC1543 and LTC1544 form the core of a complete software-
selectable DTE or DCE interface port that supports the
RS232, RS449, EIA530, EIA530-A, V.35, V.36 or X.21
protocols. Cable termination may be implemented using the
LTC1344A software-selectable cable termination chip or by
using existing discrete designs.
The LTC1543 runs from a single 5V supply using an internal
charge pump that requires only five space-saving surface
mounted capacitors. The part is available in a 28-lead SSOP
surface mount package.
2
LTC1543
sn1534 1543fas
ABSOLUTE AXI U RATI GS
WWWU
ORDER PART
NUMBER
(Note 1)
Supply Voltage ....................................................... 6.5V
Input Voltage
Transmitters ........................... –0.3V to (V
CC
+ 0.3V)
Receivers............................................... –18V to 18V
Logic Pins .............................. –0.3V to (V
CC
+ 0.3V)
Output Voltage
Transmitters ................. (V
EE
– 0.3V) to (V
DD
+ 0.3V)
Receivers................................ –0.3V to (V
CC
+ 0.3V)
Logic Pins .............................. –0.3V to (V
CC
+ 0.3V)
V
EE
........................................................ –10V to 0.3V
V
DD
....................................................... –0.3V to 10V
Short-Circuit Duration
Transmitter Output ..................................... Indefinite
Receiver Output.......................................... Indefinite
V
EE
.................................................................. 30 sec
Operating Temperature Range
LTC1543C .............................................. 0°C to 70°C
LTC1543I........................................... –40°C to 85°C
Storage Temperature Range ................ –65°C to 150°C
Lead Temperature (Soldering, 10 sec)................. 300°C
LTC1543CG
LTC1543IG
Consult LTC Marketing for parts specified with wider operating
temperature ranges.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
TOP VIEW
28
27
26
25
24
23
22
21
20
19
18
17
16
15
C1
–
C1
+
V
DD
V
CC
D1
D2
D3
R1
R2
R3
M0
M1
M2
DCE/DTE
C2
+
C2
–
V
EE
GND
D1 A
D1 B
D2 A
D2 B
D3/R1 A
D3/R1 B
R2 A
R2 B
R3 A
R3 B
R3
CHARGE PUMP
R1
D2
D1
R2
D3
G PACKAGE
28-LEAD PLASTIC SSOP
T
JMAX
= 150°C, θ
JA
= 90°C/W
The ● denotes specifications which apply over the full operating tempera-
ture range. VCC = 5V (Notes 2, 3)
ELECTRICAL CHARACTERISTICS
PACKAGE/ORDER I FOR ATIO
UU
W
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Supplies
I
CC
V
CC
Supply Current (DCE Mode, RS530, RS530-A, X.21 Modes, No Load 13 mA
All Digital Pins = GND or V
CC
) RS530, RS530-A, X.21 Modes, Full Load ●100 130 mA
V.35 Mode, No Load 20 mA
V.35 Mode, Full Load ●126 170 mA
V.28 Mode, No Load 20 mA
V.28 Mode, Full Load ●40 75 mA
No-Cable Mode ●120 500 µA
P
D
Internal Power Dissipation (DCE Mode) RS530, RS530-A, X.21 Modes, Full Load 230 mW
V.35 Mode, Full Load 600 mW
V.28 Mode, Full Load 140 mW
V
+
Positive Charge Pump Output Voltage Any Mode, No Load ●8.0 9.4 V
V.28 Mode, with Load ●8.0 8.7 V
V.28 Mode, with Load, I
DD
= 10mA 6.5 V
V
–
Negative Charge Pump Output Voltage V.28, V.35 Modes, No Load –9.6 V
V.28 Mode, Full Load ●–8.0 –8.5 V
V.35 Mode, Full Load ●–5.5 –6.7 V
RS530, RS530-A, X.21 Modes, Full Load ●–4.5 –5.7 V
f
OSC
Charge Pump Oscillator Frequency 150 kHz
t
r
Supply Rise Time No-Cable Mode or Power-Up to Turn On 2 ms
Logic Inputs and Outputs
V
IH
Logic Input High Voltage ●2V
V
IL
Logic Input Low Voltage ●0.8 V
3
LTC1543
sn1534 1543fas
The ● denotes specifications which apply over the full operating tempera-
ture range. VCC = 5V (Notes 2, 3)
ELECTRICAL CHARACTERISTICS
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
I
IN
Logic Input Current D1, D2, D3 ●±10 µA
M0, M1, M2, DCE = GND (LTC1543C) ●–100 –50 –30 µA
M0, M1, M2, DCE = GND (LTC1543I) ●–120 –50 –30 µA
M0, M1, M2, DCE = V
CC
●±10 µA
V
OH
Output High Voltage I
O
= –4mA ●3 4.5 V
V
OL
Output Low Voltage I
O
= 4mA ●0.3 0.8 V
I
OSR
Output Short-Circuit Current 0V ≤ V
O
≤ V
CC
●–50 50 mA
I
OZR
Three-State Output Current M0 = M1 = M2 = V
CC
, 0V ≤ V
O
≤ V
CC
±1µA
V.11 Driver
V
ODO
Open Circuit Differential Output Voltage R
L
= 1.95k (Figure 1) ●±5V
V
ODL
Loaded Differential Output Voltage R
L
= 50Ω (Figure 1) 0.5V
ODO
0.67V
ODO
V
R
L
= 50Ω (Figure 1) ●±2V
∆V
OD
Change in Magnitude of Differential R
L
= 50Ω (Figure 1) ●0.2 V
Output Voltage
V
OC
Common Mode Output Voltage R
L
= 50Ω (Figure 1) ●3V
∆V
OC
Change in Magnitude of Common Mode R
L
= 50Ω (Figure 1) ●0.2 V
Output Voltage
I
SS
Short-Circuit Current V
OUT
= GND 150 mA
I
OZ
Output Leakage Current –0.25V ≤ V
O
≤ 0.25V, Power Off or ●±1±100 µA
No-Cable Mode or Driver Disabled
t
r
, t
f
Rise or Fall Time (Figures 2, 6) (LTC1543C) ●21525 ns
(Figures 2, 6) (LTC1543I) ●21535 ns
t
PLH
Input to Output (Figures 2, 6) (LTC1543C) ●20 40 65 ns
(Figures 2, 6) (LTC1543I) ●20 40 75 ns
t
PHL
Input to Output (Figures 2, 6) (LTC1543C) ●20 40 65 ns
(Figures 2, 6) (LTC1543I) ●20 40 75 ns
∆t Input to Output Difference, t
PLH
– t
PHL
(Figures 2, 6) (LTC1543C) ●0312 ns
(Figures 2, 6) (LTC1543I) ●0317 ns
t
SKEW
Output to Output Skew (Figures 2, 6) 3 ns
V.11 Receiver
V
TH
Input Threshold Voltage –7V ≤ V
CM
≤ 7V ●–0.2 0.2 V
∆V
TH
Input Hysteresis –7V ≤ V
CM
≤ 7V ●15 40 mV
I
IN
Input Current (A, B) –10V ≤ V
A,B
≤ 10V ●±0.66 mA
R
IN
Input Impedance –10V ≤ V
A,B
≤ 10V ●15 30 kΩ
t
r
, t
f
Rise or Fall Time (Figures 2, 7) 15 ns
t
PLH
Input to Output (Figures 2, 7) (LTC1543C) ●50 80 ns
(Figures 2, 7) (LTC1543I) ●50 90 ns
t
PHL
Input to Output (Figures 2, 7) (LTC1543C) ●50 80 ns
(Figures 2, 7) (LTC1543I) ●50 90 ns
∆t Input to Output Difference, t
PLH
– t
PHL
(Figures 2, 7) (LTC1543C) ●0416 ns
(Figures 2, 7) (LTC1543I) ●0421 ns
V.35 Driver
V
OD
Differential Output Voltage Open Circuit ●±10.00 V
With Load, –4V ≤ V
CM
≤ 4V (Figure 3) ●±0.44 ±0.55 ±0.66 V
I
OH
Transmitter Output High Current V
A, B
= 0V ●–13 –11 –9.0 mA
I
OL
Transmitter Output Low Current V
A, B
= 0V ●9.0 11 13 mA
4
LTC1543
sn1534 1543fas
Note 1: Absolute Maximum Ratings are those beyond which the safety of a
device may be impaired.
Note 2: All currents into device pins are positive; all currents out of device
are negative. All voltages are referenced to device ground unless otherwise
specified.
Note 3: All typicals are given for V
CC
= 5V, C1 = C2 = C
VCC
= 1µF,
C
VDD
= C
VEE
= 3.3µF tantalum capacitors and T
A
= 25°C.
The ● denotes specifications which apply over the full operating tempera-
ture range. VCC = 5V (Notes 2, 3)
ELECTRICAL CHARACTERISTICS
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
I
OZ
Transmitter Output Leakage Current –0.25V ≤ V
A, B
≤ 0.25V ●±1±100 µA
t
r
, t
f
Rise or Fall Time (Figures 3, 6) 5 ns
t
PLH
Input to Output (Figures 3, 6) (LTC1543C) ●20 35 65 ns
(Figures 3, 6) (LTC1543I) ●20 35 75 ns
t
PHL
Input to Output (Figures 3, 6) (LTC1543C) ●20 35 65 ns
(Figures 3, 6) (LTC1543I) ●20 35 75 ns
∆t Input to Output Difference, t
PLH
– t
PHL
(Figures 3, 6) (LTC1543C) ●0416 ns
(Figures 3, 6) (LTC1543I) ●0421 ns
t
SKEW
Output to Output Skew (Figures 3, 6) 4 ns
V.35 Receiver
V
TH
Differential Receiver Input Threshold Voltage –2V ≤ (V
A
+ V
B
)/2 ≤ 2V (Figure 3) ●–0.2 0.2 V
∆V
TH
Receiver Input Hysteresis –2V ≤ (V
A
+ V
B
)/2 ≤ 2V (Figure 3) ●15 40 mV
I
IN
Receiver Input Current (A, B) –10V ≤ V
A,B
≤ 10V ●±0.66 mA
R
IN
Receiver Input Impedance –10V ≤ V
A,B
≤ 10V ●15 30 kΩ
t
r
, t
f
Rise or Fall Time (Figures 3, 7) 15 ns
t
PLH
Input to Output (Figures 3, 7) (LTC1543C) ●50 80 ns
(Figures 3, 7) (LTC1543I) ●50 90 ns
t
PHL
Input to Output (Figures 3, 7) (LTC1543C) ●50 80 ns
(Figures 3, 7) (LTC1543I) ●50 90 ns
∆t Input to Output Difference, t
PLH
– t
PHL
(Figures 3, 7) (LTC1543C) ●0416 ns
(Figures 3, 7) (LTC1543I) ●0421 ns
V.28 Driver
V
O
Output Voltage Open Circuit ●±10 V
R
L
= 3k (Figure 4) ●±5±8.5 V
I
SS
Short-Circuit Current V
OUT
= GND ●±150 mA
I
OZ
Output Leakage Current –0.25V ≤ V
O
≤ 0.25V, Power Off or ●±1±100 µA
No-Cable Mode or Driver Disabled
SR Slew Rate R
L
= 3k, C
L
= 2500pF (Figures 4, 8) ●430V/µs
t
PLH
Input to Output R
L
= 3k, C
L
= 2500pF (Figures 4, 8) ●1.5 2.5 µs
t
PHL
Input to Output R
L
= 3k, C
L
= 2500pF (Figures 4, 8) ●1.5 3 µs
V.28 Receiver
V
THL
Input Low Threshold Voltage ●1.2 0.8 V
V
TLH
Input High Threshold Voltage ●2 1.2 V
∆V
TH
Receiver Input Hysteresis ●0 0.05 0.3 V
R
IN
Receiver Input Impedance –15V ≤ V
A
≤ 15V ●357 kΩ
t
r
, t
f
Rise or Fall Time (Figures 5, 9) 15 ns
t
PLH
Input to Output (Figures 5, 9) ●60 100 ns
t
PHL
Input to Output (Figures 5, 9) ●160 250 ns
5
LTC1543
sn1534 1543fas
C1
–
␣ (Pin 1): Capacitor C1 Negative Terminal. Connect a
1µF capacitor between C1
+
and C1
–
.
C1
+
(Pin 2): Capacitor C1 Positive Terminal. Connect a
1µF capacitor between C1
+
and C1
–
.
V
DD
(Pin 3): Generated Positive Supply Voltage for
V.28. Connect a 1µF capacitor to ground.
V
CC
(Pin 4): Positive Supply Voltage Input. 4.75V ≤ V
CC
≤ 5.25V. Bypass with a 1µF capacitor to ground.
D1 (Pin 5): TTL Level Driver 1 Input.
D2 (Pin 6): TTL Level Driver 2 Input.
D3 (Pin 7): TTL Level Driver 3 Input.
R1 (Pin 8): CMOS Level Receiver 1 Output.
R2 (Pin 9): CMOS Level Receiver 2 Output.
R3 (Pin 10): CMOS Level Receiver 3 Output.
M0 (Pin 11): TTL Level Mode Select Input 0 with Pull-Up
to V
CC
.
M1 (Pin 12): TTL Level Mode Select Input 1 with Pull-Up
to V
CC
.
M2 (Pin 13): TTL Level Mode Select Input 2 with Pull-Up
to V
CC
.
DCE/DTE (Pin 14): TTL Level Mode Select Input with Pull-
Up to V
CC
.
UU
U
PI FU CTIO S
R3 B (Pin 15): Receiver 3 Noninverting Input with Pull-Up
to V
CC
.
R3 A (Pin 16): Receiver 3 Inverting Input.
R2 B (Pin 17): Receiver 2 Noninverting Input.
R2 A (Pin 18): Receiver 2 Inverting Input.
D3/R1 B (Pin 19): Receiver 1 Noninverting Input and
Driver 3 Noninverting Output.
D3/R1 A (Pin 20): Receiver 1 Inverting Input and Driver 3
Inverting Output.
D2 B (Pin 21): Driver 2 Noninverting Output.
D2 A (Pin 22): Driver 2 Inverting Output.
D1 B (Pin 23): Driver 1 Noninverting Output.
D1 A (Pin 24): Driver 1 Inverting Output.
GND (Pin 25): Ground.
V
EE
(Pin 26): Negative Supply Voltage. Connect a 3.3µF
capacitor to GND.
C2
–
(Pin 27): Capacitor C2 Negative Terminal. Connect a
1µF capacitor between C2
+
and C2
–
.
C2
+
(Pin 28): Capacitor C2 Positive Terminal. Connect a
1µF capacitor between C2
+
and C2
–
.
Figure 1. V.11 Driver Test Circuit Figure 2. V.11 Driver/Receiver AC Test Circuit
A
B
1543 F01
V
OD
V
OC
R
L
50Ω
R
L
50Ω
A
B
A
R
B
1543 F02
R
L
100Ω
C
L
100pF
C
L
100pF 15pF
TEST CIRCUITS
6
LTC1543
sn1534 1543fas
TEST CIRCUITS
A
B
D
A
B
1543 F03
R
V
OD
V
CM
50Ω
125Ω125Ω
50Ω
50Ω
50Ω15pF
Figure 3. V.35 Driver/Receiver Test Circuit
A
D
1543 F04
R
L
C
L
Figure 4. V.10/V.28 Driver Test Circuit Figure 5. V.10/V.28 Receiver Test Circuit
A
D
1543 F04
15pF
R
A
ODE SELECTIO
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LTC1543 MODE NAME M2 M1 M0 DCE/DTE D1 D2 D3 R1 R2 R3
Not Used (Default V.11) 0000V.11 V.11 Z V.11 V.11 V.11
RS530A 0010V.11 V.11 Z V.11 V.11 V.11
RS530 0100V.11 V.11 Z V.11 V.11 V.11
X.21 0110V.11 V.11 Z V.11 V.11 V.11
V.35 1000V.35 V.35 Z V.35 V.35 V.35
RS449/V.36 1010V.11 V.11 Z V.11 V.11 V.11
V.28/RS232 1100V.28 V.28 Z V.28 V.28 V.28
No Cable 1110ZZZZZZ
Not Used (Default V.11) 0001V.11 V.11 V.11 Z V.11 V.11
RS530A 0011V.11 V.11 V.11 Z V.11 V.11
RS530 0101V.11 V.11 V.11 Z V.11 V.11
X.21 0111V.11 V.11 V.11 Z V.11 V.11
V.35 1001V.35 V.35 V.35 Z V.35 V.35
RS449/V.36 1011V.11 V.11 V.11 Z V.11 V.11
V.28/RS232 1101V.28 V.28 V.28 Z V.28 V.28
No Cable 1111ZZZZZZ
7
LTC1543
sn1534 1543fas
SWITCHI G TI E WAVEFOR S
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Figure 7. V.11, V.35 Receiver Propagation Delays
Figure 8. V.10, V.28 Driver Propagation Delays
Figure 9. V.10, V.28 Receiver Propagation Delays
V
OD2
–V
OD2
0V
1.5V
0V
1.5V
t
PLH
V
OH
V
OL
B – A
R
t
PHL
1543 F07
f = 1MHz : t
r
≤ 10ns : t
f
≤ 10ns INPUT
OUTPUT
3V
0V
1.5V
0V
–3V
3V
1.5V
0V
3V
–3V
t
PHL
t
f
V
O
–V
O
D
A
t
PLH
t
r
1543 F08
V
IH
V
IL
1.3V
0.8V
1.7V
2.4V
t
PHL
V
OH
V
OL
A
R
t
PLH
1543 F09
Figure 6. V.11, V.35 Driver Propagation Delays
5V 1.5V 1.5V
50% 10%
90%
t
PLH
t
r
0V
V
O
V
O
–V
O
D
B – A
A
B
t
PHL
t
SKEW
t
SKEW
1543 F06
1/2 V
O
f = 1MHz : t
r
≤ 10ns : t
f
≤ 10ns
V
DIFF
= V(A) – V(B) 50% 10%
90%
t
f
8
LTC1543
sn1534 1543fas
APPLICATIO S I FOR ATIO
WUUU
Overview
The LTC1543/LTC1544 form the core of a complete soft-
ware-selectable DTE or DCE interface port that supports
the RS232, RS449, EIA530, EIA530-A, V.35, V.36 or X.21
protocols. Cable termination may be implemented using
the LTC1344A software-selectable cable termination chip
or by using existing discrete designs.
A complete DCE-to-DTE interface operating in EIA530
mode is shown in Figure 10. The LTC1543 of each port is
used to generate the clock and data signals. The LTC1544
is used to generate the control signals along with LL (Local
Loopback).The LTC1344A cable termination chip is used
only for the clock and data signals because they must
support V.35 cable termination. The control signals do not
need any external resistors.
Mode Selection
The interface protocol is selected using the mode select
pins M0, M1 and M2 (see the Mode Selection table).
For example, if the port is configured as a V.35 interface,
the mode selection pins should be M2 = 1, M1 = 0, M0 = 0.
For the control signals, the drivers and receivers will
operate in V.28 (RS232) electrical mode. For the clock and
data signals, the drivers and receivers will operate in V.35
electrical mode. The DCE/DTE pin will configure the port
for DCE mode when high, and DTE when low.
The interface protocol may be selected simply by plugging
the appropriate interface cable into the connector. The
mode pins are routed to the connector and are left uncon-
nected (1) or wired to ground (0) in the cable as shown in
Figure 11.
The internal pull-up current sources will ensure a binary 1
when a pin is left unconnected and that the LTC1543/
LTC1544 and the LTC1344A enter the no-cable mode
when the cable is removed. In the no-cable mode the
LTC1543/LTC1544 supply current drops to less than
200µA and all LTC1543/LTC1544 driver outputs and
LTC1344A resistive terminations are forced into a high
impedance state.
The mode selection may also be accomplished by using
jumpers to connect the mode pins to ground or V
CC
.
Cable Termination
Traditional implementations have included switching
resistors with expensive relays, or requiring the user to
change termination modules every time the interface
standard has changed. Custom cables have been used
with the termination in the cable head or separate termina-
tions are built on the board and a custom cable routes the
signals to the appropriate termination. Switching the
terminations with FETs is difficult because the FETs must
remain off even though the signal voltage is beyond the
supply voltage for the FET drivers or the power is off.
Using the LTC1344A along with the LTC1543/LTC1544
solves the cable termination switching problem. Via soft-
ware control, the LTC1344A provides termination for the
V.10 (RS423), V.11 (RS422), V.28 (RS232) and V.35
electrical protocols.
V.10 (RS423) Interface
A typical V.10 unbalanced interface is shown in Figure 12.
A V.10 single-ended generator output A with ground C is
connected to a differential receiver with inputs A' con-
nected to A, and input C' connected to the signal return
ground C. Usually, no cable termination is required for
V.10 interfaces, but the receiver inputs must be compliant
with the impedance curve shown in Figure 13.
The V.10 receiver configuration in the LTC1544 is shown
in Figure 14. In V.10 mode switch S3 inside the LTC1544
is turned off.The noninverting input is disconnected inside
the LTC1544 receiver and connected to ground. The cable
termination is then the 30k input impedance to ground of
the LTC1544 V.10 receiver.
9
LTC1543
sn1534 1543fas
Figure 10. Complete Multiprotocol Interface in EIA530 Mode
APPLICATIO S I FOR ATIO
WUUU
LTC1543
DCEDTE
LTC1543
LTC1344A LTC1344A
1543 F10
D3
R1 103Ω
103Ω
103Ω
R3
LTC1544
D3
D4 R4
D2
R1
R4
R2
R3
LL
TXC
RXC
RXD
TXD
SCTE
TXC
RXC
RXD
SERIAL
CONTROLLER
D2 103Ω
SCTE R2
D1 103Ω
TXD R3
R1
D2
D1
LTC1544
D3
R2
R1
D1 R3
D2
D1
D4
TXD
SCTE
TXC
RXC
RXD
RTS
DTR
DCD
DSR
CTS
LL
RTS
DTR
DCD
DSR
CTS
RTS
DTR
DCD
DSR
CTS
LL
SERIAL
CONTROLLER
R2
D3
10
LTC1543
sn1534 1543fas
APPLICATIO S I FOR ATIO
WUUU
Figure 12. Typical V.10 Interface
NC
NC
CABLE
1543 F11
11
12
13
14
LTC1543
LTC1544
CONNECTOR
14
13
12
11
22
21
M2 M1
LTC1344A
LATCH
M0 (DATA)
23 24 1
(DATA)
M0
M1
M2
DCE/DTE
DCE/DTE
M2
M1
M0
(DATA)
DCE/
DTE
Figure 11. Single Port DCE V.35 Mode Selection in the Cable
AA
'
CC
'
GENERATOR
BALANCED
INTERCONNECTING
CABLE LOAD
CABLE
TERMINATION RECEIVER
1543 F12
11
LTC1543
sn1534 1543fas
APPLICATIO S I FOR ATIO
WUUU
Figure 13. V.10 Receiver Input Impedance
V.11 (RS422) Interface
A typical V.11 balanced interface is shown in Figure 15. A
V.11 differential generator with outputs A and B with
ground C is connected to a differential receiver with
ground C', inputs A' connected to A, B' connected to B. The
V.11 interface has a differential termination at the receiver
end that has a minimum value of 100Ω. The termination
resistor is optional in the V.11 specification, but for the
high speed clock and data lines, the termination is required
to prevent reflections from corrupting the data. The
receiver inputs must also be compliant with the imped-
ance curve shown in Figure 13.
In V.11 mode, all switches are off except S1 inside the
LTC1344A which connects a 103Ω differential termina-
tion impedance to the cable as shown in Figure 16.
Figure 16. V.11 Receiver Configuration
Figure 15. Typical V.11 Interface
Figure 14. V.10 Receiver Configuration
R3
124Ω
R5
20k
LTC1344A
LTC1543
LTC1544
RECEIVER
1543 F16
A
B
A
'
B
'
C
'
R1
51.5ΩR8
6k
S2 S3
R2
51.5Ω
R6
10k
R7
10k
GND
R4
20k
S1
AA'
B
C
B'
C'
GENERATOR
BALANCED
INTERCONNECTING
CABLE LOAD
CABLE
TERMINATION RECEIVER
100Ω
MIN
1543 F15
R5
20k
LTC1544
RECEIVER
1543 F14
A
B
A'
B'
C'
R8
6k
S3
R6
10k
R7
10k
GND
R4
20k
I
Z
V
Z
–10V
–3.25mA
3.25mA
–3V
3V 10V
1543 F13
12
LTC1543
sn1534 1543fas
APPLICATIO S I FOR ATIO
WUUU
V.28 (RS232) Interface
A typical V.28 unbalanced interface is shown in Figure 17.
A V.28 single-ended generator output A with ground C is
connected to a single-ended receiver with input A' con-
nected to A, ground C' connected via the signal return
ground C.
In V.28 mode all switches are off except S3 inside the
LTC1543/LTC1544 which connects a 6k (R8) impedance
to ground in parallel with 20k (R5) plus 10k (R6) for a
combined impedance of 5k as shown in Figure 18. The
noninverting input is disconnected inside the LTC1543/
LTC1544 receiver and connected to a TTL level reference
voltage for a 1.4V receiver trip point.
Figure 17. Typical V.28 Interface
AA
'
CC
'
GENERATOR
BALANCED
INTERCONNECTING
CABLE LOAD
CABLE
TERMINATION RECEIVER
1543 F17
Figure 18. V.28 Receiver Configuration
V.35 Interface
A typical V.35 balanced interface is shown in Figure 19. A
V.35 differential generator with outputs A and B with
ground C is connected to a differential receiver with
ground C', inputs A' connected to A, B' connected to B. The
V.35 interface requires a T or delta network termination at
the receiver end and the generator end. The receiver
differential impedance measured at the connector must be
100Ω␣±10Ω, and the impedance between shorted termi-
nals (A' and B') and ground C' must be 150Ω ±15Ω.
In V.35 mode, both switches S1 and S2 inside the LTC1344A
are on, connecting the T network impedance as shown in
Figure 20. The switch in the LTC1543 is off. The 30k input
AA
'
B
C
B
'
C
'
GENERATOR
BALANCED
INTERCONNECTING
CABLE LOAD
CABLE
TERMINATION RECEIVER
1543 F19
50Ω125Ω
50Ω
50Ω
125Ω
50Ω
Figure 20. V.35 Receiver Configuration
Figure 19. Typical V.35 Interface
R3
124Ω
R5
20k
LTC1344A
LTC1543
LTC1544
RECEIVER
1543 F18
A
B
A
'
B
'
C
'
R1
51.5ΩR8
6k
S2
S3
R2
51.5Ω
R6
10k
R7
10k
GND
R4
20k
S1
R3
124Ω
R5
20k
LTC1344A
LTC1543
RECEIVER
1543 F20
A
B
A
'
B
'
C
'
R1
51.5ΩR8
6k
S2
S3
R2
51.5Ω
R6
10k
R7
10k
GND
R4
20k
S1
13
LTC1543
sn1534 1543fas
APPLICATIO S I FOR ATIO
WUUU
No-Cable Mode
The no-cable mode (M0 = M1 = M2 = 1) is intended for the
case when the cable is disconnected from the connector.
The charge pump, bias circuitry, drivers and receivers are
turned off, the driver outputs are forced into a high
impedance state, and the supply current drops to less than
200µA.
Charge Pump
The LTC1543 uses an internal capacitive charge pump to
generate V
DD
and V
EE
as shown in Figure 22. A voltage
doubler generates about 8V on V
DD
and a voltage inverter
generates about –7.5V for V
EE
. Four 1µF surface mounted
tantalum or ceramic capacitors are required for C1, C2, C3
and C4. The V
EE
capacitor C5 should be a minimum of
3.3µF. All capacitors are 16V and should be placed as close
as possible to the LTC1543 to reduce EMI.
Receiver Fail-Safe
All LTC1543/LTC1544 receivers feature fail-safe opera-
tion in all modes. If the receiver inputs are left floating or
shorted together by a termination resistor, the receiver
output will always be forced to a logic high.
impedance of the receiver is placed in parallel with the T
network termination, but does not affect the overall input
impedance significantly.
The generator differential impedance must be 50Ω to
150Ω and the impedance between shorted terminals (A
and B) and ground C must be 150Ω ±15Ω. For the
generator termination, switches S1 and S2 are both on and
the top side of the center resistor is brought out to a pin so
it can be bypassed with an external capacitor to reduce
common mode noise as shown in Figure 21.
Any mismatch in the driver rise and fall times or skew in
the driver propagation delays will force current through
the center termination resistor to ground, causing a high
frequency common mode spike on the A and B terminals.
The common mode spike can cause EMI problems that are
reduced by capacitor C1 which shunts much of the com-
mon mode energy to ground rather than down the cable.
V.35 DRIVER
A
B
C
51.5Ω
S2
ON
S1
ON
1543 F21
51.5Ω
LTC1344A
124Ω
C1
100pF
Figure 21. V.35 Driver Using the LTC1344A
28
27
26
25
1543 F22
3
2
1
4
C3
1µF
C4
1µF
5V
C1
1µF
C2
1µF
C5
3.3µF
LTC1543
V
DD
C1
+
C1
–
V
CC
C2
+
C2
–
V
EE
GND
+
Figure 22. Charge Pump
14
LTC1543
sn1534 1543fas
DTE vs DCE Operation
The DCE/DTE pin acts as an enable for Driver 3/Receiver
1 in the LTC1543, and Driver 3/Receiver 1 and Driver 4/
Receiver 4 in the LTC1544. The INVERT pin in the LTC1544
allows the Driver 4/Receiver 4 enable to be high or low true
polarity.
The LTC1543/LTC1544 can be configured for either DTE
or DCE operation in one of two ways: a dedicated DTE or
DCE port with a connector of appropriate gender or a port
with one connector that can be configured for DTE or DCE
operation by rerouting the signals to the LTC1543/LTC1544
using a dedicated DTE cable or dedicated DCE cable.
A dedicated DTE port using a DB-25 male connector is
shown in Figure 23. The interface mode is selected by logic
outputs from the controller or from jumpers to either V
CC
or GND on the mode select pins. A dedicated DCE port
using a DB-25 female connector is shown in Figure 24.
A port with one DB-25 connector, but can be configured
for either DTE or DCE operation is shown in Figure 25. The
configuration requires separate cables for proper signal
routing in DTE or DCE operation. For example, in DTE
mode, the TXD signal is routed to Pins 2 and 14 via Driver
1 in the LTC1543. In DCE mode, Driver 1 now routes the
RXD signal to Pins 2 and 14.
Multiprotocol Interface with RL, LL, TM and a DB-25
Connector
If the RL, LL and TM signals are implemented, there are not
enough drivers and receivers available in the LTC1543/
LTC1544. In Figure 26, the required control signals are
handled by the LTC1544 but the clock/data signals use the
APPLICATIO S I FOR ATIO
WUUU
LTC1343. The LTC1343 has an additional single-ended
driver/receiver pair that can handle two more optional
control signals such as TM and LL.
Cable-Selectable Multiprotocol Interface
A cable-selectable multiprotocol DTE/DCE interface is
shown in Figure 27. The select lines M0, M1 and DCE/DTE
are brought out to the connector. The mode is selected by
the cable by wiring M0 (connector Pin 18) and M1 (con-
nector Pin 21) and DCE/DTE (connector Pin 25) to ground
(connector Pin 7) or letting them float. If M0, M1 or DCE/
DTE is floating, internal pull-up current sources will pull
the signals to V
CC
. The select bit M2 is hard wired to V
CC
.
When the cable is pulled out, the interface will go into the
no-cable mode.
Compliance Testing
A European standard EN 45001 test report is available for
the LTC1543/LTC1544/LTC1344A chipset. A copy of the
test report is available from LTC or TUV Telecom Services
Inc. (formerly Detecon Inc.)
The title of the report is:
Test Report No. NET2/102201/97.
The address of TUV Telecom Services Inc. is:
TUV Telecom Services Inc.
Type Approval Division
1775 Old Highway 8, Ste 107
St. Paul, MN 55112 USA
Tel. +1 (612) 639-0775
Fax. +1 (612) 639-0873
15
LTC1543
sn1534 1543fas
TYPICAL APPLICATIO S
U
Figure 23. Controller-Selectable Multiprotocol DTE Port with DB-25 Connector
D2
D1
LTC1544
RTS
DTR
DSR
DCD
CTS
D3
R2
R1
R4
R3
D2
LTC1543
LL
TXD
SCTE
TXC
RXC
RXD
M0
M1
M2
DCE/DTE
V
CC
V
DD
V
CC
V
EE
GND
2
14
24
11
15
12
17
9
3
1
4
19
20
8
23
10
6
22
5
13
18
7
16
1543 F23
D3
R2
R1
R3
D1
C2
1µF
C1
1µF
C5
1µF
C3
1µF
C4
3.3µF
TXD A (103)
TXD B
SCTE A (113)
SCTE B
RXC A (115)
RXC B
RXD A (104)
RXD B
RTS A (105)
RTS B
DTR A (108)
DTR B
CTS A (106)
CTS B
LL A (141)
SG
SHIELD
DB-25 MALE
CONNECTOR
TXC A (114)
TXC B
DCD A (109)
DCD B
DSR A (107)
DSR B
D4
16109764
3 8 11 12 13
5
2
15 18 17 19 20 22
LTC1344A
C6
100pF C7
100pF C8
100pF
V
CC
V
CC
5V
23 24
14
1
DCE/DTE
M2
M1
M0
CHARGE
PUMP
+
28
3
1
2
4
5
6
7
8
9
10
11
12
13
14
1
2
3
4
5
6
7
8
10
9
INVERT 15
16
17
18
19
20
21
22
23
24
25
NC
27
26
25
24
23
22
21
20
19
18
17
16
15
26
27
28
V
EE
C12
1µF
C13
1µF
C11
1µF
C10
1µFC9
1µF
M0
M1
M2
DCE/DTE
M2
M1
M0
11
12
13
14
21
LATCH
16
LTC1543
sn1534 1543fas
TYPICAL APPLICATIO S
U
Figure 24. Controller-Selectable DCE Port with DB-25 Connector
D2
D1
LTC1544
CTS
DSR
DTR
DCD
RTS
D3
R2
R1
R4
R3
D2
LTC1543
LL
RXD
RXC
TXC
SCTE
TXD
M0
M1
M2
DCE/DTE
V
CC
V
DD
V
CC
V
EE
GND
3
16
17
9
15
12
24
11
2
1
5
13
6
8
22
10
20
23
4
19
18
7
14
1543 F24
D3
R2
R1
R3
D1
C2
1µF
C1
1µF
C5
1µF
C3
1µF
C4
3.3µF
RXD A (104)
RXD B
RXC A (115)
RXC B
SCTE A (113)
SCTE B
TXD A (103)
TXD B
CTS A (106)
CTS B
DSR A (107)
DSR B
RTS A (105)
RTS B
LL A (141)
SGND (102)
SHIELD (101)
DB-25 FEMALE
CONNECTOR
TXC A (114)
TXC B
DCD A (109)
DCD B
DTR A (108)
DTR B
D4
16109764
3 8 11 12 13
5
2
15 18 17 19 20 22
LTC1344A
C6
100pF C7
100pF C8
100pF
V
CC
V
CC
V
CC
5V
23 24
14
1
DCE/DTE
M2
M1
M0
CHARGE
PUMP
+
28
3
1
2
4
5
6
7
8
9
10
NC
11
12
13
14
1
2
3
4
5
6
7
8
10
9
INVERT 15
16
17
18
19
20
21
22
23
24
25
NC
NC
27
26
25
24
23
22
21
20
19
18
17
16
15
26
27
28
V
EE
M0
M1
M2
DCE/DTE
M2
M1
M0
11
12
13
14
LATCH 21
C12
1µF
C13
1µF
C11
1µF
C10
1µFC9
1µF
17
LTC1543
sn1534 1543fas
TYPICAL APPLICATIO S
U
Figure 25. Controller-Selectable Multiprotocol DTE/DCE Port with DB-25 Connector
D2
D1
LTC1544
D3
R2
R1
R4
R3
D2
LTC1543
DTE_TXD/DCE_RXD
DTE_TXC/DCE_TXC
DTE_RXC/DCE_SCTE
DTE_RXD/DCE_TXD
DTE_RTS/DCE_CTS
DTE_DTR/DCE_DSR
DTE_DCD/DCE_DCD
DTE_DSR/DCE_DTR
DTE_CTS/DCE_RTS
DTE_LL/DCE_LL
DTE_SCTE/DCE_RXC
M0
M1
M2
DCE/DTE
VCC
VDD
VCC
VEE
GND
S
S
2
14
24
11
15
12
17
9
3
1
4
19
20
8
23
10
6
22
5
13
18
7
16
1543 F25
D3
R2
R1
R3
D1
C2
1µF
C1
1µF
C5
1µF
C3
1µF
C4
3.3µF
TXD A
TXD B
SCTE A
SCTE B
RXD A
RXD B
RXC A
RXC B
RXC A
RXC B
RXD A
RXD B
RTS A
RTS B
DTR A
DTR B
CTS A
CTS B
DSR A
DSR B
CTS A
CTS B
LL A
SG
SHIELD
DB-25
CONNECTOR
TXC A
TXC B
SCTE A
SCTE B
TXD A
TXD B
TXC A
TXC B
DCD A
DCD B
DSR A
DSR B
RTS A
RTS B
LL A
DCD A
DCD B
DTR A
DTR B
D4
16109764
3 8 11 12 13
5
2
15 18 17 19 20 22
LTC1344A
C6
100pF C7
100pF C8
100pF
VCC
VCC
5V
23 24
14
1
DCE/DTE
M2
M1
M0
CHARGE
PUMP
+
28
3
1
2
4
5
6
7
8
9
10
11
12
13
14
1
2
3
4
5
6
7
8
10
9
INVERT 15
16
17
18
19
20
21
22
23
24
25
NC
27
26
25
24
23
22
21
20
19
18
17
16
15
26
27
28
VEE
M0
M1
M2
DCE/DTE
DCE/DTE
M2
M1
M0
11
12
13
14
DTE DCE
LATCH 21
C12
1µF
C13
1µF
C11
1µF
C10
1µFC9
1µF
18
LTC1543
sn1534 1543fas
TYPICAL APPLICATIO S
U
Figure 26. Controller-Selectable Multiprotocol DTE/DCE Port with RL, LL, TM and DB-25 Connector
D2
D1
LTC1544
D3
R2
R1
R4
R3
D2
LTC1343
DTE_LL/DCE_TM
DTE_TXC/DCE_TXC
DTE_RXC/DCE_SCTE
DTE_RXD/DCE_TXD
DTE_TM/DCE_LL
DTE_RTS/DCE_CTS
DTE_DTR/DCE_DSR
DTE_DCD/DCE_DCD
DTE_DSR/DCE_DTR
DTE_CTS/DCE_RTS
DTE_RL/DCE_RL
DTE_TXD/DCE_RXD
DTE_SCTE/DCE_RXC
CTRL
LATCH
INVERT
423SET
GND
DCE
M2
M1
M0
EC
VCC
VDD
VCC
VEE
GND
2
18
14
24
11
15
12
17
9
3
1
4
19
20
8
23
10
6
22
5
13
21
7
16
25
1543 F26
D3
D4
R2
R3
R4
D1
C2
1µF
C1
1µF
C5
1µF
C3
1µF
C4
3.3µF
LL A
TXD A
TXD B
SCTE A
SCTE B
TM A
RXD A
RXD B
RXC A
RXC B
RXC A
RXC B
RXD A
RXD B
RTS A
RTS B
DTR A
DTR B
CTS A
CTS B
DSR A
DSR B
CTS A
CTS B
RL A
SG
SHIELD
DB-25
CONNECTOR
TXC A
TXC B
SCTE A
SCTE B
TXD A
TXD B
TXC A
TXC B
DCD A
DCD B
DSR A
DSR B
RTS A
RTS B
RL A
DCD A
DCD B
DTR A
DTR B
D4
16109764
3 8 11 12 13
5
2
15 18 17 19 20 22
LTC1344A
C6
100pF C7
100pF C8
100pF
VCC
VCC
5V
23 24
14
1
DCE/DTE
M2
M1
M0
+
44
3
1
2
4
5
8
6
7
9
10
12
13
14
15
16
20
22
11
1
R1
100k
2
3
4
5
6
7
8
10
9
INVERT 15
16
17
18
19
20
21
22
23
24
25
NC
43
42
41
39
38
37
36
35
34
33
32
31
30
29
28
27
26
21
19
18
17
24
26
27
28
VEE
M0
M1
M2
DCE/DTE
DCE/DTE
M2
M1
M0
11
12
13
14
DTE DCE
R1
25
40
23
VCC
LB
LB
TM A LL A
LATCH 21
C12
1µF
C13
1µF
C11
1µF
C10
1µFC9
1µF
CHARGE
PUMP
19
LTC1543
sn1534 1543fas
TYPICAL APPLICATIO S
U
Figure 27. Cable-Selectable Multiprotocol DTE/DCE Port with DB-25 Connector
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
D2
D1
LTC1544
D3
R2
R1
R4
R3
D2
LTC1543
DTE_TXD/DCE_RXD
DTE_TXC/DCE_TXC
DTE_RXC/DCE_SCTE
DTE_RXD/DCE_TXD
DTE_RTS/DCE_CTS
DTE_DTR/DCE_DSR
DTE_DCD/DCE_DCD
DTE_DSR/DCE_DTR
DTE_CTS/DCE_RTS
DTE_SCTE/DCE_RXC
M0
M1
M2
DCE/DTE
V
CC
V
DD
NC
NC
V
CC
V
EE
GND
2
V
CC
14
24
11
15
12
17
9
3
1
25
21
18
4
19
20
8
23
10
6
22
5
13
7
16
1543/44 F27
D3
R2
R1
R3
D1
C2
1µF
C1
1µF
C5
1µF
C3
1µF
C4
3.3µF
TXD A
TXD B
SCTE A
SCTE B
RXD A
RXD B
RXC A
RXC B
RXC A
RXC B
RXD A
RXD B
RTS A
RTS B
DTR A
DTR B
CTS A
CTS B
DSR A
DSR B
CTS A
CTS B
SG
SHIELD
DCE/DTE
M1
M0
DB-25
CONNECTOR
TXC A
TXC B
SCTE A
SCTE B
TXD A
TXD B
TXC A
TXC B
DCD A
DCD B
DSR A
DSR B
RTS A
RTS B
DCD A
DCD B
DTR A
DTR B
D4
16109764
3 8 11 12 13
5
2
15 18 17 19 20 22
LTC1344A
C6
100pF C7
100pF C8
100pF
V
CC
V
CC
5V
23 24
14
1
DCE/DTE
M2
M1
M0
+
28
3
1
2
4
5
6
7
8
9
10
11
12
13
14
1
2
3
4
5
6
7
8
9
10
INVERT 15
17
16
18
19
20
21
22
23
24
25
NC
27
26
25
24
23
22
21
20
19
18
17
16
15
26
27
28
V
EE
M0
M1
M2
DCE/DTE
11
12
13
14
DTE DCE
MODE PIN 18 PIN 21
V.35 PIN 7 PIN 7
RS449, V.36 NC PIN 7
RS232 PIN 7 NC
CABLE WIRING FOR MODE SELECTION
MODE PIN 25
DTE PIN 7
DCE NC
CABLE WIRING FOR
DTE/DCE SELECTION
LATCH 21
C12
1µF
C13
1µF
C11
1µF
C10
1µFC9
1µF
CHARGE
PUMP
20
LTC1543
sn1534 1543fas
LW/TP 1002 1K REV A • PRINTED IN USA
LINEAR TECHNOLOGY CORPORATION 1998
Dimensions in inches (millimeters) unless otherwise noted.
U
PACKAGE DESCRIPTIO
G Package
28-Lead Plastic SSOP (0.209)
(LTC DWG # 05-08-1640)
PART NUMBER DESCRIPTION COMMENTS
LTC1321 Dual RS232/RS485 Transceiver Two RS232 Driver/Receiver Pairs or Two RS485 Driver/Receiver Pairs
LTC1334 Single 5V RS232/RS485 Multiprotocol Transceiver Two RS232 Driver/Receiver or Four RS232 Driver/Receiver Pairs
LTC1343 Software-Selectable Multiprotocol Transceiver 4-Driver/4-Receiver for Data and Clock Signals
LTC1344A Software-Selectable Cable Terminator Perfect for Terminating the LTC1543
LTC1345 Single Supply V.35 Transceiver 3-Driver/3-Receiver for Data and Clock Signals
LTC1346A Dual Supply V.35 Transceiver 3-Driver/3-Receiver for Data and Clock Signals
LTC1544 Software-Selectable Multiprotocol Transceiver 4-Driver/4-Receiver for Control Signals Including LL
LTC1545 Software-Selectable Multiprotocol Transceiver 5-Driver/5-Receiver for Control Signals Including LL, RL and TM
LTC1546 Software-Selectable Multiprotocol Transceiver with 3-Driver/3-Receiver for Data and Clock Signals
Termination
LTC2844 3.3V Multiprotocol Transceiver 4-Driver/4-Receiver for Control Signals Including LL
LTC2845 3.3V Multiprotocol Transceiver 5-Driver/5-Receiver for Control Signals Including LL, RL and TM
LTC2846 3.3V Multiprotocol Transceiver with Termination 3-Driver/3-Receiver for Data and Clock Signals
G28 SSOP 0694
0.005 – 0.009
(0.13 – 0.22)
0° – 8°
0.022 – 0.037
(0.55 – 0.95)
0.205 – 0.212**
(5.20 – 5.38)
0.301 – 0.311
(7.65 – 7.90)
12345678 9 10 11 12 1413
0.397 – 0.407*
(10.07 – 10.33)
2526 22 21 20 19 18 17 16 1523242728
0.068 – 0.078
(1.73 – 1.99)
0.002 – 0.008
(0.05 – 0.21)
0.0256
(0.65)
BSC 0.010 – 0.015
(0.25 – 0.38)
DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
*
**
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900
●
FAX: (408) 434-0507
●
www.linear.com
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