Product Specification
Single-Stage PFC Controller SG6980D
© System General Corp. - 1 - www.sg.com.tw • www.fairchildsemi.com
Version 1.0.1 (IAO33.0071.B0 September 17, 2007
FEATURES OVERVIEW
Innovative switching-charge multiplier divider
Multi-vector control for improved PFC output
transient response
1:2 synchronous switching with SYNC
Average current mode control
Remote on/off control
Power-on sequence control
Programmable PFC output-voltage control
Cycle-by-cycle current limiting
Over-voltage and under-voltage protections
Brownout and open-loop protections
Low start-up and operating current
APPLICATIONS
Active-PFC switching power supplies
TV and home appliances
Computer and telecom
DESCRIPTION
The highly integrated SG6980D is designed for power
supplies with boost power-factor-correction (PFC).
It requires very few external components to achieve
desirable operation and includes versatile protection /
compensation. It is available in 16-pin DIP and SOP
packages. The innovative switching-charge
multiplier-divider enhances the PFC circuit’s noise
immunity. The proprietary multi-vector control scheme
provides a fast transient response in a low-bandwidth PFC
loop, in which the overshoot and undershoot of the PFC
voltage are clamped. If the feedback loop is broken,
SG6980D shuts off to prevent extra-high voltage on output.
The PFC gate driver can be synchronized with external
SYNC signal and the switching noise can be reduced.
During start-up, the RDY (ready) is pulled low until the
PFC output voltage reaches to the setting level. This signal
can be used to control the second forward stage for proper
power-on sequence. In addition, SG6980D provides
complete protection functions, such as brownout protection
and RI open/short.
TYPICAL APPLICATION
SG6980
Product Specification
Single-Stage PFC Controller SG6980D
© System General Corp. - 2 - www.sg.com.tw • www.fairchildsemi.com
Version 1.0.1 (IAO33.0071.B0 September 17, 2007
MARKING DIAGRAMS PIN CONFIGURATION
ORDERING INFORMATION
Part Number Pb-Free Package
SG6980DDZ 16-Pin DIP
SG6980DSZ (Preliminary) 16-Pin SOP
SG6980DTP
XXXXXXXYWWV
T: D = DIP S=SOP
P: Z = Lead Free
XXXXXXXX: Wafer Lot
Y: Year; WW: Week
V: Assembly Location RDY
VRMS
OTP
RI
IEA
IPFC
IPK
IMP
SYNC ON/OFF
GND
OUT
VDD
FB
VEA
IAC
Product Specification
Single-Stage PFC Controller SG6980D
© System General Corp. - 3 - www.sg.com.tw • www.fairchildsemi.com
Version 1.0.1 (IAO33.0071.B0 September 17, 2007
PIN DESCRIPTIONS
Name Pin Type Function
VRMS 1 Line-Voltage Detection
Line voltage detection. The pin is used for PFC multiplier and brownout protection. For
brownout protection, the controller will be disabled with a 195ms delay time when the VRMS
voltage drops below 0.8V. There is a 200mV hysteresis for brownout protection.
OTP 2 Over-Temperature
Protection
This pin supplies an over temperature protection signal. A constant current is output from
this pin. If RI is equal to 24k, then the magnitude of the constant current will be 50uA. An
external NTC thermistor must be connected from this pin to ground. The impedance of the
NTC thermistor decreases whenever the temperature increases. Once the voltage of the
OTP pin drops below 1.2V, the SG6980D will be off, and will auto restart when the voltage is
back to 1.4V.
RI 3 Oscillator Setting
The resistance of a resistor connected between RI and ground determines the switching
frequency. A resistor with a resistance between 15k and 40K is recommended. The
switching frequency is equal to [1560 / RI]kHz, where RI is k:. For example, if RI is equal to
24k:, the switching frequency is 65kHz.
IEA 4 Current Amplifier Output
This is the output of the PFC current amplifier. The signal from this pin is compared with an
internal sawtooth and determines the pulse width for PFC gate drive.
IPFC 5 Inverting Input for PFC
Current Amplifier
The inverting input of the PFC current amplifier. Proper external compensation circuits
result in excellent input power factor via average-current-mode control.
IMP 6
Non-inverting Input for
PFC Current Amplifier
and Output of Multiplier
The non-inverting input of the PFC current amplifier and the output of multiplier. Proper
external compensation circuits results in excellent input power factor via average current
mode control.
IPK 7 Peak Current Limit The peak current setting for PFC.
SYNC 8 Synchronous Signal This pin receives the external switching signal. The PFC switching can be synchronized by
SYNC with 1:2 ratio.
ON/OFF 9 Remote On/Off Active high. The SG6980D is disabled whenever the voltage at this pin is lower than 1V or
the pin is open. When SG6980D is disabled by ON/OFF, the IDD current is lower than 35µA.
GND 10 Ground The ground.
OUT 11 Gate Drive The totem pole output drive for the PFC MOSFET. This pin is internally clamped under 18V
to protect the MOSFET.
VDD 12 Supply The power supply pin. The threshold voltages for start-up and turn-off are 12.5V and 10V,
respectively. The operating current is lower than 5mA.
RDY 13 Ready Signal Output
This pin outputs a ready signal to control the power on sequence. Once the SG6980D is
turned on and the FB (PFC feedback input) voltage is higher than 2.7V, this pin locks to the
high impedance. Disable the SG6980D resets this pin low.
FB 14 Feedback Input The feedback input for PFC voltage loop. The inverting input of PFC error amp. This pin is
connected to the PFC output through a divider network.
VEA 15 Error Amplifier Output
The error amplifier output for PFC voltage feedback loop. A compensation network (usually
a capacitor) is connected between this pin and ground. A large capacitor value results in a
narrow bandwidth and improves the power factor.
IAC 16 Input AC Current This input is used to provide current reference for the multiplier. The suggested maximum
IAC is 350µA.
Product Specification
Single-Stage PFC Controller SG6980D
© System General Corp. - 4 - www.sg.com.tw • www.fairchildsemi.com
Version 1.0.1 (IAO33.0071.B0 September 17, 2007
BLOCK DIAGRAM
Product Specification
Single-Stage PFC Controller SG6980D
© System General Corp. - 5 - www.sg.com.tw • www.fairchildsemi.com
Version 1.0.1 (IAO33.0071.B0 September 17, 2007
ABSOLUTE MAXIMUM RATING
Symbol Parameter Value Unit
VVDD DC Supply Voltage* 25 V
IAC Input AC Current 2 mA
VHigh OUT, SYNC, ON/OFF, RDY -0.3 to 25V V
VLow Others -0.3 to 7V V
DIP 0.8
PD
Power Dissipation
SOP 0.4
W
TJ Operating Junction Temperature +150 к
TA Operating Ambient Temperature Range -20~+125
TSTG Storage Temperature RDY -55 to +150 к
DIP 36.70
RӰj-C
Thermal Resistance (Junction-to-Case)
SOP 37.76
к/W
TL Lead Temperature (Wave Soldering or IR, 10 seconds) 260 к
VESD,HBM ESD Capability, Human Body Model 4 KV
VESD,MM ESD Capability, Machine Model 250 V
*All voltage values, except differential voltages, are given with respect to the network ground terminal.
*Stress beyond those listed under “ABSOLUTE MAXIMUM RATING” may cause permanent damage to the device.
RECOMMENDED OPERATING TEMPERATURE :
Symbol Parameter Value Unit
TA Operating Ambient Temperature -20 ~ 85 к
*For proper operation
Product Specification
Single-Stage PFC Controller SG6980D
© System General Corp. - 6 - www.sg.com.tw • www.fairchildsemi.com
Version 1.0.1 (IAO33.0071.B0 September 17, 2007
ELECTRICAL CHARACTERISTICS
VDD=15V, TA=25°C unless otherwise noted.
VDD Section
Symbol Parameter Test Conditions Min. Typ. Max. Unit
VDD-OP Continuously Operating Voltage 20 V
IDD-OP Operating Current RI= 24K,VDD = 15V; Gate Open 4 5 mA
I IC-OFF Input Current VON/OFF<VON , VDD=25V 25 35 µA
IDD-ST Start-up Current VDDІVDD-ON-0.16V 10 20 µA
VDD-ON Start Threshold Voltage 11.5 12.5 13.5 V
VDD-OFF Minimum Operating Voltage 9 10 11 V
VDD-OVP V
DD Over-Voltage Protection with
Debounce Time
23.5 24.5 25.5 V
tD-VDDOVP Debounce Time of VDD OVP Protection 10 40 µs
Oscillator & Green-Mode Operation
Symbol Parameter Test Conditions Min. Typ. Max. Unit
FOSC PWM Frequency RI= 24K 62 65 68 KHz
RI Nominal RI Value 15 40 K:
RIOPEN Maximum RI Value for Protection 200 K:
RISHORT Maximum RI Value for Protection 2 K:
Product Specification
Single-Stage PFC Controller SG6980D
© System General Corp. - 7 - www.sg.com.tw • www.fairchildsemi.com
Version 1.0.1 (IAO33.0071.B0 September 17, 2007
VRMS for UVP and RDY
Symbol Parameter Test Conditions Min. Typ. Max. Unit
VRMS-UVP-1 RMS AC Voltage Under-voltage Threshold
(with TUVP Delay) 0.75 0.80 0.85 V
VRMS-UVP-2 Recovery Level on VRMS for UVP Mode VRMS-UVP-1
+0.18
VRMS-UVP-1
+0.20
VRMS-UVP-1
+0.22 V
tUVP Under-Voltage Protection Propagation
Delay Time (No Delay at Start-up) 150 195 240 ms
Voltage Error Amplifier
Symbol Parameter Test Conditions Min. Typ. Max. Unit
VREF Reference Voltage 2.95 3.00 3.05 V
Av Open-Loop Gain 60 dB
Zo Output Impedance 110 K
OVPFB PFC Over-Voltage Protection on FB 1.066 •
VREF
1.083 •
VREF
1.100 •
VREF
V
ϦOVPFB PFC Feedback Voltage Protection
Hysteresis 60 90 120 mV
tOVP-PFC Debounce Time of PFC OVP 40 70 120 µs
VFB-H Clamp-High Feedback Voltage 1.033 •
VREF
1.050 •
VREF
1.066 •
VREF
V
GFB-H Clamp-High Gain 500 µA/mV
VFB-L Clamp-Low Feedback Voltage 0.916 •
VREF
0.950 •
VREF
0.966 •
VREF
V
GFB-L Clamp-Low Gain 6.5 µA/mV
IFB-L Clamp-Low Maximum Current 1.5 2 mA
UVPFB PFC Feedback Under-Voltage Protection 0.35 0.40 0.45 V
tUVP-PFC Debouce Time of PFC Feedback UVP 40 70 120 µs
Current Error Amplifier
Symbol Parameter Test Conditions Min. Typ. Max. Unit
VOFFSET Input Offset Voltage ((-) > (+)) 8 mV
AI Open-Loop Gain 60 dB
BW Unit Gain Bandwidth 1.5 MHz
CMRR Common-Mode Rejection Ratio VCM = 0 ~ 1.5V 70 dB
VOUT-HIGH Output High Voltage 3.2 V
VOUT-LOW Output Low Voltage 0.2 V
IMR1, IMR2 Reference Current source RI=24 K (IMR=20+IRI • 0.8) 50 70 µA
IL Maximum Source Current 3 mA
IH Maximum Sink Current 0.25 mA
Product Specification
Single-Stage PFC Controller SG6980D
© System General Corp. - 8 - www.sg.com.tw • www.fairchildsemi.com
Version 1.0.1 (IAO33.0071.B0 September 17, 2007
Peak Current Limit
Symbol Parameter Test Conditions Min. Typ. Max. Unit
IP Constant Current Output RI = 24K 90 100 110 µA
VRMS=1.05V 0.15 0.20 0.25 V
VPK Peak Current Limit Threshold Voltage
Cycle-by-Cycle Limit (Vsense < Vpk) VRMS=3V 0.35 0.40 0.45 V
tPD-PFC Propagation Delay 200 ns
tLEB-PFC Leading-Edge Blanking Time 250 330 430 ns
Multiplier
Symbol Parameter Test Conditions Min. Typ. Max. Unit
IAC Input AC Current Linear RDY 0 360 µA
IMO–MAX Maximum Multiplier Current Output; RI=24 K 230 250 µA
IMO-1 Multiplier Current Output
(Low-line, High-power)
VRMS=1.05V; IAC=90µA;
VEA=7.5V; RI=24K 200 250 280 µA
IMO–2 Multiplier Current Output
(High-line, High-power)
VRMS=3V; IAC=264µA;
VEA=7.5V; RI=2 K 65 85 µA
VIMP Voltage of IMP Open 3.4 3.9 4.4 V
PFC Output Driver
Symbol Parameter Test Conditions Min. Typ. Max. Unit
VZ Output Voltage Maximum (clamp) VDD=20V 15 18 V
VOL Output Voltage Low VDD = 15V; IO = 100mA 1.5 V
VOH Output Voltage High VDD = 13V; IO = 100mA 8 V
tR Rising Time VDD = 15V; CL = 5nF;
OUT = 2V to 9V
30 70 120 ns
tF Falling Time VDD = 15V; CL = 5nF;
OUT = 9V to 2V
30 50 100 ns
DCYMAX Maximum Duty Cycle 93 98 %
RDY Section
Symbol Parameter Test Conditions Min. Typ. Max. Unit
FB-RDY-high FB Voltage, RDY High Impedance 2.7 V
IFB-RDY-high Input Leakage Current, RDY High
Impedance
FB=2.5V 500 nA
VOL Output Voltage Low, RDY Failed ISINK =1mA 0.5 V
tRDY-delay time Interval Between FB > 2.7V and RDY High
Impedance
4 6 ms
tRDY-UVP_delay time Delay Time Between Gate off and RDY Pull
Low when UVP Occurs
10 16 ms
OTP Section
Symbol Parameter Test Conditions Min. Typ. Max. Unit
IOTP OTP Pin Output Current RI = 24K 90 100 110 µA
VOTP-OFF OTP Threshold Voltage 1.15 1.20 1.25 V
VOTP-ON Recovery Level on OTP 1.35 1.40 1.45 V
TOTP OTP Debounce Time 10 40 µs
Product Specification
Single-Stage PFC Controller SG6980D
© System General Corp. - 9 - www.sg.com.tw • www.fairchildsemi.com
Version 1.0.1 (IAO33.0071.B0 September 17, 2007
SYNC Section
Symbol Parameter Test Conditions Min. Typ. Max. Unit
VSYNC-HIGH Synchronizing Signal High Threshold 3.5 V
VSYNC-LOW Synchronizing Signal Low Threshold 0.9 V
FMin Minimum Synchronizing Frequency RI=24K 2 •
(FOSC-12.5) KHz
FMax Maximum Synchronizing Frequency 250 KHz
tMIN_PULSE_W Minimum Synchronizing Pulse Width RI = 24K 100 200 500 ns
tMAX_PULSE_W Maximum Synchronizing Pulse Width RI = 24K 15.8 µs
tD-65KHZ Delay Time Between SYNC and OUT,
Switching Frequency = 65KHz RI=24K 1 3 µs
tD-50KHZ Delay Time Between SYNC and OUT,
Switching Frequency = 50KHz RI=31.2K 1 3 µs
ON/OFF Section
Symbol Parameter Test Conditions Min. Typ. Max. Unit
Ron/off Impedance of ON/OFF Pin 18 27 50 K
VON High Threshold of Enable Signal 3 V
VOFF Low Threshold of Disable Signal 1 V
Product Specification
Single-Stage PFC Controller SG6980D
© System General Corp. - 10 - www.sg.com.tw • www.fairchildsemi.com
Version 1.0.1 (IAO33.0071.B0 September 17, 2007
TYPICAL CHARACTERISTICS
Operating Current (I
DD OP
) vs Temperature
ˆˁ˃
ˆˁˈ
ˇˁ˃
ˇˁˈ
ˈˁ˃
ˈˁˈ
ˉˁ˃
ˀˇ˃ ˀ˅ˈ ˀ˄˃ ˈ ˅˃ ˆˈ ˈ˃ ˉˈ ˋ˃ ˌˈ ˄˄˃ ˄˅ˈ
Temperature (к)
I
DD OP
(mA)
Reference Voltage (V
REF
) vs Temperature
˅ˁˌ˃
˅ˁˌˈ
ˆˁ˃˃
ˆˁ˃ˈ
ˆˁ˄˃
ˀˇ˃ ˀ˅ˈ ˀ˄˃ ˈ ˅˃ ˆˈ ˈ˃ ˉˈ ˋ˃ ˌˈ ˄˄˃ ˄˅ˈ
Temperature (к)
V
REF
(V)
Start Threshold Voltage (V
DD-ON
) vs Temperature
˄˅ˁ˃
˄˅ˁ˅
˄˅ˁˇ
˄˅ˁˉ
˄˅ˁˋ
˄ˆˁ˃
ˀˇ˃ ˀ˅ˈ ˀ˄˃ ˈ ˅˃ ˆˈ ˈ˃ ˉˈ ˋ˃ ˌˈ ˄˄˃ ˄˅ˈ
Temperature (к)
V
DD-ON
(V)
Start Threshold Voltage (V
DD-ON
) vs Temperature
˄˅ˁ˃
˄˅ˁ˅
˄˅ˁˇ
˄˅ˁˉ
˄˅ˁˋ
˄ˆˁ˃
ˀˇ˃ ˀ˅ˈ ˀ˄˃ ˈ ˅˃ ˆˈ ˈ˃ ˉˈ ˋ˃ ˌˈ ˄˄˃ ˄˅ˈ
Temperature (к)
V
DD-ON
(V)
PWM frequency (F
OSC
) vs Temperature
ˉ˃ˁ˃
ˉ˄ˁ˃
ˉ˅ˁ˃
ˉˆˁ˃
ˉˇˁ˃
ˉˈˁ˃
ˉˉˁ˃
ˀˇ˃ ˀ˅ˈ ˀ˄˃ ˈ ˅˃ ˆˈ ˈ˃ ˉˈ ˋ˃ ˌˈ ˄˄˃ ˄˅ˈ
Temperature (к)
F
OSC
(KHz)
Minimum synchronizing frequency (F
Min
) vs Temperature
˄˅ˁ˃
˄ˇˁ˃
˄ˉˁ˃
˄ˋˁ˃
˅˃ˁ˃
ˀˇ˃ ˀ˅ˈ ˀ˄˃ ˈ ˅˃ ˆˈ ˈ˃ ˉˈ ˋ˃ ˌˈ ˄˄˃ ˄˅ˈ
Temperature (к)
F
Min
(KHz)
Product Specification
Single-Stage PFC Controller SG6980D
© System General Corp. - 11 - www.sg.com.tw • www.fairchildsemi.com
Version 1.0.1 (IAO33.0071.B0 September 17, 2007
RMS AC Voltage Under-voltage Threshold (with TUVP delay)
(V
RM S- U VP-1
) vs Temperature
0.70
0.75
0.80
0.85
0.90
-40 -25 -10 5 20 35 50 65 80 95 110 125
Temperature (к)
V
RMS-UVP-1
(V)
PFC Feedback Voltage Protection Hysteresis (ϦOVP
VFB
) vs
Temperature
ˊ˃ˁ˃
ˋ˃ˁ˃
ˌ˃ˁ˃
˄˃˃ˁ˃
˄˄˃ˁ˃
˄˅˃ˁ˃
ˀˇ˃ ˀ˅ˈ ˀ˄˃ ˈ ˅˃ ˆˈ ˈ˃ ˉˈ ˋ˃ ˌˈ ˄˄˃ ˄˅ˈ
Temperature (к)
ϦOVP
VFB
(mV)
Multiplier Current Output (IMO-1
) vs Temperature
˅˅˃ˁ˃
˅˅ˈˁ˃
˅ˆ˃ˁ˃
˅ˆˈˁ˃
˅ˇ˃ˁ˃
ˀˇ˃ ˀ˅ˈ ˀ˄˃ ˈ ˅˃ ˆˈ ˈ˃ ˉˈ ˋ˃ ˌˈ ˄˄˃ ˄˅ˈ
Temperature (к)
IMO-1 (uA)
Multiplier Current Output (I
MO-2
) vs Temperature
ˉˊˁ˃
ˉˌˁ˃
ˊ˄ˁ˃
ˊˆˁ˃
ˊˈˁ˃
ˀˇ˃ ˀ˅ˈ ˀ˄˃ ˈ ˅˃ ˆˈ ˈ˃ ˉˈ ˋ˃ ˌˈ ˄˄˃ ˄˅ˈ
Temperature (к)
I
MO-2
(uA)
OTP Threshold Voltage (V
OTP-OFF
) vs Temperature
˄ˁ˄˃
˄ˁ˄ˈ
˄ˁ˅˃
˄ˁ˅ˈ
˄ˁˆ˃
ˀˇ˃ ˀ˅ˈ ˀ˄˃ ˈ ˅˃ ˆˈ ˈ˃ ˉˈ ˋ˃ ˌˈ ˄˄˃ ˄˅ˈ
Temperature (к)
V
OTP-OFF
(V)
Recovery Level on OTP (V
OTP-ON
) vs Temperature
˄ˁˆˈ
˄ˁˆˊ
˄ˁˆˌ
˄ˁˇ˄
˄ˁˇˆ
ˀˇ˃ ˀ˅ˈ ˀ˄˃ ˈ ˅˃ ˆˈ ˈ˃ ˉˈ ˋ˃ ˌˈ ˄˄˃ ˄˅ˈ
Temperature (к)
V
OTP-ON
(V)
Product Specification
Single-Stage PFC Controller SG6980D
© System General Corp. - 12 - www.sg.com.tw • www.fairchildsemi.com
Version 1.0.1 (IAO33.0071.B0 September 17, 2007
OPERATION DESCRIPTION
The highly integrated SG6980D is designed for a power
supply with boost PFC. It requires very few external
components to achieve high performance and versatile
protections / compensation.
The PFC function is implemented by average current mode
control. The patented switching-charge multiplier-divider
provides a high-degree of noise immunity for the PFC
circuit. This also enables the PFC circuit to operate over a
much wider region. The proprietary multi-vector output
voltage control scheme provides a fast transient response in
a low-bandwidth PFC loop, in which the overshoot and
undershoot of the PFC voltage are clamped. If the feedback
loop is broken, the SG6980D shuts off the PFC to prevent
extra-high voltage on output. Programmable two-level
high/low line compensation optimizes THD performance.
In addition, SG6980D provides complete protection
functions, such as brownout protection and RI open/short.
Switching Frequency and Current
Sources
The switching frequency of SG6980D can be programmed
by the resistor RI connected between RI pin and GND. The
relationship is:
)(kHz
)(k R
1560
f
I
PWM :
------------- (1)
For example, a 24k resistor RI results in a 65kHz
switching frequency. Accordingly, constant current IT
flows through RI:
)(mA
)(k R
1.2V
T
I
I:
---------------- (2)
IT is used to generate internal current reference.
If there is a SYNC signal input, the switching frequency is
defined by the SYNC signal. The SNYC frequency must be
larger than the programmed switching frequency,
less 6KHz.
Line Voltage Detection (VRMS)
Figure 1 shows a resistive divider with low-pass filtering
for line-voltage detection on VRMS pin. The VRMS voltage
is used for the PFC multiplier, brownout protection, and
RDY control.
For brownout protection, the SG6980D is disabled with a
195ms delay time if the voltage VRMS drops below 0.8V.
For PFC multiplier and RDY control, please refer to below
sections for more detail.
FIG.1
PFC Output Voltage Control
For a universal input (90VAC ~ 264VAC) power supply
applying active boost PFC and forward as a second stage,
the output voltage of PFC is usually designed around 400V.
V
R
RR
Vo
B
BA 3u
---- (3)
FIG.2 Output Voltage Setting
Product Specification
Single-Stage PFC Controller SG6980D
© System General Corp. - 13 - www.sg.com.tw • www.fairchildsemi.com
Version 1.0.1 (IAO33.0071.B0 September 17, 2007
ON/OFF
For ON/OFF control, the SG6980D is disabled
immediately if the voltage at this pin is below 1V. Usually,
the pin opens when turn off can have the best power saving.
The operating current during turn off is less than 35µA.
SYNC Signal Section
The SG6980D can synchronize half frequency of the
SYNC signal and the synchronize signal provided by
second stage. This reduces switching noise and the ripple
on the output voltage. Figure 3 shows the relationship
between the OUT and SYNC signals.
FIG.3 Synchronized Interleaving-Switching
RDY Signal Section
SG6980D provides a RDY pin to inform the next stage and
other applications. RDY signal is high impedance when the
FB voltage goes up to 2.7V and the delay around 5ms. Use
the pin to turn on the second stage PWM when the bulk
capacitor voltage is high enough. The RDY pin (open-drain
structure) is used for the next-stage-ready signal.
PFC Operation
The purpose of a boost active power factor corrector (PFC)
is to shape the input current of a power supply. The input
current waveform and phase follow that of the input
voltage. Using SG6980D, average-current-mode control is
utilized for continuous current mode for the PFC booster.
With the innovative multi-vector control for voltage loop
and switching-charge multiplier/divider for current
reference, excellent input power factor is achieved with
good noise immunity and transient response. Figure 4
shows the total control loop for the average-current-mode
control circuit of SG6980D.
FIG.4 Multiplier and Control Loop of PFC Stage
The current source output from the switching-charge
multiplier/divider can be expressed as:
)µA(
RMS
V
EA
V
AC
I
K
MO
I2
u
u ----------------- (4)
IIMP, the current output from IMP pin, is the summation of
IMO and IMR1. IMR1 and IMR2 are identical fixed current
sources. R2 and R3 are also identical. They are used to pull
high the operating point of the IMP and ICS pins if the
voltage across RS goes negative with respect to ground.
Through the differential amplification of the signal across
RS, better noise immunity is achieved. The output of IEA is
compared with an internal sawtooth and the pulse width for
PFC is determined. Through the average current-mode
control loop, the input current IS is proportional to IMO.
S
R
S
I
2
R
MO
Iu u --------------- (5)
According to Equation 5, the minimum value of R2 and
maximum of RS can be determined because IMO should not
exceed the specified maximum value.
There are different concerns in determining the value of the
sense resistor RS. The value of RS should be small enough
to reduce power consumption, but large enough to maintain
the resolution. A current transformer (CT) may be used to
improve the efficiency of high-power converters.
To achieve a good power factor, the voltage for VRMS and
VEA should be kept as DC as possible according to
Equation 4. Good RC filtering for VRMS and narrow
bandwidth (lower than the line frequency) for voltage loop
are suggested for better input current shaping. The
transconductance error amplifier has output impedance RO
and a capacitor CEA (1µF ~ 10µF) connected to ground
(as shown in FIG. 4). This establishes a dominant pole f1
(Equation 6) for the voltage loop.
Product Specification
Single-Stage PFC Controller SG6980D
© System General Corp. - 14 - www.sg.com.tw • www.fairchildsemi.com
Version 1.0.1 (IAO33.0071.B0 September 17, 2007
EA0
1CR2
1
f
uuS
---------------------------- (6)
The average total input power can be expressed as:
EA
2
RMS
EA
AC
RMS
2
RMS
EAAC
RMS
MORMS
V
V
V
R
Vin
V
V
VI
V
IV
)rms(Iin)rms(VinPin
v
u
uv
u
uv
uv
u
From Equation 7, VEA, the output of the voltage error
amplifier, controls the total input power and the power
delivered to the load.
Multi-Vector Error Amplifier
The voltage-loop error amplifier is transconductance,
which has high output impedance (> 90k:). A capacitor
CEA (1µF ~ 10µF) connected from VEA to ground provides
a dominant pole for the voltage loop. Although the PFC
stage has a low bandwidth voltage loop for better input
power factor, the innovative multi-vector error amplifier
provides a fast transient response to clamp the overshoot
and undershoot of the PFC output voltage. Figure 5 shows
the voltage loop with multi-vector for fast transient error
amplifier. When the variation of the feedback voltage
exceeds r 5% of the reference voltage, the
transconductance error amplifier adjusts its output
impedance to increase the loop response. If the feedback
resistance is opened, SG6980D shuts off immediately to
prevent extra-high voltage on the output capacitor.
FIG. 5 Voltage Error Amplifier with Multi-Vector
Cycle-by-Cycle Current Limiting
SG6980D provides cycle-by-cycle current limiting for PFC
stages. Figure 6 shows the peak current limit for the PFC
stage. The PFC gate drive is terminated once the voltage on
IPK pin goes below VPK.
The voltage of VRMS determines the voltage of VPK. The
relationship between VPK and VRMS is shown in Figure 6.
The amplitude of the constant current IP is determined by
the internal current reference IT, according to the following
equation:
I
R
1.2V
2
T
I2 Ip u u ----------------------- (8)
Therefore the peak current of the IS is given by:
S
P
S_peak R
pk
V-)R(Ip
I
u
------------------ (9)
FIG.6 Current Limit
-------------- (7)
Product Specification
Single-Stage PFC Controller SG6980D
© System General Corp. - 15 - www.sg.com.tw • www.fairchildsemi.com
Version 1.0.1 (IAO33.0071.B0 September 17, 2007
Gate Drivers
SG6980D output stages are fast totem-pole gate drivers.
The output driver is clamped by an internal 18V Zener
diode to protect the power MOSFET.
Over-Temperature Protection
SG6980D provides an OTP pin for over-temperature
protection. A constant current is output from this pin. If RI
is equal to 24k, the magnitude of the constant current is
50µA. An external NTC thermistor must be connected
from this pin to ground. When the OTP voltage drops
below 1.2V, SG6980D shuts down. SG6980D auto restarts
when the OTP voltage is higher than 1.4V.
Protections & Built-in Latch Circuit
The SG6980D provides full protection functions to prevent
the power supply and the load from being damaged. The
protection features include:
PFC Feedback Over-Voltage Protection. When the PFC
feedback voltage exceeds the over-voltage threshold, the
SG6980D inhibits the PFC switching signal. This
protection prevents the PFC power converter from
operating abnormally while the FB pin is open.
PFC Feedback Under-Voltage Protection. The SG6980D
stops the PFC switching signal whenever the PFC feedback
voltage drops below the under-voltage threshold. This
protection feature is designed to prevent the PFC power
converter from experiencing abnormal conditions while the
FB pin is shorted to ground.
VDD Over-Voltage Protection. The built-in clamping
circuit clamps VDD whenever the VDD voltage exceeds the
over-voltage threshold.
RI Pin Open / Short Protection. The RI pin is used to set the
switching frequency and internal current reference. If the
RI pin is shorted or open, SG6980D turns off.
PCB Layout
The SG6980D has a single ground pin. High sink currents
in the output cannot be returned separately. Good
high-frequency or RF layout practices should be followed.
Avoid long PCB traces and component leads. Locate
decoupling capacitors near the SG6980D. A resistor of 5 ~
20: is recommended for connecting in series from the
output to the gate of the MOSFET.
Isolating the interference between the PFC and PWM
stages is also important. Figure 7 shows an example of the
PCB layout. The ground trace 1 is connected from the
ground pin of SG6980D to the decoupling capacitor, which
should be low impedance and as short as possible. The
ground trace 2 provides a signal ground. It should be
connected directly to the decoupling capacitor CDD and/or
to the ground pin of the SG6980D. The ground trace 3 is
independently tied from the decoupling capacitor to the
PFC output capacitor CO. The ground in the output
capacitor CO is the major ground reference for power
switching. To provide a good ground reference and reduce
the switching noise of both the PFC and PWM stages, the
ground traces 6 and 7 should be located very near and be
low impedance.
The ICS pin is connected directly to RS through R3 to
improve noise immunity. (Beware that it may incorrectly
be connected to the ground trace 2). The IMP and IPK pins
should be connected directly via the resistors R2 and RP to
another terminal of RS.
FIG. 7 PCB Layout
Product Specification
Single-Stage PFC Controller SG6980D
© System General Corp. - 16 - www.sg.com.tw • www.fairchildsemi.com
Version 1.0.1 (IAO33.0071.B0 September 17, 2007
PACKAGE INFORMATION
16 PINS – PLASTIC DIP (D)
Dimensions:
Millimeter Inch
Symbol Min. Typ. Max. Min. Typ. Max.
A 5.334 0.210
A1 0.381 0.015
A2 3.175 3.302 3.429 0.125 0.130 0.135
b 1.524 0.060
b1 0.457 0.018
D 18.669 19.177 19.685 0.735 0.755 0.775
E 7.620 0.300
E1 6.121 6.299 6.477 0.241 0.248 0.255
e 2.540 0.100
L 2.921 3.302 3.810 0.115 0.130 0.150
eB 8.509 9.017 9.525 0.335 0.355 0.375
Ӱ 0 7150715
Ӱ
eB
E
A
A2
e
A1
L
b1
8
1
D
16 9
E1
Product Specification
Single-Stage PFC Controller SG6980D
© System General Corp. - 17 - www.sg.com.tw • www.fairchildsemi.com
Version 1.0.1 (IAO33.0071.B0 September 17, 2007
16 PINS – PLASTIC SOP (S)
Dimension:
Millimeter Inch
Symbol Min. Typ. Max. Min. Typ. Max.
A 1.346 1.753 0.053 0.069
A1 0.101 0.254 0.004 0.010
A2 1.244 1.499 0.049 0.059
b 0.406 0.016
c 0.203 0.008
D 9.804 10.008 0.386 0.394
E 3.810 3.988 0.150 0.157
e 1.270 0.050
H 5.791 6.198 0.228 0.244
L 0.406 1.270 0.016 0.050
F
0.381X45
0.015X45
y 0.101 0.004
Ӱ
0 8 0 8
Ӱ
Detail A
Detail A
y
18
16 9
b
e
E H
Fc
D
A2
A1
AL
Product Specification
Single-Stage PFC Controller SG6980D
© System General Corp. - 18 - www.sg.com.tw • www.fairchildsemi.com
Version 1.0.1 (IAO33.0071.B0 September 17, 2007