To our customers,
Old Company Name in Catalogs and Other Documents
On April 1st, 2010, NEC Electronics Corporation merged with Renesas Technology
Corporation, and Renesas Electronics Corporation took over all the business of both
companies. Therefore, although the old company name remains in this document, it is a valid
Renesas Electronics document. We appreciate your understanding.
Renesas Electronics website: http://www.renesas.com
April 1st, 2010
Renesas Electronics Corporation
Issued by: Renesas Electronics Corporation (http://www.renesas.com)
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(Note 1) “Renesas Electronics” as used in this document means Renesas Electronics Corporation and also includes its majority-
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(Note 2) “Re nesas Electronics produc t(s)” means any product develope d or manufactured by or for Re nesas Electronics.
H8S/2626 Group, H8S/2623 Group,
H8S/2626F-ZTATTM,
H8S/2623F-ZTATTM
Hardware Manual
16
User’s Manual
Rev.5.00 2006.01
Renesas 16-Bit Single-Chip
Microcomputer
H8S Family/H8S/2600 Series
H8S/2626 HD6432626
HD64F2626
H8S/2625 HD6432625
H8S/2623 HD6432623
HD64F2623
H8S/2622 HD6432622
H8S/2621 HD64F2621
Rev. 5.00 Jan 10, 2006 page ii of xxiv
1. These materials are intended as a reference to assist our customers in the selection of the Renesas
Technology Corp. product best suited to the customer's application; they do not convey any license
under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or
a third party.
2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any third-
party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or
circuit application examples contained in these materials.
3. All information contained in these materials, including product data, diagrams, charts, programs and
algorithms represents information on products at the time of publication of these materials, and are
subject to change by Renesas Technology Corp. without notice due to product improvements or
other reasons. It is therefore recommended that customers contact Renesas Technology Corp. or
an authorized Renesas Technology Corp. product distributor for the latest product information
before purchasing a product listed herein.
The information described here may contain technical inaccuracies or typographical errors.
Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss rising
from these inaccuracies or errors.
Please also pay attention to information published by Renesas Technology Corp. by various means,
including the Renesas Technology Corp. Semiconductor home page (http://www.renesas.com).
4. When using any or all of the information contained in these materials, including product data,
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information contained herein.
5. Renesas Technology Corp. semiconductors are not designed or manufactured for use in a device or
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7. If these products or technologies are subject to the Japanese export control restrictions, they must
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Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the
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8. Please contact Renesas Technology Corp. for further details on these materials or the products
contained therein.
1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and
more reliable, but there is always the possibility that trouble may occur with them. Trouble with
semiconductors may lead to personal injury, fire or property damage.
Remember to give due consideration to safety when making your circuit designs, with appropriate
measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or
(iii) prevention against any malfunction or mishap.
Keep safety first in your circuit designs!
Notes regarding these materials
Rev. 5.00 Jan 10, 2006 page iii of xxiv
General Precautions on the Handling of Products
1. Treatment of NC Pins
Note: Do not connect anything to the NC pins.
The NC (not connected) pins are either not connected to any of the internal circuitry or are
used as test pins or to reduce noise. If something is connected to the NC pins, the
operation of the LSI is not guaranteed.
2. Treatment of Unused Input Pins
Note: Fix all unused input pins to high or low level.
Generally, the input pins of CMOS products are high-impedance input pins. If unused pins
are in their open states, intermediate levels are induced by noise in the vicinity, a pass-
through cu rrent f lows internally, and a malfunction may occur.
3. Processing befo re Initialization
Note: When power is first supplied, the product’s state is undefined. The states of internal
circuits are undefined until full power is supplied throughout the chip and a low level is
input on the reset pin. During the period where the states are undefined, the register
settings and the output state of each pin are also undefined. Design your system so that it
does not malfunction because of processing while it is in this undefined state. For those
products which have a reset function, reset the LSI immediately after the power supply has
been turned on.
4. Prohibition of Access to Undefined or Reserved Address
Note: Access to undefined or reserved addresses is prohibited.
The undefined or reserved addresses may be used to expand functions, or test registers
may have been be allocated to these address. Do not access these registers: the system’s
operation is not guaranteed if they are accessed.
Rev. 5.00 Jan 10, 2006 page iv of xxiv
Rev. 5.00 Jan 10, 2006 page v of xxiv
Preface
The H8S/2626 Group and H8S/2623 Group are series of high-performance microcontrollers with a
32-bit H8S/2600 CPU core, and a set of on-chip supporting modules required for system
configuration.
The H8S/2600 CPU can execute basic instructions in one state, and is provided with sixteen 16-bit
general r egisters with a 32-bit in ternal co nfiguration, and a concise and optimized instructio n set.
The CPU can handle a 16 Mbyte linear address space (architecturally 4 Gbytes). Programs based
on the high-level language C can also be run efficiently.
The address space is divided into eight areas. The data bus width and access states can be selected
for each of these areas, and various kinds of memory can be connected fast and easily.
Single-power-supply flash memory (F-ZTAT™*), and mask ROM versions are available,
providing a quick and flexib le response to conditions from ramp-up through full-scale volume
production, even for applications with frequently changing specifications.
On-chip supporting functions include a 16-bit timer pulse unit (TPU), programmable pulse
generator (PPG), watchdog timer (WDT), serial communication interface (SCI), controller area
network (HCAN), A/D converter, D/A converter (H8S/2626 Group only), and I/O ports.
In addition, d a ta tr ansfer contr oller (DTC) is provid ed, enabling high-speed data transfer without
CPU intervention.
Use of the H8S/2626 Group or H8S/2623 Group enables easy implementation of compact, high-
performance systems capable of processing large volumes of data.
This manual describes the hardware of the H8S/2626 Group and H8S/2623 Group. Refer to the
H8S/2600 Series and H8S/2000 Series Programming Manual for a detailed description of the
instructio n set.
Note: * F-ZTAT (Flexible-ZTAT) is a trademark of Renesas Technology Corp.
Rev. 5.00 Jan 10, 2006 page vi of xxiv
Rev. 5.00 Jan 10, 2006 page vii of xxiv
Main Revisions in This Edition
Item Page Revision (See Manual for Details)
All — • All references to Hitachi, Hitachi, Ltd., Hitachi Semiconductors, and
other Hitachi brand names changed to Renesas Technology Corp.
• Designation for categories changed from “series” to “group”
19.13 Flash
Memory
Programming
and Erasing
Precautions
Figure 19.26
Power-On/Off
Timing (Boot
Mode)
682 Figure 19.26 amended
Period during which flash memory access is prohibited
(x: Wait time after setting SWE1 bit)
*2
Period during which flash memory can be programmed
(Execution of program in flash memory prohibited, and data reads other than verify operations
prohibited)
φ
VCC
FWE
t
OSC1
Min 0 µs
t
MDS*3
t
MDS*3
MD2 to MD0
*1
RES
SWE1 bit
SWE1 set SWE1 cleared
Program-
ming/
erasing
possible
Wait time:
xWait time:
100 µs
Min 0 µs
Rev. 5.00 Jan 10, 2006 page viii of xxiv
Item Page Revision (See Manual for Details)
19.13 Flash
Memory
Programming
and Erasing
Precautions
Figure 19.27
Power-On/Off
Timing (User
Program Mode)
683 Figure 19.27 amended
Period during which flash memory access is prohibited
(x: Wait time after setting SWE1 bit)
*2
Period during which flash memory can be programmed
(Execution of program in flash memory prohibited, and data reads other than verify operations
prohibited)
φ
VCC
FWE
t
OSC1
Min 0 µs
MD2 to MD0
*1
RES
SWE1 bit
SWE1 set SWE1 cleared
Program-
ming/
erasing
possible
Wait time:
xWait time:
100 µs
tMDS*3
Figure 19.28
Mode
Transition
Timing
(Example: Boot
Mode → User
Mode ↔ User
Program Mode)
684 Figure 19.28 amended
Period during which flash memory access is prohibited
(x: Wait time after setting SWE1 bit)
*3
Period during which flash memory can be programmed
(Execution of program in flash memory prohibited, and data reads other than verify operations prohibited)
φ
VCC
FWE
t
OSC1
Min 0µs
t
MDS
t
MDS*2
t
MDS
t
RESW
MD2 to MD0
RES
SWE1 bit
Mode
change
*1
User
mode
Boot
mode User program mode
SWE1 set SWE1
cleared
Programming/
erasing possible
Wait time: x
Wait time: 100 µs
Programming/
erasing possible
Wait time: x
Wait time: 100 µs
Programming/
erasing possible
Wait time: x
Programming/
erasing possible
Wait time: x
Wait time: 100 µs
Wait time: 100 µs
Mode
change
*1
User
mode User program
mode
Rev. 5.00 Jan 10, 2006 page ix of xxiv
Contents
Section 1 Overview............................................................................................................. 1
1.1 Overview........................................................................................................................... 1
1.2 Internal Block Diagram..................................................................................................... 6
1.3 Pin Descriptions................................................................................................................ 8
1.3.1 Pin Arrangement.................................................................................................. 8
1.3.2 Pin Functions in Each Operating Mode............................................................... 10
1.3.3 Pin Functions ....................................................................................................... 18
Section 2 CPU...................................................................................................................... 23
2.1 Overview........................................................................................................................... 23
2.1.1 Features................................................................................................................ 23
2.1.2 Differences between H8S/2600 CPU and H8S/2000 CPU.................................. 24
2.1.3 Differences from H8/300 CPU ............................................................................ 25
2.1.4 Differences from H8/300H CPU.......................................................................... 25
2.2 CPU Operating Modes...................................................................................................... 26
2.3 Address Space................................................................................................................... 31
2.4 Register Configuration...................................................................................................... 32
2.4.1 Overview.............................................................................................................. 32
2.4.2 General Registers................................................................................................. 33
2.4.3 Control Registers ................................................................................................. 34
2.4.4 Initial Register Values.......................................................................................... 36
2.5 Data Formats..................................................................................................................... 37
2.5.1 General Register Data Formats............................................................................ 37
2.5.2 Memory Data Formats......................................................................................... 39
2.6 Instruction Set................................................................................................................... 40
2.6.1 Overview.............................................................................................................. 40
2.6.2 Instructions and Addressing Modes..................................................................... 41
2.6.3 Table of Instructions Classified by Function ....................................................... 42
2.6.4 Basic Instruction Formats.................................................................................... 51
2.7 Addressing Modes and Effective Address Calculation..................................................... 53
2.7.1 Addressing Mode................................................................................................. 53
2.7.2 Effective Address Calculation ............................................................................. 56
2.8 Processing States............................................................................................................... 60
2.8.1 Overview.............................................................................................................. 60
2.8.2 Reset State............................................................................................................ 61
2.8.3 Exception-Handling State.................................................................................... 62
2.8.4 Program Execution State...................................................................................... 65
Rev. 5.00 Jan 10, 2006 page x of xxiv
2.8.5 Bus-Released State............................................................................................... 65
2.8.6 Power-Down State............................................................................................... 65
2.9 Basic Timing..................................................................................................................... 66
2.9.1 Overview.............................................................................................................. 66
2.9.2 On-Chip Memory (ROM, RAM)......................................................................... 66
2.9.3 On-Chip Supporting Module Access Timing ...................................................... 68
2.9.4 On-Chip HCAN Module Access Timing............................................................. 70
2.9.5 External Address Space Access Timing .............................................................. 72
2.10 Usage Note................................................................................................................. ....... 72
2.10.1 TAS Instruction.................................................................................................... 72
Section 3 MCU Operating Modes .................................................................................. 73
3.1 Overview........................................................................................................................... 73
3.1.1 Operating Mode Selection ................................................................................... 73
3.1.2 Register Configuration......................................................................................... 74
3.2 Register Descriptions....................................................................................................... .75
3.2.1 Mode Control Register (MDCR) ......................................................................... 75
3.2.2 System Control Register (SYSCR)...................................................................... 75
3.2.3 Pin Function Control Register (PFCR)................................................................ 77
3.3 Operating Mode Descriptions........................................................................................... 79
3.3.1 Mode 4................................................................................................................. 79
3.3.2 Mode 5................................................................................................................. 79
3.3.3 Mode 6................................................................................................................. 79
3.3.4 Mode 7................................................................................................................. 79
3.4 Pin Functions in Each Operating Mode ............................................................................ 80
3.5 Address Map in Each Operating Mode............................................................................. 80
Section 4 Exception Handling ......................................................................................... 85
4.1 Overview........................................................................................................................... 85
4.1.1 Exception Handling Types and Priority............................................................... 85
4.1.2 Exception Handling Operation............................................................................. 86
4.1.3 Exception Vector Table ....................................................................................... 86
4.2 Reset.................................................................................................................................. 88
4.2.1 Overview.............................................................................................................. 88
4.2.2 Reset Sequence.................................................................................................... 88
4.2.3 Interrupts after Reset............................................................................................ 90
4.2.4 State of On-Chip Supporting Modules after Reset Release ................................. 90
4.3 Traces................................................................................................................................ 91
4.4 Interrupts........................................................................................................................... 92
4.5 Trap Instruction............................................................................................................ ..... 93
4.6 Stack Status after Exception Handling.............................................................................. 94
Rev. 5.00 Jan 10, 2006 page xi of xxiv
4.7 Notes on Use of the Stack................................................................................................. 95
Section 5 Interrupt Controller.......................................................................................... 97
5.1 Overview........................................................................................................................... 97
5.1.1 Features................................................................................................................ 97
5.1.2 Block Diagram..................................................................................................... 98
5.1.3 Pin Configuration ................................................................................................. 99
5.1.4 Register Configuration......................................................................................... 99
5.2 Register Descriptions....................................................................................................... . 100
5.2.1 System Control Register (SYSCR)...................................................................... 100
5.2.2 Interrupt Priority Registers A to K, M (IPRA to IPRK, IPRM)........................... 101
5.2.3 IRQ Enable Register (IER).................................................................................. 103
5.2.4 IRQ Sense Control Registers H and L (ISCRH, ISCRL)..................................... 104
5.2.5 IRQ Status Register (ISR).................................................................................... 105
5.3 Interrupt Sources............................................................................................................... 106
5.3.1 External Interrupts ............................................................................................... 106
5.3.2 Internal Interrupts................................................................................................. 108
5.3.3 Interrupt Exception Handling Vector Table......................................................... 108
5.4 Interrupt Operation............................................................................................................ 112
5.4.1 Interrupt Control Modes and Interrupt Operation................................................ 112
5.4.2 Interrupt Control Mode 0..................................................................................... 116
5.4.3 Interrupt Control Mode 2..................................................................................... 118
5.4.4 Interrupt Exception Handling Sequence .............................................................. 120
5.4.5 Interrupt Response Times.................................................................................... 121
5.5 Usage Notes...................................................................................................................... 122
5.5.1 Contention between Interrupt Generation and Disabling..................................... 122
5.5.2 Instructions that Disable Interrupts...................................................................... 123
5.5.3 Times when Interrupts are Disabled .................................................................... 123
5.5.4 Interrupts during Execution of EEPMOV Instruction.......................................... 124
5.6 DTC Activation by Interrupt............................................................................................. 124
5.6.1 Overview.............................................................................................................. 124
5.6.2 Block Diagram..................................................................................................... 125
5.6.3 Operation ............................................................................................................. 125
Section 6 PC Break Controller (PBC)........................................................................... 127
6.1 Overview........................................................................................................................... 127
6.1.1 Features................................................................................................................ 127
6.1.2 Block Diagram..................................................................................................... 128
6.1.3 Register Configuration......................................................................................... 129
6.2 Register Descriptions....................................................................................................... . 129
6.2.1 Break Address Register A (BARA)..................................................................... 129
Rev. 5.00 Jan 10, 2006 page xii of xxiv
6.2.2 Break Address Register B (BARB)...................................................................... 130
6.2.3 Break Control Register A (BCRA)...................................................................... 130
6.2.4 Break Control Register B (BCRB)....................................................................... 132
6.2.5 Module Stop Control Register C (MSTPCRC).................................................... 132
6.3 Operation .......................................................................................................................... 133
6.3.1 PC Break Interrupt Due to Instruction Fetch ....................................................... 133
6.3.2 PC Break Interrupt Due to Data Access............................................................... 134
6.3.3 Notes on PC Break Interrupt Handling................................................................ 134
6.3.4 Operation in Transitions to Power-Down Modes ................................................ 135
6.3.5 PC Break Operation in Continuous Data Transfer............................................... 136
6.3.6 When Instruction Execution is Delayed by One State......................................... 137
6.3.7 Additional Notes.................................................................................................. 138
Section 7 Bus Controller ................................................................................................... 139
7.1 Overview........................................................................................................................... 139
7.1.1 Features................................................................................................................ 139
7.1.2 Block Diagram..................................................................................................... 140
7.1.3 Pin Configuration ................................................................................................. 141
7.1.4 Register Configuration......................................................................................... 142
7.2 Register Descriptions....................................................................................................... . 143
7.2.1 Bus Width Control Register (ABWCR)............................................................... 143
7.2.2 Access State Control Register (ASTCR) ............................................................. 144
7.2.3 Wait Control Registers H and L (WCRH, WCRL).............................................. 145
7.2.4 Bus Control Register H (BCRH).......................................................................... 149
7.2.5 Bus Control Register L (BCRL) .......................................................................... 151
7.2.6 Pin Function Control Register (PFCR)................................................................ 152
7.3 Overview of Bus Control.................................................................................................. 154
7.3.1 Area Partitioning.................................................................................................. 154
7.3.2 Bus Specifications................................................................................................ 155
7.3.3 Memory Interfaces............................................................................................... 156
7.3.4 Interface Specifications for Each Area ................................................................ 157
7.4 Basic Bus Interface ........................................................................................................... 158
7.4.1 Overview.............................................................................................................. 158
7.4.2 Data Size and Data Alignment............................................................................. 158
7.4.3 Valid Strobes........................................................................................................ 160
7.4.4 Basic Timing........................................................................................................ 161
7.4.5 Wait Control ........................................................................................................ 169
7.5 Burst ROM Interface......................................................................................................... 171
7.5.1 Overview.............................................................................................................. 171
7.5.2 Basic Timing........................................................................................................ 171
7.5.3 Wait Control ........................................................................................................ 173
Rev. 5.00 Jan 10, 2006 page xiii of xxiv
7.6 Idle Cycle.......................................................................................................................... 174
7.6.1 Operation ............................................................................................................. 174
7.6.2 Pin States in Idle Cycle........................................................................................ 176
7.7 Write Data Buffer Function .............................................................................................. 177
7.8 Bus Release....................................................................................................................... 178
7.8.1 Overview.............................................................................................................. 178
7.8.2 Operation ............................................................................................................. 178
7.8.3 Pin States in External Bus Released State............................................................ 179
7.8.4 Transition Timing................................................................................................ 180
7.8.5 Usage Note........................................................................................................... 181
7.9 Bus Arbitration.................................................................................................................. 181
7.9.1 Overview.............................................................................................................. 181
7.9.2 Operation ............................................................................................................. 181
7.9.3 Bus Transfer Timing............................................................................................ 182
7.10 Resets and the Bus Controller........................................................................................... 182
Section 8 Data Transfer Controller (DTC)................................................................... 183
8.1 Overview........................................................................................................................... 183
8.1.1 Features................................................................................................................ 183
8.1.2 Block Diagram..................................................................................................... 184
8.1.3 Register Configuration......................................................................................... 185
8.2 Register Descriptions....................................................................................................... . 186
8.2.1 DTC Mode Register A (MRA) ............................................................................ 186
8.2.2 DTC Mode Register B (MRB)............................................................................. 188
8.2.3 DTC Source Address Register (SAR).................................................................. 189
8.2.4 DTC Destination Address Register (DAR).......................................................... 189
8.2.5 DTC Transfer Count Register A (CRA) .............................................................. 190
8.2.6 DTC Transfer Count Register B (CRB)............................................................... 190
8.2.7 DTC Enable Registers (DTCER)......................................................................... 191
8.2.8 DTC Vector Register (DTVECR)........................................................................ 192
8.2.9 Module Stop Control Register A (MSTPCRA) ................................................... 193
8.3 Operation .......................................................................................................................... 193
8.3.1 Overview.............................................................................................................. 193
8.3.2 Activation Sources............................................................................................... 195
8.3.3 DTC Vector Table................................................................................................ 197
8.3.4 Location of Register Information in Address Space............................................ 200
8.3.5 Normal Mode....................................................................................................... 201
8.3.6 Repeat Mode........................................................................................................ 202
8.3.7 Block Transfer Mode........................................................................................... 203
8.3.8 Chain Transfer ..................................................................................................... 205
8.3.9 Operation Timing................................................................................................. 206
Rev. 5.00 Jan 10, 2006 page xiv of xxiv
8.3.10 Number of DTC Execution States........................................................................ 207
8.3.11 Procedures for Using DTC................................................................................... 209
8.3.12 Examples of Use of the DTC............................................................................... 210
8.4 Interrupts........................................................................................................................... 213
8.5 Usage Notes...................................................................................................................... 213
Section 9 I/O Ports.............................................................................................................. 215
9.1 Overview........................................................................................................................... 215
9.2 Port 1................................................................................................................................. 219
9.2.1 Overview.............................................................................................................. 219
9.2.2 Register Configuration......................................................................................... 220
9.2.3 Pin Functions ....................................................................................................... 222
9.3 Port 4................................................................................................................................. 234
9.3.1 Overview.............................................................................................................. 234
9.3.2 Register Configuration......................................................................................... 235
9.3.3 Pin Functions ....................................................................................................... 235
9.4 Port 9................................................................................................................................. 236
9.4.1 Overview.............................................................................................................. 236
9.4.2 Register Configuration......................................................................................... 237
9.4.3 Pin Functions ....................................................................................................... 237
9.5 Port A................................................................................................................................ 237
9.5.1 Overview.............................................................................................................. 237
9.5.2 Register Configuration......................................................................................... 238
9.5.3 Pin Functions ....................................................................................................... 242
9.5.4 MOS Input Pull-Up Function............................................................................... 245
9.6 Port B................................................................................................................................ 246
9.6.1 Overview.............................................................................................................. 246
9.6.2 Register Configuration......................................................................................... 247
9.6.3 Pin Functions ....................................................................................................... 249
9.6.4 MOS Input Pull-Up Function............................................................................... 258
9.7 Port C................................................................................................................................ 259
9.7.1 Overview.............................................................................................................. 259
9.7.2 Register Configuration......................................................................................... 260
9.7.3 Pin Functions ....................................................................................................... 263
9.7.4 MOS Input Pull-Up Function............................................................................... 268
9.8 Port D................................................................................................................................ 269
9.8.1 Overview.............................................................................................................. 269
9.8.2 Register Configuration......................................................................................... 270
9.8.3 Pin Functions ....................................................................................................... 272
9.8.4 MOS Input Pull-Up Function............................................................................... 273
9.9 Port E ................................................................................................................................ 274
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9.9.1 Overview.............................................................................................................. 274
9.9.2 Register Configuration......................................................................................... 275
9.9.3 Pin Functions ....................................................................................................... 277
9.9.4 MOS Input Pull-Up Function............................................................................... 278
9.10 Port F................................................................................................................................. 279
9.10.1 Overview.............................................................................................................. 279
9.10.2 Register Configuration......................................................................................... 280
9.10.3 Pin Functions....................................................................................................... 282
Section 10 16-Bit Timer Pulse Unit (TPU).................................................................. 285
10.1 Overview........................................................................................................................... 285
10.1.1 Features................................................................................................................ 285
10.1.2 Block Diagram..................................................................................................... 289
10.1.3 Pin Configuration................................................................................................. 290
10.1.4 Register Configuration......................................................................................... 292
10.2 Register Descriptions........................................................................................................ 294
10.2.1 Timer Control Register (TCR)............................................................................. 294
10.2.2 Timer Mode Register (TMDR)............................................................................ 299
10.2.3 Timer I/O Control Register (TIOR)..................................................................... 301
10.2.4 Timer Interrupt Enable Register (TIER).............................................................. 314
10.2.5 Timer Status Register (TSR)................................................................................ 316
10.2.6 Timer Counter (TCNT)........................................................................................ 320
10.2.7 Timer General Register (TGR)............................................................................ 320
10.2.8 Timer Start Register (TSTR)................................................................................ 321
10.2.9 Timer Synchro Register (TSYR) ......................................................................... 321
10.2.10 Module Stop Control Register A (MSTPCRA) ................................................... 322
10.3 Interface to Bus Master..................................................................................................... 323
10.3.1 16-Bit Registers ................................................................................................... 323
10.3.2 8-Bit Registers ..................................................................................................... 323
10.4 Operation .......................................................................................................................... 325
10.4.1 Overview.............................................................................................................. 325
10.4.2 Basic Functions.................................................................................................... 326
10.4.3 Synchronous Operation........................................................................................ 331
10.4.4 Buffer Operation.................................................................................................. 334
10.4.5 Cascaded Operation............................................................................................. 338
10.4.6 PWM Modes........................................................................................................ 340
10.4.7 Phase Counting Mode.......................................................................................... 345
10.5 Interrupts........................................................................................................................... 351
10.5.1 Interrupt Sources and Priorities............................................................................ 351
10.5.2 DTC Activation.................................................................................................... 353
10.5.3 A/D Converter Activation.................................................................................... 353
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10.6 Operation Timing.............................................................................................................. 354
10.6.1 Input/Output Timing............................................................................................ 354
10.6.2 Interrupt Signal Timing........................................................................................ 358
10.7 Usage Notes...................................................................................................................... 362
Section 11 Programmable Pulse Generator (PPG) .................................................... 373
11.1 Overview........................................................................................................................... 373
11.1.1 Features................................................................................................................ 373
11.1.2 Block Diagram..................................................................................................... 374
11.1.3 Pin Configuration................................................................................................. 375
11.1.4 Registers............................................................................................................... 376
11.2 Register Descriptions........................................................................................................ 377
11.2.1 Next Data Enable Registers H and L (NDERH, NDERL)................................... 377
11.2.2 Output Data Registers H and L (PODRH, PODRL)............................................ 378
11.2.3 Next Data Registers H and L (NDRH, NDRL).................................................... 379
11.2.4 Notes on NDR Access.......................................................................................... 379
11.2.5 PPG Output Control Register (PCR).................................................................... 381
11.2.6 PPG Output Mode Register (PMR)...................................................................... 383
11.2.7 Port 1 Data Direction Register (P1DDR)............................................................. 385
11.2.8 Module Stop Control Register A (MSTPCRA) ................................................... 386
11.3 Operation .......................................................................................................................... 387
11.3.1 Overview.............................................................................................................. 387
11.3.2 Output Timing...................................................................................................... 388
11.3.3 Normal Pulse Output............................................................................................ 389
11.3.4 Non-Overlapping Pulse Output............................................................................ 391
11.3.5 Inverted Pulse Output .......................................................................................... 394
11.3.6 Pulse Output Triggered by Input Capture............................................................ 395
11.4 Usage Notes...................................................................................................................... 396
Section 12 Watchdog Timer............................................................................................. 399
12.1 Overview........................................................................................................................... 399
12.1.1 Features................................................................................................................ 399
12.1.2 Block Diagram..................................................................................................... 400
12.1.3 Pin Configuration................................................................................................. 402
12.1.4 Register Configuration......................................................................................... 402
12.2 Register Descriptions........................................................................................................ 403
12.2.1 Timer Counter (TCNT)........................................................................................ 403
12.2.2 Timer Control/Status Register (TCSR)................................................................ 404
12.2.3 Reset Control/Status Register (RSTCSR)............................................................ 408
12.2.4 Pin Function Control Register (PFCR)................................................................ 410
12.2.5 Notes on Register Access..................................................................................... 410
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12.3 Operation .......................................................................................................................... 412
12.3.1 Watchdog Timer Operation ................................................................................. 412
12.3.2 Interval Timer Operation ..................................................................................... 415
12.3.3 Timing of Setting Overflow Flag (OVF)............................................................. 415
12.3.4 Timing of Setting of Watchdog Timer Overflow Flag (WOVF)......................... 416
12.4 Interrupts........................................................................................................................... 417
12.5 Usage Notes...................................................................................................................... 417
12.5.1 Contention between Timer Counter (TCNT) Write and Increment..................... 417
12.5.2 Changing Value of PSS and CKS2 to CKS0 ....................................................... 418
12.5.3 Switching between Watchdog Timer Mode and Interval Timer Mode................ 418
12.5.4 System Reset by WDTOVF Signal...................................................................... 418
12.5.5 Internal Reset in Watchdog Timer Mode............................................................. 418
12.5.6 OVF Flag Clearing in Interval Timer Mode........................................................ 419
Section 13 Serial Communication Interface (SCI) .................................................... 421
13.1 Overview........................................................................................................................... 421
13.1.1 Features................................................................................................................ 421
13.1.2 Block Diagram..................................................................................................... 423
13.1.3 Pin Configuration................................................................................................. 424
13.1.4 Register Configuration......................................................................................... 425
13.2 Register Descriptions........................................................................................................ 426
13.2.1 Receive Shift Register (RSR) .............................................................................. 426
13.2.2 Receive Data Register (RDR).............................................................................. 426
13.2.3 Transmit Shift Register (TSR)............................................................................. 427
13.2.4 Transmit Data Register (TDR)............................................................................. 427
13.2.5 Serial Mode Register (SMR)................................................................................ 428
13.2.6 Serial Control Register (SCR).............................................................................. 431
13.2.7 Serial Status Register (SSR) ................................................................................ 435
13.2.8 Bit Rate Register (BRR) ...................................................................................... 439
13.2.9 Smart Card Mode Register (SCMR).................................................................... 447
13.2.10 Module Stop Control Register B (MSTPCRB).................................................... 448
13.3 Operation .......................................................................................................................... 450
13.3.1 Overview.............................................................................................................. 450
13.3.2 Operation in Asynchronous Mode....................................................................... 452
13.3.3 Multiprocessor Communication Function............................................................ 463
13.3.4 Operation in Clocked Synchronous Mode........................................................... 471
13.4 SCI Interrupts.................................................................................................................... 480
13.5 Usage Notes...................................................................................................................... 482
Section 14 Smart Card Interface ..................................................................................... 491
14.1 Overview........................................................................................................................... 491
Rev. 5.00 Jan 10, 2006 page xviii of xxiv
14.1.1 Features................................................................................................................ 491
14.1.2 Block Diagram..................................................................................................... 492
14.1.3 Pin Configuration................................................................................................. 493
14.1.4 Register Configuration......................................................................................... 494
14.2 Register Descriptions........................................................................................................ 495
14.2.1 Smart Card Mode Register (SCMR).................................................................... 495
14.2.2 Serial Status Register (SSR) ................................................................................ 496
14.2.3 Serial Mode Register (SMR)................................................................................ 498
14.2.4 Serial Control Register (SCR).............................................................................. 500
14.3 Operation .......................................................................................................................... 501
14.3.1 Overview.............................................................................................................. 501
14.3.2 Pin Connections................................................................................................... 501
14.3.3 Data Format ......................................................................................................... 503
14.3.4 Register Settings .................................................................................................. 505
14.3.5 Clock.................................................................................................................... 507
14.3.6 Data Transfer Operations..................................................................................... 509
14.3.7 Operation in GSM Mode ..................................................................................... 516
14.3.8 Operation in Block Transfer Mode...................................................................... 517
14.4 Usage Notes...................................................................................................................... 518
Section 15 Controller Area Network (HCAN)............................................................ 523
15.1 Overview........................................................................................................................... 523
15.1.1 Features................................................................................................................ 523
15.1.2 Block Diagram..................................................................................................... 524
15.1.3 Pin Configuration................................................................................................. 525
15.1.4 Register Configuration......................................................................................... 526
15.2 Register Descriptions........................................................................................................ 528
15.2.1 Master Control Register (MCR)........................................................................... 528
15.2.2 General Status Register (GSR) ............................................................................ 530
15.2.3 Bit Configuration Reg ister (BCR) ....................................................................... 53 1
15.2.4 Mailbox Configuration Register (MBCR) ........................................................... 534
15.2.5 Transmit Wait Register (TXPR).......................................................................... 535
15.2.6 Transmit Wait Cancel Register (TXCR).............................................................. 536
15.2.7 Transmit Acknowledge Register (TXACK) ........................................................ 537
15.2.8 Abort Acknowledge Register (ABACK) ............................................................. 538
15.2.9 Receive Complete Register (RXPR).................................................................... 539
15.2.10 Remote Request Register (RFPR)........................................................................ 540
15.2.11 Interrupt Register (IRR)....................................................................................... 541
15.2.12 Mailbox Interrupt Mask Register (MBIMR)........................................................ 545
15.2.13 Interrupt Mask Register (IMR)............................................................................ 546
15.2.14 Receive Error Counter (REC).............................................................................. 549
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15.2.15 Transmit Error Counter (TEC)............................................................................. 549
15.2.16 Unread Message Status Register (UMSR)........................................................... 550
15.2.17 Local Acceptance Filter Masks (LAFML, LAFMH)........................................... 551
15.2.18 Message Control (MC0 to MC15)....................................................................... 553
15.2.19 Message Data (MD0 to MD15) ........................................................................... 557
15.2.20 Module Stop Control Register C (MSTPCRC).................................................... 559
15.3 Operation .......................................................................................................................... 560
15.3.1 Hardware and Software Resets ............................................................................ 560
15.3.2 Initialization after Hardware Reset...................................................................... 563
15.3.3 Transmit Mode..................................................................................................... 568
15.3.4 Receive Mode...................................................................................................... 574
15.3.5 HCAN Sleep Mode.............................................................................................. 579
15.3.6 HCAN Halt Mode................................................................................................ 582
15.3.7 Interrupt Interface................................................................................................ 583
15.3.8 DTC Interface...................................................................................................... 584
15.4 CAN Bus Interface............................................................................................................ 585
15.5 Usage Notes...................................................................................................................... 585
Section 16 A/D Converter................................................................................................. 589
16.1 Overview........................................................................................................................... 589
16.1.1 Features................................................................................................................ 589
16.1.2 Block Diagram..................................................................................................... 590
16.1.3 Pin Configuration................................................................................................. 591
16.1.4 Register Configuration......................................................................................... 592
16.2 Register Descriptions........................................................................................................ 593
16.2.1 A/D Data Registers A to D (ADDRA to ADDRD).............................................. 593
16.2.2 A/D Control/Status Register (ADCSR) ............................................................... 594
16.2.3 A/D Control Register (ADCR) ............................................................................ 597
16.2.4 Module Stop Control Register A (MSTPCRA) ................................................... 598
16.3 Interface to Bus Master..................................................................................................... 599
16.4 Operation .......................................................................................................................... 600
16.4.1 Single Mode (SCAN = 0) .................................................................................... 600
16.4.2 Scan Mode (SCAN = 1)....................................................................................... 602
16.4.3 Input Sampling and A/D Conversion Time ......................................................... 604
16.4.4 External Trigger Input Timing............................................................................. 605
16.5 Interrupts........................................................................................................................... 606
16.6 Usage Notes...................................................................................................................... 607
Section 17 D/A Converter [Provided in the H8S/2626 Group only].................... 613
17.1 Overview........................................................................................................................... 613
17.1.1 Features................................................................................................................ 613
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17.1.2 Block Diagram..................................................................................................... 614
17.1.3 Pin Configuration................................................................................................. 615
17.1.4 Register Configuration......................................................................................... 615
17.2 Register Descriptions........................................................................................................ 616
17.2.1 D/A Data Registers 2 and 3 (DADR2, DADR3) ................................................. 616
17.2.2 D/A Control Register 23 (DACR23).................................................................... 616
17.2.3 Module Stop Control Register C (MSTPCRC).................................................... 618
17.3 Operation .......................................................................................................................... 618
Section 18 RAM .................................................................................................................. 621
18.1 Overview........................................................................................................................... 621
18.1.1 Block Diagram..................................................................................................... 621
18.1.2 Register Configuration......................................................................................... 622
18.2 Register Descriptions........................................................................................................ 622
18.2.1 System Control Register (SYSCR)...................................................................... 622
18.3 Operation .......................................................................................................................... 623
18.4 Usage Notes...................................................................................................................... 623
Section 19 ROM (Preliminary)........................................................................................ 625
19.1 Features............................................................................................................................. 625
19.2 Overview........................................................................................................................... 626
19.2.1 Block Diagram..................................................................................................... 626
19.2.2 Mode Transitions................................................................................................. 627
19.2.3 On-Board Programming Modes........................................................................... 628
19.2.4 Flash Memory Emulation in RAM ...................................................................... 630
19.2.5 Differences between Boot Mode and User Program Mode ................................. 631
19.2.6 Block Configuration ............................................................................................ 632
19.3 Pin Configuration.............................................................................................................. 632
19.4 Register Configuration...................................................................................................... 633
19.5 Register Descriptions........................................................................................................ 633
19.5.1 Flash Memory Control Register 1 (FLMCR1)..................................................... 633
19.5.2 Flash Memory Control Register 2 (FLMCR2)..................................................... 637
19.5.3 Erase Block Register 1 (EBR1) ........................................................................... 638
19.5.4 Erase Block Register 2 (EBR2) ........................................................................... 638
19.5.5 RAM Emulation Register (RAMER)................................................................... 639
19.5.6 Flash Memory Power Control Register (FLPWCR)............................................ 641
19.5.7 Serial Control Register X (SCRX)....................................................................... 641
19.6 On-Board Programming Modes........................................................................................ 642
19.6.1 Boot Mode........................................................................................................... 643
19.6.2 User Program Mode............................................................................................. 647
19.7 Flash Memory Programming/Erasing............................................................................... 649
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19.7.1 Program Mode ..................................................................................................... 651
19.7.2 Program-Verify Mode.......................................................................................... 652
19.7.3 Erase Mode.......................................................................................................... 656
19.7.4 Erase-Verify Mode .............................................................................................. 656
19.8 Protection.......................................................................................................................... 658
19.8.1 Hardware Protection............................................................................................ 658
19.8.2 Software Protection.............................................................................................. 659
19.8.3 Error Protection.................................................................................................... 660
19.9 Flash Memory Emulation in RAM ................................................................................... 662
19.10 Interrupt Handling when Programming/Erasing Flash Memory....................................... 664
19.11 Flash Memory Programmer Mode.................................................................................... 664
19.11.1 Socket Adapter Pin Correspondence Diagram..................................................... 665
19.11.2 Programmer Mode Operation.............................................................................. 667
19.11.3 Memory Read Mode............................................................................................ 668
19.11.4 Auto-Program Mode............................................................................................ 672
19.11.5 Auto-Erase Mode................................................................................................. 674
19.11.6 Status Read Mode................................................................................................ 676
19.11.7 Status Polling....................................................................................................... 677
19.11.8 Programmer Mode Transition Time .................................................................... 677
19.11.9 Notes on Memory Programming.......................................................................... 678
19.12 Flash Memory and Power-Down States............................................................................ 679
19.12.1 Note on Power-Down States................................................................................ 679
19.13 Flash Memory Programming and Erasing Precautions..................................................... 680
19.14 Note on Switching from F-ZTAT Version to Mask ROM Version.................................. 685
Section 20 Clock Pulse Generator.................................................................................. 687
20.1 Overview........................................................................................................................... 687
20.1.1 Block Diagram..................................................................................................... 688
20.1.2 Register Configuration......................................................................................... 688
20.2 Register Descriptions........................................................................................................ 689
20.2.1 System Clock Control Register (SCKCR)........................................................... 689
20.2.2 Low-Power Control Register (LPWRCR) ........................................................... 690
20.3 Oscillator........................................................................................................................... 691
20.3.1 Connecting a Crystal Resonator........................................................................... 691
20.3.2 External Clock Input............................................................................................ 694
20.4 PLL Circuit ....................................................................................................................... 696
20.5 Medium-Speed Clock Divider .......................................................................................... 696
20.6 Bus Master Clock Selection Circuit.................................................................................. 697
20.7 Subclock Oscillator (H8S/2626 Group Only)................................................................... 697
20.8 Subclock Waveform Shaping Circuit (H8S/2626 Group Only)........................................ 698
20.9 Note on Crystal Resonator................................................................................................ 698
Rev. 5.00 Jan 10, 2006 page xxii of xxiv
Section 21A Power-Down Modes [H8S/2623 Group]............................................. 699
21A.1 Overview....................................................................................................................... 699
21A.1.1 Register Configuration.................................................................................. 702
21A.2 Register Descriptions..................................................................................................... 702
21A.2.1 Standby Control Register (SBYCR)............................................................. 702
21A.2.2 System Clock Control Register (SCKCR).................................................... 704
21A.2.3 Low-Power Control Register (LPWRCR).................................................... 705
21A.2.4 Module Stop Control Register (MSTPCR)................................................... 706
21A.3 Medium-Speed Mode.................................................................................................... 707
21A.4 Sleep Mode.................................................................................................................... 708
21A.4.1 Sleep Mode................................................................................................... 708
21A.4.2 Exiting Sleep Mode ...................................................................................... 708
21A.5 Module Stop Mode........................................................................................................ 708
21A.5.1 Module Stop Mode....................................................................................... 708
21A.5.2 Usage Notes.................................................................................................. 710
21A.6 Software Standby Mode................................................................................................ 710
21A.6.1 Software Standby Mode................................................................................ 710
21A.6.2 Clearing Software Standby Mode................................................................. 710
21A.6.3 Setting Oscillation Stabilizat ion Time after Clearing Software
Standby Mode............................................................................................... 711
21A.6.4 Software Standby Mode Application Example ............................................. 712
21A.6.5 Usage Notes.................................................................................................. 713
21A.7 Hardware Standby Mode............................................................................................... 713
21A.7.1 Hardware Standby Mode.............................................................................. 713
21A.7.2 Hardware Standby Mode Timing.................................................................. 714
21A.8 φ Clock Output Disabling Function............................................................................... 714
Section 21B Power-Down Modes [H8S/2626 Group].............................................. 715
21B.1 Overview....................................................................................................................... 715
21B.1.1 Register Configuration .................................................................................. 719
21B.2 Register Descriptions..................................................................................................... 719
21B.2.1 Standby Control Register (SBYCR)............................................................. 719
21B.2.2 System Clock Control Register (SCKCR).................................................... 721
21B.2.3 Low-Power Control Register (LPWRCR).................................................... 722
21B.2.4 Timer Control/Status Register (TCSR)......................................................... 725
21B.2.5 Module Stop Control Register (MSTPCR)................................................... 726
21B.3 Medium-Speed Mode.................................................................................................... 727
21B.4 Sleep Mode.................................................................................................................... 728
21B.4.1 Sleep Mode................................................................................................... 728
21B.4.2 Exiting Sleep Mode ...................................................................................... 728
21B.5 Module Stop Mode........................................................................................................ 728
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21B.5.1 Module Stop Mode....................................................................................... 728
21B.5.2 Usage Notes.................................................................................................. 730
21B.6 Software Standby Mode................................................................................................ 730
21B.6.1 Software Standby Mode................................................................................ 730
21B.6.2 Clearing Software Standby Mode................................................................. 730
21B.6.3 Settin g Oscillation Stabilization Time after Clearing Software
Standby Mode............................................................................................... 731
21B.6.4 Software Standby Mode Application Example ............................................. 732
21B.6.5 Usage Notes.................................................................................................. 733
21B.7 Hardware Standby Mode............................................................................................... 733
21B.7.1 Hardware Standby Mode.............................................................................. 733
21B.7.2 Hardware Standby Mode Timing.................................................................. 734
21B.8 Watch Mode.................................................................................................................. 734
21B.8.1 Watch Mode.................................................................................................. 734
21B.8.2 Exiting Watch Mode..................................................................................... 735
21B.8.3 Notes............................................................................................................. 735
21B.9 Sub-Sleep Mode............................................................................................................ 736
21B.9.1 Sub-Sleep Mode............................................................................................ 736
21B.9.2 Exiting Sub-Sleep Mode............................................................................... 736
21B.10 Sub-Active Mode.......................................................................................................... 737
21B.10.1 Sub-Active Mode......................................................................................... 737
21B.10.2 Exiting Sub-Active Mode............................................................................ 737
21B.11 Direct Transitions.......................................................................................................... 738
21B.11.1 Overview of Direct Transitions.................................................................... 738
21B.12 φ Clock Output Disabling Function .............................................................................. 738
21B.13 Usage Notes................................................................................................................... 739
Section 22 Electrical Characteristics (Preliminary)................................................... 741
22.1 Absolute Maximum Ratings ............................................................................................. 741
22.2 DC Characteristics ............................................................................................................ 742
22.3 AC Characteristics ............................................................................................................ 745
22.3.1 Clock Timing....................................................................................................... 746
22.3.2 Control Signal Timing ......................................................................................... 747
22.3.3 Bus Timing .......................................................................................................... 749
22.3.4 Timing of On-Chip Supporting Modules............................................................. 756
22.4 A/D Conversion Characteristics........................................................................................ 760
22.5 D/A Conversion Characteristics........................................................................................ 760
22.6 Flash Memory Characteristics........................................................................................... 761
22.7 Usage Note................................................................................................................. ....... 762
Rev. 5.00 Jan 10, 2006 page xxiv of xxiv
Appendix A Instruction Set.............................................................................................. 763
A.1 Instruction List.................................................................................................................. 763
A.2 Instruction Codes.............................................................................................................. 787
A.3 Operation Code Map......................................................................................................... 802
A.4 Number of States Required for Instruction Execution...................................................... 806
A.5 Bus States during Instruction Execution........................................................................... 817
A.6 Condition Code Modification ........................................................................................... 831
Appendix B Internal I/O Register................................................................................... 837
B.1 Address ............................................................................................................................. 837
B.2 Functions........................................................................................................................... 852
Appendix C I/O Port Block Diagrams......................................................................... 1008
C.1 Port 1 Block Diagrams.................................................................................................... 1008
C.2 Port 4 Block Diagram ..................................................................................................... 1014
C.3 Port 9 Block Diagram ..................................................................................................... 1014
C.4 Port A Block Diagrams................................................................................................... 1015
C.5 Port B Block Diagram..................................................................................................... 1020
C.6 Port C Block Diagrams ................................................................................................... 1021
C.7 Port D Block Diagram..................................................................................................... 1025
C.8 Port E Block Diagram..................................................................................................... 1026
C.9 Port F Block Diagrams.................................................................................................... 1027
Appendix D Pin States...................................................................................................... 1036
D.1 Port States in Each Mode................................................................................................ 1036
Appendix E Timing of Transition to and Recovery from Hardware
Standby Mode............................................................................................. 1039
Appendix F Product Code Lineup................................................................................ 1040
Appendix G Package Dimensions................................................................................. 1041
Section 1 Overview
Rev. 5.00 Jan 10, 2006 page 1 of 1042
REJ09B0275-0500
Section 1 Overview
1.1 Overview
The H8S/2626 Group and H8S/2623 Group are series of microcomputers (MCUs) that integrate
peripheral functions required for system configuration together with an H8S/2600 CPU employing
an original Renesas architecture.
The H8S/2600 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general
registers and a concise, optimized instruction set designed for high-speed operation, and can
address a 16-Mbyte linear address space. The instruction set is upward-compatible with H8/300
and H8/300H CPU in structions at the object-code level, facilitating migration from the H8/300,
H8/300L, or H8/300H Series.
On-chip peripheral functions required for system configuration include a data transfer controller
(DTC) bus master, ROM and RAM, a16-bit timer-pulse unit (TPU), programmable pulse
generator (PPG), watchdog timer (WDT), serial communication interface (SCI), controller area
network (HCAN), A/D converter, D/A converter (H8S/2626 Group only), and I/O ports.
The on-chip ROM is 256-kbyte flash memory (F-ZTAT™)* or 256-, 128-, or 64-kbyte mask
ROM. The ROM is connected to the CPU by a 16-bit d ata bus, enabling both byte and word data
to be accessed in one state. Instruction fetching has been speeded up, and processing speed
increased.
Four operating modes, modes 4 to 7, are provided, and there is a choice of single-chip mode or
external expansion mode.
The features of the H8S/2626 Group and H8S/2623 Group are shown in table 1.1.
Note: * F-ZTAT is a trademark of Renesas Technology Corp.
Section 1 Overview
Rev. 5.00 Jan 10, 2006 page 2 of 1042
REJ09B0275-0500
Table 1.1 Overview
Item Specifications
CPU • General-register machine
Sixteen 16-bit general registers
(also usable as sixteen 8-bit registers or eight 32-bit registers)
• High-speed operation suitable for realtime control
Maximum operating frequency: 20 MHz
High-speed arithmetic operations
8/16/32-bit register-register add/subtract: 50 ns
16 × 16-bit register-register multiply: 200 ns
16 × 16 + 42-bit multiply and accumulate: 200 ns
32 ÷ 16-bit register-register divide: 1000 ns
• Instruction set suitable for high-speed operation
69 basic instructions
8/16/32-bit move/arithmetic and logic instructions
Unsigned/signed multiply and divide instructions
Multiply-and accumulate instruction
Powerful bit-manipu lati on instructions
• Two CPU operating modes
Normal mode: 64-kbyte address space
(Not available in the H8S/2626 Group or H8S/2623 Group)
Advanced mode: 16-Mbyte address space
Bus controller • Address space divided into 8 areas, with bus specific ations settable
independently for each area
• Choice of 8-bit or 16-bit access space for each area
• 2-state or 3-state access space can be designated for each area
• Number of program wait states can be set for each area
• Burst ROM directly connectable
• External bus release function
PC break
controller • Supports debugging functions by means of PC break interrupts
• Two break channels
Section 1 Overview
Rev. 5.00 Jan 10, 2006 page 3 of 1042
REJ09B0275-0500
Item Specifications
Data transfer
controller (DTC) • Can be activated by internal interrupt or software
• Multiple transfers or multiple types of transfer possible for one activation
source
• Transfer possible in repeat mode, block transfer mode, etc.
• Request can be sent to CPU for interrupt that activated DTC
16-bit timer-pulse
unit (TPU) • 6-channel 16-bit timer
• Pulse input/output processing capability for up to 16 pins
• Automatic 2-phase encoder count capability
Programmable
pulse generator
(PPG)
• Maximum 8-bit pulse output possible with TPU as time base
• Output trigger selectable in 4-bit groups
• Non-overlap margin can be set
• Direct output or invers e output set tin g
Watchdog timer
(WDT), 2 channels
(H8S/2626 Group)
• Watchdog tim er or interva l timer selectable
• Subclock operation possible (one channel only)
Watchdog timer
(WDT), 1 channel
(H8S/2623 Group)
• Watchdog tim er or interva l timer selectable
Serial communi-
cation interface
(SCI), 3 channels
(SCI0 to SCI2)
• Asynchronous mode or synchronous mode selectable
• Multiprocessor communication function
• Smart card interface function
Controller area
network (HCAN), 1
channel
• CAN: Ver. 2.0B compliant
• Buffer size: 15 transmit/receive buffers, one transmit-only buffer
• Receive message filtering
A/D converter • Resolution: 10 bits
• Input: 16 channe ls
• 13.3 µs minimum conversion time (at 20 MHz operation)
• Single or scan mode selectable
• Sample-and-hold function
• A/D conversion can be activated by external trigger or timer trigger
Section 1 Overview
Rev. 5.00 Jan 10, 2006 page 4 of 1042
REJ09B0275-0500
Item Specifications
D/A converter
(H8S/2626 Group
only)
• Resolution: 8 bits
• Output: 2 channels
I/O ports
(H8S/2626 Group) • 51 input/output pins, 17 input-only pins
I/O ports
(H8S/2623 Group) • 53 input/output pins, 17 input-only pins
Memory • Flash memory or masked ROM
• High-speed static RAM
Product Name ROM RAM
H8S/2626, H8S/ 2623 256 kbytes 12 kbytes
H8S/2625, H8S/ 2622 128 kbytes 8 kbytes
H8S/2624, H8S/ 2621 64 kbytes 4 kbytes
Interrupt controller • Seven external interrupt pins (NMI, IRQ0 to IRQ5)
• Internal interrupt sources
H8S/2626: 48
H8S/2623: 47
• Eight priority lev el s settable
Power-down state • Medium-speed mode
• Sleep mode
• Module stop mode
• Software standb y mode
• Hardware stan dby mode
• Subclock operation (H8S/2626 Group only)
Section 1 Overview
Rev. 5.00 Jan 10, 2006 page 5 of 1042
REJ09B0275-0500
Item Specifications
Operating modes • Four MCU operating modes
External Data Bus
Mode
CPU
Operating
Mode Description On-Chip
ROM Initial
Width Max.
Width
4 Advanced On-chip ROM disabled
expansion mode Disabled 16 bits 16 bits
5 On-chip ROM disabled
expansion mode Disabled 8 bits 16 bits
6 On-chip ROM enabled
expansion mode Enabled 8 bits 16 bits
7 Single-c hi p mode Enabled — —
Clock pulse
generator • Built-in PLL circuit (×1, ×2, ×4)
• Input clock frequency: 2 to 20 MHz
Package • 100-pin plastic QFP (FP-100B)
Product lineup Model
Mask ROM Version F-ZTAT Version ROM/RAM (Bytes) Package
HD6432626
HD6432623 HD64F2626
HD64F2623 256 k/12 k FP-100B
HD6432625
HD6432622 — 128 k/8 k FP-100B
HD6432624
HD6432621 — 64 k/4 k FP-100B
Section 1 Overview
Rev. 5.00 Jan 10, 2006 page 6 of 1042
REJ09B0275-0500
1.2 Internal Block Diagram
Figures 1.1 and 1.2 show internal block diagrams of the H8S/2623 Group and H8S/2626 Group.
Internal data bus
Peripheral data bus
Peripheral address bus
PD7/D15
PD6/D14
PD5/D13
PD4/D12
PD3/D11
PD2/D10
PD1/D9
PD0/D8
Port D
PE7/D7
PE6/D6
PE5/D5
PE4/D4
PE3/D3
PE2/D2
PE1/D1
PE0/D0
PVCC1
PVCC2
PVCC3
PVCC4
VCC
VCC
VSS
VSS
VSS
VSS
VSS
PA5
PA4
PA3/A19/SCK2
PA2/A18/RxD2
PA1/A17/TxD2
PA0/A16
PB7/A15/TIOCB5
PB6/A14/TIOCA5
PB5/A13/TIOCB4
PB4/A12/TIOCA4
PB3/A11/TIOCD3
PB2/A10/TIOCC3
PB1/A9/TIOCB3
PB0/A8/TIOCA3
PC7/A7
PC6/A6
PC5/A5/SCK1/IRQ
5
PC4/A4/RxD1
PC3/A3/TxD1
PC2/A2/SCK0/IRQ
4
PC1/A1/RxD0
PC0/A0/TxD0
P97/AN15
P96/AN14
P95/AN13
P94/AN12
P93/AN11
P92/AN10
P91/AN9
P90/AN8
P47/AN7
P46/AN6
P45/AN5
P44/AN4
P43/AN3
P42/AN2
P41/AN1
P40/AN0
HRxD
HTxD
Vref
AVCC
AVSS
P17/PO15/TIOCB2/TCLKD
P16/PO14/TIOCA2/IRQ1
P15/PO13/TIOCB1/TCLKC
P14/PO12/TIOCA1/IRQ0
P13/PO11/TIOCD0/TCLKB/A23
P12/PO10/TIOCC0/TCLKA/A22
P11/PO9/TIOCB0/A21
P10/PO8/TIOCA0/A20
PF7/φ
PF6/AS
PF5/RD
PF4/HWR
PF3/LWR/ADTRG/IRQ3
PF2/WAIT/BREQO
PF1/BACK
PF0/BREQ/IRQ2
ROM
(Mask ROM,
flash memory)
PC break controller
(2 channels)
RAM
WDT × 1 channel
TPU
SCI × 3 channels
HCAN × 1 channel
A/D converter
PPG
MD2
MD1
MD0
EXTAL
XTAL
PLLVCC
PLLCAP
PLLVSS
STBY
RES
WDTOVF
NMI
FWE
*
H8S/2600 CPU
DTC
Interrupt controller
Port 4Port 1
Internal address bus
Note: * The FWE pin is used only in the flash memory version.
Port E
Port APort BPort CPort 9
Bus controller
Clock pulse
generator
PLL
Port F
Figure 1.1 Internal Block Diagram (H8S/2623 Group)
Section 1 Overview
Rev. 5.00 Jan 10, 2006 page 7 of 1042
REJ09B0275-0500
Internal data bus
Peripheral data bus
Peripheral address bus
PD7/D15
PD6/D14
PD5/D13
PD4/D12
PD3/D11
PD2/D10
PD1/D9
PD0/D8
Port D
PE7/D7
PE6/D6
PE5/D5
PE4/D4
PE3/D3
PE2/D2
PE1/D1
PE0/D0
PVCC1
PVCC2
PVCC3
PVCC4
VCC
VCC
VSS
VSS
VSS
VSS
VSS
PA3/A19/SCK2
PA2/A18/RxD2
PA1/A17/TxD2
PA0/A16
PB7/A15/TIOCB5
PB6/A14/TIOCA5
PB5/A13/TIOCB4
PB4/A12/TIOCA4
PB3/A11/TIOCD3
PB2/A10/TIOCC3
PB1/A9/TIOCB3
PB0/A8/TIOCA3
PC7/A7
PC6/A6
PC5/A5/SCK1/IRQ
5
PC4/A4/RxD1
PC3/A3/TxD1
PC2/A2/SCK0/IRQ
4
PC1/A1/RxD0
PC0/A0/TxD0
P97/AN15/DA3
P96/AN14/DA2
P95/AN13
P94/AN12
P93/AN11
P92/AN10
P91/AN9
P90/AN8
P47/AN7
P46/AN6
P45/AN5
P44/AN4
P43/AN3
P42/AN2
P41/AN1
P40/AN0
HRxD
HTxD
Vref
AVCC
AVSS
P17/PO15/TIOCB2/TCLKD
P16/PO14/TIOCA2/IRQ1
P15/PO13/TIOCB1/TCLKC
P14/PO12/TIOCA1/IRQ0
P13/PO11/TIOCD0/TCLKB/A23
P12/PO10/TIOCC0/TCLKA/A22
P11/PO9/TIOCB0/A21
P10/PO8/TIOCA0/A20
PF7/φ
PF6/AS
PF5/RD
PF4/HWR
PF3/LWR/ADTRG/IRQ3
PF2/WAIT/BREQO
PF1/BACK
PF0/BREQ/IRQ2
ROM
(mask ROM or
flash memory)
PC break controller
(2 channels)
RAM
WDT × 2 channels
TPU
SCI × 3 channels
HCAN × 1 channel
A/D converter
PPG
MD2
MD1
MD0
OSC1
OSC2
EXTAL
XTAL
PLLVCC
PLLCAP
PLLVSS
STBY
RES
WDTOVF
NMI
FWE*
H8S/2600 CPU
DTC
Interrupt controller
Port 4Port 1
Internal address bus
Note: * The FWE pin is provided in the flash memory version only.
Port E
D/A converter
PLL
Port APort BPort CPort 9
Port F
Clock pulse
generator
Bus controller
Figure 1.2 Internal Block Diagram (H8S/2626 Group)
Section 1 Overview
Rev. 5.00 Jan 10, 2006 page 8 of 1042
REJ09B0275-0500
1.3 Pin Descriptions
1.3.1 Pin Arrangement
Figures 1.3 and 1.4 show pin arrangements of the H8S/2623 Group and H8S/2626 Group.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
Top view
(FP-100B)
P13/PO11/TIOCD0/TCLKB/A23
P14/PO12/TIOCA1/IRQ0
P15/PO13/TIOCB1/TCLKC
P16/PO14/TIOCA2/IRQ1
P17/PO15/TIOCB2/TCLKD
VCC
HTxD
VSS
HRxD
PE0/D0
PE1/D1
PE2/D2
PE3/D3
PE4/D4
VSS
PE5/D5
PVCC1
PE6/D6
PE7/D7
PD0/D8
PD1/D9
PD2/D10
PD3/D11
PD4/D12
PD5/D13
PA4
PA3/A19/SCK2
PA2/A18/RxD2
PA1/A17/TxD2
PA0/A16
PB7/A15/TIOCB5
PB6/A14/TIOCA5
PB5/A13/TIOCB4
PB4/A12/TIOCA4
PB3/A11/TIOCD3
PB2/A10/TIOCC3
PVCC2
PB1/A9/TIOCB3
VSS
PB0/A8/TIOCA3
PC7/A7
PC6/A6
PC5/A5/SCK1/IRQ
5
PC4/A4/RxD1
PC3/A3/TxD1
PC2/A2/SCK0/IRQ
4
PC1/A1/RxD0
PC0/A0/TxD0
PD7/D15
PD6/D14
PF0/BREQ/IRQ2
PF1/BACK
PF2/WAIT/BREQO
PF3/LWR/ADTRG/IRQ
3
PF4/HWR
PF5/PD
PF6/AS
PF7/φ
FWE
EXTAL
VSS
XTAL
VCC
STBY
NMI
RES
PLLVCC
PLLCAP
PLLVSS
MD2
MD1
VSS
MD0
PVCC3
PA5
AVCC
Vref
P40/AN0
P41/AN1
P42/AN2
P43/AN3
P44/AN4
P45/AN5
P46/AN6
P47/AN7
P90/AN8
P91/AN9
P92/AN10
P93/AN11
P94/AN12
P95/AN13
P96/AN14
P97/AN15
AVSS
VSS
WDTOVF
PVCC4
P10/PO8/TIOCA0/A20
P11/PO9/TIOCB0/A21
P12/PO10/TIOCC0/TCLKA/A22
Figure 1.3 Pin Arrangement (FP-100B: Top View) (H8S/2623 Group)
Section 1 Overview
Rev. 5.00 Jan 10, 2006 page 9 of 1042
REJ09B0275-0500
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
Top view
(FP-100B)
P13/PO11/TIOCD0/TCLKB/A23
P14/PO12/TIOCA1/IRQ0
P15/PO13/TIOCB1/TCLKC
P16/PO14/TIOCA2/IRQ1
P17/PO15/TIOCB2/TCLKD
VCC
HTxD
VSS
HRxD
PE0/D0
PE1/D1
PE2/D2
PE3/D3
PE4/D4
VSS
PE5/D5
PVCC1
PE6/D6
PE7/D7
PD0/D8
PD1/D9
PD2/D10
PD3/D11
PD4/D12
PD5/D13
OSC1
PA3/A19/SCK2
PA2/A18/RxD2
PA1/A17/TxD2
PA0/A16
PB7/A15/TIOCB5
PB6/A14/TIOCA5
PB5/A13/TIOCB4
PB4/A12/TIOCA4
PB3/A11/TIOCD3
PB2/A10/TIOCC3
PVCC2
PB1/A9/TIOCB3
VSS
PB0/A8/TIOCA3
PC7/A7
PC6/A6
PC5/A5/SCK1/IRQ
5
PC4/A4/RxD1
PC3/A3/TxD1
PC2/A2/SCK0/IRQ
4
PC1/A1/RxD0
PC0/A0/TxD0
PD7/D15
PD6/D14
PF0/BREQ/IRQ2
PF1/BACK/BUZZ
PF2/WAIT/BREQO
PF3/LWR/ADTRG/IRQ
3
PF4/HWR
PF5/PD
PF6/AS
PF7/φ
FWE
EXTAL
VSS
XTAL
VCC
STBY
NMI
RES
PLLVCC
PLLCAP
PLLVSS
MD2
MD1
VSS
MD0
PVCC3
OSC2
AVCC
Vref
P40/AN0
P41/AN1
P42/AN2
P43/AN3
P44/AN4
P45/AN5
P46/AN6
P47/AN7
P90/AN8
P91/AN9
P92/AN10
P93/AN11
P94/AN12
P95/AN13
P96/AN14/DA2
P97/AN15/DA3
AVSS
VSS
WDTOVF
PVCC4
P10/PO8/TIOCA0/A20
P11/PO9/TIOCB0/A21
P12/PO10/TIOCC0/TCLKA/A22
Figure 1.4 Pin Arrangement (FP-100B: Top View) (H8S/2626 Group)