PIC24F16KA102 FAMILY PIC24F16KA102 Family Silicon Errata and Data Sheet Clarification The PIC24F16KA102 family devices that you have received conform functionally to the current Device Data Sheet (DS39927B), except for the anomalies described in this document. The silicon issues discussed in the following pages are for silicon revisions with the Device and Revision IDs listed in Table 1. The silicon issues are summarized in Table 2. The errata described in this document will be addressed in future revisions of the PIC24F16KA102 family silicon. Note: This document summarizes all silicon errata issues from all revisions of silicon, previous as well as current. Only the issues indicated in the last column of Table 2 apply to the current silicon revision (B0). Data Sheet clarifications and corrections start on page 7, following the discussion of silicon issues. The silicon revision level can be identified using the current version of MPLAB(R) IDE and Microchip's programmers, debuggers and emulation tools, which are available at the Microchip corporate web site (www.microchip.com). TABLE 1: Device ID(1) PIC24F08KA101 0B08h PIC24F08KA102 0B0Ah PIC24F16KA101 0B01h PIC24F16KA102 0B03h 2: 1. 2. 3. 4. Using the appropriate interface, connect the device to the MPLAB ICD 2 programmer/debugger or PICkitTM 3. From the main menu in MPLAB IDE, select Configure>Select Device and then select the target part number in the dialog box. Select the MPLAB hardware tool (Debugger>Select Tool). Perform a "Connect" operation to the device (Debugger>Connect). Depending on the development tool used, the part number and Device Revision ID value appear in the Output window. Note: If you are unable to extract the silicon revision level, please contact your local Microchip sales office for assistance. The DEVREV values for the various PIC24F16KA102 family silicon revisions are shown in Table 1. SILICON DEVREV VALUES Part Number Note 1: For example, to identify the silicon revision level using MPLAB IDE in conjunction with MPLAB ICD 2 or PICkitTM 3: Revision ID for Silicon Revision(2) A5 A6 A7 B0 05h 06h 07h 08h The Device IDs (DEVID and DEVREV) are located at the last two implemented addresses in program memory. They are shown in hexadecimal in the format, "DEVID DEVREV". Refer to the "PIC24FXXKAXXX Flash Programming Specification" (DS39919) for detailed information on Device and Revision IDs for your specific device. 2011 Microchip Technology Inc. DS80473G-page 1 PIC24F16KA102 FAMILY TABLE 2: SILICON ISSUE SUMMARY Module Feature CTMU -- Item Number Affected Revisions(1) Issue Summary A5 A6 A7 1. Module operates in Sleep mode. X X X X X X X Resets BOR 2. Inadvertent Reset when disabling/enabling BOR. X Core ICSPTM 3. Unable to use PGC/PGD pair under certain conditions. X Core Deep Sleep 4. Failure to avoid Deep Sleep entry. X Memory Code Protection 5. No direct jump to Boot Sector from Reset Vector. X -- 6. Change in maximum VIOFF. X X X SPI Enhanced Buffer mode 7. Errors when polling SPITBF flag. X X X I/O Ports PORTA and PORTB 8. Under certain conditions, functionality for RB0 and RA0 pins do not work correctly. X X X I/O Ports PORTA and PORTB 9. Under certain conditions, functionality for RB2 does not work correctly. X X X Core Low-Voltage BOR 10. LPBOR configuration results in ambiguous Resets. X X X -- 11. Output polarity inversion also inverts edge-detect sensing. X X X 12. Instruction execution glitches following DOZE bit changes. X X X 13. Module continues to draw current when disabled. X X X Comparator Comparator Core Doze mode A/D Converter Note 1: -- B0 X X Only those issues indicated in the last column apply to the current silicon revision. DS80473G-page 2 2011 Microchip Technology Inc. PIC24F16KA102 FAMILY Silicon Errata Issues Note: This document summarizes all silicon errata issues from all revisions of silicon, previous as well as current. Only the issues indicated by the shaded column in the following tables apply to the current silicon revision (B0). 3. Module: Core (ICSPTM) Under certain circumstances, a PGC/PGD pin pair may not function to enter ICSP Programming mode. This has been observed only when both the following conditions are met: a) Pin, RA5, is configured as MCLR (FPOR<5> = 1), and The pins of the PGEC/PGED pair were configured as digital outputs (corresponding TRIS bit cleared) in software. b) 1. Module: CTMU The CTMU and its current source may continue to operate in Sleep mode. This results in current consumption in excess of the specifications for Sleep. Work around Clear the CTMU Enable bit (CTMUCON<15>) prior to entering Sleep mode. Affected Silicon Revisions A5 A6 A7 X X X B0 In these circumstances, the pins do not switch to a high-impedance state upon entry into Programming mode, but remain configured as outputs. Work around Choose a PGC/PGD pair with pins that are always configured as inputs (TRIS bits are set). Affected Silicon Revisions A5 A6 A7 B0 X 2. Module: Resets (BOR) A device Reset may occur if the BOR is disabled and immediately re-enabled in software (RCON<14> is cleared and then immediately set). Work around It is recommended that several NOP instructions be added to a BOR disable/enable sequence. Alternatively, place several instructions or a short routine between the instructions to disable and enable the BOR. Affected Silicon Revisions A5 A6 A7 B0 X X X X 4. Module: Core (Deep Sleep) Deep Sleep wake-up sources may be ignored if they occur just prior to entry into Deep Sleep mode. As a result, the device may enter Deep Sleep mode when it should not. Work around If possible, configure external Deep Sleep wake-up sources to repeat themselves once. If the device does enter Deep Sleep, the second occurrence of the wake-up source will wake the device. Alternatively, synchronize the entry into Deep Sleep with external wake-up sources, where possible. Affected Silicon Revisions 2011 Microchip Technology Inc. A5 A6 A7 X X X B0 DS80473G-page 3 PIC24F16KA102 FAMILY 5. Module: Memory (Code Protection) 7. Module: SPI (Enhanced Buffer Mode) When any boot segment is enabled in program memory (FBS<3:1> 111), it is not possible to jump directly from the Reset vector to any address in the boot segment. In Enhanced Buffer mode (SPI1CON2<0> = 1), polling the SPI Transmit Buffer Full bit, SPITBF (SPI1STAT<1>), may produce erroneous results. This occurs only under two circumstances: Work around a) Point the Reset vector to an address in the general segment. From there, it is possible to jump into the boot segment. b) Affected Silicon Revisions A5 A6 A7 For Master mode, this includes all combinations of the primary prescale bits (SPI11CON1<1:0>) and secondary prescale bits (SPI1CON1<4:2>) that, when combined, create an SPI sample clock divisor with a value of four or greater. B0 X Work around 6. Module: Comparator Instead of polling the SPITBF bit to test for an empty buffer (SPI1STAT<1> = 0), implement a SPI receive interrupt handler in software and add to the SPI transmit buffer in this routine. The maximum value for the input offset voltage (specification D300, VIOFF), shown in Table 29-13 of the Device Data Sheet, has changed for this silicon revision. The new value is shown in Table 3 (changes in bold). Alternatively, poll the SPI Receive Full bit, SPIRBF (SPI1STAT<0>), or the Shift Register Empty bit, SRMPT (SPI1STAT<7>), to determine when to service the SPI transmit and transmit buffers. Work around None. Affected Silicon Revisions A5 A6 A7 X X X TABLE 3: In Master mode, when the SPI divide clock is 4 or greater. In Slave mode, when the SPI sample clock is slower than 1/4 of the CPU instruction time (TCY). Affected Silicon Revisions B0 A5 A6 A7 X X X B0 COMPARATOR DC SPECIFICATIONS (PARTIAL) Param Symbol No. VIOFF DS80473G-page 4 Characteristics Input Offset Voltage Min Typ Max Units -- 20 60 mV Comments 2011 Microchip Technology Inc. PIC24F16KA102 FAMILY 8. Module: I/O Ports (PORTA and PORTB) The functions associated with port pins, RB0 and RA0, may be interconnected in unexpected ways. PORTB pin, RB0, may not operate correctly as an input if the SPI module is enabled (SPI1CON<15> = 1). Additionally, the pull-up, pull-down and the Change Notification (CN4) functionality are disabled. RB0 does operate correctly with the SPI enabled if it is configured as an output. PORTA pin, RA0, may not operate correctly as an input when the open-drain output is enabled for RB0 (ODCB<0>). RA0 will operate correctly as an output. However, when the analog input on RB0 (AN2) is enabled (AD1PCFG<2> = 0) and the SPI module is enabled, RB0 will be driven as a digital output, not as a analog input. To enable RB0 as a digital input, enable the open-drain output for RB0 (ODCB<0>) and set the latch bit (LATB<0> = 1). The Change Notification (CN4), pull-up and pull-down for this pin will function correctly as well. This work around may cause RA0 to function incorrectly. There is no known work around for RA0 as an input and RB0 with the open-drain output enabled. To enable RB0 as an analog input when SPI is enabled: Enable the open-drain output for RB0 (ODCB<0>). Set the latch bit (LATB<0> = 1). Clear TRISB<0>. Clear AD1PCFG<2>. 2. 3. 4. Note: This issue occurs in PIC24FXXKA101 (20-pin) devices only. On 20-pin devices of the PIC24F16KA102 family, the functions associated with port pins, RB2 and RA2, may be interconnected in unexpected ways. PORTB pin, RB2, may not operate correctly as a digital I/O if the analog input on PORTA pin, RA2 (AN4), is enabled (AD1PCFG<4> = 0). Both the digital port, and the U1RX functionality multiplexed to RB2, are disabled. Although this issue is similar in form to silicon issue 8, it appears to be independent in its root cause. Work around None. Affected Silicon Revisions Work around 1. 9. Module: I/O Ports (PORTA and PORTB) A5 A6 A7 X X X B0 10. Module: Core (Low-Power BOR) When the Low-Power BOR (LPBOR) is enabled (FPOR<6:5> = 00), BOR events may result in a device Reset in which both the BOR and POR bits are set. This differs from the expected behavior of simply re-arming the POR circuit to ensure that a POR occurs when VDD drops below the POR threshold. Work around None. Affected Silicon Revisions Affected Silicon Revisions A5 A6 A7 X X X B0 2011 Microchip Technology Inc. A5 A6 A7 X X X B0 DS80473G-page 5 PIC24F16KA102 FAMILY 11. Module: Comparator When a comparator is programmed to trigger on certain edge-detect events (CMxCON<7:6> = 10 or 01), setting the CPOL bit (CMxCON<13> = 1) may cause the comparator to flag the opposite edge-detect event (e.g., a high-to-low edge instead of the programmed low-to-high). Work around Leave CPOL = 0. Affected Silicon Revisions A5 A6 A7 B0 X X X X 13. Module: A/D Converter Once the A/D module is enabled (AD1CON1<15> = 1), it may continue to draw extra current even if the module is later disabled (AD1CON1<15> = 0). Work around In addition to disabling the module through the ADON bit, set the corresponding PMD bit (ADC1MD, PMD1<0>) to power it down completely. Disabling the A/D module through the PMD register also disables the AD1PCFG registers, which in turn, affects the state of any port pins with analog inputs. Users should consider the effect on I/O ports and other digital peripherals on those ports when ADC1MD is used for power conservation. 12. Module: Core (Doze Mode) Operations that immediately follow any manipulations of the DOZE<2:0> or DOZEN bits (CLDIV<14:11>) may not execute properly. In particular, for instructions that operate on an SFR, data may not be read properly. Also, bits automatically cleared in hardware may not be cleared if the operation occurs during this interval. Affected Silicon Revisions A5 A6 A7 X X X B0 Work around Always insert a NOP instruction before and after either of the following: * Enabling or disabling Doze mode by setting or clearing the DOZEN bit Before or after changing the DOZE<2:0> bits * Affected Silicon Revisions A5 A6 A7 X X X DS80473G-page 6 B0 2011 Microchip Technology Inc. PIC24F16KA102 FAMILY Data Sheet Clarifications The following typographic corrections and clarifications are to be noted for the latest version of the Device Data Sheet (DS39927B): Note: 2. Module: Electrical Specifications (AC Specifications) In Table 29-25, the maximum Differential Nonlinearity specification for the A/D module (parameter AD22b) has changed. The new value is shown below (changes in bold). Corrections are shown in bold. Where possible, the original bold text formatting has been removed for clarity. 1. Module: Memory In Table 4-4, the CN9IE, CN9PUE and CN9PDE bits (CNEN1<9>, CNPU1<9> and CNPD1<9>, respectively) are not implemented on 20-pin devices. These bits are to be marked with the existing footnote 1 ("These bits are not implemented in 20-pin devices"). TABLE 29-25: ADC MODULE SPECIFICATIONS Standard Operating Conditions: 1.8V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial AC CHARACTERISTICS Param No. Symbol Characteristic Min. Typ Max. Units Conditions -1 +1.5 LSb VINL = AVSS = VREFL = 0V, AVDD = VREFH = 3V ADC Accuracy AD22b DNL Note 1: 2: Differential Nonlinearity -- 1 The ADC conversion result never decreases with an increase in the input voltage and has no missing codes. Measurements taken with external VREF+ and VREF- used as the ADC voltage reference. 2011 Microchip Technology Inc. DS80473G-page 7 PIC24F16KA102 FAMILY 3. Module: Electrical Specifications (DC Specifications) In Table 29-6, the values for parameters, DC20d and DC20e (IDD for Deep Sleep), have changed. The corrected values are shown below (changes in bold). TABLE 29-6: DC CHARACTERISTICS: OPERATING CURRENT (IDD) Standard Operating Conditions: 1.8V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial DC CHARACTERISTICS Parameter No. Typical(1) Max Units Conditions IDD Current DC20 330 -40C DS20a 330 +25C 195 A 1.8V DC20b 330 +60C DC20c 330 +85C 0.5 MIPS, FOSC = 1 MHz DC20d 590 -40C DC20e 590 +25C 365 A 3.3V DC20f 645 +60C DC20g 720 +85C Note 1: Data in "Typical" column is at 3.3V, 25C unless otherwise stated. Parameters are for design guidance only and are not tested. 2: Operating Parameters: * EC mode with clock input driven with a square wave rail-to-rail * I/O configured as outputs driven low * MCLR - VDD * WDT FSCM disabled * SRAM, program and data memory active * All PMD bits set except for modules being measured 4. Module: Electrical Specifications (DC Specifications) In Table 29-8, the typical values for the Watchdog Timer Current at 1.8V and all temperatures (parameters D61 through D61C) are changed to 0.55 A. DS80473G-page 8 5. Module: Electrical Specifications (DC Specifications) In Table 29-8, footnote 2 includes the text: "All I/Os are configured as inputs and pulled high....". This is changed to read as, "All I/Os are configured as outputs and set low....". 2011 Microchip Technology Inc. PIC24F16KA102 FAMILY 6. Module: A/D In Register 22-3, the values shown for AD1CON3<5:0> (ADCS<5:0>) are incorrect. The corrected values are shown below (changes in bold). REGISTER 22-3: AD1CON3: A/D CONTROL REGISTER 3 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ADRC -- -- SAMC4 SAMC3 SAMC2 SAMC1 SAMC0 bit 15 bit 8 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 -- -- ADCS5 ADCS4 ADCS3 ADCS2 ADCS1 ADCS0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 5-0 x = Bit is unknown ADCS<5:0>: A/D Conversion Clock Select bits 111111 = 64 * TCY 111110 = 63 * TCY * * * 000001 = 2 * TCY 000000 = TCY 2011 Microchip Technology Inc. DS80473G-page 9 PIC24F16KA102 FAMILY 7. Module: Comparators The descriptions given for the CMIDL bit (CMSTAT<15>) are incorrect. The correct descriptions are shown below (changes in bold). REGISTER 23-2: CMSTAT: COMPARATOR MODULE STATUS REGISTER R/W-0 U-0 U-0 U-0 U-0 U-0 R-0, HSC R-0, HSC CMIDL -- -- -- -- -- C2EVT C1EVT bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 R-0, HSC R-0, HSC -- -- -- -- -- -- C2OUT C1OUT bit 7 bit 0 Legend: HSC = Hardware Settable/Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 15 x = Bit is unknown CMIDL: Stop in Idle Mode bit 1 = Disable comparator interrupts when the device enters Idle mode; the module is still enabled 0 = Continue normal module operation in Idle mode 8. Module: Pin Diagrams In many places in the data sheet, the UART Baud Clock output functions, U1BCLK and U2BCLK, are shown as being multiplexed on the same pins as the UART Receive input functions (U1RX and U2RX). The Baud Clock is actually multiplexed with the UART Ready-to-Send output function (U1RTS and U2RTS) on completely different pins. This mapping is correctly described in the UART chapter, but incorrectly shown on pin diagrams and pin function listings. DS80473G-page 10 The pin diagrams from the data sheet are replaced by the pin diagrams shown in Figure 1, Figure 2 and Figure 3. Changes are noted in bold. Footnotes present in the original diagrams have been omitted here for clarity. In addition, Table 1-2 of the device data sheet is amended as shown. Footnotes in the original table have been omitted for clarity. Changes are indicated in bold. 2011 Microchip Technology Inc. PIC24F16KA102 FAMILY FIGURE 1: PIN DIAGRAMS MCLR/VPP/RA5 PGC2/AN0/VREF+/CN2/RA0 PGD2/AN1/VREF-/CN3/RA1 PGD1/AN2/C1IND/C2INB/U2TX/CN4/RB0 PGC1/AN3/C1INC/C2INA/U2RX/CN5/RB1 U1RX/CN6/RB2 OSCI/CLKI/AN4/C1INB/C2IND/CN30/RA2 OSCO/CLKO/AN5/C1INA/C2INC/CN29/RA3 PGD3/SOSCI/U2RTS/U2BCLK/CN1/RB4 PGC3/SOSCO/T1CK/U2CTS/CN0/RA4 1 2 3 4 5 6 7 8 9 10 PIC24XXKAX01 20-Pin PDIP, SSOP, SOIC 20 19 18 17 16 15 14 13 12 11 VDD VSS REFO/SS1/T2CK/T3CK/CN11/RB15 AN10/CVREF/RTCC/SDI1/OCFA/C1OUT/INT1/CN12/RB14 AN11/SDO1/CTPLS/CN13/RB13 AN12/HLVDIN/SCK1/CTED2/CN14/RB12 OC1/IC1/C2OUT/INT2/CTED1/CN8/RA6 U1RTS/U1BCLK/SDA1/CN21/RB9 U1CTS/SCL1/CN22/RB8 U1TX/INT0/CN23/RB7 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VDD VSS REFO/SS1/T2CK/T3CK/CN11/RB15 AN10/CVREF/RTCC/OCFA/C1OUT/INT1/CN12/RB14 AN11/SDO1/CTPLS/CN13/RB13 AN12/HLVDIN/CTED2/CN14/RB12 PGC2/SCK1/CN15/RB11 PGD2/SDI1/PMD2/CN16/RB10 OC1/C2OUT/INT2/CTED1/CN8/RA6 IC1/CN9/RA7 U1RTS/U1BCLK/SDA1/CN21/RB9 U1CTS/SCL1/CN22/RB8 U1TX/INT0/CN23/RB7 PGC3/SCL1/CN24/RB6 MCLR/VPP/RA5 AN0/VREF+/CN2/RA0 AN1/VREF-/CN3/RA1 PGD1/AN2/C1IND/C2INB/U2TX/CN4/RB0 PGC1/AN3/C1INC/C2INA/U2RX/CN5/RB1 AN4/C1INB/C2IND/U1RX/CN6/RB2 AN5/C1INA/C2INC/CN7/RB3 VSS OSCI/CLKI/CN30/RA2 OSCO/CLKO/CN29/RA3 SOSCI/U2RTS/U2BCLK/CN1/RB4 SOSCO/T1CK/U2CTS/CN0/RA4 VDD PGD3/SDA1/CN27/RB5 PIN DIAGRAMS (CONTINUED) 20-Pin QFN 20 19 18 17 16 15 1 14 2 3 PIC24FXXKA10213 12 4 11 5 6 7 8 9 10 REFO/SS1/T2CK/T3CK/CN11/RB15 AN10/CVREF/RTCC/SDI1/OCFA/C1OUT/INT1/CN12/RB14 AN11/SDO1/CTPLS/ CN13/RB13 AN12/HLVDIN/SCK1/CTED2/CN14/RB12 OC1/IC1/C2OUT/INT2/CTED1/CN8/RA6 PGD3/SOSCI/U2RTS//U2BCLK/CN1/RB4 PGC3/SOSCO/T1CK/U2CTS/CN0/RA4 U1TX/INT0/CN23/RB7 U1CTS/SCL1/CN22/RB8 U1RTS/U1BCLK/SDA1/CN21/RB9 PGD1/AN2/C1IND/C2INB/U2TX/CN4/RB0 PGC1/AN3/C1INC/C2INA/U2RX/CN5/RB1 U1RXCN6/RB2 OSCI/CLKI/AN4/C1INB/C2IND/CN30/RA2 OSCO/CLKO/AN5/C1INA/C2INC/CN29/RA3 PGD2/AN1/VREF-/CN3/RA1 PGC2/AN0/VREF+/CN2/RA0 MCLR/VPP/RA5 VDD VSS FIGURE 2: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PIC24FXXKAX02 28-Pin SPDIP, SSOP, SOIC 2011 Microchip Technology Inc. DS80473G-page 11 PIC24F16KA102 FAMILY PIN DIAGRAMS (CONTINUED) AN1/VREF-/CN3/RA1 AN0/VREF+/CN2/RA0 MCLR/VPP/RA5 VDD Vss REFO/SS1/T2CK/T3CK/CN11/RB15 AN10/CVREF/RTCC/OCFA/C1OUT/INT1/CN12/RB14 FIGURE 3: 28-Pin QFN 28 27 26 25 24 23 22 1 2 3 4 5 6 7 PIC24FXXKA102 8 9 10 11 12 13 14 21 20 19 18 17 16 15 AN11/SDO1/CTPLS/CN13/RB13 AN12/HLVDIN/CTED2/CN14/RB12 PGC2/SCK1/CN15/RB11 PGD2/SDI1/PMD2/CN16/RB10 OC1/C2OUT/INT2/CTED1/CN8/RA6 IC1/CN9/RA7 U1RTS/U1BCLK/SDA1/CN21/RB9 SOSCI/U2RTS/U2BCLK/CN1/RB4 SOSCO/T1CK/U2CTS/CN0/RA4 VDD PGD3/SDA1(1)/CN27/RB5 (1) PGC3/SCL1 /CN24/RB6 U1TX/INT0/CN23/RB7 U1CTS/SCL1/CN22/RB8 PGD1/AN2/C1IND/C2INB/U2TX/CN4/RB0 PGC1/AN3/C1INC/C2INA/U2RX/CN5/RB1 AN4/C1INB/C2IND/U1RX/CN6/RB2 AN5/C1INA/C2INC/CN7/RB3 VSS OSCI/CLKI/CN30/RA2 OSCO/CLKO/CN29/RA3 TABLE 1-2: PIC24F16KA102 FAMILY PINOUT DESCRIPTIONS (PARTIAL REPRESENTATION) Pin Number Function 20-Pin PDIP/SSOP/ SOIC 20-Pin QFN 28-Pin SPDIP/ SSOP/SOIC 28-Pin QFN I/O Input Buffer AN0 2 19 2 27 I ANA AN1 3 20 3 28 I ANA AN2 4 1 4 1 I ANA AN3 5 2 5 2 I ANA AN4 7 4 6 3 I ANA AN5 8 5 7 4 I ANA AN10 17 14 25 22 I ANA Description A/D Analog Inputs AN11 16 13 24 21 I ANA AN12 15 12 23 20 I ANA U1BCLK 13 10 18 15 O -- UART1 IrDA(R) Baud Clock U2BCLK 9 6 11 8 O -- UART2 IrDA Baud Clock DS80473G-page 12 2011 Microchip Technology Inc. PIC24F16KA102 FAMILY In addition, the CH0SA bit field is only four bits wide, comprising AD1CHS<3:0>; CH0SA4 is not implemented. This deletion applies to all occurrences of CH0SA4, including the device memory map. 9. Module: A/D Converter (AD1CHS Register) In Register 22-4, the bit fields, CHOSB<3:0> and CHOSA<3:0>, both assign the value `0110' to both AVDD and AVSS inputs. For both bit fields, `0111' corresponds to AVDD and `0110' corresponds to AVSS. All changes to AD1CHS are shown Register 22-4 below; changes are in bold. in Also, the bit fields, CHOSB<3:0> and CHOSA<3:0>, both assign the value, `0010', to both AN2 and AN3 inputs. For both bit fields, `0011' corresponds to AN3 and `0110' corresponds to AN2. - REGISTER 22-4: AD1CHS: A/D INPUT SELECT REGISTER (PARTIAL REPRESENTATION) R/W-0 CH0NB bit 15 U-0 -- U-0 -- U-0 -- R/W-0 CH0SB3 R/W-0 CH0SB2 R/W-0 CH0SB1 R/W-0 CH0SB0 bit 8 R/W-0 CH0NA bit 7 U-0 -- U-0 -- U-0 -- R/W-0 CH0SA3 R/W-0 CH0SA2 R/W-0 CH0SA1 R/W-0 CH0SA0 bit 0 Legend: R = Readable bit -n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown bit 11-8 CH0SB<3:0>: Channel 0 Positive Input Select for MUX B Multiplexer Setting bits 1111 = Channel 0 positive input is band gap reference (VBG) . . 1000 = Reserved 0111 = AVDD 0110 = AVSS . . 0100 = Channel 0 positive input is AN4 0011 = Channel 0 positive input is AN3 0010 = Channel 0 positive input is AN2 bit 4-0 CH0SA<4:0>: Channel 0 Positive Input Select for Sample A bits 1111 = Channel 0 positive input is band gap reference (VBG) . . 1000 = Reserved 0111 = AVDD 0110 = AVSS . . 0100 = Channel 0 positive input is AN4 0011 = Channel 0 positive input is AN3 0010 = Channel 0 positive input is AN2 2011 Microchip Technology Inc. DS80473G-page 13 PIC24F16KA102 FAMILY 10. Module: A/D Converter 13. Module: Electrical Specifications (AC Specifications) In Figure 22-2, the interconnect resistance, RIC, is shown as having a value of no more than 250W. The proper value for RIC is no more than 250 ohms. Parameter, AD08 (current specification for the external ADC voltage reference), has been added to the specifications for the A/D module. Table 29-25 is amended as shown (additions in bold). 11. Module: Special Features (Configuration Bits) 14. Module: Electrical Specifications (DC Specifications) In the FDS Configuration register, the Configuration bits, DSLPBOR and DSWCKSEL (FDS<6,4>), have been renamed: DSBOREN and DSWDTOSC. This has been done to unify the naming conventions for all nanoWatt XLP devices. The changes apply to all occurrences throughout the device data sheet. In Table 29-9 ("DC Characteristics: I/O Pin Input Specifications"), the maximum value of Parameter D151, the input leakage current (IIL) on the VREF+ and VREF- pins has been changed to +1.00 A. The rest of the parameter is unchanged. It is anticipated that the former names of these bits will be supported through the next release of all Microchip development tools. 12. Module: Power-Saving Features The Deep Sleep Wake-up Source register, DSWSRC (Register 10-2), has been renamed DSWAKE. This has been done to unify the naming conventions for all nanoWatt XLP devices. This change applies to all occurrences throughout the device data sheet, including the device memory map. It is anticipated that the register name, DSWSRC, will be supported through the next release of all Microchip development tools. TABLE 29-25: ADC MODULE SPECIFICATIONS (PARTIAL REPRESENTATION) Standard Operating Conditions: 1.8V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial AC CHARACTERISTICS Param No. Symbol Characteristic Min. Typ Max. Units Conditions Reference Inputs AD05 VREFH Reference Voltage High AVSS + 1.7 -- AVDD V AD06 VREFL Reference Voltage Low AVSS -- AVDD - 1.7 V AD07 VREF Absolute Reference Voltage AVSS - 0.3 -- AVDD + 0.3 V AD08 IVREF+ External VREF+ Current -- 200 -- A VREF+ = 3.3V; sampling -- 1.0 -- mA VREF+ = 3.3V; converting DS80473G-page 14 2011 Microchip Technology Inc. PIC24F16KA102 FAMILY 15. Module: Electrical Specifications (DC Specification) Table 29-5 ("BOR Trip Points") has changed to reflect the functionality of the LPBOR trip point (BORV<1:0> = 00), and to make other typographic corrections. The minimum and maximum values for the BOR trip points in Table 29-5 have changed. The new version of the table is shown below (changes in bold). TABLE 29-5: BOR TRIP POINTS Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial Param Sym No. DC19 Note 1: Characteristic BOR Voltage on VDD Transition Min Typ Max Units BORV = 00 -- BORV = 01 2.92 -- -- -- 3 3.25 V BORV = 10 2.63 2.7 2.92 V BORV = 11 1.75 1.82 2.01 V Conditions LPBOR (Note 1) LPBOR re-arms the POR circuit, but does not cause a BOR. LPBOR can be used to ensure a POR after the supply voltage rises to a safe operating level. It does not stop code execution after the supply voltage falls below a chosen trip point. 2011 Microchip Technology Inc. DS80473G-page 15 PIC24F16KA102 FAMILY APPENDIX A: DOCUMENT REVISION HISTORY Rev A Document (6/2009) Initial release of this document; issued for revision A5. Includes silicon issues 1 (CTMU), 2 (Resets - BOR), 3 (Core - ICSP), 4 (Core - Deep Sleep), 5 (Memory - Code Protection), 6 (Comparator) and 7 (SPI - Enhanced Buffer Mode). Includes data sheet clarifications 1 (Memory), 2 (Electrical Specifications - AC Specifications), 3-6 (Electrical Specifications - DC Specifications), 7 (A/D) and 8 (Comparators). Rev B Document (6/2009) Revision issued for silicon revision A6. Existing silicon issues 1 (CTMU), 2 (Resets - BOR), 4 (Core - Deep Sleep), 6 (Comparator) and 7 (SPI - Enhanced Buffer Mode) added to revision A6. No new issues added. Rev C Document (10/2009) Revision issued for silicon revision A7. Existing silicon issues 1 (CTMU), 2 (Resets - BOR), 4 (Core - Deep Sleep), 6 (Comparator) and 7 (SPI - Enhanced Buffer Mode) added to revision A7. Added new silicon issue 8 (I/O Ports - PORTA and PORTB). To revision B of the data sheet, adds data sheet clarifications 9 (Pin Diagrams), 10 (A/D Converter - AD1CHS Register), 11 (A/D Converter - AD1CHS Register), 12 (Special Features - Configuration Bits), 13 (Power-Saving Features) and 14 (Electrical Specifications - AC Specifications). Rev D Document (10/2009) Typographic correction: updated Table 2 with the correct associations between silicon issues and silicon revisions. Rev F Document (11/2010) Revision issued for silicon revision B0. Existing silicon issues 2 (Resets - BOR) and 6 (Comparator) added to revision B0. Amended existing silicon issue 8 (I/O Ports - PORTA and PORTB), to change "digital input" to analog input" at the end of the fourth paragraph. Added new silicon issue 10 (Core - Low Power BOR) to silicon revisions A5, A6 and A7. Added new silicon issues 11, 12 (Comparator) and 13 (Core - Doze Mode) to silicon revisions A5, A6 and A7. Removed data sheet clarification 16 (Electrical Specifications - DC Specifications) to revision B of the data sheet. Removed data sheet clarification 6 (Electrical Specifications - DC Specifications) and combined it with data sheet clarification 16 which is now data sheet clarification 15. Rev G Document (4/2011) Added silicon issue 13 (A/D Converter) to silicon revisions A5, A6 and A7. Silicon issue 6 (Comparator) edited to no longer affect revision B0. Silicon issue 10 (Core - Low-Power BOR) description was edited to explicitly include the acronym, LPBOR. Silicon issue 11 (Comparator) was published in error and has been deleted. Silicon issue 12 (Comparator) work around has been shortened for clarity. Data sheet clarification 15 (Electrical Specifications - DC Specification) has been edited to explicitly name BORV = 00 as the LPBOR. Note 1, explaining the LPBOR, explicitly differentiates BOR and LPBOR functionality. Rev E Document (4/2010) Added new silicon issue 9 (I/O Ports - PORTA and PORTB) to all silicon revisions. Updated existing silicon issue 8 to include additional interactions and work arounds between RA0 and RB0. Added data sheet clarification 15 (Electrical Specifications - DC Specifications) to revision B of the data sheet. Updated revision history to include entry for revision D. DS80473G-page 16 2011 Microchip Technology Inc. Note the following details of the code protection feature on Microchip devices: * Microchip products meet the specification contained in their particular Microchip Data Sheet. * Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. * There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. * Microchip is willing to work with the customer who is concerned about the integrity of their code. * Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable." Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip's code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer's risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, PIC32 logo, rfPIC and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, MXDEV, MXLAB, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, mTouch, Omniscient Code Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. (c) 2011, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. ISBN: 978-1-61341-085-1 Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company's quality system processes and procedures are for its PIC(R) MCUs and dsPIC(R) DSCs, KEELOQ(R) code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001:2000 certified. 2011 Microchip Technology Inc. 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