OM13035,598 - NXP Semiconductors - Datasheet.Directory

ES_LPC111x

Errata sheet LPC1111/12/13/14/15

Rev. 5 — 26 September 2013 Errata sheet

Document information

Info Content

Keywords LPC1111FHN33, LPC1112FHN33, LPC1112FHI33, LPC1113F HN33,

LPC1113FBD48, LPC1114FHN33, LPC1114FHI33, LPC1114FBD48,

LPC1115FBD48, LPC1115FET48 LPC1112JHI33, LPC1114JHN33,

LPC1115JBD48, and LPC1115JET48 errata

Abstract This errata sheet describes both the known functional problems and any

deviations from the electrical specifications known at the release date of

this document.

Each deviation is assigned a number and its history is tracked in a table at

the end of the document.

Errata sheet Rev. 5 — 26 September 2013 2 of 8

Contact information

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

NXP Semiconductors ES_LPC111x

Errata sheet LPC1111/12 /1 3/ 14 /1 5

Revision history

Rev Date Description

5 20130926 •Added Rev. ‘C ’.

•Added LPC1115FET48, LPC1112JHI33, LPC1114JHN33, LPC1115JBD48, and

LPC1115JET48.

4.1 20130201 •Clarified VDD.1, does not apply to LPC1100XL series (LPC111x/103/203/303/323/333).

4 20130116 •Added I2C.1.

3.3 20120501 •Removed LPC1110FD20, LPC1111FDH20, LPC1112FD20, LPC1112FDH20,

LPC1112FDH28, LPC1114FDH28, LPC1114FN28 ; placed in separate errata

ES_LPC1110_11_12_14.

3.2 20120117 •Added ADC.2.

3.1 20110901 •Added Note.1.

3 20110301 •Combined LPC1111/12/13/14 errata into one document.

•Added VDD.1.

•Section 3.1: Removed text “For PCLK_ADC = 100 MHz....”

2 20101115 •Added ADC.1.

•Added Rev. ‘B’.

1 20100510 •Initial version

Errata sheet Rev. 5 — 26 September 2013 3 of 8

NXP Semiconductors ES_LPC111x

Errata sheet LPC1111/12 /1 3/ 14 /1 5

1. Product identification

The LPC111x devices typically have the following top- side marking:

LPC111xx

/xxx

xxxxxxx

xxYYWWxR[x]

The last letter in the last line (field ‘R’) will identify the device revision. This Errata Sheet

covers the following revisions of the LPC111x:

Field ‘YY’ states the year the device was manufactured. Field ‘WW’ states the week the

device was manufactured during that year.

2. Errata overview

[1] This errata does not apply to the LPC1100XL series (LPC111x/103/203/303/323/333).

Table 1. Device revision table

Revision identifier (R) Revision descrip tion

‘A’ Initial device revision

‘B’ Second device revision

‘C’ Third device revision

Table 2. Functional problems table

Functional

problems Short description Revision identifier Deta iled descrip tio n

ADC.1 External sync inputs not operational ‘A’, ‘B’, ‘C’ Section 3.1

ADC.2 A/D Global Data register should not be used with burst

mode or hardware triggering. ‘A’, ‘B’, ‘C’ Section 3.2

I2C.1 In the slave-transmitter mode, the device set in the

monitor mode must write a dummy value of 0xFF into

the DAT register.

‘A’, ‘B’, ‘C’ Section 3.3

VDD.1[1] The minimum vo ltage of the power supply ramp must

be 200 mV or below. ‘A’, ‘B’, ‘C’ Section 3.4

Table 3. AC/DC deviations table

AC/DC

deviations Short description Revision identifier Detailed description

n/a n/a n/a n/a

Table 4. Errata notes

Note Short descriptio n Revision identifier Det a ile d de s criptio n

Note.1 During power-up, an unexpected glitch (low pulse)

could occur on the port pins as the VDD supp ly ramps

up.

‘A’, ‘B’, ‘C’ Section 5.1

Errata sheet Rev. 5 — 26 September 2013 4 of 8

NXP Semiconductors ES_LPC111x

Errata sheet LPC1111/12 /1 3/ 14 /1 5

3. Functional problems detail

3.1 ADC.1: External sync inputs not operational

Introduction:

In software-controlled mode (BURST bit is 0), the 10-bit ADC can start conversion by

using the following options in the A/D Control Register:

Problem:

The external st art conver sion feature , AD0CR:START = 0x2 or 0x3, may not work r eliably

and ADC external trigger edges on PIO0_2 or PIO1_5 may be missed. The occurre nce of

this problem is peripheral clock (pclk) dependent. The probability of error (missing a ADC

trigger from GPIO) is estimated as follows:

•For PCLK_ADC = 50 MHz, probability error = 6 %

•For PCLK_ADC = 12 MHz, probability error = 1.5 %

The probability of error is not affected by the frequency of ADC start conversion edges.

Work-around:

In software-controlled mode (BURST bit is 0), the START conversion options (bits 26:24

set to 0x1 or 0x4 or 0x5 or 0x6 or 0x7) can be used. The user can also st art a conversion

by connecting an external trigger signal to a capture input pin (CAPx) from a Timer

peripheral to generate an interrupt. The timer interrupt routine can then start the ADC

conversion by se ttin g the START bits (26:24) to 0x1. The trigger can also be generated

from a timer match register.

26:24 START

0x0

When the BURST bit is 0, these bits control whether and when an A/D conversion is

started:

No start (this value should be used when clearing PDN to 0).

0x1 Start conversion now.

0x2 Start conversion when the edge selected by bit 27 occurs on

PIO0_2/SSEL/CT16B0_CAP0.

0x3 Start conversion when the edge selected by bit 27 occurs on

PIO1_5/DIR/CT32B0_CAP0.

0x4 Start conversion when the edge selected by bit 27 occurs on CT32B0_MAT0.

0x5 Start conversion when the edge selected by bit 27 occurs on CT32B0_MAT1.

0x6 Start conversion when the edge selected by bit 27 occurs on CT16B0_MAT0.

0x7 Start conversion when the edge selected by bit 27 occurs on CT16B0_MAT1.

Errata sheet Rev. 5 — 26 September 2013 5 of 8

NXP Semiconductors ES_LPC111x

Errata sheet LPC1111/12 /1 3/ 14 /1 5

3.2 ADC.2: A/D Global Data register should not be used with burst mode

or hardware triggering

Introduction:

On the LPC111x, the START field and the BURST bit in the A/D control register specify

whether A/D conv er sion s ar e init iat ed via software comm a nd , in re sp on se to some

hardware trigger, or continuously in burst ("hardware-scan") mode. Results of the ADC

conversions can be read in one of two ways. One is to use the A/D Global Data Register

to read all data from the ADC. Another is to use the individual A/D Channel Data

Registers.

Problem:

If the burst mode is enable d (BURST bit set to ‘1’) or if hardware triggering is specified,

the A/D conversion results read from the A/D Global Data register could be incorrect. If

conversions are only lau nched directly by software command (BURST bit = '0' and ST AR T

= ‘001’), the results read from the A/D Global Data register will be correct provided the

previous result is read prior to launching a new conversion.

Work-around:

When using either burst mode or hardware triggering, the individual A/D Channel Data

registers should be used instead of the A/D Global Data register to read the A/D

conversion results.

3.3 I2C.1: In the slave-transmitter mode, the device set in the monitor

mode must write a dummy value of 0xFF into the DAT register

Introduction:

The I2C monitor allows the device to monitor the I2C traffic on the I2 C bus in a

non-intrusive way.

Problem:

In the slave-transmitter mode, the device set in the monitor mode must write a dummy

value of 0xFF into the DAT register. If this is not done, the received data from the slave

device will be corrupted. To allow the monitor mode to have sufficient time to process the

data on the I2C bus, the device may need to have the ability to stretch the I2C clock.

Under this condition, the I2C monitor mode is not 100% non-intrusive.

Work-around:

When setting the device in monitor mode, enable the ENA_SCL bit in the MMCTRL

Software code example to enable the ENA_SCL bit:

LPC_I2C_MMCTRL |= (1<<1); //Enable ENA_SCL bit

In the I2C ISR routine, for the status code related to the slave-transmitter mode, write the

value of 0xFF into the DAT register to prevent data corrupti on. In order to avoid stretching

the SCL clock, the data byte can be saved in a buffer and processed in the Main loop.

This ensures the SI flag is cleared as fast as possible.

Software code example for the slave-transmitter mode:

Errata sheet Rev. 5 — 26 September 2013 6 of 8

NXP Semiconductors ES_LPC111x

Errata sheet LPC1111/12 /1 3/ 14 /1 5

case 0xA8: // Own SLA + R has been received, ACK returned

case 0xB0:

case 0xB8: // data byte in DAT transmitted, ACK received

case 0xC0: // (last) data byte transmitted, NACK received

case 0xC8: // last data byte in DAT transmitted, ACK received

DataByte = LPC_I2C->DATA_BUFFER; //Save data. Data can be process in Main loop

LPC_I2C->DAT = 0xFF; // Pretend to shift out 0xFF

LPC_I2C->CONCLR = 0x08; // clear flag SI

break;

3.4 VDD.1: The minimum voltage of the power supply ramp must be

200 mV or below1

Introduction:

The datasheet specifies that the power supply (on the VDD pin) must ramp -up from a

minimum voltage of 400 mV or below with a ramp-up time of 500 ms or faster. Also, the

minimum time the power supply (on the VDD pin) needs to be below 400 mV or below

before ramping up is 12 us.

Problem:

The device might not always start-up if the power supply (on the VDD pin) does not reach

200 mV. The minimu m voltage of the p ower supply ramp (o n the VDD pin) must be 200 mV

or below with ramp-up time of 500 ms or faster.

Work-around:

None.

4. AC/DC deviations detail

No known errata.

5. Errata notes

5.1 Note.1

The General Purpose I/O (GPIO) pins have configurable pull-up/pull-down resistors whe re

the pins are pulled up to the VDD level by default. During power-up, an unexpected glitch

(low pulse) could occur on the port pins as the VDD supply ramps up.

1. This errata does not apply to the LPC1100XL series (LPC111x/103/203/303/323/333).

Errata sheet Rev. 5 — 26 September 2013 7 of 8

NXP Semiconductors ES_LPC111x

Errata sheet LPC1111/12 /1 3/ 14 /1 5

6. Legal information

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6.3 Trademarks

Notice: All referenced b rands, produc t names, service names and trademarks

are the property of their respect i ve ow ners.

NXP Semiconductors ES_LPC111x

Errata sheet LPC1111/12 /1 3/ 14 /1 5

For more information, please visit: http://www.nxp.co m

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 26 September 2013

Document identifier: ES_LPC111X

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

7. Contents

1 Product identification . . . . . . . . . . . . . . . . . . . . 3

2 Errata overview . . . . . . . . . . . . . . . . . . . . . . . . . 3

3 Functional problems detail. . . . . . . . . . . . . . . . 4

3.1 ADC.1: External sync inputs not operational . . 4

Introduction: . . . . . . . . . . . . . . . . . . . . . . . . . . . .4

Problem: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4

Work-around: . . . . . . . . . . . . . . . . . . . . . . . . . . .4

3.2 ADC.2: A/D Global Data register should not be

used with burst mo de or ha rd w a re tri g ge ri n g. . 5

Introduction: . . . . . . . . . . . . . . . . . . . . . . . . . . . .5

Problem: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5

Work-around: . . . . . . . . . . . . . . . . . . . . . . . . . . .5

3.3 I2C.1: In the slave-transmitter mode, the device

set in the monitor mode must write a dummy value

of 0xFF into the DAT register . . . . . . . . . . . . . . 5

Introduction: . . . . . . . . . . . . . . . . . . . . . . . . . . . .5

Problem: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5

Work-around: . . . . . . . . . . . . . . . . . . . . . . . . . . .5

3.4 VDD.1: The minimum voltage of the power supply

ramp must be 200 mV or below . . . . . . . . . . . . 6

Introduction: . . . . . . . . . . . . . . . . . . . . . . . . . . . .6

Problem: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6

Work-around: . . . . . . . . . . . . . . . . . . . . . . . . . . .6

4 AC/DC deviations detail . . . . . . . . . . . . . . . . . . 6

5 Errata notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

5.1 Note.1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

6 Legal information. . . . . . . . . . . . . . . . . . . . . . . . 7

6.1 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

6.2 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

6.3 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

7 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8