Agilent HCPL-9000/-0900, -9030/-0930,
HCPL-9031/-0931, -900J/-090J,
HCPL-901J/-091J, -902J/-092J
High Speed Digital Isolators
Data Sheet
Description
The HCPL-90xx and HCPL-09xx
CMOS digital isolators feature
high speed performance and
excellent transient immunity
specifications. The symmetric
magnetic coupling barrier gives
these devices a typical pulse
width distortion of 2 ns, a typical
propagation delay skew of 4 ns
and 100 Mbaud data rate, making
them the industry’s fastest
digital isolators.
The single channel digital isola-
tors (HCPL-9000/-0900) features
an active-low logic output enable.
The dual channel digital isolators
are configured as unidirectional
(HCPL-9030/-0930) and bi-
directional (HCPL-9031/-0931),
operating in full duplex mode
making it ideal for digital
fieldbus applications.
The quad channel digital isola-
tors are configured as unidirec-
Features
• +3.3V and +5V TTL/CMOS
compatible
• 3 ns max. pulse width distortion
•
6 ns max. propagation delay skew
• 15 ns max. propagation delay
• High speed: 100 MBd
• 15 kV/µs min. common mode
rejection
• Tri-state output
(HCPL-9000/-0900)
• 2500V RMS isolation
• UL1577 and IEC 61010-1 approved
Applications
• Digital fieldbus isolation
• Multiplexed data transmission
• Computer peripheral interface
• High speed digital systems
• Isolated data interfaces
• Logic level shifting
tional (HCPL-900J/-090J), two
channels in one direction and
two channels in opposite direc-
tion (HCPL-901J/-091J), and one
channel in one direction and
three channels in opposite
direction (HCPL-902J/-092J).
These high channel density make
them ideally suited to isolating
data conversion devices, parallel
buses and peripheral interfaces.
They are available in 8-pin PDIP,
8-pin Gull Wing, 8-pin SOIC
packages, and 16–pin SOIC
narrow-body and wide-body
packages. They are specified over
the temperature range of -40°C
to +100°C.
CAUTION: It is advised that
normal static precautions be
taken in handling and assembly
of this component to prevent
damage and/or degradation,
which may be induced by ESD.
2
Selection Guide
Device Number Channel Configuration Package
HCPL-9000 Single 8-pin DIP (300 Mil)
HCPL-0900 Single 8-pin Small Outline
HCPL-9030 Dual 8-pin DIP (300 Mil)
HCPL-0930 Dual 8-pin Small Outline
HCPL-9031 Dual, Bi-Directional 8-pin DIP (300 Mil)
HCPL-0931 Dual, Bi-Directional 8-pin Small Outline
HCPL-900J Quad 16-pin Small Outline, Wide Body
HCPL-090J Quad 16-pin Small Outline, Narrow Body
HCPL-901J Quad, 2/2, Bi-Directional 16-pin Small Outline, Wide Body
HCPL-091J Quad, 2/2, Bi-Directional 16-pin Small Outline, Narrow Body
HCPL-902J Quad, 1/3, Bi-Directional 16-pin Small Outline, Wide Body
HCPL-092J Quad, 1/3, Bi-Directional 16-pin Small Outline, Narrow Body
Ordering Information
Specify Part Number followed by Option Number (if desired).
Examples:
HCPL-90xx-xxx
xxx:
No option = 300 Mil PDIP-8 package, 50 units per tube.
300 = Gull Wing Surface Mount Option, 50 units per tube.
500 = Tape and Reel Packaging Option, 1000 units per reel.
HCPL-09xx-xxx
xxx:
No option = SO-8 package, 100 units per tube.
500 = Tape and Reel Packaging Option, 1500 units per reel.
HCPL-90xJ-xxx
xxx:
No option = Wide Body SOIC-16 package, 50 units per tube.
500 = Tape and Reel Packaging Option, 1000 units per reel.
HCPL-09xJ-xxx
xxx:
No option = Narrow Body SOIC-16 package, 50 per tube.
500 = Tape and Reel Packaging Option, 1000 units per reel.
3
Pin Description
Symbol Description
VDD1 Power Supply 1
VDD2 Power Supply 2
INXLogic Input Signal
OUTXLogic Output Signal
GND1Power Supply Ground 1
GND2Power Supply Ground 2
VOE Logic Output Enable
(Single Channel), Active Low
NC Not Connected
Functional Diagrams
Truth Table
IN1VOE OUT1
LLL
HL H
LHZ
HHZ
V
DD1
IN
1
NC
GND
1
GND
2
OUT
1
V
DD2
V
OE
8
7
6
5
1
2
3
4
Galvanic Isolation
HCPL-9000/0900
Single Channel
Dual Channel
VDD1
IN1
IN2
GND1GND2
OUT2
VDD2
OUT1
8
7
6
5
1
2
3
4
Galvanic Isolation
HCPL-9030/0930
Quad Channel
1
2
3
4
5
6
7
89
10
11
12
13
14
15
16
VDD1
GND1
IN1
IN2
IN3
IN4
NC
GND1GND2
NC
OUT4
OUT3
OUT2
OUT1
GND2
VDD2
Galvanic Isolation
HCPL-900J/-090J
1
2
3
4
5
6
7
89
10
11
12
13
14
15
16
V
DD1
GND
1
IN
1
IN
2
OUT
3
OUT
4
NC
GND
1
GND
2
NC
IN
4
IN
3
OUT
2
OUT
1
GND
2
V
DD2
Galvanic Isolation
HCPL-901J/-091J
1
2
3
4
5
6
7
89
10
11
12
13
14
15
16
V
DD1
GND
1
IN
1
IN
2
IN
3
OUT
4
NC
GND
1
GND
2
NC
IN
4
OUT
3
OUT
2
OUT
1
GND
2
V
DD2
Galvanic Isolation
HCPL-902J/-092J
V
DD1
IN
1
OUT
2
GND
1
GND
2
IN
2
V
DD2
OUT
1
8
7
6
5
1
2
3
4
Galvanic Isolation
HCPL-9031/0931
4
Package Outline Drawings
HCPL-9000, HCPL-9030 and HCPL-9031 Standard DIP Packages
HCPL-9000, HCPL-9030 and HCPL-9031 Gull Wing Surface Mount Option 300
0.030 (0.762)
0.045 (1.143)
0.370 (9.400)
0.390 (9.900)
0.240 (6.100)
0.260 (6.600)
87 65
4321
0.045 (1.143)
0.065 (1.651)
0.120 (3.048)
0.150 (3.810)
0.047 (1.194)
0.070 (1.778)
0.040 (1.016)
0.047 (1.194)
0.370 (9.398)
0.390 (9.906)
0.190
(4.826)
0.015 (0.381)
0.025 (0.635)
0.025 (0.632)
0.035 (0.892)
0.030 (0.760)
0.056 (1.400) 0.015 (0.385)
0.035 (0.885)
0.290 (7.370)
0.310 (7.870)
0.370 (9.400)
0.390 (9.900)
PAD LOCATION (for reference only)
TYP.
12° NOM.
0.008 (0.203)
0.013 (0.330)
0.100
(2.540)
BSC
DIMENSIONS INCHES (MILLIMETERS)
LEAD COPLANARITY = 0.004 INCHES
(
0.10 mm
)
MIN
MAX
5678
4321
DIMENSIONS: INCHES (MILLIMETERS) MIN
MAX
0.120 (3.048)
0.150 (3.810)
0.240 (6.096)
0.260 (6.604)
0.015 (0.381)
0.035 (0.889)
0.55 (1.397)
0.65 (1.651)
0.008 (0.203)
0.015 (0.381)
3°
8°
0.030 (0.762)
0.045 (1.143)
0.015 (0.380)
0.023 (0.584) 0.045 (1.143)
0.065 (1.651)
0.090 (2.286)
0.110 (2.794)
0.370 (9.398)
0.400 (10.160)
0.290 (7.366)
0.310 (7.874)
0.300 (7.620)
0.370 (9.398)
5
8765
4
3
2
1
0.228 (5.80)
0.244 (6.20)
0.189 (4.80)
0.197 (5.00)
0.150 (3.80)
0.157 (4.00)
0.013 (0.33)
0.020 (0.51)
0.040 (1.016)
0.060 (1.524)
0.004 (0.10)
0.010 (0.25)
0.054 (1.37)
0.069 (1.75)
0.016 (0.40)
0.050 (1.27)
0.008 (0.19)
0.010 (0.25)
0.010 (0.25)
0.020 (0.50)
x 45°
0°
8°
DIMENSIONS: INCHES (MILLIMETERS) MIN
MAX
HCPL-0900, HCPL-0930 and HCPL-0931 Small Outline SO-8 Package
HCPL-900J, HCPL-901J and HCPL-902J Wide Body SOIC-16 Package
1
Pin 1 indent
8
7° TYP
0.394 (10.007)
0.419 (10.643)
0.397 (10.084)
0.413 (10.490)
0.291 (7.391)
0.299 (7.595)
0.013 (0.330)
0.020 (0.508)
0.040 (1.016)
0.060 (1.524)
0.080 (2.032)
0.100 (2.54)
0.092 (2.337)
0.104 (2.642)
0.004 (0.1016)
0.011 (0.279)
0.016 (0.40)
0.050 (1.27)
0.010 (0.254)
0.020 (0.508)
0.287 (7.290)
0.297 (7.544) x 45°
0° – 8° TYP
7° TYP
0.009 (0.229)
0.012 (0.305)
DIMENSIONS: INCHES (MILLIMETERS) MIN
MAX
6
HCPL-090J, HCPL-091J and HCPL-092J Narrow Body SOIC-16 Package
1
Pin 1 indent
8
0.228 (5.791)
0.244 (6.197)
0.386 (9.802)
0.394 (9.999)
0.152 (3.861)
0.157 (3.988)
0.013 (0.330)
0.020 (0.508)
0.040 (1.016)
0.060 (1.524)
0.050 (1.270)
0.060 (1.524)
0.054 (1.372)
0.068 (1.727)
0.004 (0.102)
0.010 (0.249)
0.016 (0.406)
0.050 (1.270)
0.010 (0.245)
0.020 (0.508)
0.008 (0.191)
0.010 (0.249)
x 45°
0° – 8° TYP
DIMENSIONS: INCHES (MILLIMETERS) MIN
MAX
Package Characteristics
Parameter Symbol Min. Typ. Max. Units Test Conditions
Capacitance (Input-Output)[1] CI-O pF f = 1 MHz
Single Channel 1.1
Dual Channel 2.0
Quad Channel 4.0
Thermal Resistance θJCT °C/W Thermocouple located at
8-Pin PDIP 150 center underside of package
8-Pin SOIC 240
Package Power Dissipation PPD mW
8-Pin PDIP 150
8-Pin SOIC 150
Notes:
1. Single and dual channels device are considered two-terminal devices: pins 1-4 shorted and pins 5-8 shorted. Quad channel devices are considered
two-terminal devices: pins 1-8 shorted and pins 9-16 shorted.
This product has been tested for electrostatic sensitivity to the limits stated in the specifications. However, Agilent recommends that all integrated circuits
be handled with appropriate care to avoid damage. Damage caused by inappropriate handling or storage could range from performance degradation to
complete failure.
7
Insulation and Safety Related Specifications
Parameters Condition Min. Typ. Max. Units
Barrier Impedance Ω||pF
Single Channel >1014|| 3
Dual Channel >1014|| 3
Quad Channel >1014|| 7
Creepage Distance (External) mm
8-Pin PDIP 7.036
8-Pin SOIC 4.026
16-Pin SOIC Narrow Body 4.026
16-Pin SOIC Wide Body 8.077
Leakage Current 240 VRMS 0.2 µA
60 Hz
Absolute Maximum Ratings
Parameters Symbol Min. Max. Units
Storage Temperature TS–55 175 °C
Ambient Operating Temperature[1] TA–55 125 °C
Supply Voltage VDD1, VDD2 –0.5 7 V
Input Voltage VIN –0.5 VDD1 +0.5 V
Voltage Output Enable (HCPL-9000/-0900) VOE –0.5 VDD2 +0.5 V
Output Voltage VOUT –0.5 VDD2 +0.5 V
Output Current Drive IOUT 10 mA
Lead Solder Temperature (10s) 260 °C
ESD 2 kV Human Body Model
Notes:
1. Absolute Maximum ambient operating temperature means the device will not be damaged if operated under these conditions. It does not
guarantee performance.
Recommended Operating Conditions
Parameters Symbol Min. Max. Units
Ambient Operating Temperature TA–40 100 °C
Supply Voltage VDD1, VDD2 3.0 5.5 V
Logic High Input Voltage VIH 2.4 VDD1 V
Logic Low Input Voltage VIL 0 0.8 V
Input Signal Rise and Fall Times tIR, tIF 1µs
This product has been tested for electrostatic sensitivity to the limits stated in the specifications. However, Agilent recommends that all integrated circuits
be handled with appropriate care to avoid damage. Damage caused by inappropriate handling or storage could range from performance degradation to
complete failure.
8
Electrical Specifications
Test conditions that are not specified can be anywhere within the recommended operating range.
All typical specifications are at TA=+25°C, VDD1 = VDD2 = +3.3V.
Parameter Symbol Min. Typ. Max. Units Test Conditions
Quiescent Supply Current 1 IDD1 mA VIN = 0V
HCPL-9000/-0900 0.008 0.01
HCPL-9030/-0930 0.008 0.01
HCPL-9031/-0931 1.5 2.0
HCPL-900J/-090J 0.016 0.02
HCPL-901J/-091J 3.3 4.0
HCPL-902J/-092J 1.5 2.0
Quiescent Supply Current 2 IDD2 mA VIN = 0V
HCPL-9000/-0900 3.3 4.0
HCPL-9030/-0930 3.3 4.0
HCPL-9031/-0931 1.5 2.0
HCPL-900J/-090J 5.5 8.0
HCPL-901J/-091J 3.3 4.0
HCPL-902J/-092J 3.0 6.0
Logic Input Current IIN -10 10 µA
Logic High Output Voltage VOH VDD2 –0.1 VDD2 VI
OUT = -20 µA, VIN =V
IH
0.8*VDD2 VDD2 –0.5 V IOUT = -4 mA, VIN=V
IH
Logic Low Output Voltage VOL 0 0.1 V IOUT = 20 µA, VIN =V
IL
0.5 0.8 V IOUT = 4 mA, VIN=V
IL
Switching Specifications
Maximum Data Rate 100 110 MBd CL = 15 pF
Clock Frequency fmax 50 MHz
Propagation Delay Time to Logic tPHL 12 18 ns
Low Output
Propagation Delay Time toLogic tPLH 12 18 ns
High Output
Pulse Width tPW 10 ns
Pulse Width Distortion[1] |PWD| 2 3 ns
|tPHL – tPLH|
Propagation Delay Skew[2] tPSK 46ns
Output Rise Time (10 –90%) tR24ns
Output Fall Time (10 –90%) tF24ns
Propagation Delay Enable to Output (Single Channel)
High to High Impedance tPHZ 35ns
Low to High Impedance tPLZ 35ns
High Impedance to High tPZH 35ns
High Impedance to Low tPZL 35ns
Channel-to-Channel Skew tCSK 23ns
(Dual and Quad Channels)
Common Mode Transient Immunity |CMH| 15 18 kV/µsV
cm = 1000V
(Output Logic High or Logic Low)[3] |CML|
Notes:
1. PWD is defined as |tPHL -tPLH|. %PWD is equal to the PWD divided by the pulse width.
2. tPSK is equal to the magnitude of the worst case difference in tPHL and/or tPLH that will be seen between units at 25°C.
3. CMH is the maximum common mode voltage slew rate that can be sustained while maintaining VOUT > 0.8VDD2. CML is the maximum common mode
input voltage that can be sustained while maintaining VOUT < 0.8V. The common mode voltage slew rates apply to both rising and falling common mode
voltage edges.
This product has been tested for electrostatic sensitivity to the limits stated in the specifications. However, Agilent recommends that all integrated circuits
be handled with appropriate care to avoid damage. Damage caused by inappropriate handling or storage could range from performance degradation to
complete failure.
9
Electrical Specifications
Test conditions that are not specified can be anywhere within the recommended operating range.
All typical specifications are at TA=+25°C, VDD1 = VDD2 = +5.0V.
Parameter Symbol Min. Typ. Max. Units Test Conditions
Quiescent Supply Current 1 IDD1 mA VIN = 0V
HCPL-9000/-0900 0.012 0.018
HCPL-9030/-0930 0.012 0.018
HCPL-9031/-0931 2.5 3.0
HCPL-900J/-090J 0.024 0.036
HCPL-901J/-091J 5.0 6.0
HCPL-902J/-092J 2.5 3.0
Quiescent Supply Current 2 IDD2 mA VIN = 0V
HCPL-9000/-0900 5.0 6.0
HCPL-9030/-0930 5.0 6.0
HCPL-9031/-0931 2.5 3.0
HCPL-900J/-090J 8.0 12.0
HCPL-901J/-091J 5.0 6.0
HCPL-902J/-092J 6.0 9.0
Logic Input Current IIN -10 10 µA
Logic High Output Voltage VOH VDD2 –0.1 VDD2 VI
OUT= -20 µA, VIN =V
IH
0.8*VDD2 VDD2 –0.5 V IOUT= -4 mA, VIN=V
IH
Logic Low Output Voltage VOL 0 0.1 V IOUT= 20 µA, VIN=V
IL
0.5 0.8 V IOUT= 4 mA, VIN=V
IL
Switching Specifications
Maximum Data Rate 100 110 MBd CL = 15 pF
Clock Frequency fmax 50 MHz
Propagation Delay Time to Logic tPHL 10 15 ns
Low Output
Propagation Delay Time to Logic tPLH 10 15 ns
High Output
Pulse Width tPW 10 ns
Pulse Width Distortion[1] |PWD| 2 3 ns
|tPHL – tPLH|
Propagation Delay Skew[2] tPSK 46ns
Output Rise Time (10 –90%) tR13ns
Output Fall Time (10 –90%) tF13ns
Propagation Delay Enable to Output (Single Channel)
High to High Impedance tPHZ 35ns
Low to High Impedance tPLZ 35ns
High Impedance to High tPZH 35ns
High Impedance to Low tPZL 35ns
Channel-to-Channel Skew tCSK 23ns
(Dual and Quad Channels)
Common Mode Transient Immunity |CMH| 15 18 kV/µsV
cm = 1000V
(Output Logic High or Logic Low)[3] |CML|
Notes:
1. PWD is defined as |tPHL -tPLH|. %PWD is equal to the PWD divided by the pulse width.
2. tPSK is equal to the magnitude of the worst case difference in tPHL and/or tPLH that will be seen between units at 25°C.
3. CMH is the maximum common mode voltage slew rate that can be sustained while maintaining VOUT > 0.8VDD2. CML is the maximum common mode
input voltage that can be sustained while maintaining VOUT < 0.8V. The common mode voltage slew rates apply to both rising and falling common mode
voltage edges.
This product has been tested for electrostatic sensitivity to the limits stated in the specifications. However, Agilent recommends that all integrated circuits
be handled with appropriate care to avoid damage. Damage caused by inappropriate handling or storage could range from performance degradation to
complete failure.
10
Applications Information
Power Consumption
The HCPL-90xx and HCPL-09xx
CMOS digital isolators achieves
low power consumption from the
manner by which they transmit
data across isolation barrier. By
detecting the edge transitions of
the input logic signal and con-
verting this to a narrow current
pulse, which drives the isolation
barrier, the isolator then latches
the input logic state in the output
latch. Since the current pulses
are narrow, about 2.5 ns wide, the
power consumption is indepen-
dent of mark-to-space ratio and
solely dependent on frequency.
The approximate power supply
current per channel is:
I(Input) = 40(f/fmax)(1/4) mA
where f = operating frequency,
fmax = 50 MHz.
Signal Status on Start-up and
Shut Down
To minimize power dissipation,
the input signals to the channels
of HCPL-90xx and HCPL-09xx
digital isolators are differenti-
ated and then latched on the
output side of the isolation
barrier to reconstruct the signal.
This could result in an ambigu-
ous output state depending on
power up, shutdown and power
loss sequencing. Therefore, the
designer should consider the
inclusion of an initialization
signal in this start-up circuit.
Bypassing and PC Board Layout
The HCPL-90xx and HCPL-09xx
digital isolators are extremely
easy to use. No external interface
circuitry is required because the
isolators use high-speed CMOS IC
technology allowing CMOS logic
to be connected directly to the
inputs and outputs. As shown in
Figure 1, the only external
components required for proper
operation are two 47 nF ceramic
capacitors for decoupling the
power supplies. For each capaci-
tor, the total lead length between
both ends of the capacitor and the
power-supply pins should not
exceed 20 mm. Figure 2 illustrates
the recommended printed circuit
board layout for the HCPL-9000
or HCPL-0900. For data rates in
excess of 10MBd, use of ground
planes for both GND1 and GND2 is
highly recommended.
Figure 1. Functional Diagram of Single Channel HCPL-0900 or HCPL-0900.
1
2
3
45
6
7
8
VDD1
IN1
C1 C2
Note: C1, C2 = 47 nF ceramic capacitors
NC
GND1
VDD2
OUT1
GND2
HCPL-9000
or
HCPL-0900
VOE
Figure 2. Recommended Printed Circuit Board Layout.
C2
V
DD2
OUT
1
GND
2
V
DD1
GND
1
IN
1
C1
V
OE
HCPL-9000
or
HCPL-0900
11
Propagation Delay, Pulse Width
Distortion and Propagation Delay Skew
Propagation Delay is a figure of
merit, which describes how
quickly a logic signal propagates
through a system as illustrated in
Figure 3.
The propagation delay from low to
high, t
PLH
, is the amount of time
required for an input signal to
propagate to the output, causing
the output to change from low to
high. Similarly, the propagation
delay from high to low, t
PHL
, is the
amount of time required for the
input signal to propagate to the
output, causing the output to
change from high to low.
Figure 3. Timing Diagrams to Illustrate Propagation Delay, tPLH and tPHL.
Figure 4. Timing Diagrams to Illustrate
Propagation Delay Skew.
V
IN
V
OUT
V
OUT
V
IN
t
PSK
50%
50%
2.5 V
CMOS
2.5 V
CMOS
Pulse Width Distortion, PWD, is
the difference between t
PHL
and
t
PLH
and often determines the
maximum data rate capability of
a transmission system. PWD can
be expressed in percent by
dividing the PWD (in ns) by the
minimum pulse width (in ns)
being transmitted. Typically, PWD
on the order of 20–30% of the
minimum pulse width is tolerable.
Propagation Delay Skew, tPSK,
and Channel-to-Channel Skew,
tCSK, are critical parameters to
consider in parallel data trans-
mission applications where
synchronization of signals on
parallel data lines is a concern.
If the parallel data is being sent
through channels of the digital
isolators, differences in propaga-
tion delays will cause the data to
arrive at the outputs of the
digital isolators at different
times. If this difference in
propagation delay is large
enough, it will limit the maxi-
mum transmission rate at which
parallel data can be sent through
the digital isolators.
t
PSK
is defined as the difference
between the minimum and
maximum propagation delays,
either t
PLH
or t
PHL
, among two or
more devices which are operating
under the same conditions (i.e.,
the same drive current, supply
voltage, output load, and operat-
ing temperature). t
CSK
is defined
as the difference between the
minimum and maximum propaga-
tion delays, either t
PLH
or t
PHL
,
among two or more channels
within a single device (applicable
to dual and quad channel de-
vices) which are operating under
the same conditions.
As illustrated in Figure 4, if the
inputs of two or more devices are
switched either ON or OFF at the
same time, tPSK is the difference
between the minimum propaga-
tion delay, either tPLH or tPHL, and
the maximum propagation delay,
either tPLH or tPHL.
As mentioned earlier, tPSK, can
determine the maximum parallel
data transmission rate. Figure 5
shows the timing diagram of a
typical parallel data transmission
application with both the clock
and data lines being sent through
the digital isolators. The figure
shows data and clock signals at
the inputs and outputs of the
digital isolators. In this case, the
data is clocked off the rising edge
of the clock.
Figure 5. Parallel Data Transmission.
DATA
DATA
INPUTS
CLOCK
OUTPUTS
CLOCK
tPSK
tPSK
INPUT
OUTPUT
5 V CMOS
2.5 V CMOS
0 V
VOH
VOL
VOUT
VIN
tPLH tPHL
50%
10%
90%
90%
10%
www.agilent.com/semiconductors
For product information and a complete list of
distributors, please go to our web site.
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Data subject to change.
Copyright © 2002 Agilent Technologies, Inc.
October 31, 2002
5988-5626EN
Propagation delay skew repre-
sents the uncertainty of where
an edge might be after being sent
through a digital isolator. Figure
5 shows that there will be uncer-
tainty in both the data and clock
lines. It is important that these
two areas of uncertainty not
overlap, otherwise the clock
signal might arrive before all of
the data outputs have settled, or
some of the data outputs may
start to change before the clock
signal has arrived. From these
considerations, the absolute
minimum pulse width that can be
sent through digital isolators in a
parallel application is twice tPSK.
A cautious design should use a
slightly longer pulse width to
Figure 6. Timing Diagrams to Illustrate the Minimum Pulse Width, Rise and Fall Time, and Propagation Delay Enable to
Output Waveforms for HCPL-9000 or HCPL-0900.
ensure that any additional
uncertainty in the rest of the
circuit does not cause a problem.
Figure 6 shows the minimum
pulse width, rise and fall time,
and propagation delay enable to
output waveforms for HCPL-9000
or HCPL-0900.
50%
50%
90%
10% 10%
90%
VIN
VOUT
VOE
t
PW
t
PLZ
t
PZH
t
PHZ
t
PZL
t
F
t
R
t
PW
Minimum Pulse Width t
PHZ
Propagation Delay, High to High Impedance
t
PLZ
Propagation Delay, Low to High Impedance t
PZL
Propagation Delay, High Impedance to Low
t
PZH
Propagation Delay, High Impedance to High t
R
Rise Time
t
F
Fall Time
