PDM Digital Input, Mono 2.4 W Class-D Audio Amplifier SSM2517 Data Sheet enables extremely low real-world power consumption from digital audio sources with excellent audio performance. Using the SSM2517, audio can be transmitted digitally to the audio amplifier, significantly reducing the effect of noise sources such as GSM interference or other digital signals on the transmitted audio. The SSM2517 is capable of delivering 2.4 W of continuous output power with <1% THD + N driving a 4 load from a 5.0 V supply. FEATURES Filterless digital Class-D amplifier Pulse density modulation (PDM) digital input interface 2.4 W into 4 load and 1.38 W into 8 load at 5.0 V supply with <1% total harmonic distortion plus noise (THD + N) Available in 9-ball, 1.5 mm x 1.5 mm, 0.5 mm pitch WLCSP 92% efficiency into 8 at full scale Output noise: 43 V rms at 3.6 V, A-weighted THD + N: 0.035% at 1 kHz, 100 mW output power PSRR: 85 dB at 217 Hz, input referred with dither input Quiescent power consumption: 10.4 mW (VDD = 1.8 V, PVDD = 3.6 V, 8 + 33 H load) Pop-and-click suppression Configurable with PDM pattern inputs Short-circuit and thermal protection with autorecovery Smart power-down when PDM stop condition or no clock input detected 64 x fS or 128 x fS operation supporting 3 MHz and 6 MHz clocks DC blocking high-pass filter and static input dc protection User-selectable ultralow EMI emissions mode Power-on reset (POR) Minimal external passive components The SSM2517 features a high efficiency, low noise modulation scheme that requires no external LC output filters. The closed-loop, three-level modulator design retains the benefits of an all-digital amplifier, yet enables very good PSRR and audio performance. The modulation continues to provide high efficiency even at low output power and has an SNR of 96 dB. Spread-spectrum pulse density modulation is used to provide lower EMI-radiated emissions compared with other Class-D architectures. The SSM2517 has a four-state gain and sample frequency selection pin that can select two different gain settings, optimized for 3.6 V and 5 V operation. This same pin also controls the internal digital filtering and clocking, which can be set for 64 x fS or 128 x fS input sample rates to support both 3 MHz and 6 MHz PDM clock rates. The SSM2517 has a micropower shutdown mode with a typical shutdown current of 1 A for both power supplies. Shutdown is enabled automatically by gating input clock and data signals. A standby mode can be entered by applying a designated PDM stop condition sequence. The device also includes pop-and-click suppression circuitry. This suppression circuitry minimizes voltage glitches at the output when entering or leaving the low power state, reducing audible noises on activation and deactivation. APPLICATIONS Mobile handsets GENERAL DESCRIPTION The SSM2517 is a PDM digital input Class-D power amplifier that offers higher performance than existing DAC plus Class-D solutions. The SSM2517 is ideal for power sensitive applications, such as mobile phones and portable media players, where system noise can corrupt the small analog signal sent to the amplifier. The SSM2517 is specified over the industrial temperature range of -40C to +85C. It has built-in thermal shutdown and output short-circuit protection. It is available in a 9-ball, 1.5 mm x 1.5 mm wafer level chip scale package (WLCSP). The SSM2517 combines an audio digital-to-analog converter (DAC), a power amplifier, and a PDM digital interface on a single chip. The integrated DAC plus analog - modulator architecture FUNCTIONAL BLOCK DIAGRAM VDD CLOCKING POWER CONTROL INPUT INTERFACE FILTERING/ DAC PDAT PGND SSM2517 - CLASS-D MODULATOR OUT+ FULL-BRIDGE POWER STAGE PCLK OUT- GAIN_FS LRSEL 09211-001 POWER-ON RESET PVDD Figure 1. Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2010-2011 Analog Devices, Inc. All rights reserved. SSM2517 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Master Clock ............................................................................... 13 Applications....................................................................................... 1 Power Supplies ............................................................................ 13 General Description ......................................................................... 1 Power Control............................................................................. 13 Functional Block Diagram .............................................................. 1 Power-On Reset/Voltage Supervisor ....................................... 13 Revision History ............................................................................... 2 System Gain/Input Frequency .................................................. 13 Specifications..................................................................................... 3 PDM Pattern Control ................................................................ 14 Digital Input Specifications......................................................... 4 EMI Noise.................................................................................... 14 PDM Interface Digital Timing Specifications .......................... 5 Output Modulation Description .............................................. 14 Absolute Maximum Ratings............................................................ 6 Applications Information .............................................................. 15 Thermal Resistance ...................................................................... 6 Layout .......................................................................................... 15 ESD Caution.................................................................................. 6 Power Supply Decoupling ......................................................... 15 Pin Configuration and Function Descriptions............................. 7 Outline Dimensions ....................................................................... 16 Typical Performance Characteristics ............................................. 8 Ordering Guide .......................................................................... 16 Theory of Operation ...................................................................... 13 REVISION HISTORY 9/11--Rev. A to Rev. B Changes to Table 3, Endnote 1, and Figure 2................................ 5 5/11--Rev. 0 to Rev. A Changes to Table 6, LRSEL Pin Description................................. 7 10/10--Revision 0: Initial Version Rev. B | Page 2 of 16 Data Sheet SSM2517 SPECIFICATIONS PVDD = 5.0 V, VDD = 1.8 V, fS = 128x, TA = 25C, RL = 8 + 33 H, unless otherwise noted. When fS = 128x, PDM clock = 6.144 MHz; when fS = 64x, PDM clock = 3.072 MHz. Table 1. Parameter DEVICE CHARACTERISTICS Output Power Total Harmonic Distortion Plus Noise Symbol Test Conditions/Comments PO f = 1 kHz, BW = 20 kHz RL = 4 , THD = 1%, PVDD = 5.0 V RL = 8 , THD = 1%, PVDD = 5.0 V RL = 4 , THD = 1%, PVDD = 3.6 V RL = 8 , THD = 1%, PVDD = 3.6 V RL = 4 , THD = 10%, PVDD = 3.6 V RL = 8 , THD = 10%, PVDD = 3.6 V f = 1 kHz, BW = 20 kHz PO = 100 mW into 8 , PVDD = 3.6 V PO = 500 mW into 8 , PVDD = 3.6 V PO = 1 W into 8 , PVDD = 5.0 V RL = 4 , -6 dBFS input, PVDD = 5.0 V RL = 8 , -6 dBFS input, PVDD = 5.0 V RL = 4 , -6 dBFS input, PVDD = 3.6 V RL = 8 , -6 dBFS input, PVDD = 3.6 V PO = 2.4 W into 4 , PVDD = 5.0 V PO = 1.38 W into 8 , PVDD = 5.0 V No input -6 dBFS PDM input, BTL output, f = 1 kHz PVDD = 3.6 V PVDD = 5.0 V Gain = 6 dB THD + N Efficiency Average Switching Frequency Closed-Loop Gain fSW Gain Differential Output Offset Voltage Low Power Mode Wake Time Input Sampling Frequency POWER SUPPLY Supply Voltage Range Amplifier Power Supply Digital Power Supply Power Supply Rejection Ratio Supply Current, H-Bridge Standby Current Power-Down Current Supply Current, Modulator VOOS tWAKE fS PVDD VDD PSRRGSM IPVDD IVDD fS = 64x fS = 128x VRIPPLE = 100 mV at 217 Hz Dither input, 8 + 33 H load PVDD = 5.0 V, fS = 64x PVDD = 5.0 V, fS = 128x PVDD = 3.6 V, fS = 64x PVDD = 3.6 V, fS = 128x PVDD = 2.5 V, fS = 64x PVDD = 2.5 V, fS = 128x PVDD = 5.0 V Dither input, 8 + 33 H load VDD = 3.3 V, fS = 64x VDD = 3.3 V, fS = 128x VDD = 1.8 V, fS = 64x VDD = 1.8 V, fS = 128x Rev. B | Page 3 of 16 Min Typ Max Unit 2.4 1.38 1.2 0.7 1.5 0.9 W W W W W W 0.035 0.1 0.12 3.6 1.0 5.2 2.3 86 92 290 % % % % % % % % % kHz 3.5 4.78 0.5 VP VP mV ms MHz MHz 1.84 3.68 3.072 6.144 2.5 1.62 3.6 1.8 85 0.5 3.23 6.46 5.5 3.6 V V dB 3.1 3.2 2.6 2.7 2.2 2.3 0.0 100 mA mA mA mA mA mA mA nA 1.3 2.4 0.6 1.2 mA mA mA mA SSM2517 Parameter Standby Current Data Sheet Symbol Test Conditions/Comments VDD = 1.8 V, fS = 64x VDD = 1.8 V, fS = 128x VDD = 3.3 V VDD = 1.8 V en Dithered input, A-weighted PVDD = 3.6 V, fS = 64x PVDD = 3.6 V, fS = 128x PVDD = 5.0 V, fS = 64x PVDD = 5.0 V, fS = 128x PO = 1.38 W, PVDD = 5.0 V, RL = 8 , A-weighted fS = 64x fS = 128x Shutdown Current NOISE PERFORMANCE Output Voltage Noise Signal-to-Noise Ratio SNR Min DIGITAL INPUT SPECIFICATIONS Table 2. Parameter INPUT SPECIFICATIONS Input Voltage High PCLK, PDAT, LRSEL Pins GAIN_FS Pin Input Voltage Low PCLK, PDAT, LRSEL Pins GAIN_FS Pin Input Leakage High PDAT, LRSEL, GAIN_FS Pins PCLK Pin Input Leakage Low PDAT, LRSEL, GAIN_FS Pins PCLK Pin Input Capacitance Symbol Min Typ Max Unit 0.7 x VDD 1.35 3.6 5.5 -0.3 -0.3 0.3 x VDD +0.35 V V V V V 1 3 A A 1 3 5 A A pF VIH VIL IIH IIL Rev. B | Page 4 of 16 Typ 57 114 3.0 0.9 Max Unit A A A A 43 52 52 60 V V V V 96 95 dB dB Data Sheet SSM2517 PDM INTERFACE DIGITAL TIMING SPECIFICATIONS Table 3. Parameter tDS tDE 1 tMIN 44 Limit tMAX 7 Unit ns ns Description Valid data start time 1 Valid data end time1 The SSM2517 was designed so that the data line can transition coincident with or close to a clock edge. It is not necessary to delay the data line transition until after the clock edge because the SSM2517 does this internally to ensure good timing margins. The data line should remain constant during the valid sample period illustrated in Figure 2; it may transition at any other time. Timing is measured from 70% of VDD on the rising edge or 30% VDD on the falling edge. Timing Diagram PCLK tDS tDE VALID LEFT SAMPLE VALID RIGHT SAMPLE Figure 2. PDM Interface Timing Rev. B | Page 5 of 16 VALID LEFT SAMPLE 09211-002 PDAT SSM2517 Data Sheet ABSOLUTE MAXIMUM RATINGS Absolute maximum ratings apply at 25C, unless otherwise noted. THERMAL RESISTANCE Table 4. Junction-to-air thermal resistance (JA) is specified for the worstcase conditions, that is, a device soldered in a printed circuit board (PCB) for surface-mount packages. JA and JB (junction-to-board thermal resistance) are determined according to JEDEC JESD51-9 on a 4-layer PCB with natural convection cooling. Parameter PVDD Supply Voltage VDD Supply Voltage Input Voltage (Signal Source) ESD Susceptibility OUT- and OUT+ Pins Storage Temperature Range Operating Temperature Range Junction Temperature Range Lead Temperature (Soldering, 60 sec) Rating -0.3 V to +6 V -0.3 V to +3.6 V -0.3 V to +3.6 V 4 kV 8 kV -65C to +150C -40C to +85C -65C to +165C 300C Table 5. Thermal Resistance Package Type 9-Ball, 1.5 mm x 1.5 mm WLCSP Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION Rev. B | Page 6 of 16 PCB 1S0P 2S0P JA 162 76 JB 39 21 Unit C/W C/W Data Sheet SSM2517 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS BALL A1 CORNER 1 2 3 OUT+ PVDD PGND OUT- LRSEL VDD PCLK PDAT GAIN_FS A B TOP VIEW (BALL SIDE DOWN) Not to Scale 09211-003 C Figure 3. Pin Configuration Table 6. Pin Function Descriptions Pin No. A1 A2 A3 B1 B2 B3 C1 C2 C3 Mnemonic OUT+ PVDD PGND OUT- LRSEL VDD PCLK PDAT GAIN_FS Function Output Supply Ground Output Input Supply Input Input Input Description Noninverting Output. Amplifier Power, 2.5 V to 5.5 V. Amplifier Ground. Inverting Output. Left/Right Channel Select. Pull up to VDD for right channel; tie to ground for left channel. Digital Power, 1.62 V to 3.6 V. PDM Interface Master Clock. PDM Data Signal. Gain and Sample Rate Selection Pin. Rev. B | Page 7 of 16 SSM2517 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS THD + N (%) 10 1 PVDD = 2.5V PVDD = 3.6V 0.1 0.01 0.001 0.01 0.1 1 10 OUTPUT POWER (W) PVDD = 2.5V PVDD = 3.6V PVDD = 5V 0.01 0.1 1 Figure 7. THD + N vs. Output Power into 8 , Gain = 5 V, fS = 128x 100 RL = 8 + 33H GAIN = 3.6V SAMPLE RATE = 64x (3.072MHz) THD + N (%) 10 1 PVDD = 2.5V RL = 8 + 33H GAIN = 3.6V SAMPLE RATE = 128x (6.144MHz) 1 PVDD = 2.5V PVDD = 3.6V PVDD = 3.6V 0.1 0.1 0.01 0.1 1 10 OUTPUT POWER (W) 0.01 0.001 09211-012 0.01 0.001 0.01 Figure 5. THD + N vs. Output Power into 8 , Gain = 3.6 V, fS = 64x 1 10 Figure 8. THD + N vs. Output Power into 8 , Gain = 3.6 V, fS = 128x 100 100 RL = 4 + 15H GAIN = 5V SAMPLE RATE = 64x (3.072MHz) 10 RL = 4 + 15H GAIN = 5V SAMPLE RATE = 128x (6.144MHz) PVDD = 3.6V 1 PVDD = 2.5V 0.1 0.01 0.1 1 PVDD = 2.5V 0.1 PVDD = 5V 10 OUTPUT POWER (W) 09211-014 0.01 0.001 1 Figure 6. THD + N vs. Output Power into 4 , Gain = 5 V, fS = 64x 0.01 0.001 PVDD = 5V 0.01 0.1 1 10 OUTPUT POWER (W) Figure 9. THD + N vs. Output Power into 4 , Gain = 5 V, fS = 128x Rev. B | Page 8 of 16 09211-015 THD + N (%) PVDD = 3.6V THD + N (%) 0.1 OUTPUT POWER (W) 09211-013 PVDD = 5V PVDD = 5V 10 10 OUTPUT POWER (W) 100 THD + N (%) 1 0.01 0.001 Figure 4. THD + N vs. Output Power into 8 , Gain = 5 V, fS = 64x 10 RL = 8 + 33H GAIN = 5V SAMPLE RATE = 128x (6.144MHz) 0.1 PVDD = 5V 09211-010 THD + N (%) 10 100 RL = 8 + 33H GAIN = 5V SAMPLE RATE = 64x (3.072MHz) 09211-011 100 Data Sheet SSM2517 100 10 RL = 4 + 15H GAIN = 3.6V SAMPLE RATE = 128x (6.144MHz) PVDD = 3.6V PVDD = 2.5V 0.1 0.01 0.1 1 10 OUTPUT POWER (W) 0.01 THD + N (%) 10 0.5W 0.1 RL = 4 + 15H PVDD = 5V GAIN = 5V SAMPLE RATE = 64x (3.072MHz) 1 1.0W 0.5W 0.1 0.25W 0.25W 1k 10k 100k 0.01 10 09211-018 100 FREQUENCY (Hz) 100 1k 10k 100k FREQUENCY (Hz) Figure 11. THD + N vs. Frequency, PVDD = 5 V, Gain = 5 V, RL = 8 , fS = 64x Figure 14. THD + N vs. Frequency, PVDD = 5 V, Gain = 5 V, RL = 4 , fS = 64x 100 100 RL = 8 + 33H PVDD = 3.6V GAIN = 3.6V SAMPLE RATE = 64x (3.072MHz) THD + N (%) 10 1 0.5W RL = 4 + 15H PVDD = 3.6V GAIN = 3.6V SAMPLE RATE = 64x (3.072MHz) 1 0.5W 0.25W 0.25W 0.1 0.1 100 1k 10k 100k FREQUENCY (Hz) Figure 12. THD + N vs. Frequency, PVDD = 3.6 V, Gain = 3.6 V, RL = 8 , fS = 64x 0.01 10 100 1k 10k 100k FREQUENCY (Hz) Figure 15. THD + N vs. Frequency, PVDD = 3.6 V, Gain = 3.6 V, RL = 4 , fS = 64x Rev. B | Page 9 of 16 09211-021 0.125W 0.125W 0.01 10 09211-020 THD + N (%) 10 100 RL = 8 + 33H PVDD = 5V GAIN = 5V SAMPLE RATE = 64x (3.072MHz) 1.0W 10 1 Figure 13. THD + N vs. Output Power into 4 , Gain = 3.6 V, fS = 128x 1 0.01 10 0.1 OUTPUT POWER (W) 100 THD + N (%) PVDD = 5V 0.01 0.001 Figure 10. THD + N vs. Output Power into 4 , Gain = 3.6 V, fS = 64x 10 PVDD = 2.5V 0.1 PVDD = 5V 0.01 0.001 1 09211-017 THD + N (%) 1 09211-016 THD + N (%) PVDD = 3.6V 09211-019 10 100 RL = 4 + 15H GAIN = 3.6V SAMPLE RATE = 64x (3.072MHz) SSM2517 Data Sheet 100 RL = 4 + 15H PVDD = 2.5V GAIN = 3.6V SAMPLE RATE = 64x (3.072MHz) 10 THD + N (%) 1 0.2W 1 0.25W 0.1W 0.1W 0.1 0.1 0.05W 0.05W 100 1k 10k 100k FREQUENCY (Hz) 0.01 10 09211-022 0.01 10 100k 0 GAIN = 5V SAMPLE RATE = 64x (3.072MHz) RL = 8 + 33H PVDD = 3.6V GAIN = 3.6V SAMPLE RATE = 128x (6.144MHz) -20 RL = 4 + 15H -40 AMPLITUDE (dBV) QUIESCENT CURRENT (mA) 10k Figure 19. THD + N vs. Frequency, PVDD = 2.5 V, Gain = 3.6 V, RL = 4 , fS = 64x 4.0 3.0 1k FREQUENCY (Hz) Figure 16. THD + N vs. Frequency, PVDD = 2.5 V, Gain = 3.6 V, RL = 8 , fS = 64x 3.5 100 09211-023 THD + N (%) 10 100 RL = 8 + 33H PVDD = 2.5V GAIN = 3.6V SAMPLE RATE = 64x (3.072MHz) RL = 8 + 33H NO LOAD 2.5 -60 -80 -100 -120 2.0 3.0 3.5 4.0 4.5 5.0 5.5 6.0 SUPPLY VOLTAGE (V) -160 09211-024 1.6 OUTPUT POWER (W) 1.4 1.0 THD + N = 10% 0.8 0.6 THD + N = 1% 8 10 12 14 16 18 20 1.0 THD + N = 10% 0.8 0.6 0.4 0.2 0.2 3.0 3.5 4.0 4.5 5.0 SUPPLY VOLTAGE (V) Figure 18. Maximum Output Power vs. Supply Voltage, Gain = 5 V, RL = 8 , fS = 64x RL = 8 + 33H GAIN = 5V SAMPLE RATE = 128x (6.144MHz) 1.2 0.4 09211-025 OUTPUT POWER (W) 6 1.8 RL = 8 + 33H GAIN = 5V SAMPLE RATE = 64x (3.072MHz) 1.2 0 2.5 4 FREQUENCY (kHz) 1.8 1.4 2 Figure 20. Output Spectrum vs. Frequency, PVDD = 3.6 V, Gain = 3.6 V, RL = 8 , fS = 128x Figure 17. Quiescent Current (H-Bridge) vs. Supply Voltage, Gain = 5 V, fS = 64x 1.6 0 0 2.5 THD + N = 1% 3.0 3.5 4.0 4.5 5.0 SUPPLY VOLTAGE (V) Figure 21. Maximum Output Power vs. Supply Voltage, Gain = 5 V, RL = 8 , fS = 128x Rev. B | Page 10 of 16 09211-026 1.5 2.5 09211-033 -140 Data Sheet SSM2517 3.5 3.5 RL = 4 + 15H GAIN = 5V SAMPLE RATE = 64x (3.072MHz) 3.0 2.0 THD + N = 10% THD + N = 1% 1.0 2.5 OUTPUT POWER (W) 2.0 3.5 4.0 4.5 0 2.5 09211-027 3.0 5.0 SUPPLY VOLTAGE (V) 4.0 4.5 5.0 Figure 25. Maximum Output Power vs. Supply Voltage, Gain = 5 V, RL = 4 , fS = 128x 100 PVDD = 3.6V PVDD = 2.5V 3.5 SUPPLY VOLTAGE (V) Figure 22. Maximum Output Power vs. Supply Voltage, Gain = 5 V, RL = 4 , fS = 64x 100 3.0 09211-028 0.5 0 2.5 90 PVDD = 5V 90 80 80 PVDD = 5V 70 PVDD = 3.6V 70 EFFICIENCY (%) 60 50 40 30 PVDD = 2.5V 60 50 40 30 10 OUTPUT POWER (W) 3.4 3.2 3.0 2.8 0 2.6 2.0 2.4 1.8 2.2 1.6 2.0 1.4 1.8 1.2 1.6 1.0 1.4 0.8 1.2 0.6 1.0 0.4 0.8 0.2 0.6 0 0 0 09211-029 10 RL = 4 + 15H GAIN = 5V SAMPLE RATE = 64x (3.072MHz) 20 OUTPUT POWER (W) Figure 23. Efficiency vs. Output Power into 8 , Gain = 5 V, fS = 64x 09211-031 RL = 8 + 33H GAIN = 5V SAMPLE RATE = 64x (3.072MHz) 20 0.4 Figure 26. Efficiency vs. Output Power into 4 , Gain = 5 V, fS = 64x 450 800 RL = 8 + 33H GAIN = 5V SAMPLE RATE = 64x (3.072MHz) 350 PVDD = 5V 300 PVDD = 3.6V 250 PVDD = 2.5V 200 RL = 4 + 15H GAIN = 5V SAMPLE RATE = 64x (3.072MHz) 700 SUPPLY CURRENT (mA) 400 150 100 PVDD = 5V 600 PVDD = 3.6V 500 400 PVDD = 2.5V 300 200 100 0 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 OUTPUT POWER (W) 09211-032 50 Figure 24. Supply Current (H-Bridge) vs. Output Power into 8 , Gain = 5 V, fS = 64x 0 0 0.5 1.0 1.5 2.0 2.5 3.0 OUTPUT POWER (W) Figure 27. Supply Current (H-Bridge) vs. Output Power into 4 , Gain = 5 V, fS = 64x Rev. B | Page 11 of 16 09211-036 EFFICIENCY (%) THD + N = 1% 1.0 0.5 SUPPLY CURRENT (mA) THD + N = 10% 1.5 0.2 OUTPUT POWER (W) 2.5 1.5 RL = 4 + 15H GAIN = 5V SAMPLE RATE = 128x (6.144MHz) 3.0 SSM2517 Data Sheet 5 0 OUTPUT PCLK -10 4 -20 3 VOLTAGE (V) -40 -50 -60 2 1 PVDD = 3.6V -70 0 -80 -100 10 100 1k FREQUENCY (Hz) 10k 100k -2 -40 09211-035 -1 PVDD = 5V -90 09211-034 PSRR (dB) -30 -20 0 20 40 60 80 100 TIME (s) Figure 29. Turn-On Response Figure 28. Power Supply Rejection Ratio (PSRR) vs. Frequency Rev. B | Page 12 of 16 120 140 160 Data Sheet SSM2517 THEORY OF OPERATION MASTER CLOCK SYSTEM GAIN/INPUT FREQUENCY The SSM2517 requires a clock present at the PCLK input pin. This clock must be fully synchronous with the incoming digital audio on the serial interface. The clock frequencies must fall into one of these ranges: 1.84 MHz to 3.23 MHz or 3.68 MHz to 6.46 MHz. The GAIN_FS pin is used to set the internal gain and filtering configuration for different sample rates of the SSM2517. This pin can be set to one of four states by connecting the pin to PVDD or PGND (see Table 7). The internal gain and filtering can also be set via PDM pattern control, allowing these settings to be modified during operation (see the PDM Pattern Control section). POWER SUPPLIES The SSM2517 requires two power supplies: PVDD and VDD. Table 7. GAIN_FS Function Descriptions PVDD Device Setting fS = 64 x PCLK, Gain = 5 V The PVDD pin supplies power to the full-bridge power stage of a MOSFET and its associated drive, control, and protection circuitry. It also supplies power to the digital-to-analog converter (DAC) and to the Class-D PDM modulator. PVDD can operate from 2.5 V to 5.5 V and must be present to obtain audio output. Lowering the supply voltage of PVDD results in lower maximum output power and, therefore, lower power consumption. VDD The VDD pin provides power to the digital logic circuitry. VDD can operate from 1.62 V to 3.6 V and must be present to obtain audio output. Lowering the supply voltage of VDD results in lower power consumption but does not affect audio performance. POWER CONTROL On device power-up, PVDD must first be applied to the device, which latches in the designated GAIN_FS pin functionality. The SSM2517 contains a smart power-down feature. When enabled, the smart power-down feature looks at the incoming digital audio and, if it receives the PDM stop condition of at least 128 repeated 0xAC bytes (1024 clock cycles), it places the SSM2517 in the standby state. In the standby state, the PCLK can be removed, resulting in a full power-down state. This state is the lowest power condition possible. When the PCLK is turned on again and a single non-stop condition input is received, the SSM2517 leaves the full power-down state and resumes normal operation. fS = 128 x PCLK, Gain = 5 V fS = 64 x PCLK, Gain = 3.6 V fS = 128 x PCLK, Gain = 3.6 V GAIN Pin Configuration Pull up to PVDD with a 47 k resistor Pull down to PGND with a 47 k resistor Pull up to PVDD Pull down to PGND The SSM2517 has an internal analog gain control such that when GAIN_FS is tied to PGND or PVDD via a 47 k resistor (5 V gain setting), a -6.02 dBFS PDM input signal results in an amplifier output voltage of 5 V peak. This setting should produce optimal noise performance when PVDD = 5 V. When the GAIN_FS pin is tied directly to PGND or PVDD, the gain is adjusted so that a -6.02 dBFS PDM input signal results in an amplifier output voltage of 3.6 V peak. This setting should produce optimal noise performance when PVDD = 3.6 V. The SSM2517 can handle input sample rates of 64 x fS (~3 MHz) and 128 x fS (~6 MHz). Different internal digital filtering is used in each of these cases. Selection of the sample rate is also set via the GAIN_FS pin (see Table 7). Because the 64 x fS mode provides better performance with lower power consumption, its use is recommended. The 128 x fS mode should be used only when overall system noise performance is limited by the source modulator. POWER-ON RESET/VOLTAGE SUPERVISOR The SSM2517 includes an internal power-on reset and voltage supervisor circuit. This circuit provides an internal reset to all circuitry whenever PVDD or VDD is substantially below the nominal operating threshold. This circuit simplifies supply sequencing during initial power-on. The circuit also monitors the power supplies to the SSM2517. If the supply voltages fall below the nominal operating threshold, this circuit stops the output and issues a reset. This ensures that no damage occurs due to low voltage operation and that no pops can occur under nearly any power removal condition. Rev. B | Page 13 of 16 SSM2517 Data Sheet PDM PATTERN CONTROL OUTPUT MODULATION DESCRIPTION The SSM2517 has a simple control mechanism that can set the part for low power states and control functionality. This is accomplished by sending a repeating 8-bit pattern to the device. Different patterns set different functionality (see Table 8). The SSM2517 uses three-level, - output modulation. Each output can swing from PGND to PVDD and vice versa. Ideally, when no input signal is present, the output differential voltage is 0 V because there is no need to generate a pulse. In a real-world situation, noise sources are always present. All functionality set via patterns returns to its default value after a clock-loss power-down. Table 8. PDM Watermarking Pattern Control Descriptions Pattern 0xAC 0xD8 0xD4 0xD2 0xD1 0xE1 0xE2 0xE4 Control Description Power-down. All blocks off except for PDM interface. Normal start-up time. Gain optimized for PVDD = 5 V operation. Overrides GAIN_FS pin setting. Gain optimized for PVDD = 3.6 V operation. Overrides GAIN_FS pin setting. Gain optimized for PVDD = 2.5 V operation. Overrides GAIN_FS pin setting. fS set to opposite value determined by GAIN_FS pin. Ultralow EMI mode. Half clock cycle pulse mode for power savings. Special 32 kHz/128 x fS operation mode. Due to this constant presence of noise, a differential pulse is generated, when required, in response to this stimulus. A small amount of current flows into the inductive load when the differential pulse is generated. Most of the time, however, the output differential voltage is 0 V, due to the Analog Devices, Inc., three-level, - output modulation. This feature ensures that the current flowing through the inductive load is small. When the user wants to send an input signal, an output pulse (OUT+ and OUT-) is generated to follow the input voltage. The differential pulse density (VOUT) is increased by raising the input signal level. Figure 30 depicts three-level, - output modulation with and without input stimulus. OUTPUT = 0V OUT+ 0V +5V OUT- 0V +5V VOUT 0V -5V OUTPUT > 0V EMI NOISE OUT+ The SSM2517 uses a proprietary modulation and spreadspectrum technology to minimize EMI emissions from the device. For applications that have difficulty passing FCC Class-B emission tests, the SSM2517 includes a modulation select mode (ultralow EMI emissions mode) that significantly reduces the radiated emissions at the Class-D outputs, particularly above 100 MHz. This mode is enabled by activating PDM Watermarking Pattern 0xE1 (see Table 8). +5V 0V +5V OUT- 0V +5V VOUT 0V OUTPUT < 0V OUT+ OUT- VOUT +5V +5V 0V +5V 0V 0V -5V 09211-009 Any pattern must be repeated a minimum of 128 times. The part is automatically muted when a pattern is detected so that a pattern can be set while the part is operational without a pop/click due to pattern transition. Figure 30. Three-Level, - Output Modulation With and Without Input Stimulus Rev. B | Page 14 of 16 Data Sheet SSM2517 APPLICATIONS INFORMATION LAYOUT As output power increases, care must be taken to lay out PCB traces and wires properly among the amplifier, load, and power supply. A good practice is to use short, wide PCB tracks to decrease voltage drops and minimize inductance. The PCB layout engineer must avoid ground loops where possible to minimize common-mode current associated with separate paths to ground. Ensure that track widths are at least 200 mil per inch of track length for lowest DCR, and use 1 oz or 2 oz copper PCB traces to further reduce IR drops and inductance. A poor layout increases voltage drops, consequently affecting efficiency. Use large traces for the power supply inputs and amplifier outputs to minimize losses due to parasitic trace resistance. Proper grounding guidelines help to improve audio performance, minimize crosstalk between channels, and prevent switching noise from coupling into the audio signal. To maintain high output swing and high peak output power, the PCB traces that connect the output pins to the load, as well as the PCB traces to the supply pins, should be as wide as possible to maintain the minimum trace resistances. It is also recommended that a large ground plane be used for minimum impedances. Properly designed multilayer PCBs can reduce EMI emissions and increase immunity to the RF field by a factor of 10 or more, compared with double-sided boards. A multilayer board allows a complete layer to be used for the ground plane, whereas the ground plane side of a double-sided board is often disrupted by signal crossover. POWER SUPPLY DECOUPLING To ensure high efficiency, low total harmonic distortion (THD), and high PSRR, proper power supply decoupling is necessary. Noise transients on the power supply lines are short-duration voltage spikes. These spikes can contain frequency components that extend into the hundreds of megahertz. The power supply inputs must be decoupled with a good quality, low ESL, low ESR capacitor, with a minimum value of 4.7 F for the PVDD pin and 0.1 F for the VDD pin. This capacitor bypasses low frequency noises to the ground plane. For high frequency transient noises, use a 0.1 F capacitor as close as possible to the PVDD and VDD pins of the device. Placing the decoupling capacitors as close as possible to the SSM2517 helps to maintain efficient performance. In addition, good PCB layout isolates critical analog paths from sources of high interference. High frequency circuits (analog and digital) should be separated from low frequency circuits. Rev. B | Page 15 of 16 SSM2517 Data Sheet OUTLINE DIMENSIONS 0.655 0.600 0.545 SEATING PLANE 3 2 A 0.350 0.320 0.290 BALL A1 IDENTIFIER B C 0.50 BALL PITCH TOP VIEW (BALL SIDE DOWN) 0.385 0.360 0.335 1 BOTTOM VIEW 0.270 0.240 0.210 (BALL SIDE UP) 101507-C 1.490 1.460 SQ 1.430 Figure 31. 9-Ball Wafer Level Chip Scale Package [WLCSP] (CB-9-2) Dimensions shown in millimeters ORDERING GUIDE Model 1 SSM2517CBZ-R7 SSM2517CBZ-RL EVAL-SSM2517Z 1 Temperature Range -40C to +85C -40C to +85C Package Description 9-Ball Wafer Level Chip Scale Package [WLCSP] 9-Ball Wafer Level Chip Scale Package [WLCSP] Evaluation Board Z = RoHS Compliant Part. (c)2010-2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D09211-0-9/11(B) Rev. B | Page 16 of 16 Package Option CB-9-2 CB-9-2 Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: Analog Devices Inc.: EVAL-SSM2517Z SSM2517CBZ-R7 SSM2517CBZ-RL