PDM Digital Input, Mono
2.4 W Class-D Audio Amplifier
Data Sheet SSM2517
Rev. B
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FEATURES
Filterless digital Class-D amplifier
Pulse density modulation (PDM) digital input interface
2.4 W into 4 Ω load and 1.38 W into 8 Ω load at 5.0 V supply
with <1% total harmonic distortion plus noise (THD + N)
Available in 9-ball, 1.5 mm × 1.5 mm, 0.5 mm pitch WLCSP
92% efficiency into 8 Ω at full scale
Output noise: 43 μV rms at 3.6 V, A-weighted
THD + N: 0.035% at 1 kHz, 100 mW output power
PSRR: 85 dB at 217 Hz, input referred with dither input
Quiescent power consumption: 10.4 mW
(VDD = 1.8 V, PVDD = 3.6 V, 8 Ω + 33 μH load)
Pop-and-click suppression
Configurable with PDM pattern inputs
Short-circuit and thermal protection with autorecovery
Smart power-down when PDM stop condition
or no clock input detected
64 × fS or 128 × fS operation supporting 3 MHz and 6 MHz clocks
DC blocking high-pass filter and static input dc protection
User-selectable ultralow EMI emissions mode
Power-on reset (POR)
Minimal external passive components
APPLICATIONS
Mobile handsets
GENERAL DESCRIPTION
The SSM2517 is a PDM digital input Class-D power amplifier
that offers higher performance than existing DAC plus Class-D
solutions. The SSM2517 is ideal for power sensitive applications,
such as mobile phones and portable media players, where system
noise can corrupt the small analog signal sent to the amplifier.
The SSM2517 combines an audio digital-to-analog converter
(DAC), a power amplifier, and a PDM digital interface on a single
chip. The integrated DAC plus analog Σ-Δ modulator architecture
enables extremely low real-world power consumption from
digital audio sources with excellent audio performance. Using
the SSM2517, audio can be transmitted digitally to the audio
amplifier, significantly reducing the effect of noise sources such as
GSM interference or other digital signals on the transmitted audio.
The SSM2517 is capable of delivering 2.4 W of continuous output
power with <1% THD + N driving a 4 Ω load from a 5.0 V supply.
The SSM2517 features a high efficiency, low noise modulation
scheme that requires no external LC output filters. The closed-loop,
three-level modulator design retains the benefits of an all-digital
amplifier, yet enables very good PSRR and audio performance. The
modulation continues to provide high efficiency even at low output
power and has an SNR of 96 dB. Spread-spectrum pulse density
modulation is used to provide lower EMI-radiated emissions
compared with other Class-D architectures.
The SSM2517 has a four-state gain and sample frequency selection
pin that can select two different gain settings, optimized for 3.6 V
and 5 V operation. This same pin also controls the internal digital
filtering and clocking, which can be set for 64 × fS or 128 × fS input
sample rates to support both 3 MHz and 6 MHz PDM clock rates.
The SSM2517 has a micropower shutdown mode with a typical
shutdown current of 1 μA for both power supplies. Shutdown is
enabled automatically by gating input clock and data signals. A
standby mode can be entered by applying a designated PDM stop
condition sequence. The device also includes pop-and-click sup-
pression circuitry. This suppression circuitry minimizes voltage
glitches at the output when entering or leaving the low power
state, reducing audible noises on activation and deactivation.
The SSM2517 is specified over the industrial temperature range
of −40°C to +85°C. It has built-in thermal shutdown and output
short-circuit protection. It is available in a 9-ball, 1.5 mm × 1.5 mm
wafer level chip scale package (WLCSP).
FUNCTIONAL BLOCK DIAGRAM
PDAT
V
DD
POWER-ON
RESET
CLOCKING POWER
CONTROL
PCLK
GAIN_FS LRSEL
OUT+
OUT–
PVDD PGND
INPUT
INTERFACE
FILTERING/
DAC
Σ-∆
CLASS-D
MODULATOR
FULL-BRIDGE
POWER STAGE
09211-001
SSM2517
Figure 1.
SSM2517 Data Sheet
Rev. B | Page 2 of 16
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
General Description......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Digital Input Specifications......................................................... 4
PDM Interface Digital Timing Specifications .......................... 5
Absolute Maximum Ratings............................................................ 6
Thermal Resistance ...................................................................... 6
ESD Caution.................................................................................. 6
Pin Configuration and Function Descriptions............................. 7
Typical Performance Characteristics ............................................. 8
Theory of Operation ...................................................................... 13
Master Clock............................................................................... 13
Power Supplies............................................................................ 13
Power Control............................................................................. 13
Power-On Reset/Voltage Supervisor ....................................... 13
System Gain/Input Frequency.................................................. 13
PDM Pattern Control ................................................................ 14
EMI Noise.................................................................................... 14
Output Modulation Description .............................................. 14
Applications Information.............................................................. 15
Layout .......................................................................................... 15
Power Supply Decoupling ......................................................... 15
Outline Dimensions ....................................................................... 16
Ordering Guide .......................................................................... 16
REVISION HISTORY
9/11—Rev. A to Rev. B
Changes to Table 3, Endnote 1, and Figure 2................................ 5
5/11—Rev. 0 to Rev. A
Changes to Table 6, LRSEL Pin Description................................. 7
10/10—Revision 0: Initial Version
Data Sheet SSM2517
Rev. B | Page 3 of 16
SPECIFICATIONS
PVDD = 5.0 V, VDD = 1.8 V, fS = 128×, TA = 25°C, RL = 8 Ω + 33 μH, unless otherwise noted. When fS = 128×, PDM clock = 6.144 MHz;
when fS = 64×, PDM clock = 3.072 MHz.
Table 1.
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
DEVICE CHARACTERISTICS
Output Power PO f = 1 kHz, BW = 20 kHz
RL = 4 Ω, THD = 1%, PVDD = 5.0 V 2.4 W
R
L = 8 Ω, THD = 1%, PVDD = 5.0 V 1.38 W
R
L = 4 Ω, THD = 1%, PVDD = 3.6 V 1.2 W
R
L = 8 Ω, THD = 1%, PVDD = 3.6 V 0.7 W
R
L = 4 Ω, THD = 10%, PVDD = 3.6 V 1.5 W
R
L = 8 Ω, THD = 10%, PVDD = 3.6 V 0.9 W
Total Harmonic Distortion Plus Noise THD + N f = 1 kHz, BW = 20 kHz
P
O = 100 mW into 8 Ω, PVDD = 3.6 V 0.035 %
P
O = 500 mW into 8 Ω, PVDD = 3.6 V 0.1 %
P
O = 1 W into 8 Ω, PVDD = 5.0 V 0.12 %
R
L = 4 Ω, −6 dBFS input, PVDD = 5.0 V 3.6 %
R
L = 8 Ω, −6 dBFS input, PVDD = 5.0 V 1.0 %
R
L = 4 Ω, −6 dBFS input, PVDD = 3.6 V 5.2 %
R
L = 8 Ω, −6 dBFS input, PVDD = 3.6 V 2.3 %
Efficiency η PO = 2.4 W into 4 Ω, PVDD = 5.0 V 86 %
P
O = 1.38 W into 8 Ω, PVDD = 5.0 V 92 %
Average Switching Frequency fSW No input 290 kHz
Closed-Loop Gain Gain −6 dBFS PDM input, BTL output,
f = 1 kHz
PVDD = 3.6 V 3.5 VP
PVDD = 5.0 V 4.78 VP
Differential Output Offset Voltage VOOS Gain = 6 dB 0.5 mV
Low Power Mode Wake Time tWAKE 0.5 ms
Input Sampling Frequency fS f
S = 64× 1.84 3.072 3.23 MHz
f
S = 128× 3.68 6.144 6.46 MHz
POWER SUPPLY
Supply Voltage Range
Amplifier Power Supply PVDD 2.5 3.6 5.5 V
Digital Power Supply VDD 1.62 1.8 3.6 V
Power Supply Rejection Ratio PSRRGSM VRIPPLE = 100 mV at 217 Hz 85 dB
Supply Current, H-Bridge IPVDD Dither input, 8 Ω + 33 μH load
PVDD = 5.0 V, fS = 64× 3.1 mA
PVDD = 5.0 V, fS = 128× 3.2 mA
PVDD = 3.6 V, fS = 64× 2.6 mA
PVDD = 3.6 V, fS = 128× 2.7 mA
PVDD = 2.5 V, fS = 64× 2.2 mA
PVDD = 2.5 V, fS = 128× 2.3 mA
Standby Current PVDD = 5.0 V 0.0 mA
Power-Down Current 100 nA
Supply Current, Modulator IVDD Dither input, 8 Ω + 33 μH load
VDD = 3.3 V, fS = 64× 1.3 mA
VDD = 3.3 V, fS = 128× 2.4 mA
VDD = 1.8 V, fS = 64× 0.6 mA
VDD = 1.8 V, fS = 128× 1.2 mA
SSM2517 Data Sheet
Rev. B | Page 4 of 16
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
Standby Current VDD = 1.8 V, fS = 64× 57 μA
VDD = 1.8 V, fS = 128× 114 μA
Shutdown Current VDD = 3.3 V 3.0 μA
VDD = 1.8 V 0.9 μA
NOISE PERFORMANCE
Output Voltage Noise en Dithered input, A-weighted
PVDD = 3.6 V, fS = 64× 43 μV
PVDD = 3.6 V, fS = 128× 52 μV
PVDD = 5.0 V, fS = 64× 52 μV
PVDD = 5.0 V, fS = 128× 60 μV
Signal-to-Noise Ratio SNR PO = 1.38 W, PVDD = 5.0 V, RL = 8 Ω,
A-weighted
f
S = 64× 96 dB
f
S = 128× 95 dB
DIGITAL INPUT SPECIFICATIONS
Table 2.
Parameter Symbol Min Typ Max Unit
INPUT SPECIFICATIONS
Input Voltage High VIH
PCLK, PDAT, LRSEL Pins 0.7 × VDD 3.6 V
GAIN_FS Pin 1.35 5.5 V
Input Voltage Low VIL V
PCLK, PDAT, LRSEL Pins −0.3 0.3 × VDD V
GAIN_FS Pin −0.3 +0.35 V
Input Leakage High IIH
PDAT, LRSEL, GAIN_FS Pins 1 μA
PCLK Pin 3 μA
Input Leakage Low IIL
PDAT, LRSEL, GAIN_FS Pins 1 μA
PCLK Pin 3 μA
Input Capacitance 5 pF
Data Sheet SSM2517
Rev. B | Page 5 of 16
PDM INTERFACE DIGITAL TIMING SPECIFICATIONS
Table 3.
Limit
Parameter tMIN t
MAX Unit Description
tDS 44 ns Valid data start time1
tDE 7 ns Valid data end time1
1 The SSM2517 was designed so that the data line can transition coincident with or close to a clock edge. It is not necessary to delay the data line transition until after the
clock edge because the SSM2517 does this internally to ensure good timing margins. The data line should remain constant during the valid sample period illustrated
in Figure 2; it may transition at any other time. Timing is measured from 70% of VDD on the rising edge or 30% VDD on the falling edge.
Timing Diagram
09211-002
t
DS
t
DE
PCLK
PDAT
VALID LEFT SAMPLE VALID LEFT SAMPLEVALID RIGHT SAMPLE
Figure 2. PDM Interface Timing
SSM2517 Data Sheet
Rev. B | Page 6 of 16
ABSOLUTE MAXIMUM RATINGS
Absolute maximum ratings apply at 25°C, unless otherwise noted.
Table 4.
Parameter Rating
PVDD Supply Voltage −0.3 V to +6 V
VDD Supply Voltage −0.3 V to +3.6 V
Input Voltage (Signal Source) −0.3 V to +3.6 V
ESD Susceptibility 4 kV
OUT− and OUT+ Pins 8 kV
Storage Temperature Range −65°C to +150°C
Operating Temperature Range −40°C to +85°C
Junction Temperature Range −65°C to +165°C
Lead Temperature (Soldering, 60 sec) 300°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
Junction-to-air thermal resistance (θJA) is specified for the worst-
case conditions, that is, a device soldered in a printed circuit board
(PCB) for surface-mount packages. θJA and θJB (junction-to-board
thermal resistance) are determined according to JEDEC JESD51-9
on a 4-layer PCB with natural convection cooling.
Table 5. Thermal Resistance
Package Type PCB θJA θ
JB Unit
9-Ball, 1.5 mm × 1.5 mm WLCSP 1S0P 162 39 °C/W
2S0P 76 21 °C/W
ESD CAUTION
Data Sheet SSM2517
Rev. B | Page 7 of 16
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
TOP VIEW
(BALL SIDE DOWN)
Not to Scale
09211-003
BALL
A
1
CORNER
A
321
B
C
OUT+ PGNDPVDD
OUT– LRSEL VDD
PCLK PDAT GAIN_FS
Figure 3. Pin Configuration
Table 6. Pin Function Descriptions
Pin No. Mnemonic Function Description
A1 OUT+ Output Noninverting Output.
A2 PVDD Supply Amplifier Power, 2.5 V to 5.5 V.
A3 PGND Ground Amplifier Ground.
B1 OUT− Output Inverting Output.
B2 LRSEL Input Left/Right Channel Select. Pull up to VDD for right channel; tie to ground for left channel.
B3 VDD Supply Digital Power, 1.62 V to 3.6 V.
C1 PCLK Input PDM Interface Master Clock.
C2 PDAT Input PDM Data Signal.
C3 GAIN_FS Input Gain and Sample Rate Selection Pin.
SSM2517 Data Sheet
Rev. B | Page 8 of 16
TYPICAL PERFORMANCE CHARACTERISTICS
100
10
1
0.1
0.01
0.001 0.01 0.1 1 10
THD + N (%)
OUTPUT POWER (W)
09211-010
RL = 8Ω + 33µH
GAIN = 5V
SAMPLE RATE = 64×
(3.072MHz)
PVDD = 2.5V
PVDD = 3.6V
PVDD = 5V
Figure 4. THD + N vs. Output Power into 8 Ω, Gain = 5 V, fS = 64×
100
10
1
0.1
0.01
0.001 0.01 0.1 1 10
THD + N (%)
OUTPUT POWER (W)
09211-012
RL = 8Ω + 33µH
GAIN = 3.6V
SAMPLE RATE = 64×
(3.072MHz)
PVDD = 2.5V
PVDD = 3.6V
PVDD = 5V
Figure 5. THD + N vs. Output Power into 8 Ω, Gain = 3.6 V, fS = 64×
100
10
1
0.1
0.01
0.001 0.01 0.1 1 10
THD + N (%)
OUTPUT POWER (W)
09211-014
RL = 4Ω + 15µH
GAIN = 5V
SAMPLE RATE = 64×
(3.072MHz)
PVDD = 2.5V
PVDD = 5V
PVDD = 3.6V
Figure 6. THD + N vs. Output Power into 4 Ω, Gain = 5 V, fS = 64×
100
10
1
0.1
0.01
0.001 0.01 0.1 1 10
THD + N (%)
OUTPUT POWER (W)
09211-011
RL = 8Ω + 33µH
GAIN = 5V
SAMPLE RATE = 128×
(6.144MHz)
PVDD = 2.5V
PVDD = 3.6V
PVDD = 5V
Figure 7. THD + N vs. Output Power into 8 Ω, Gain = 5 V, fS = 128×
100
10
1
0.1
0.01
0.001 0.01 0.1 1 10
THD + N (%)
OUTPUT POWER (W)
09211-013
RL = 8Ω + 33µH
GAIN = 3.6V
SAMPLE RATE = 128×
(6.144MHz)
PVDD = 2.5V
PVDD = 5V
PVDD = 3.6V
Figure 8. THD + N vs. Output Power into 8 Ω, Gain = 3.6 V, fS = 128×
100
10
1
0.1
0.01
0.001 0.01 0.1 1 10
THD + N (%)
OUTPUT POWER (W)
09211-015
RL = 4Ω + 15µH
GAIN = 5V
SAMPLE RATE = 128×
(6.144MHz)
PVDD = 2.5V
PVDD = 3.6V
PVDD = 5V
Figure 9. THD + N vs. Output Power into 4 Ω, Gain = 5 V, fS = 128×
Data Sheet SSM2517
Rev. B | Page 9 of 16
100
10
1
0.1
0.01
0.001 0.01 0.1 1 10
THD + N (%)
OUTPUT POWER (W)
09211-016
RL = 4Ω + 15µH
GAIN = 3.6V
SAMPLE RATE = 64×
(3.072MHz)
PVDD = 2.5V
PVDD = 3.6V
PVDD = 5V
Figure 10. THD + N vs. Output Power into 4 Ω, Gain = 3.6 V, fS = 64×
100
10
1
0.1
0.01
10 100 1k 10k 100k
THD + N (%)
FREQUENCY (Hz)
09211-018
RL = 8Ω + 33µH
PVDD = 5V
GAIN = 5V
SAMPLE RATE = 64×
(3.072MHz)
1.0W 0.5W
0.25W
Figure 11. THD + N vs. Frequency, PVDD = 5 V, Gain = 5 V,
RL = 8 Ω, fS = 64×
100
10
1
0.1
0.01
10 100 1k 10k 100k
THD + N (%)
FREQUENCY (Hz)
09211-020
RL = 8Ω + 33µH
PVDD = 3.6V
GAIN = 3.6V
SAMPLE RATE = 64×
(3.072MHz)
0.5W
0.25W
0.125W
Figure 12. THD + N vs. Frequency, PVDD = 3.6 V, Gain = 3.6 V,
RL = 8 Ω, fS = 64×
100
10
1
0.1
0.01
0.001 0.01 0.1 1 10
THD + N (%)
OUTPUT POWER (W)
09211-017
RL = 4Ω + 15µH
GAIN = 3.6V
SAMPLE RATE = 128×
(6.144MHz)
PVDD = 2.5V
PVDD = 5V
PVDD = 3.6V
Figure 13. THD + N vs. Output Power into 4 Ω, Gain = 3.6 V, fS = 128×
100
10
1
0.1
0.01
10 100 1k 10k 100k
THD + N (%)
FREQUENCY (Hz)
09211-019
RL = 4Ω + 15µH
PVDD = 5V
GAIN = 5V
SAMPLE RATE = 64×
(3.072MHz)
1.0W
0.25W
0.5W
Figure 14. THD + N vs. Frequency, PVDD = 5 V, Gain = 5 V,
RL = 4 Ω, fS = 64×
100
10
1
0.1
0.01
10 100 1k 10k 100k
THD + N (%)
FREQUENCY (Hz)
09211-021
RL = 4Ω + 15µH
PVDD = 3.6V
GAIN = 3.6V
SAMPLE RATE = 64×
(3.072MHz)
0.5W
0.125W
0.25W
Figure 15. THD + N vs. Frequency, PVDD = 3.6 V, Gain = 3.6 V,
RL = 4 Ω, fS = 64×
SSM2517 Data Sheet
Rev. B | Page 10 of 16
100
10
1
0.1
0.01
10 100 1k 10k 100k
THD + N (%)
FREQUENCY (Hz)
09211-022
RL = 8Ω + 33µH
PVDD = 2.5V
GAIN = 3.6V
SAMPLE RATE = 64×
(3.072MHz)
0.2W
0.1W
0.05W
Figure 16. THD + N vs. Frequency, PVDD = 2.5 V, Gain = 3.6 V,
RL = 8 Ω, fS = 64×
4.0
3.5
3.0
2.5
2.0
1.5
2.5 3.0 3.5 5.55.04.54.0 6.0
QUIESCENT CURRENT (mA)
SUPPLY VOLTAGE (V)
09211-024
GAIN = 5V
SAMPLE RATE = 64×
(3.072MHz)
R
L
= 4Ω + 15µH
NO LOAD
R
L
= 8Ω + 33µH
Figure 17. Quiescent Current (H-Bridge) vs. Supply Voltage,
Gain = 5 V, fS = 64×
1.8
0
2.5 5.0
OUTPUT POWER (W)
SUPPLY VOLTAGE (V)
09211-025
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
3.0 3.5 4.0 4.5
R
L
= 8Ω + 33µH
GAIN = 5V
SAMPLE RATE = 64×
(3.072MHz)
THD + N = 10%
THD + N = 1%
Figure 18. Maximum Output Power vs. Supply Voltage, Gain = 5 V,
RL = 8 Ω, fS = 64×
100
10
1
0.1
0.01
10 100 1k 10k 100k
THD + N (%)
FREQUENCY (Hz)
09211-023
R
L
= 4Ω + 15µH
PVDD = 2.5V
GAIN = 3.6V
SAMPLE RATE = 64×
(3.072MHz)
0.25W
0.05W
0.1W
Figure 19. THD + N vs. Frequency, PVDD = 2.5 V, Gain = 3.6 V,
RL = 4 Ω, fS = 64×
–160
–140
–120
–100
–80
–60
–40
–20
0
0 2 4 6 8 101214161820
AMPLITUDE (dBV)
FREQUENCY (kHz)
R
L
= 8Ω + 33µH
PVDD = 3.6V
GAIN = 3.6V
SAMPLE RATE = 128×
(6.144MHz)
09211-033
Figure 20. Output Spectrum vs. Frequency, PVDD = 3.6 V, Gain = 3.6 V,
RL = 8 Ω, fS = 128×
1.8
0
2.5 5.0
OUTPUT POWER (W)
SUPPLY VOLTAGE (V)
09211-026
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
3.0 3.5 4.0 4.5
R
L
= 8Ω + 33µH
GAIN = 5V
SAMPLE RATE = 128×
(6.144MHz)
THD + N = 10%
THD + N = 1%
Figure 21. Maximum Output Power vs. Supply Voltage, Gain = 5 V,
RL = 8 Ω, fS = 128×
Data Sheet SSM2517
Rev. B | Page 11 of 16
3.5
0
2.5 5.0
OUTPUT POWER (W)
SUPPLY VOLTAGE (V)
09211-027
0.5
1.0
1.5
2.0
2.5
3.0
3.0 3.5 4.0 4.5
R
L
= 4Ω + 15µH
GAIN = 5V
SAMPLE RATE = 64×
(3.072MHz)
THD + N = 10%
THD + N = 1%
Figure 22. Maximum Output Power vs. Supply Voltage, Gain = 5 V,
RL = 4 Ω, fS = 64×
0
10
20
30
40
50
60
70
80
90
100
0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
EFFICIENCY (%)
OUTPUT POWER (W)
R
L
= 8Ω + 33µH
GAIN = 5V
SAMPLE RATE = 64×
(3.072MHz)
PVDD = 2.5V PVDD = 3.6V
PVDD = 5V
09211-029
Figure 23. Efficiency vs. Output Power into 8 Ω, Gain = 5 V, fS = 64×
0
50
100
150
200
250
300
350
400
450
0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
SUPPLY CURRENT (mA)
OUTPUT POWER (W)
R
L
= 8Ω + 33µH
GAIN = 5V
SAMPLE RATE = 64×
(3.072MHz)
09211-032
PVDD = 2.5V
PVDD = 3.6V
PVDD = 5V
Figure 24. Supply Current (H-Bridge) vs. Output Power into 8 Ω,
Gain = 5 V, fS = 64×
3.5
0
2.5 5.0
OUTPUT POWER (W)
SUPPLY VOLTAGE (V)
09211-028
0.5
1.0
1.5
2.0
2.5
3.0
3.0 3.5 4.0 4.5
R
L
= 4Ω + 15µH
GAIN = 5V
SAMPLE RATE = 128×
(6.144MHz)
THD + N = 10%
THD + N = 1%
Figure 25. Maximum Output Power vs. Supply Voltage, Gain = 5 V,
RL = 4 Ω, fS = 128×
0
10
20
30
40
50
60
70
80
90
100
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.4
3.2
EFFICIEN
C
Y (%)
OUTPUT POWER (W)
PVDD = 5V
PVDD = 3.6V
09211-031
R
L
= 4Ω + 15µH
GAIN = 5V
SAMPLE RATE = 64×
(3.072MHz)
PVDD = 2.5V
Figure 26. Efficiency vs. Output Power into 4 Ω, Gain = 5 V, fS = 64×
0
100
200
300
400
500
600
700
800
0 0.5 1.0 1.5 2.0 2.5 3.0
SUPPLY CURRENT (mA)
OUTPUT POWER (W)
R
L
= 4Ω + 15µH
GAIN = 5V
SAMPLE RATE = 64×
(3.072MHz)
09211-036
PVDD = 2.5V
PVDD = 3.6V
PVDD = 5V
Figure 27. Supply Current (H-Bridge) vs. Output Power into 4 Ω,
Gain = 5 V, fS = 64×
SSM2517 Data Sheet
Rev. B | Page 12 of 16
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
10 100 1k 10k 100k
FREQUENCY (Hz)
PSRR (dB)
PVDD = 3.6V
PVDD = 5V
0
9211-034
Figure 28. Power Supply Rejection Ratio (PSRR) vs. Frequency
5
4
3
2
1
0
–1
–2
–40 0 60 120 160–20 20 8040 100 140
09211-035
VOLTAGE (V)
TIME (µs)
PCLK
OUTPUT
Figure 29. Turn-On Response
Data Sheet SSM2517
Rev. B | Page 13 of 16
THEORY OF OPERATION
MASTER CLOCK
The SSM2517 requires a clock present at the PCLK input pin.
This clock must be fully synchronous with the incoming digital
audio on the serial interface. The clock frequencies must fall
into one of these ranges: 1.84 MHz to 3.23 MHz or 3.68 MHz
to 6.46 MHz.
POWER SUPPLIES
The SSM2517 requires two power supplies: PVDD and VDD.
PVDD
The PVDD pin supplies power to the full-bridge power stage
of a MOSFET and its associated drive, control, and protection
circuitry. It also supplies power to the digital-to-analog converter
(DAC) and to the Class-D PDM modulator. PVDD can operate
from 2.5 V to 5.5 V and must be present to obtain audio output.
Lowering the supply voltage of PVDD results in lower maximum
output power and, therefore, lower power consumption.
VDD
The VDD pin provides power to the digital logic circuitry.
VDD can operate from 1.62 V to 3.6 V and must be present
to obtain audio output. Lowering the supply voltage of VDD
results in lower power consumption but does not affect audio
performance.
POWER CONTROL
On device power-up, PVDD must first be applied to the device,
which latches in the designated GAIN_FS pin functionality.
The SSM2517 contains a smart power-down feature. When
enabled, the smart power-down feature looks at the incoming
digital audio and, if it receives the PDM stop condition of at
least 128 repeated 0xAC bytes (1024 clock cycles), it places the
SSM2517 in the standby state. In the standby state, the PCLK can
be removed, resulting in a full power-down state. This state is
the lowest power condition possible. When the PCLK is turned
on again and a single non-stop condition input is received, the
SSM2517 leaves the full power-down state and resumes normal
operation.
POWER-ON RESET/VOLTAGE SUPERVISOR
The SSM2517 includes an internal power-on reset and voltage
supervisor circuit. This circuit provides an internal reset to all
circuitry whenever PVDD or VDD is substantially below the
nominal operating threshold. This circuit simplifies supply
sequencing during initial power-on.
The circuit also monitors the power supplies to the SSM2517. If
the supply voltages fall below the nominal operating threshold,
this circuit stops the output and issues a reset. This ensures that
no damage occurs due to low voltage operation and that no
pops can occur under nearly any power removal condition.
SYSTEM GAIN/INPUT FREQUENCY
The GAIN_FS pin is used to set the internal gain and filtering
configuration for different sample rates of the SSM2517. This pin
can be set to one of four states by connecting the pin to PVDD or
PGND (see Table 7). The internal gain and filtering can also be
set via PDM pattern control, allowing these settings to be modi-
fied during operation (see the PDM Pattern Control section).
Table 7. GAIN_FS Function Descriptions
Device Setting GAIN Pin Configuration
fS = 64 × PCLK, Gain = 5 V Pull up to PVDD with a 47 kΩ
resistor
fS = 128 × PCLK, Gain = 5 V Pull down to PGND with a 47 kΩ
resistor
fS = 64 × PCLK, Gain = 3.6 V Pull up to PVDD
fS = 128 × PCLK, Gain = 3.6 V Pull down to PGND
The SSM2517 has an internal analog gain control such that
when GAIN_FS is tied to PGND or PVDD via a 47 kΩ resistor
(5 V gain setting), a −6.02 dBFS PDM input signal results in
an amplifier output voltage of 5 V peak. This setting should
produce optimal noise performance when PVDD = 5 V.
When the GAIN_FS pin is tied directly to PGND or PVDD, the
gain is adjusted so that a −6.02 dBFS PDM input signal results
in an amplifier output voltage of 3.6 V peak. This setting should
produce optimal noise performance when PVDD = 3.6 V.
The SSM2517 can handle input sample rates of 64 × fS (~3 MHz)
and 128 × fS (~6 MHz). Different internal digital filtering is used
in each of these cases. Selection of the sample rate is also set via
the GAIN_FS pin (see Table 7).
Because the 64 × fS mode provides better performance with lower
power consumption, its use is recommended. The 128 × fS mode
should be used only when overall system noise performance is
limited by the source modulator.
SSM2517 Data Sheet
Rev. B | Page 14 of 16
PDM PATTERN CONTROL
The SSM2517 has a simple control mechanism that can set the
part for low power states and control functionality. This is
accomplished by sending a repeating 8-bit pattern to the device.
Different patterns set different functionality (see Table 8).
Any pattern must be repeated a minimum of 128 times. The
part is automatically muted when a pattern is detected so that
a pattern can be set while the part is operational without a
pop/click due to pattern transition.
All functionality set via patterns returns to its default value after
a clock-loss power-down.
Table 8. PDM Watermarking Pattern Control Descriptions
Pattern Control Description
0xAC Power-down. All blocks off except for PDM interface.
Normal start-up time.
0xD8 Gain optimized for PVDD = 5 V operation.
Overrides GAIN_FS pin setting.
0xD4 Gain optimized for PVDD = 3.6 V operation.
Overrides GAIN_FS pin setting.
0xD2 Gain optimized for PVDD = 2.5 V operation.
Overrides GAIN_FS pin setting.
0xD1 fS set to opposite value determined by GAIN_FS pin.
0xE1 Ultralow EMI mode.
0xE2 Half clock cycle pulse mode for power savings.
0xE4 Special 32 kHz/128 × fS operation mode.
EMI NOISE
The SSM2517 uses a proprietary modulation and spread-
spectrum technology to minimize EMI emissions from the
device. For applications that have difficulty passing FCC
Class-B emission tests, the SSM2517 includes a modulation
select mode (ultralow EMI emissions mode) that significantly
reduces the radiated emissions at the Class-D outputs, particu-
larly above 100 MHz. This mode is enabled by activating PDM
Water mark ing Patter n 0 xE1 (s ee Table 8).
OUTPUT MODULATION DESCRIPTION
The SSM2517 uses three-level, Σ-Δ output modulation. Each
output can swing from PGND to PVDD and vice versa. Ideally,
when no input signal is present, the output differential voltage is
0 V because there is no need to generate a pulse. In a real-world
situation, noise sources are always present.
Due to this constant presence of noise, a differential pulse is
generated, when required, in response to this stimulus. A small
amount of current flows into the inductive load when the differ-
ential pulse is generated.
Most of the time, however, the output differential voltage is 0 V,
due to the Analog Devices, Inc., three-level, Σ-Δ output modula-
tion. This feature ensures that the current flowing through the
inductive load is small.
When the user wants to send an input signal, an output pulse
(OUT+ and OUT−) is generated to follow the input voltage.
The differential pulse density (VOUT) is increased by raising
the input signal level. Figure 30 depicts three-level, Σ-Δ output
modulation with and without input stimulus.
OUTPUT > 0V
+5V
0V
OUT+
+5V
0V
OUT–
+5V
0V
VOUT
OUTPUT < 0V
+5V
0V
OUT+
+5V
0V
OUT–
0V
–5V
VOUT
OUTPUT = 0V
OUT+
+5V
0V
+5V
0V
OUT–
+5V
–5V
0V
VOUT
0
9211-009
Figure 30. Three-Level, Σ-Δ Output Modulation With and Without Input Stimulus
Data Sheet SSM2517
Rev. B | Page 15 of 16
APPLICATIONS INFORMATION
LAYOUT
As output power increases, care must be taken to lay out PCB
traces and wires properly among the amplifier, load, and power
supply. A good practice is to use short, wide PCB tracks to
decrease voltage drops and minimize inductance. The PCB
layout engineer must avoid ground loops where possible to
minimize common-mode current associated with separate paths
to ground. Ensure that track widths are at least 200 mil per inch
of track length for lowest DCR, and use 1 oz or 2 oz copper PCB
traces to further reduce IR drops and inductance. A poor layout
increases voltage drops, consequently affecting efficiency. Use
large traces for the power supply inputs and amplifier outputs to
minimize losses due to parasitic trace resistance.
Proper grounding guidelines help to improve audio performance,
minimize crosstalk between channels, and prevent switching
noise from coupling into the audio signal. To maintain high
output swing and high peak output power, the PCB traces that
connect the output pins to the load, as well as the PCB traces to
the supply pins, should be as wide as possible to maintain the
minimum trace resistances. It is also recommended that a large
ground plane be used for minimum impedances.
In addition, good PCB layout isolates critical analog paths from
sources of high interference. High frequency circuits (analog
and digital) should be separated from low frequency circuits.
Properly designed multilayer PCBs can reduce EMI emissions
and increase immunity to the RF field by a factor of 10 or more,
compared with double-sided boards. A multilayer board allows
a complete layer to be used for the ground plane, whereas the
ground plane side of a double-sided board is often disrupted by
signal crossover.
POWER SUPPLY DECOUPLING
To ensure high efficiency, low total harmonic distortion (THD),
and high PSRR, proper power supply decoupling is necessary.
Noise transients on the power supply lines are short-duration
voltage spikes. These spikes can contain frequency components
that extend into the hundreds of megahertz.
The power supply inputs must be decoupled with a good quality,
low ESL, low ESR capacitor, with a minimum value of 4.7 μF
for the PVDD pin and 0.1 μF for the VDD pin. This capacitor
bypasses low frequency noises to the ground plane. For high
frequency transient noises, use a 0.1 μF capacitor as close as
possible to the PVDD and VDD pins of the device. Placing the
decoupling capacitors as close as possible to the SSM2517 helps
to maintain efficient performance.
SSM2517 Data Sheet
Rev. B | Page 16 of 16
OUTLINE DIMENSIONS
101507-C
1.490
1.460 SQ
1.430
0.350
0.320
0.290
0.655
0.600
0.545
BOTTOM VIEW
(BALL SIDE UP)
TOP VIEW
(BALL SIDE DOWN)
A
123
B
C
0.270
0.240
0.210
0.385
0.360
0.335
SEATING
PLANE
0.50
BALL PITCH
BALL A1
IDENTIFIER
Figure 31. 9-Ball Wafer Level Chip Scale Package [WLCSP]
(CB-9-2)
Dimensions shown in millimeters
ORDERING GUIDE
Model1 Temperature Range Package Description Package Option
SSM2517CBZ-R7 −40°C to +85°C 9-Ball Wafer Level Chip Scale Package [WLCSP] CB-9-2
SSM2517CBZ-RL −40°C to +85°C 9-Ball Wafer Level Chip Scale Package [WLCSP] CB-9-2
EVAL-SSM2517Z Evaluation Board
1 Z = RoHS Compliant Part.
©2010-2011 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D09211-0-9/11(B)
