ADF4157BRUZ-RL71 - Analog Devices

High Resolution 6 GHz Fractional-N

Frequency Synthesizer

ADF4157

Rev. 0

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responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

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FEATURES

RF bandwidth to 6 GHz

25-bit fixed modulus allows subhertz frequency resolution

2.7 V to 3.3 V power supply

Separate VP allows extended tuning voltage

Programmable charge pump currents

3-wire serial interface

Digital lock detect

Power-down mode

Pin compatible with the following frequency synthesizers:

ADF4110/ADF4111/ADF4112/ADF4113/

ADF4106/ADF4153/ADF4154/ADF4156

Cycle slip reduction for faster lock times

APPLICATIONS

Satellite communications terminals, radar equipment

Instrumentation equipment

Personal mobile radio (PMR)

Base stations for mobile radio

Wireless handsets

GENERAL DESCRIPTION

The ADF4157 is a 6 GHz fractional-N frequency synthesizer

with a 25-bit fixed modulus, allowing subhertz frequency

resolution at 6 GHz. It consists of a low noise digital phase

frequency detector (PFD), a precision charge pump, and

a programmable reference divider. There is a Σ- based

fractional interpolator to allow programmable fractional-N

division. The INT and FRAC registers define an overall

N divider, N = INT + (FRAC/225). The ADF4157 features cycle

slip reduction circuitry, which leads to faster lock times without

the need for modifications to the loop filter.

Control of all on-chip registers is via a simple 3-wire interface.

The device operates with a power supply ranging from

2.7 V to 3.3 V and can be powered down when not in use.

FUNCTIONAL BLOCK DIAGRAM

LOCK

DETECT

N COUNTER

RFCP3 RFCP2RFCP4 RFCP1

REFERENCE

DATA

32-BIT

DATA

CLK

REF

AGND

DGND

DIV

OUT

DIV

DGND CPGND

SET

OUTPUT

MUX

MUXOUT

–

HIGH Z

PHASE

FREQUENCY

DETECTOR

ADF4157

THIRD ORDER

FRACTIONAL

INTERPOLATOR

MODULUS

FRACTION

REG

INTEGER

REG

CURRENT

SETTING

×2

DOUBLER

4-BIT

R COUNTER

CHARGE

PUMP

CSR

÷2

DIVIDER

05874-001

Figure 1.

ADF4157

Rev. 0 | Page 2 of 20

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications....................................................................................... 1

General Description......................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Timing Specifications .................................................................. 4

Absolute Maximum Ratings............................................................ 5

Thermal Resistance ...................................................................... 5

ESD Caution.................................................................................. 5

Pin Configurations and Function Descriptions ........................... 6

Typical Performance Characteristics ............................................. 7

Circuit Description........................................................................... 8

Reference Input Section............................................................... 8

RF Input Stage............................................................................... 8

RF INT Divider............................................................................. 8

25-Bit Fixed Modulus .................................................................. 8

INT, FRAC, and R Relationship ................................................. 8

RF R Counter ................................................................................ 8

Phase Frequency Detector (PFD) and Charge Pump.............. 9

MUXOUT and LOCK Detect..................................................... 9

Input Shift Registers......................................................................9

Program Modes .............................................................................9

FRAC/INT Register (R0) Map.................................................. 11

LSB FRAC Register (R1) Map .................................................. 12

R Divider Register (R2) Map .................................................... 13

Function Register (R3) Map ..................................................... 15

Test Register (R4) Map .............................................................. 16

Applications Information.............................................................. 17

Initialization Sequence .............................................................. 17

RF Synthesizer: A Worked Example........................................ 17

Reference Doubler and Reference Divider ............................. 17

Cycle Slip Reduction for Faster Lock Times........................... 17

Spur Mechanisms ....................................................................... 18

Low Frequency Applications .................................................... 18

Filter Design—ADIsimPLL....................................................... 18

Interfacing ................................................................................... 18

PCB Design Guidelines for the Chip Scale Package.............. 18

Outline Dimensions ....................................................................... 19

Ordering Guide .......................................................................... 19

REVISION HISTORY

7/07—Revision 0: Initial Revision

ADF4157

Rev. 0 | Page 3 of 20

SPECIFICATIONS

AVDD = DVDD = 2.7 V to 3.3 V; VP = AVDD to 5.5 V; AGND = DGND = 0 V; TA = TMIN to TMAX, unless otherwise noted;

dBm referred to 50 Ω.

Table 1.

Parameter B Version1Unit Test Conditions/Comments

RF CHARACTERISTICS (3 V)

RF Input Frequency (RFIN) 0.5/6.0 GHz min/max

−10 dBm/0 dBm min/max. For lower frequencies, ensure slew

rate (SR) > 400 V/μs.

REFERENCE CHARACTERISTICS

REFIN Input Frequency 10/300 MHz min/max For f < 10 MHz, ensure slew rate > 50 V/μs.

REFIN Input Sensitivity 0.4/AVDD V p-p min/max For 10 MHz < REFIN < 250 MHz. Biased at AVDD/22.

0.7/AVDD V p-p min/max For 250 MHz < REFIN < 300 MHz. Biased at AVDD/22.

REFIN Input Capacitance 10 pF max

REFIN Input Current ±100 μA max

PHASE DETECTOR

Phase Detector Frequency332 MHz max

CHARGE PUMP

ICP Sink/Source Programmable.

High Value 5 mA typ With RSET = 5.1 kΩ.

Low Value 312.5 μA typ

Absolute Accuracy 2.5 % typ With RSET = 5.1 kΩ.

RSET Range 2.7/10 kΩ min/max

ICP Three-State Leakage Current 1 nA typ Sink and source current.

Matching 2 % typ 0.5 V < VCP < VP – 0.5.

ICP vs. VCP 2 % typ 0.5 V < VCP < VP – 0.5.

ICP vs. Temperature 2 % typ VCP = VP/2.

LOGIC INPUTS

VINH, Input High Voltage 1.4 V min

VINL, Input Low Voltage 0.6 V max

IINH/IINL, Input Current ±1 μA max

CIN, Input Capacitance 10 pF max

LOGIC OUTPUTS

VOH, Output High Voltage 1.4 V min Open-drain 1 kΩ pull-up to 1.8 V.

VOH, Output High Voltage VDD – 0.4 V min CMOS output chosen.

VOL, Output Low Voltage 0.4 V max IOL = 500 μA.

POWER SUPPLIES

AVDD 2.7/3.3 V min/V max

DVDD AVDD

VP AVDD/5.5 V min/V max

IDD 29 mA max 23 mA typical.

Low Power Sleep Mode 10 μA typ

NOISE CHARACTERISTICS

Phase Noise Figure of Merit4−207 dBc/Hz typ

ADF4157 Phase Noise Floor5−137 dBc/Hz typ @ 10 MHz PFD frequency.

−133 dBc/Hz typ @ 25 MHz PFD frequency.

Phase Noise Performance6 @ VCO output.

5800 MHz Output7−87 dBc/Hz typ @ 2 kHz offset, 25 MHz PFD frequency.

1 Operating temperature of B version is −40°C to +85°C.

2 AC-coupling ensures AVDD/2 bias.

3 Guaranteed by design. Sample tested to ensure compliance.

4 This figure can be used to calculate phase noise for any application. Use the formula –207 + 10log(fPFD) + 20logN to calculate in-band phase noise performance as seen

at the VCO output.

5 The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20logN (where N is the N divider value).

6 The phase noise is measured with the EVAL-ADF4157EB1Z and the Agilent E5052A phase noise system.

7 fREFIN = 100 MHz; fPFD = 25 MHz; offset frequency = 2 kHz; RFOUT = 5800.25 MHz; N = 232; loop bandwidth = 20 kHz.

ADF4157

Rev. 0 | Page 4 of 20

TIMING SPECIFICATIONS

AVDD = DVDD = 2.7 V to 3.3 V; VP = AVDD to 5.5 V; AGND = DGND = 0 V; TA = TMIN to TMAX, unless otherwise noted;

dBm referred to 50 Ω.

Table 2.

Parameter Limit at TMIN to TMAX (B Version) Unit Test Conditions/Comments

t1 20 ns min LE setup time

t2 10 ns min DATA to CLOCK setup time

t3 10 ns min DATA to CLOCK hold time

t4 25 ns min CLOCK high duration

t5 25 ns min CLOCK low duration

t6 10 ns min CLOCK to LE setup time

t7 20 ns min LE pulse width

CLK

DATA

DB23 (MSB) DB22 DB2

(CONTROL BIT C3)

DB1

(CONTROL BIT C2)

DB0 (LSB)

(CONTROL BIT C1)

t2t3

t4t5

05874-002

Figure 2. Timing Diagram

ADF4157

Rev. 0 | Page 5 of 20

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, GND = AGND = DGND = 0 V, VDD = AVDD = DVDD, unless otherwise noted.

THERMAL RESISTANCE

Table 3.

Parameter Rating

θJA is specified for the worst-case conditions, that is, a device

soldered in a circuit board for surface-mount packages.

VDD to GND −0.3 V to +4 V

VDD to VDD −0.3 V to +0.3 V

Table 4. Thermal Resistance

VP to GND −0.3 V to +5.8 V

VP to VDD −0.3 V to +5.8 V Package Type θJA Unit

Digital I/O Voltage to GND −0.3 V to VDD + 0.3 V TSSOP 112 °C/W

Analog I/O Voltage to GND −0.3 V to VDD + 0.3 V LFCSP (Paddle Soldered) 30.4 °C/W

REFIN, RFIN to GND −0.3 V to VDD + 0.3 V

ESD CAUTION

Operating Temperature Range

Industrial (B Version) −40°C to +85°C

Storage Temperature Range −65°C to +125°C

Maximum Junction Temperature 150°C

Reflow Soldering

Peak Temperature 260°C

Time at Peak Temperature 40 sec

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any

other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

ADF4157

Rev. 0 | Page 6 of 20

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

CPGND

AGND

SET

MUXOUT

REF

DGND

CLK

DATA

ADF4157

TOP VIEW

(Not to Scale)

05874-003

PIN 1

INDICATOR

1CPGND

2AGND

3AGND

4RF

5RF

13 DATA

14 LE

15 MUXOUT

12 CLK

11 CE

REF

DGND

18 V

19 R

SET

20 CP

17 DV

16 DV

TOP VIEW

(Not to Scale)

ADF4157

05874-004

Figure 3. TSSOP Pin Configuration Figure 4. LFCSP Pin Configuration

Table 5. Pin Function Descriptions

TSSOP LFCSP Mnemonic Description

1 19 RSET Connecting a resistor between this pin and ground sets the maximum charge pump output current.

The relationship between ICP and RSET is

SET

CPMAX R

I5.25

where:

RSET = 5.1 kΩ.

ICPMAX = 5 mA.

2 20 CP Charge Pump Output. When enabled, this provides ±ICP to the external loop filter which, in turn, drives

the external VCO.

3 1 CPGND Charge Pump Ground. This is the ground return path for the charge pump.

4 2, 3 AGND Analog Ground. This is the ground return path of the prescaler.

5 4 RFINB Complementary Input to the RF Prescaler. This point should be decoupled to the ground plane with

a small bypass capacitor, typically 100 pF.

6 5 RFINA Input to the RF Prescaler. This small-signal input is normally ac-coupled from the VCO.

7 6, 7 AVDD Positive Power Supply for the RF Section. Decoupling capacitors to the digital ground plane should be

placed as close as possible to this pin. AVDD has a value of 3 V ± 10%. AVDD must have the same voltage as

DVDD.

8 8 REFIN Reference Input. This is a CMOS input with a nominal threshold of VDD/2 and an equivalent input

resistance of 100 kΩ. This input can be driven from a TTL or CMOS crystal oscillator, or it can be ac-

coupled.

9 9, 10 DGND Digital Ground.

10 11 CE Chip Enable. A logic low on this pin powers down the device and puts the charge pump output into three-

state mode.

11 12 CLK Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is latched

into the shift register on the CLK rising edge. This input is a high impedance CMOS input.

12 13 DATA Serial Data Input. The serial data is loaded MSB first with the three LSBs being the control bits. This input is

a high impedance CMOS input.

13 14 LE Load Enable, CMOS Input. When LE is high, the data stored in the shift registers is loaded into one of

the five latches, the latch being selected using the control bits.

14 15 MUXOUT

This multiplexer output allows the lock detect, the scaled RF, or the scaled reference frequency to be

accessed externally.

15 16, 17 DVDD Positive Power Supply for the Digital Section. Decoupling capacitors to the digital ground plane should be

placed as close as possible to this pin. DVDD has a value of 3 V ± 10%. DVDD must have the same voltage as

AVDD.

16 18 VP Charge Pump Power Supply. This should be greater than or equal to VDD. In systems where VDD is 3 V, it can

be set to 5.5 V and used to drive a VCO with a tuning range of up to 5.5 V.

ADF4157

Rev. 0 | Page 7 of 20

TYPICAL PERFORMANCE CHARACTERISTICS

PFD = 25 MHz, loop bandwidth = 20 kHz, reference = 100 MHz, ICP = 313 A, phase noise measurements taken on the Agilent E5052A

phase noise system.

–40

FREQUENCY (GHz)

POWER (dBm)

–5

–10

–15

–20

–25

–30

–35

12345678

P = 4/5 P = 8/9

05874-016

6.00

5.65

–100 900

TIME (µs)

FREQUENCY (GHz)

5.95

5.90

5.85

5.80

5.75

5.70

0 100 200 300 400 500 600 700 800

CSR OFF

CSR ON

05874-019

Figure 5. RF Input Sensitivity Figure 8. Lock Time for 200 MHz Jump from 5705 MHz to 5905 MHz

with CSR On and Off

–40

5.65

5.60

5.95

5.90

5.85

5.80

5.75

5.70

–100 900

TIME (µs)

FREQUENCY (GHz)

FREQUENCY (MHz)

POWER (dBm)

100 200 300 400

VDD = 3V

–5

–10

–15

–20

–25

–30

–35

CSR ON

05874-017

0 100 200 300 400 500 600 700 800

CSR OFF

05874-020

Figure 9. Lock Time for 200 MHz Jump from 5905 MHz to 5705 MHz

with CSR On and Off

Figure 6. Reference Input Sensitivity

–160

1k 10M

FREQUENCY (Hz)

PHASE NOISE (dBc/Hz)

–20

–40

–60

–80

–100

–120

–140

10k 100k 1M

RF = 5800.25MHz, PFD = 25MHz, N = 232,

FRAC = 335544, FREQUENCY RESOLUTION = 0.74Hz,

20kHz LOOP BW, ICP = 313µA, DSB INTEGRATED PHASE

ERROR = 0.97° RMS, PHASE NOISE @ 2kHz = –87dBc/Hz.

05874-018

–6

05874-021

(V)

(mA)

–2

–4

0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5

Figure 10. Charge Pump Output Characteristics, Pump Up and Pump Down

Figure 7. Phase Noise and Spurs

(Note that the 250 kHz spur is an integer boundary spur; see the Spur

Mechanisms section for more information.)

ADF4157

Rev. 0 | Page 8 of 20

CIRCUIT DESCRIPTION

INT, FRAC, AND R RELATIONSHIP

REFERENCE INPUT SECTION

The INT and FRAC values, in conjunction with the R counter,

make it possible to generate output frequencies that are spaced

by fractions of the phase frequency detector (PFD). See the

The reference input stage is shown in Figure 11. SW1 and SW2

are normally closed switches. SW3 is normally open. When

power-down is initiated, SW3 is closed and SW1 and SW2 are

opened. This ensures that there is no loading of the REFIN pin

on power-down.

Synthesizer: A Worked Example section for more information.

The RF VCO frequency (RFOUT) equation is

RFOUT = fPFD × (INT + (FRAC/225)) (1)

BUFFER

TO R COUNTER

REF

100kΩ

SW2

SW3

SW1

POWER-DOWN

CONTROL

05874-005

where:

RFOUT is the output frequency of the external voltage controlled

oscillator (VCO).

INT is the preset divide ratio of the binary 12-bit counter (23 to

4095).

FRAC is the numerator of the fractional division (0 to 225 − 1).

Figure 11. Reference Input Stage fPFD = REFIN × [(1 + D)/(R × (1+T))] (2)

RF INPUT STAGE where:

REFIN is the reference input frequency.

D is the REFIN doubler bit.

R is the preset divide ratio of the binary 5-bit programmable

reference counter (1 to 32).

T is the REFIN divide-by-2 bit (0 or 1).

The RF input stage is shown in Figure 12. It is followed by

a 2-stage limiting amplifier to generate the current-mode logic

(CML) clock levels needed for the prescaler.

BIAS

GENERATOR

1.6V

AGND

2kΩ2kΩ

5874-006

RF R COUNTER

The 5-bit RF R counter allows the input reference frequency

(REFIN) to be divided down to produce the reference clock to

the PFD. Division ratios from 1 to 32 are allowed.

THIRD-ORDER

FRACTIONAL

INTERPOLATOR

FRAC

VALUE

MOD

REG

INT

REG

RF N DIVIDER N = INT + FRAC/MOD

FROM RF

INPUT STAGE TO PFD

N-COUNTER

05874-007

Figure 12. RF Input Stage

RF INT DIVIDER

Figure 13. RF N Divider

The RF INT counter allows a division ratio in the PLL feedback

counter. Division ratios from 23 to 4095 are allowed.

25-BIT FIXED MODULUS

The ADF4157 has a 25-bit fixed modulus. This allows output

frequencies to be spaced with a resolution of

fRES = fPFD/225

where fPFD is the frequency of the phase frequency detector

(PFD). For example, with a PFD frequency of 10 MHz,

frequency steps of 0.298 Hz are possible.

ADF4157

Rev. 0 | Page 9 of 20

PHASE FREQUENCY DETECTOR (PFD) AND

CHARGE PUMP INPUT SHIFT REGISTERS

The ADF4157 digital section includes a 5-bit RF R counter,

a 12-bit RF N counter, and a 25-bit FRAC counter. Data is

clocked into the 32-bit shift register on each rising edge of CLK.

The data is clocked in MSB first. Data is transferred from

the shift register to one of five latches on the rising edge of LE.

The destination latch is determined by the state of the three

control bits (C3, C2, and C1) in the shift register. These are

the three LSBs, DB2, DB1, and DB0, as shown in

The PFD takes inputs from the R counter and the N counter

and produces an output proportional to the phase and

frequency difference between them. Figure 14 is a simplified

schematic of the phase frequency detector. The PFD includes

a fixed delay element that sets the width of the antibacklash

pulse, which is typically 3 ns. This pulse ensures that there is no

dead zone in the PFD transfer function and gives a consistent

reference spur level.

Figure 2.

The truth table for these bits is shown in Table 6. Figure 16

shows a summary of how the latches are programmed.

CLR2

Q2D2

DOWN

–IN

+IN

CHARGE

PUMP

DELAY

CLR1

Q1D1

05874-008

PROGRAM MODES

Tabl e 6 and Figure 16 through Figure 21 show how to set up

the program modes in the ADF4157.

Several settings in the ADF4157 are double-buffered. These

include the LSB FRAC value, R counter value, reference doubler,

and current setting. This means that two events have to occur

before the part uses a new value of any of the double-buffered

settings. First, the new value is latched into the device by

writing to the appropriate register. Second, a new write must be

performed on Register R0.

Figure 14. PFD Simplified Schematic

For example, updating the fractional value can involve a write

to the 13 LSB bits in R1 and the 12 MSB bits in R0. R1 should

be written to first, followed by the write to R0. The frequency

change begins after the write to R0. Double buffering ensures

that the bits written to in R1 do not take effect until after

the write to R0.

MUXOUT AND LOCK DETECT

The output multiplexer on the ADF4157 allows the user to

access various internal points on the chip. The state of

MUXOUT is controlled by M4, M3, M2, and M1 (see Figure

17). Figure 15 shows the MUXOUT section in block diagram

form. Table 6. C3, C2, and C1 Truth Table

Control Bits

05874-009

NALOG LOCK DETECT MUXOUT

THREE-STATE OUTPUT

N DIVIDER OUTPUT

DGND

R DIVIDER OUTPUT

DIGITAL LOCK DETECT

SERIAL DATA OUTPUT

CLK DIVIDER OUTPUT

R DIVIDER/2

N DIVIDER/2

CONTROLMUX

C3 C2 C1 Register

0 0 0 Register R0

0 0 1 Register R1

0 1 0 Register R2

0 1 1 Register R3

1 0 0 Register R4

Figure 15. MUXOUT Schematic

ADF4157

Rev. 0 | Page 10 of 20

DB31

CONTROL

BITS

12-BIT MSB FRACTIONAL VALUE

(FRAC)

12-BIT INTEGER VALUE (INT)

MUXOUT

CONTROL

DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0 M4 M3 M2 M1 N12 N11 N10 N9 N8 N7 N6 N5 N4 N3 N2 N1 F25 F24 F23 F22 F21 F20 F19 F18 F17 F16 F15 F14 C3(0) C2(0) C1(0)

RESERVED

FRAC/INT REGISTER (R0)

DB31

CONTROL

BITS

RESERVED

13-BIT LSB FRACTIONAL VALUE

(FRAC) (DBB)

RESERVED

DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0 0 0 0 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 0 0 0 0 0 0 0 0 0 0 0 0 C3(0) C2(0) C1(1)

LSB FRAC REGISTER (R1)

DB31

RESERVED

POLARITY

LDP

COUNTER

RESET

THREE-STATE

CONTROL

BITS

DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

00000000000000000U12000000U11U10U9U8U7C3(0)C2(1)C1(1)

FUNCTION REGISTER (R3)

DB31

RESERVED CONTROL

BITS

DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

00000000000000000000000000000C3(1)C2(0)C1(0)

TEST REGISTER (R4)

NOTES

1. DBB = DOUBLE BUFFERED BIT(S).

DB31

RESERVED5-BIT R-COUNTER

RESERVED

CSR EN

RESERVED

PRESCALER

RDIV2 DBB

CURRENT

SETTING

REFERENCE

DOUBLER DBB

CONTROL

BITS

DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

000C1CPI4CPI3CPI2CPI10P1U2U1R5R4R3R2R1000000000000C3(0)C2(1)C1(0)

R DIVIDER REGISTER (R2)

DBB DBB

05874-010

RESET

RESERVED

Figure 16. Register Summary

ADF4157

Rev. 0 | Page 11 of 20

FRAC/INT REGISTER (R0) MAP

With R0[2, 1, 0] set to [0, 0, 0], the on-chip Frac/Int register is

programmed as shown in Figure 17.

Reserved Bit

The reserved bit should be set to 0 for normal operation.

MUXOUT

The on-chip multiplexer is controlled by DB[30], DB[29],

DB[28] and DB[27] on the ADF4157. See Figure 17 for

the truth table.

12-Bit INT Value

These twelve bits control what is loaded as the INT value. This

is used to determine the overall feedback division factor. It is

used in Equation 1. See the INT, FRAC, and R Relationship

section for more information.

12-Bit MSB FRAC Value

These twelve bits, along with Bits DB[27:15] in the LSB FRAC

the fractional interpolator. This is part of what determines the

overall feedback division factor. It is also used in Equation 1.

These 12 bits are the most significant bits (MSB) of the 25-bit

FRAC value, and Bits DB[27:15] in the LSB FRAC register (R1)

are the least significant bits (LSB). See the RF Synthesizer: A

Worked Example section for more information.

DB31

CONTROL

BITS

12-BIT MSB FRACTIONAL VALUE

(FRAC)

12-BIT INTEGER VALUE (INT)

MUXOUT

CONTROL

DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0 M4 M3 M2 M1 N12 N11 N10 N9 N8 N7 N6 N5 N4 N3 N2 N1 F25 F24 F23 F22 F21 F20 F19 F18 F17 F16 F15 F14 C3(0) C2(0) C1(0)

RESERVED

M4 M3 M2 M1 OUTPUT

0 0 0 0 THREE-STATE OUTPUT

0001DV

0010DGND

0 0 1 1 R DIVIDER OUTPUT

0 1 0 0 N DIVIDER OUTPUT

0 1 0 1 RESERVED

0 1 1 0 DIGITAL LOCK DETECT

0 1 1 1 SERIAL DATA OUTPUT

1 0 0 0 RESERVED

1 0 0 1 RESERVED

1010CLKDIVIDER

1 0 1 1 RESERVED

1 1 0 0 RESERVED

1 1 0 1 R DIVIDER/2

1 1 1 0 N DIVIDER/2

1 1 1 1 RESERVED

F12 F11 .......... F2 F1

MSB FRACTIONAL VALUE

(FRAC)*

0 0 .......... 0 0 0

0 0 .......... 0 1 1

0 0 .......... 1 0 2

0 0 .......... 1 1 3

. . .......... . . .

1 1 .......... 0 0 4092

1 1 .......... 0 1 4093

1 1 .......... 1 0 4094

1 1 .......... 1 1 4095

N12N11N10N9N8N7N6N5N4N3N2N1

INTEGER VALUE

(INT)

0 0 0 00001011123

0 0 0 00001100024

0 0 0 00001100125

0 0 0 00001101026

. . . ..........

1 1 1 1111111014093

1 1 1 1111111104094

1 1 1 1111111114095

*THE FRAC VALUE IS MADE UP OF THE 12-BIT MSB STORED IN

05874-011

Figure 17. FRAC/INT Register (R0) Map

ADF4157

Rev. 0 | Page 12 of 20

LSB FRAC REGISTER (R1) MAP

With R1[2, 1, 0] set to [0, 0, 1], the on-chip LSB FRAC register

is programmed as shown in Figure 18.

13-Bit LSB FRAC Value

These thirteen bits, along with Bits DB[14:3] in the INT/FRAC

the fractional interpolator. This is part of what determines

the overall feedback division factor. It is also used in Equation 1.

These 13 bits are the least significant bits of the 25-bit FRAC

value, and Bits DB[14:3] in the INT/FRAC register are the most

significant bits. See the RF Synthesizer: A Worked Example

section for more information.

Reserved Bits

All reserved bits should be set to 0 for normal operation.

DB31

CONTROL

BITS

RESERVED

13-BIT LSB FRACTIONAL VALUE

(FRAC)

RESERVED

DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0 0 0 0 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 0 0 0 0 0 0 0 0 0 0 0 0 C3(0) C2(0) C1(1)

F25 F24 .......... F14 F13

LSB FRACTIONAL VALUE

(FRAC)*

0 0 .......... 0 0 0

0 0 .......... 0 1 1

0 0 .......... 1 0 2

0 0 .......... 1 1 3

. . .......... . . .

1 1 .......... 0 0 8188

1 1 .......... 0 1 8189

1 1 .......... 1 0 8190

1 1 .......... 1 1 8191

*THE FRAC VALUE IS MADE UP OF THE 12-BIT MSB STORED IN

05874-012

Figure 18. LSB FRAC Register (R1) Map

ADF4157

Rev. 0 | Page 13 of 20

R DIVIDER REGISTER (R2) MAP

With R1[2, 1, 0] set to [0, 1, 0], the on-chip R divider register is

programmed as shown in Figure 19.

CSR Enable

Setting this bit to 1 enables cycle slip reduction. This is a

method for improving lock times. Note that the signal at the PFD

must have a 50% duty cycle in order for cycle slip reduction to

work. In addition, the charge pump current setting must be set

to a minimum. See the Cycle Slip Reduction for Faster Lock

Times section for more information.

Note also that the cycle slip reduction feature can only be

operated when the phase detector polarity setting is positive

(DB6 in Register R3). It cannot be used if the phase detector

polarity is set to negative.

Charge Pump Current Setting

DB[27], DB[26], DB[25], and DB[24] set the charge pump

current setting. This should be set to the charge pump current

that the loop filter is designed with (see Figure 19).

Prescaler (P/P + 1)

The dual-modulus prescaler (P/P + 1), along with the INT,

FRAC, and MOD counters, determines the overall division ratio

from the RFIN to the PFD input.

Operating at CML levels, it takes the clock from the RF input

stage and divides it down for the counters. It is based on

a synchronous 4/5 core. When set to 4/5, the maximum RF

frequency allowed is 3 GHz. Therefore, when operating

the ADF4157 above 3 GHz, the prescaler must be set to 8/9.

The prescaler limits the INT value.

With P = 4/5, NMIN = 23.

With P = 8/9, NMIN = 75.

RDIV2

Setting this bit to 1 inserts a divide-by-2 toggle flip flop between

the R counter and the PFD. This can be used to provide a 50%

duty cycle signal at the PFD for use with cycle slip reduction.

Reference Doubler

Setting DB[20] to 0 feeds the REFIN signal directly to the 5-bit

RF R counter, disabling the doubler. Setting this bit to 1

multiplies the REFIN frequency by a factor of 2 before feeding

into the 5-bit R counter. When the doubler is disabled,

the REFIN falling edge is the active edge at the PFD input to

the fractional synthesizer. When the doubler is enabled, both

the rising edge and falling edge of REFIN become active edges at

the PFD input.

The maximum allowed REFIN frequency when the doubler is

enabled is 30 MHz.

5-Bit R Counter

The 5-bit R counter allows the input reference frequency

(REFIN) to be divided down to produce the reference clock to

the phase frequency detector (PFD). Division ratios from

1 to 32 are allowed.

Reserved Bits

All reserved bits should be set to 0 for normal operation.

ADF4157

Rev. 0 | Page 14 of 20

DB31

RESERVED5-BIT R-COUNTER

RESERVED

CSR EN

RESERVED

PRESCALER

RDIV2

CURRENT

SETTING

REFERENCE

DOUBLER

CONTROL

BITS

DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

000C1CPI4CPI3CPI2CPI10P1U2U1R5R4R3R2R1000000000000C3(0)C2(1)C1(0

)

CYCLE SLIP

REDUCTION

0DISABLED

1ENABLED

REFERENCE

DOUBLER

0 DISABLED

1ENABLED

R5 R4 R3 R2 R1 R COUNTER DIVIDE RATIO

000011

000102

000113

001004

.....

1110129

1111 .30

1111131

0000032

U2 R DIVIDER

0DISABLED

1ENABLED

P1 PRESCALER

04/5

18/9

ICP (mA)

CPI4 CPI3 CPI2 CPI1 5.1kΩ

00000.31

00010.63

00100.94

00111.25

01001.57

01011.88

01102.19

01112.5

10002.81

10013.13

10103.44

10113.75

11004.06

11014.38

11104.69

11115

05874-013

Figure 19. R Divider Register (R2) Map

ADF4157

Rev. 0 | Page 15 of 20

FUNCTION REGISTER (R3) MAP

With R2[2, 1, 0] set to [0, 1, 1], the on-chip function register is

programmed as shown in Figure 20.

Reserved Bits

All reserved bits should be set to 0 for normal operation.

Σ-Δ Reset

For most applications, DB14 should be set to 0. When DB14 is

set to 0, the Σ- modulator is reset on each write to Register 0.

If it is not required that the Σ- modulator be reset on each

Lock Detect Precision (LDP)

When DB[7] is programmed to 0, 24 consecutive PFD cycles of

15 ns must occur before digital lock detect is set. When this bit

is programmed to 1, 40 consecutive reference cycles of 15 ns

must occur before digital lock detect is set.

Phase Detector Polarity

DB[6] in the ADF4157 sets the phase detector polarity. When

the VCO characteristics are positive, this should be set to 1.

When they are negative, it should be set to 0.

RF Power-Down

DB[5] on the ADF4157 provides the programmable power-

down mode. Setting this bit to 1 performs a power-down.

Setting this bit to 0 returns the synthesizer to normal operation.

While in software power-down mode, the part retains all

information in its registers. Only when supplies are removed are

the register contents lost.

When a power-down is activated, the following events occur:

1. All active dc current paths are removed.

2. The synthesizer counters are forced to their load state

conditions.

3. The charge pump is forced into three-state mode.

4. The digital lock detect circuitry is reset.

5. The RFIN input is debiased.

6. The input register remains active and capable of loading

and latching data.

RF Charge Pump Three-State

DB[4] puts the charge pump into three-state mode when

programmed to 1. It should be set to 0 for normal operation.

RF Counter Reset

DB[3] is the RF counter reset bit for the ADF4157. When this is

1, the RF synthesizer counters are held in reset. For normal

operation, this bit should be 0.

DB31

RESERVED

POLARITY

LDP

COUNTER

RESET

THREE-STATE

CONTROL

BITS

DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

00000000000000000U12000000U11U10U9U8U7C3(0)C2(1)C1(1)

U9 POWER DOWN

0 DISABLED

1ENABLED

U11 LDP

0 24 PFD CYCLES

1 40 PFD CYCLES

COUNTER

RESET

0DISABLED

1ENABLED

U10 PD POLARITY

0NEGATIVE

1POSITIVE

THREE-STATE

0DISABLED

1ENABLED

05874-014

RESET

RESERVED

U12 SD RESET

0 ENABLED

1 DISABLED

Figure 20. Function Register (R3) Map

ADF4157

Rev. 0 | Page 16 of 20

TEST REGISTER (R4) MAP

Reserved Bits

With R3[2, 1, 0] set to [1, 0, 0], the on-chip test register (R4) is

programmed as shown in Figure 21. DB[31:3] should be set to 0 in this register.

DB31

RESERVED CONTROL

BITS

DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

00000000000000000000000000000C3(1)C2(0)C1(0)

SET THESE BITS TO 0

05874-015

Figure 21. Test Register (R4) Map

ADF4157

Rev. 0 | Page 17 of 20

APPLICATIONS INFORMATION

INITIALIZATION SEQUENCE

After powering up the part, this programming sequence must

be followed:

1. Test Register (R4)

2. Function Register (R3)

3. R Divider Register (R2)

4. LSB FRAC Register (R1)

5. FRAC/INT Register (R0)

RF SYNTHESIZER: A WORKED EXAMPLE

The following equation governs how the synthesizer should be

programmed:

RFOUT = [N + (FRAC/225)] × [fPFD] (3)

where:

RFOUT is the RF frequency output.

N is the integer division factor.

FRAC is the fractionality.

fPFD = REFIN × [(1 + D)/(R × (1 + T))] (4)

where:

REFIN is the reference frequency input.

D is the RF REFIN doubler bit.

R is the RF reference division factor.

T is the reference divide-by-2 bit (0 or 1).

For example, in a system where a 5.8002 GHz RF frequency

output (RFOUT) is required and a 10 MHz reference frequency

input (REFIN) is available, the frequency resolution is

fRES = REFIN/225

fRES = 10 MHz/225 = 0.298 Hz

From Equation 4,

fPFD = [10 MHz × (1 + 0)/1] = 10 MHz

5.8002 GHz = 10 MHz × (N + FRAC/225)

Calculating N and FRAC values,

N = int(RFOUT/fPFD) = 580

FRAC = FMSB × 213 + FLSB

FMSB = int(((RFOUT/fPFD) − N) × 212) = 81

FLSB = int(((((RFOUT/fPFD) − N) × 212) − FMSB) × 213) = 7537

where:

FMSB is the 12-bit MSB FRAC value in Register R0.

FLSB is the 13-bit LSB FRAC value in Register R1.

int() makes an integer of the argument in brackets.

REFERENCE DOUBLER AND REFERENCE DIVIDER

The reference doubler on-chip allows the input reference signal

to be doubled. This is useful for increasing the PFD comparison

frequency. Making the PFD frequency higher improves the noise

performance of the system. Doubling the PFD frequency

usually improves noise performance by 3 dB. It is important to

note that the PFD cannot be operated above 32 MHz due to

a limitation in the speed of the Σ- circuit of the N divider.

CYCLE SLIP REDUCTION FOR FASTER LOCK TIMES

In fast-locking applications, a wide loop filter bandwidth is

required for fast frequency acquisition, resulting in increased

integrated phase noise and reduced spur attenuation. Using

cycle slip reduction, the loop bandwidth can be kept narrow to

reduce integrated phase noise and attenuate spurs while still

realizing fast lock times.

Cycle Slips

Cycle slips occur in integer-N/fractional-N synthesizers when

the loop bandwidth is narrow compared to the PFD frequency.

The phase error at the PFD inputs accumulates too fast for the PLL

to correct, and the charge pump temporarily pumps in the wrong

direction, slowing down the lock time dramatically. The ADF4157

contains a cycle slip reduction circuit to extend the linear range

of the PFD, allowing faster lock times without loop filter changes.

When the ADF4157 detects that a cycle slip is about to occur, it

turns on an extra charge pump current cell. This outputs a constant

current to the loop filter or removes a constant current from the

loop filter (depending on whether the VCO tuning voltage needs

to increase or decrease to acquire the new frequency). The effect is

that the linear range of the PFD is increased. Stability is main-

tained because the current is constant and is not a pulsed current.

If the phase error increases again to a point where another cycle

slip is likely, the ADF4157 turns on another charge pump cell.

This continues until the ADF4157 detects that the VCO

frequency has gone past the desired frequency. It then begins to

turn off the extra charge pump cells one by one until they are all

turned off and the frequency is settled.

Up to seven extra charge pump cells can be turned on. In most

applications, it is enough to eliminate cycle slips altogether,

giving much faster lock times.

Setting Bit DB28 in the R Divider register (R2) to 1 enables

cycle slip reduction. Note that a 45% to 55% duty cycle is

needed on the signal at the PFD in order for CSR to operate

correctly. The reference divide-by-2 flip-flop can help to

provide a 50% duty cycle at the PFD. For example, if a 100 MHz

reference frequency is available, and the user wants to run the

PFD at 10 MHz, setting the R divide factor to 10 results in a 10

MHz PFD signal that is not 50% duty cycle. By setting the R

divide factor to 5 and enabling the reference divide-by-2 bit, a

50% duty cycle 10 MHz signal can be achieved.

Note that the cycle slip reduction feature can only be operated

when the phase detector polarity setting is positive (DB6 in

set to negative.

ADF4157

Rev. 0 | Page 18 of 20

SPUR MECHANISMS

The fractional interpolator in the ADF4157 is a third-order Σ-

modulator (SDM) with a 25-bit fixed modulus (MOD). The SDM

is clocked at the PFD reference rate (fPFD) that allows PLL output

frequencies to be synthesized at a channel step resolution of

fPFD/MOD. The various spur mechanisms possible with

fractional-N synthesizers, and how they affect the ADF4157,

are discussed in this section.

Fractional Spurs

In most fractional synthesizers, fractional spurs can appear at

the set channel spacing of the synthesizer. In the ADF4157,

these spurs do not appear. The high value of the fixed modulus

in the ADF4157 makes the Σ- modulator quantization error

spectrum look like broadband noise, effectively spreading

the fractional spurs into noise.

Integer Boundary Spurs

Interactions between the RF VCO frequency and the PFD

frequency can lead to spurs known as integer boundary spurs.

When these frequencies are not integer related (which is

the purpose of the fractional-N synthesizer), spur sidebands

appear on the VCO output spectrum at an offset frequency that

corresponds to the beat note or difference frequency between

an integer multiple of the PFD and the VCO frequency.

These spurs are named integer boundary spurs because they are

more noticeable on channels close to integer multiples of the PFD

where the difference frequency can be inside the loop band-

width. These spurs are attenuated by the loop filter.

Figure 7 shows an integer boundary spur. The RF frequency is

5800.25 MHz, and the PFD frequency is 25 MHz. The integer

boundary spur is 250 kHz from the carrier at an integer times

the PFD frequency (232 × 25 MHz = 5800 MHz). The spur also

appears on the upper sideband.

Reference Spurs

Reference spurs are generally not a problem in fractional-N

synthesizers because the reference offset is far outside the loop

bandwidth. However, any reference feedthrough mechanism

that bypasses the loop can cause a problem. One such

mechanism is the feedthrough of low levels of on-chip reference

switching noise out through the RFIN pin back to the VCO,

resulting in reference spur levels as high as –90 dBc. Care

should be taken in the PCB layout to ensure that the VCO is

well separated from the input reference to avoid a possible

feedthrough path on the board.

LOW FREQUENCY APPLICATIONS

The specification on the RF input is 0.5 GHz minimum;

however, RF frequencies lower than this can be used providing

the minimum slew rate specification of 400 V/µs is met.

An appropriate LVDS driver can be used to square up the RF

signal before it is fed back to the ADF4157 RF input. The FIN1001

from Fairchild Semiconductor is one such LVDS driver.

FILTER DESIGN—ADIsimPLL

A filter design and analysis program is available to help the user

implement PLL design. Visit www.analog.com/pll for a free

download of the ADIsimPLL™ software. The software designs,

simulates, and analyzes the entire PLL frequency domain and

time domain response. Various passive and active filter

architectures are allowed.

INTERFACING

The ADF4157 has a simple SPI-compatible serial interface for

writing to the device. CLK, DATA, and LE control the data

transfer. When latch enable (LE) is high, the 29 bits that have

been clocked into the input register on each rising edge of

SCLK are transferred to the appropriate latch. See Figure 2 for

the timing diagram and Table 6 for the latch truth table.

The maximum allowable serial clock rate is 20 MHz.

PCB DESIGN GUIDELINES FOR THE CHIP SCALE

PACKAGE

The lands on the chip scale package (CP-20) are rectangular.

The printed circuit board pad for these should be 0.1 mm

longer than the package land length and 0.05 mm wider than

the package land width. The land should be centered on the pad.

This ensures that the solder joint size is maximized.

The bottom of the chip scale package has a central thermal pad.

The thermal pad on the printed circuit board should be at least

as large as this exposed pad. On the printed circuit board, there

should be a clearance of at least 0.25 mm between the thermal

pad and the inner edges of the pad pattern. This ensures that

shorting is avoided.

Thermal vias can be used on the printed circuit board thermal

pad to improve thermal performance of the package. If vias are

used, they should be incorporated into the thermal pad at

1.2 mm pitch grid. The via diameter should be between 0.3 mm

and 0.33 mm, and the via barrel should be plated with 1 ounce

of copper to plug the via. The user should connect the printed

circuit board thermal pad to AGND.

ADF4157

Rev. 0 | Page 19 of 20

OUTLINE DIMENSIONS

16 9

PIN 1

SEATING

PLANE

8°

0°

4.50

4.40

4.30

6.40

BSC

5.10

5.00

4.90

0.65

BSC

0.15

0.05

1.20

MAX

0.20

0.09 0.75

0.60

0.45

0.30

0.19

COPLANARITY

0.10

COMPLIANT TO JEDEC STANDARDS MO-153-AB

Figure 22. 16-Lead Thin Shrink Small Outline Package [TSSOP]

(RU-16)

Dimensions shown in millimeters

2.25

2.10 SQ

1.95

0.75

0.55

0.35

0.30

0.23

0.18

0.50

BSC

12° MAX

0.20

REF

0.80 MAX

0.65 TYP

0.05 MAX

0.02 NOM

1.00

0.85

0.80

SEATING

PLANE

PIN 1

INDICATO

TOP

BCS SQ

4.00

BSC SQ

COPLANARITY

0.08

0.60

MAX

0.60

MAX

0.25 MIN

COMPLIANT TO JEDEC STANDARDS MO-220-VGGD-1

PIN 1

INDICATOR

Figure 23. 20-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

4mm × 4 mm Body, Very Thin Quad

(CP-20-1)

Dimensions shown in millimeters

ORDERING GUIDE

Model Description Temperature Range Package Option

ADF4157BRUZ 16-Lead Thin Shrink Small Outline Package [TSSOP] −40°C to +85°C RU-16

ADF4157BRUZ-RL 16-Lead Thin Shrink Small Outline Package [TSSOP] −40°C to +85°C RU-16

ADF4157BRUZ-RL7 16-Lead Thin Shrink Small Outline Package [TSSOP] −40°C to +85°C RU-16

ADF4157BCPZ 20-Lead Lead Frame Chip Scale Package [LFCSP_VQ] −40°C to +85°C CP-20-1

ADF4157BCPZ-RL 20-Lead Lead Frame Chip Scale Package [LFCSP_VQ] −40°C to +85°C CP-20-1

ADF4157BCPZ-RL7 20-Lead Lead Frame Chip Scale Package [LFCSP_VQ] −40°C to +85°C CP-20-1

EVAL-ADF4157EB1Z Evaluation Board

1 Z = RoHS Compliant Part.

ADF4157

Rev. 0 | Page 20 of 20

NOTES

registered trademarks are the property of their respective owners.

D05874-0-7/07(0)