MC74HC4316ADT - Motorola / Freescale Semiconductor



SEMICONDUCTOR TECHNICAL DATA

1REV 0

 Motorola, Inc. 1995

10/95

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High–Performance Silicon–Gate CMOS

The MC74HC4316A utilizes silicon–gate CMOS technology to achieve

fast propagation delays, low ON resistances, and low OFF–channel leakage

current. This bilateral switch/multiplexer/demultiplexer controls analog and

digital voltages that may vary across the full analog power–supply range

(from VCC to VEE).

The HC4316A is similar in function to the metal–gate CMOS MC14016

and MC14066, and to the High–Speed CMOS HC4016A and HC4066A.

Each device has four independent switches. The device control and Enable

inputs are compatible with standard CMOS outputs; with pullup resistors,

they are compatible with LSTTL outputs. The device has been designed so

that the ON resistances (RON) are much more linear over input voltage than

RON of metal–gate CMOS analog switches. Logic–level translators are

provided so that the On/Off Control and Enable logic–level voltages need

only be VCC and GND, while the switch is passing signals ranging between

VCC and VEE. When the Enable pin (active–low) is high, all four analog

switches are turned off.

•Logic–Level Translator for On/Off Control and Enable Inputs

•Fast Switching and Propagation Speeds

•High ON/OFF Output Voltage Ratio

•Diode Protection on All Inputs/Outputs

•Analog Power–Supply Voltage Range (VCC – VEE) = 2.0 to 12.0 Volts

•Digital (Control) Power–Supply Voltage Range (VCC – GND) = 2.0 to

6.0 Volts, Independent of VEE

•Improved Linearity of ON Resistance

•Chip Complexity: 66 FETs or 16.5 Equivalent Gates

LOGIC DIAGRAM

A ON/OFF CONTROL

ANALOG

SWITCH

LEVEL

TRANSLATOR

ANALOG

OUTPUTS/INPUTS

PIN 16 = VCC

PIN 8 = GND

PIN 9 = VEE

GND

≥

VEE

2YA

B ON/OFF CONTROL

ANALOG

SWITCH

LEVEL

TRANSLATOR

3YB

C ON/OFF CONTROL

ANALOG

SWITCH

LEVEL

TRANSLATOR

11 YC

D ON/OFF CONTROL

ANALOG

SWITCH

LEVEL

TRANSLATOR

12 YD

ENABLE 7

ANALOG INPUTS/OUTPUTS = XA, XB, XC, XD

This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice.



FUNCTION TABLE

PIN ASSIGNMENT

125

D ON/OFF

CONTROL

A ON/OFF

CONTROL

VCC

VEE

GND

ENABLE

C ON/OFF

CONTROL

B ON/OFF

CONTROL

Inputs State of

On/Off Analog

Enable Control Switch

L H On

L L Off

H X Off

X = don’t care

D SUFFIX

SOIC PACKAGE

CASE 751B–05

N SUFFIX

PLASTIC PACKAGE

CASE 648–08

ORDERING INFORMATION

MC74HCXXXXAN

MC74HCXXXXAD

MC74HCXXXXADT

Plastic

SOIC

TSSOP

14 DT SUFFIX

TSSOP PACKAGE

CASE 948G–01

MC74HC4316A

MOTOROLA High–Speed CMOS Logic Data

DL129 — Rev 6

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

MAXIMUM RATINGS*

ÎÎÎ

Symbol

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Parameter

ÎÎÎÎÎÎ

Value

ÎÎÎ

Unit

ÎÎÎ

VCC

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Positive DC Supply Voltage (Ref. to GND)

(Ref. to VEE)

ÎÎÎÎÎÎ

– 0.5 to + 7.0

– 0.5 to + 14.0

ÎÎÎ

VEE

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Negative DC Supply Voltage (Ref. to GND)

ÎÎÎÎÎÎ

– 7.0 to + 0.5

ÎÎÎ

VIS

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Analog Input Voltage

ÎÎÎÎÎÎ

VEE – 0.5

to VCC + 0.5

ÎÎÎ

Vin

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Input Voltage (Ref. to GND)

ÎÎÎÎÎÎ

– 0.5 to VCC + 0.5

ÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Current Into or Out of Any Pin

ÎÎÎÎÎÎ

± 25

ÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Power Dissipation in Still Air Plastic DIP†

SOIC Package†

TSSOP Package†

ÎÎÎÎÎÎ

750

500

450

ÎÎÎ

Tstg

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Storage Temperature

ÎÎÎÎÎÎ

– 65 to + 150

ÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Lead Temperature, 1 mm from Case for 10 Seconds

(Plastic DIP, SOIC or TSSOP Package)

ÎÎÎÎÎÎ

260

ÎÎÎ

*Maximum Ratings are those values beyond which damage to the device may occur.

Functional operation should be restricted to the Recommended Operating Conditions.

†Derating — Plastic DIP: – 10 mW/

C from 65

to 125

SOIC Package: – 7 mW/

C from 65

to 125

TSSOP Package: – 6.1 mW/

C from 65

to 125

For high frequency or heavy load considerations, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).

RECOMMENDED OPERATING CONDITIONS

ÎÎÎÎ

Symbol

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Parameter

ÎÎÎ

Min

ÎÎÎ

Max

ÎÎÎ

Unit

ÎÎÎÎ

VCC

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Positive DC Supply Voltage (Ref. to GND)

ÎÎÎ

2.0

ÎÎÎ

6.0

ÎÎÎ

ÎÎÎÎ

VEE

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Negative DC Supply Voltage (Ref. to GND)

ÎÎÎ

– 6.0

ÎÎÎ

GND

ÎÎÎ

ÎÎÎÎ

VIS

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Analog Input Voltage

ÎÎÎ

VEE

ÎÎÎ

VCC

ÎÎÎ

ÎÎÎÎ

Vin

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Digital Input Voltage (Ref. to GND)

ÎÎÎ

GND

ÎÎÎ

VCC

ÎÎÎ

ÎÎÎÎ

VIO*

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Static or Dynamic Voltage Across Switch

ÎÎÎ

—

ÎÎÎ

1.2

ÎÎÎ

ÎÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Operating Temperature, All Package Types

ÎÎÎ

– 55

ÎÎÎ

+ 125

ÎÎÎ

ÎÎÎÎ

tr, tf

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Input Rise and Fall Time VCC = 2.0 V

(Control or Enable Inputs) VCC = 3.0 V

(Figure 10) VCC = 4.5 V

VCC = 6.0 V

ÎÎÎ

1000

600

500

400

ÎÎÎ

*For voltage drops across the switch greater than 1.2 V (switch on), excessive VCC current may

be drawn; i.e., the current out of the switch may contain both VCC and switch input components.

The reliability of the device will be unaffected unless the Maximum Ratings are exceeded.

DC ELECTRICAL CHARACTERISTICS Digital Section (Voltages Referenced to GND) VEE = GND Except Where Noted

ÎÎÎÎ

Symbol

ÎÎÎÎÎÎÎÎÎ

Parameter

ÎÎÎÎÎÎÎÎÎ

Test Conditions

ÎÎÎÎ

VCC

ÎÎÎÎÎÎÎÎÎ

Guaranteed Limit

ÎÎÎ

Unit

ÎÎÎÎ

Symbol

ÎÎÎÎÎÎÎÎÎ

Parameter

ÎÎÎÎÎÎÎÎÎ

Test Conditions

ÎÎÎÎ

VCC

ÎÎÎ

– 55 to

ÎÎÎÎ

125

ÎÎÎ

Unit

ÎÎÎÎ

VIH

ÎÎÎÎÎÎÎÎÎ

Minimum High–Level Voltage,

Control or Enable Inputs

ÎÎÎÎÎÎÎÎÎ

Ron = Per Spec

ÎÎÎÎ

2.0

3.0

4.5

6.0

ÎÎÎ

1.5

2.1

3.15

4.2

ÎÎÎÎ

1.5

2.1

3.15

4.2

ÎÎÎÎ

1.5

2.1

3.15

4.2

ÎÎÎ

ÎÎÎÎ

VIL

ÎÎÎÎÎÎÎÎÎ

Maximum Low–Level Voltage,

Control or Enable Inputs

ÎÎÎÎÎÎÎÎÎ

Ron = Per Spec

ÎÎÎÎ

2.0

3.0

4.5

6.0

ÎÎÎ

0.5

0.9

1.35

1.8

ÎÎÎÎ

0.5

0.9

1.35

1.8

ÎÎÎÎ

0.5

0.9

1.35

1.8

ÎÎÎ

ÎÎÎÎ

Iin

ÎÎÎÎÎÎÎÎÎ

Maximum Input Leakage

Current, Control or Enable

Inputs

ÎÎÎÎÎÎÎÎÎ

Vin = VCC or GND

VEE = – 6.0 V

ÎÎÎÎ

6.0

ÎÎÎ

± 0.1

ÎÎÎÎ

± 1.0

ÎÎÎÎ

± 1.0

ÎÎÎ

µA

ÎÎÎÎ

ICC

ÎÎÎÎÎÎÎÎÎ

Maximum Quiescent Supply

Current (per Package)

ÎÎÎÎÎÎÎÎÎ

Vin = VCC or GND

VIO = 0 V VEE = GND

VEE = – 6.0

ÎÎÎÎ

6.0

ÎÎÎ

ÎÎÎÎ

160

ÎÎÎ

µA

NOTE:Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).

This device contains protection

circuitry to guard against damage

due to high static voltages or electric

fields. However, precautions must

be taken to avoid applications of any

voltage higher than maximum rated

voltages to this high–impedance cir-

cuit. For proper operation, Vin and

Vout should be constrained to the

range GND

(Vin or V out)

VCC.

Unused inputs must always be

tied to an appropriate logic voltage

level (e.g., either GND or VCC).

Unused outputs must be left open.

I/O pins must be connected to a

properly terminated line or bus.

MC74HC4316A

High–Speed CMOS Logic Data

DL129 — Rev 6 3 MOTOROLA

DC ELECTRICAL CHARACTERISTICS Analog Section (Voltages Referenced to VEE)

ÎÎÎ

Symbol

ÎÎÎÎÎÎÎÎÎ

Parameter

ÎÎÎÎÎÎÎÎÎ

Test Conditions

ÎÎÎ

VCC

ÎÎÎ

VEE

ÎÎÎÎÎÎÎÎÎ

Guaranteed Limit

ÎÎÎ

Unit

ÎÎÎ

Symbol

ÎÎÎÎÎÎÎÎÎ

Parameter

ÎÎÎÎÎÎÎÎÎ

Test Conditions

ÎÎÎ

VCC

ÎÎÎ

VEE

ÎÎÎÎ

– 55 to

ÎÎÎÎ

ÎÎÎ

125

ÎÎÎ

Unit

ÎÎÎ

Ron

ÎÎÎÎÎÎÎÎÎ

Maximum “ON” Resistance

ÎÎÎÎÎÎÎÎÎ

Vin = VIH

VIS = VCC to VEE

2.0 mA (Figures 1, 2)

ÎÎÎ

2.0*

4 5

4.5

6.0

ÎÎÎ

0.0

– 4.5

– 6.0

ÎÎÎÎ

—

160

ÎÎÎÎ

—

200

110

ÎÎÎ

—

240

130

ÎÎÎ

Ω

ÎÎÎ

ÎÎÎÎÎÎÎÎÎ

Vin = VIH

VIS = VCC or VEE (Endpoints)

2.0 mA (Figures 1, 2)

ÎÎÎ

2.0

4.5

6.0

ÎÎÎ

0.0

– 4.5

– 6.0

ÎÎÎÎ

—

ÎÎÎÎ

—

115

ÎÎÎ

—

140

105

ÎÎÎ

∆Ron

ÎÎÎÎÎÎÎÎÎ

Maximum Difference in “ON”

Resistance Between Any Two

Channels in the Same Package

ÎÎÎÎÎÎÎÎÎ

Vin = VIH

VIS = 1/2 (VCC – VEE)

2.0 mA

ÎÎÎ

2.0

4.5

6.0

ÎÎÎ

0.0

– 4.5

– 6.0

ÎÎÎÎ

—

ÎÎÎÎ

—

ÎÎÎ

—

ÎÎÎ

Ω

ÎÎÎ

Ioff

ÎÎÎÎÎÎÎÎÎ

Maximum Off–Channel Leakage

Current, Any One Channel

ÎÎÎÎÎÎÎÎÎ

Vin = VIL

VIO = VCC or VEE

Switch Off (Figure 3)

ÎÎÎ

6.0

ÎÎÎ

– 6.0

ÎÎÎÎ

0.1

ÎÎÎÎ

0.5

ÎÎÎ

1.0

ÎÎÎ

µA

ÎÎÎ

Ion

ÎÎÎÎÎÎÎÎÎ

Maximum On–Channel Leakage

Current, Any One Channel

ÎÎÎÎÎÎÎÎÎ

Vin = VIH

VIS = VCC or VEE

(Figure 4)

ÎÎÎ

6.0

ÎÎÎ

– 6.0

ÎÎÎÎ

0.1

ÎÎÎÎ

0.5

ÎÎÎ

1.0

ÎÎÎ

µA

*At supply voltage (VCC – VEE) approaching 2 V the analog switch–on resistance becomes extremely non–linear. Therefore, for low–voltage

operation, it is recommended that these devices only be used to control digital signals.

NOTE:Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).

AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Control or Enable tr = tf = 6 ns, VEE = GND)

ÎÎÎÎ

Symbol

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Parameter

ÎÎÎÎ

VCC

ÎÎÎÎÎÎÎÎÎ

Guaranteed Limit

ÎÎÎ

Unit

ÎÎÎÎ

Symbol

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Parameter

ÎÎÎÎ

VCC

ÎÎÎ

– 55 to

ÎÎÎÎ

125

ÎÎÎ

Unit

ÎÎÎÎ

tPLH,

tPHL

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Maximum Propagation Delay, Analog Input to Analog Output

(Figures 8 and 9)

ÎÎÎÎ

2.0

4.5

6.0

ÎÎÎ

ÎÎÎÎ

ÎÎÎ

ÎÎÎÎ

tPLZ,

tPHZ

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Maximum Propagation Delay, Control or Enable to Analog Output

(Figures 10 and 11)

ÎÎÎÎ

2.0

4.5

6.0

ÎÎÎ

130

ÎÎÎÎ

160

ÎÎÎÎ

200

ÎÎÎ

ÎÎÎÎ

tPZL,

tPZH

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Maximum Propagation Delay, Control or Enable to Analog Output

(Figures 10 and 11)

ÎÎÎÎ

2.0

4.5

6.0

ÎÎÎ

140

ÎÎÎÎ

175

ÎÎÎÎ

250

ÎÎÎ

ÎÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Maximum Capacitance ON/OFF Control

and Enable Inputs

ÎÎÎÎ

—

ÎÎÎ

ÎÎÎÎ

ÎÎÎ

ÎÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Control Input = GND

Analog I/O

Feedthrough

ÎÎÎÎ

—

ÎÎÎ

1.0

ÎÎÎÎ

1.0

ÎÎÎÎ

1.0

ÎÎÎ

NOTES:

1. For propagation delays with loads other than 50 pF, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).

2. Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).

CPD

Power Dissipation Capacitance (Per Switch) (Figure 13)*

Typical @ 25°C, VCC = 5.0 V

CPD Power Dissipation Capacitance (Per Switch) (Figure 13)*

*Used to determine the no–load dynamic power consumption: PD = CPD VCC2f + ICC VCC. For load considerations, see Chapter 2 of the

Motorola High–Speed CMOS Data Book (DL129/D).

MC74HC4316A

MOTOROLA High–Speed CMOS Logic Data

DL129 — Rev 6

ADDITIONAL APPLICATION CHARACTERISTICS (GND = 0 V)

ÎÎÎÎ

Symbol

ÎÎÎÎÎÎÎÎÎÎ

Parameter

ÎÎÎÎÎÎÎÎÎÎÎÎ

Test Conditions

ÎÎÎÎ

VCC

ÎÎÎ

VEE

ÎÎÎ

Limit*

ÎÎÎ

Unit

ÎÎÎÎ

ÎÎÎÎÎÎÎÎÎÎ

Maximum On–Channel Bandwidth or

Minimum Frequency Response

(Figure 5)

ÎÎÎÎÎÎÎÎÎÎÎÎ

fin = 1 MHz Sine Wave

Adjust fin Voltage to Obtain 0 dBm at VOS

Increase fin Frequency Until dB Meter

Reads – 3 dB RL = 50 Ω, CL = 10 pF

ÎÎÎÎ

2.25

4.50

6.00

ÎÎÎ

– 2.25

– 4.50

– 6.00

ÎÎÎ

150

160

ÎÎÎ

MHz

ÎÎÎÎ

—

ÎÎÎÎÎÎÎÎÎÎ

Off–Channel Feedthrough Isolation

(Figure 6)

ÎÎÎÎÎÎÎÎÎÎÎÎ

fin



Sine Wave

Adjust fin Voltage to Obtain 0 dBm at VIS

fin = 10 kHz, RL = 600 Ω, CL = 50 pF

ÎÎÎÎ

2.25

4.50

6.00

ÎÎÎ

– 2.25

– 4.50

– 6.00

ÎÎÎ

– 50

ÎÎÎ

ÎÎÎÎ

ÎÎÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎÎ

fin = 1.0 MHz, RL = 50 Ω, CL = 10 pF

ÎÎÎÎ

2.25

4.50

6.00

ÎÎÎ

– 2.25

– 4.50

– 6.00

ÎÎÎ

– 40

ÎÎÎ

ÎÎÎÎ

—

ÎÎÎÎÎÎÎÎÎÎ

Feedthrough Noise, Control to

Switch

(Figure 7)

ÎÎÎÎÎÎÎÎÎÎÎÎ

Vin

1 MHz Square Wave (tr = tf = 6 ns)

Adjust RL at Setup so that IS = 0 A

RL = 600 Ω, CL = 50 pF

ÎÎÎÎ

2.25

4.50

6.00

ÎÎÎ

– 2.25

– 4.50

– 6.00

ÎÎÎ

130

200

ÎÎÎ

mVPP

ÎÎÎÎ

ÎÎÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎÎ

RL = 10 kΩ, CL = 10 pF

ÎÎÎÎ

2.25

4.50

6.00

ÎÎÎ

– 2.25

– 4.50

– 6.00

ÎÎÎ

100

ÎÎÎ

ÎÎÎÎ

—

ÎÎÎÎÎÎÎÎÎÎ

Crosstalk Between Any Two

Switches

(Figure 12)

ÎÎÎÎÎÎÎÎÎÎÎÎ

fin



Sine Wave

Adjust fin Voltage to Obtain 0 dBm at VIS

fin = 10 kHz, RL = 600 Ω, CL = 50 pF

ÎÎÎÎ

2.25

4.50

6.00

ÎÎÎ

– 2.25

– 4.50

– 6.00

ÎÎÎ

– 70

ÎÎÎ

ÎÎÎÎ

ÎÎÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎÎ

fin = 1.0 MHz, RL = 50 Ω, CL = 10 pF

ÎÎÎÎ

2.25

4.50

6.00

ÎÎÎ

– 2.25

– 4.50

– 6.00

ÎÎÎ

– 80

ÎÎÎ

ÎÎÎÎ

THD

ÎÎÎÎÎÎÎÎÎÎ

Total Harmonic Distortion

(Figure 14)

ÎÎÎÎÎÎÎÎÎÎÎÎ

fin = 1 kHz, RL = 10 kΩ, CL = 50 pF

THD = THDMeasured – THDSource

VIS = 4.0 VPP sine wave

VIS = 8.0 VPP sine wave

VIS = 11.0 VPP sine wave

ÎÎÎÎ

2.25

4.50

6.00

ÎÎÎ

– 2.25

– 4.50

– 6.00

ÎÎÎ

0.10

0.06

0.04

ÎÎÎ

*Limits not tested. Determined by design and verified by qualification.

MC74HC4316A

High–Speed CMOS Logic Data

DL129 — Rev 6 5 MOTOROLA

Figure 1b. Typical On Resistance,

VCC – VEE = 4.5 V

Figure 1d. Typical On Resistance,

VCC – VEE = 9.0 V

Figure 1c. Typical On Resistance,

VCC – VEE = 6.0 V

Figure 1e. Typical On Resistance,

VCC – VEE = 12.0 V

Figure 1a. Typical On Resistance,

VCC – VEE = 2.0 V

Figure 2. On Resistance Test Set–Up

PLOTTER

MINI COMPUTER

PROGRAMMABLE

POWER

SUPPLY DC ANALYZER

VCC

+–

ANALOG IN COMMON OUT

GND

DEVICE

UNDER TEST

VEE

TBD TBD

TBD

MC74HC4316A

MOTOROLA High–Speed CMOS Logic Data

DL129 — Rev 6

Figure 3. Maximum Off Channel Leakage Current,

Any One Channel, Test Set–Up Figure 4. Maximum On Channel Leakage Current,

Test Set–Up

OFF

16 VCC

VEE

VCC

VEE

VCC

O/I

SELECTED

CONTROL

INPUT

VIL

16 VCC

N/C

VEE

VCC

VEE

SELECTED

CONTROL

INPUT

VIH

Figure 5. Maximum On–Channel Bandwidth

Test Set–Up

VCC

0.1

FCL*

fin TO dB

METER

*Includes all probe and jig capacitance.

VEE

SELECTED

CONTROL

INPUT

VCC

Figure 6. Off–Channel Feedthrough Isolation,

Test Set–Up

OFF

16 VCC

0.1

FCL*

fin TO dB

METER

*Includes all probe and jig capacitance.

VEE

SELECTED

CONTROL

INPUT

VCC

Figure 7. Feedthrough Noise, Control to Analog Out,

Test Set–Up

16 VCC

*Includes all probe and jig capacitance.

ON/OFF

CONTROL

SELECTED

CONTROL

INPUT

VEE

CL*

TEST

POINT

RLVCC

GND

ANALOG IN

ANALOG OUT 50%

tPLH tPHL

50%

Figure 8. Propagation Delays, Analog In to

Analog Out

VIS

MC74HC4316A

High–Speed CMOS Logic Data

DL129 — Rev 6 7 MOTOROLA

POSITION WHEN TESTING tPLZ AND tPZL

Figure 9. Propagation Delay Test Set–Up

16 VCC

*Includes all probe and jig capacitance.

TEST

POINT

ANALOG O/IANALOG I/O

50 pF*

SELECTED

CONTROL

INPUT

VCC

Figure 10. Propagation Delay, ON/OFF Control

to Analog Out

ON/OFF

VCC

TEST

POINT

VCC 1 k

Ω

POSITION WHEN TESTING tPHZ AND tPZH

50 pF*

Figure 11. Propagation Delay Test Set–Up

Figure 12. Crosstalk Between Any Two Switches,

Test Set–Up (Adjacent Channels Used)

*Includes all probe and jig capacitance.

OFF

VIS

fin 0.1

Figure 13. Power Dissipation Capacitance

Test Set–Up

VCC

N/C

ON/OFF

N/C

SELECTED

CONTROL

INPUT

CONTROL

VCC

CL*

fin RL

DISTORTION

METER

*Includes all probe and jig capacitance.

VOS

VIS

SELECTED

CONTROL

INPUT

VCC

Figure 14. Total Harmonic Distortion, Test Set–Up

*Includes all probe and jig capacitance.

CONTROL

ENABLE

VCC

VEE

CL*

SELECTED

CONTROL

INPUT

VCC

TEST

POINT

ANALOG I/O

VEE

50%

50% 90%

10%

tPZL tPLZ

tPZH tPHZ

HIGH

IMPEDANCE

VOL

VOH

HIGH

IMPEDANCE

VCC

GND

50%

ANALOG

OUT

CONTROL

ENABLE trtf

MC74HC4316A

MOTOROLA High–Speed CMOS Logic Data

DL129 — Rev 6

–10

–20

–30

–40

–50

–100 1.0 2.0

FREQUENCY (kHz)

dBm

–60

–70

–80

–90

FUNDAMENTAL FREQUENCY

DEVICE

SOURCE

Figure 15. Plot, Harmonic Distortion

3.0

APPLICATION INFORMATION

The Enable and Control pins should be at VCC or GND

logic levels, VCC being recognized as logic high and GND

being recognized as a logic low. Unused analog inputs/out-

puts may be left floating (not connected). However, it is ad-

visable to tie unused analog inputs and outputs to VCC or

VEE through a low value resistor. This minimizes crosstalk

and feedthrough noise that may be picked up by the unused

I/O pins.

The maximum analog voltage swings are determined by

the supply voltages VCC and VEE. The positive peak analog

voltage should not exceed VCC. Similarly, the negative peak

analog voltage should not go below VEE. In the example

below, the difference between VCC and VEE is twelve volts.

Therefore, using the configuration in Figure 16, a maximum

analog signal of twelve volts peak–to–peak can be con-

trolled.

When voltage transients above VCC and/or below VEE are

anticipated on the analog channels, external diodes (Dx) are

recommended as shown in Figure 17. These diodes should

be small signal, fast turn–on types able to absorb the maxi-

mum anticipated current surges during clipping. An alternate

method would be to replace the Dx diodes with MO



sorbs

(Motorola high current surge protectors). MO



sorbs are fast

turn–on devices ideally suited for precise dc protection with

no inherent wear out mechanism.

ANALOG O/I

VCC = 6 V

ANALOG I/O

+ 6 V

–6 V

+ 6 V

–6 V

ENABLE CONTROL

INPUTS

(VCC OR GND)

VCC

Figure 16. Figure 17. Transient Suppressor Application

SELECTED

CONTROL

INPUT

SELECTED

CONTROL

INPUT

+ 6 V

VEE

–6 V

VCC

VEE ENABLE CONTROL

INPUTS

(VCC OR GND)

VEE

MC74HC4316A

High–Speed CMOS Logic Data

DL129 — Rev 6 9 MOTOROLA

VCC = 5 V

HC4316A

ENABLE

AND

CONTROL

INPUTS

TTL

ANALOG

SIGNALS

ANALOG

SIGNALS

HCT

BUFFER

R* = 2 TO 10 k

Ω

CHANNEL 4

CHANNEL 3

CHANNEL 2

CHANNEL 1

1 OF 4

SWITCHES

COMMON I/O

1 2 3 4

CONTROL INPUTS

INPUT OUTPUT

0.01

LF356 OR

EQUIVALENT

a. Using Pull–Up Resistors b. Using HCT Buffer

Figure 18. LSTTL/NMOS to HCMOS Interface

Figure 19. Switching a 0–to–12 V Signal Using a

Single Power Supply (GND ≠ 0 V)

Figure 20. 4–Input Multiplexer Figure 21. Sample/Hold Amplifier

–

1 OF 4

SWITCHES

+5 V

HC4016A

CONTROL

INPUTS

LSTTL/

NMOS

ANALOG

SIGNALS ANALOG

SIGNALS

1 OF 4

SWITCHES

1 OF 4

SWITCHES

1 OF 4

SWITCHES

R*R*R*

R* VEE = 0

TO –6 V

VEE = 0

TO –6 V

12 V

POWER

SUPPLY

R1 = R2

VCC = 12 V

VEE = 0 V

GND = 6 V

12 VPP

ANALOG

INPUT

SIGNAL

VCC

VEE

1 OF 4

SWITCHES

ANALOG

OUTPUT

SIGNAL 12 V

R1 = R2

R3 = R4

MC74HC4316A

MOTOROLA High–Speed CMOS Logic Data

DL129 — Rev 6

OUTLINE DIMENSIONS

N SUFFIX

PLASTIC PACKAGE

CASE 648–08

ISSUE R

MIN MINMAX MAX

INCHES MILLIMETERS

DIM

18.80

6.35

3.69

0.39

1.02

0.21

2.80

7.50

0.51

19.55

6.85

4.44

0.53

1.77

0.38

3.30

7.74

1.01

0.740

0.250

0.145

0.015

0.040

0.008

0.110

0.295

0.020

0.770

0.270

0.175

0.021

0.070

0.015

0.130

0.305

0.040

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. DIMENSION L TO CENTER OF LEADS WHEN

FORMED PARALLEL.

4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.

5. ROUNDED CORNERS OPTIONAL.

2.54 BSC

1.27 BSC

0.100 BSC

0.050 BSC

–A

–

1 8

916

HGD 16 PL

–T

–

SEATING

PLANE

KJM

T A0.25 (0.010) M M

0.25 (0.010) T B A

MS S

MIN MINMAX MAX

MILLIMETERS INCHES

DIM

9.80

3.80

1.35

0.35

0.40

0.19

0.10

5.80

0.25

10.00

4.00

1.75

0.49

1.25

0.25

6.20

0.50

0.386

0.150

0.054

0.014

0.016

0.008

0.004

0.229

0.010

0.393

0.157

0.068

0.019

0.049

0.009

0.244

0.019

1.27 BSC 0.050 BSC

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS A AND B DO NOT INCLUDE

MOLD PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)

PER SIDE.

5. DIMENSION D DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE DAMBAR

PROTRUSION SHALL BE 0.127 (0.005) TOTAL

IN EXCESS OF THE D DIMENSION AT

MAXIMUM MATERIAL CONDITION.

916

–A

–

–B

–

D16 PL

–T

–

SEATING

PLANE

R X 45°

P 8 PL

0.25 (0.010) B

M M

D SUFFIX

PLASTIC SOIC PACKAGE

CASE 751B–05

ISSUE J

MC74HC4316A

High–Speed CMOS Logic Data

DL129 — Rev 6 11 MOTOROLA

OUTLINE DIMENSIONS

DT SUFFIX

TSSOP PACKAGE

CASE 948G–01

ISSUE O

DIM MIN MAX MIN MAX

INCHESMILLIMETERS

A4.90 5.10 0.193 0.200

B4.30 4.50 0.169 0.177

C––– 1.20 ––– 0.047

D0.05 0.15 0.002 0.006

F0.50 0.75 0.020 0.030

G0.65 BSC 0.026 BSC

H0.50 0.60 0.020 0.024

J0.09 0.20 0.004 0.008

J1 0.09 0.16 0.004 0.006

K0.19 0.30 0.007 0.012

K1 0.19 0.25 0.007 0.010

L6.40 BSC 0.252 BSC

M0 8 0 8

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION A DOES NOT INCLUDE MOLD FLASH,

PROTRUSIONS OR GATE BURRS. MOLD FLASH

OR GATE BURRS SHALL NOT EXCEED 0.15

(0.006) PER SIDE.

3. DIMENSION B DOES NOT INCLUDE INTERLEAD

FLASH OR PROTRUSION. INTERLEAD FLASH OR

PROTRUSION SHALL NOT EXCEED

0.25 (0.010) PER SIDE.

4. DIMENSION K DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE DAMBAR

PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN

EXCESS OF THE K DIMENSION AT MAXIMUM

MATERIAL CONDITION.

5. TERMINAL NUMBERS ARE SHOWN FOR

REFERENCE ONLY.

6. DIMENSION A AND B ARE TO BE DETERMINED

AT DATUM PLANE –W–.

_ _ _ _

U0.15 (0.006) T

2X L/2

0.10 (0.004) V S

L–U–

SEATING

PLANE

0.10 (0.004)

–T–

ÇÇÇ

SECTION N–N

DETAIL E

JJ1

ÉÉÉ

DETAIL E

–W–

0.25 (0.010)

PIN 1

IDENT.

U0.15 (0.006) T

–V–

14X REFK

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Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty , representation or guarantee regarding

the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit,

and specifically disclaims any and all liability , including without limitation consequential or incidental damages. “Typical” parameters can and do vary in different

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MC74HC4316A/D

*MC74HC4316A/D*

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