Single-Channel, 1024-Position, 1% R-Tolerance Digital Potentiometer AD5293 FEATURES FUNCTIONAL BLOCK DIAGRAM VDD Single-channel, 1024-position resolution 20 k, 50 k, and 100 k nominal resistance Calibrated 1% nominal resistor tolerance (resistor performance mode) Rheostat mode temperature coefficient: 35 ppm/C Voltage divider temperature coefficient: 5 ppm/C Single-supply operation: 9 V to 33 V Dual-supply operation: 9 V to 16.5 V SPI-compatible serial interface Wiper setting readback RESET POWER-ON RESET AD5293 VLOGIC 10 SCLK SYNC RDAC REGISTER SERIAL INTERFACE A W DIN B SDO APPLICATIONS VSS EXT_CAP GND 07675-001 RDY Mechanical potentiometer replacement Instrumentation: gain and offset adjustment Programmable voltage-to-current conversion Programmable filters, delays, and time constants Programmable power supply Low resolution DAC replacements Sensor calibration Figure 1. GENERAL DESCRIPTION The AD5293 is a single-channel, 1024-position digital potentiometer 1 with a <1% end-to-end resistor tolerance error. The AD5293 performs the same electronic adjustment function as a mechanical potentiometer with enhanced resolution, solid state reliability, and superior low temperature coefficient performance. This device is capable of operating at high voltages and supporting both dual-supply operation at 10.5 V to 15 V and single-supply operation at 21 V to 30 V. The AD5293 offers guaranteed industry-leading low resistor tolerance errors of 1% with a nominal temperature coefficient of 35 ppm/C. The low resistor tolerance feature simplifies openloop applications as well as precision calibration and tolerance matching applications. The AD5293 is available in a compact 14-lead TSSOP package. The part is guaranteed to operate over the extended industrial temperature range of -40C to +105C. 1 In this data sheet, the terms digital potentiometer and RDAC are used interchangeably. Rev. D Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2009-2011 Analog Devices, Inc. All rights reserved. AD5293 TABLE OF CONTENTS Features ...............................................................................................1 RDAC Register............................................................................ 18 Applications........................................................................................1 Write Protection ......................................................................... 18 Functional Block Diagram ...............................................................1 Basic Operation .......................................................................... 18 General Description ..........................................................................1 Shutdown Mode.......................................................................... 18 Revision History ................................................................................2 Reset ............................................................................................. 19 Specifications......................................................................................3 Resistor Performance Mode...................................................... 19 Electrical Characteristics--20 k Versions ...............................3 SDO Pin and Daisy-Chain Operation ..................................... 19 Resistor Performance Mode Code Range--20 k Versions ...4 RDAC Architecture .................................................................... 20 Electrical Characteristics--50 k and 100 k Versions..........5 Programming the Variable Resistor......................................... 20 Resistor Performance Mode Code Range--50 k and 100 k Versions...........................................................................................6 Programming the Potentiometer Divider ............................... 21 Interface Timing Specifications...................................................7 Terminal Voltage Operating Range.......................................... 21 Timing Diagrams...........................................................................8 Applications Information .............................................................. 22 Absolute Maximum Ratings.............................................................9 High Voltage DAC...................................................................... 22 Thermal Resistance .......................................................................9 Programmable Voltage Source with Boosted Output............ 22 ESD Caution...................................................................................9 High Accuracy DAC .................................................................. 22 Pin Configuration and Function Descriptions........................... 10 Variable Gain Instrumentation Amplifier............................... 22 Typical Performance Characteristics ........................................... 11 Audio Volume Control .............................................................. 23 Test Circuits..................................................................................... 17 Outline Dimensions ....................................................................... 24 Theory of Operation ...................................................................... 18 Ordering Guide........................................................................... 24 EXT_CAP Capacitor.................................................................. 21 Serial Data Interface................................................................... 18 Shift Register ............................................................................... 18 REVISION HISTORY 3/11--Rev. C to Rev. D Changes to Table 1, Endnote 2 ................................................................4 Changes to Table 3, Endnote 2........................................................ 6 9/10--Rev. B to Rev. C Added CPOL = 0, CPHA = 1 to Figure 3 and Figure 4 Captions.....8 Changes to SDO Pin and Daisy-Chain Operation Section....... 19 3/10--Rev. A to Rev. B Changes to Resistor Noise Density Conditions (Table 3) ........... 6 12/09--Rev. 0 to Rev. A Added 50 k and 100 k Specifications.........................Universal Changes to Features Section............................................................ 1 Changes to Table 1............................................................................ 3 Changes to Table 2............................................................................ 4 Added Table 3; Renumbered Sequentially .................................... 5 Added Table 4.................................................................................... 6 Changes to Table 5............................................................................ 7 Changes to Table 6 and Note 1, Table 7 ......................................... 9 Changes to Typical Performance Characteristics Section......... 11 Changes to Programming the Variable Resistor Section .......... 20 Changes to Programming the Potentiometer Divider Section ............................................................................... 21 Changes to Ordering Guide Section ............................................ 24 4/09--Revision 0: Initial Version Rev. D | Page 2 of 24 AD5293 SPECIFICATIONS ELECTRICAL CHARACTERISTICS--20 k VERSIONS VDD = 21 V to 33 V, VSS = 0 V; VDD = 10.5 V to 16.5 V, VSS = -10.5 V to -16.5 V; VLOGIC = 2.7 V to 5.5 V, VA = VDD, VB = VSS, -40C < TA < +105C, unless otherwise noted. Table 1. Parameter DC CHARACTERISTICS, RHEOSTAT MODE Resolution Resistor Differential Nonlinearity 2 Resistor Integral Nonlinearity2 Nominal Resistor Tolerance (R-Perf Mode) 3 Nominal Resistor Tolerance (Normal Mode) Resistance Temperature Coefficient 4 Wiper Resistance DC CHARACTERISTICS, POTENTIOMETER DIVIDER MODE Resolution Differential Nonlinearity 5 Integral Nonlinearity5 Voltage Divider Temperature Coefficient4 Full-Scale Error Zero-Scale Error RESISTOR TERMINALS Terminal Voltage Range 6 Capacitance A, Capacitance B4 Capacitance W4 Common-Mode Leakage Current DIGITAL INPUTS Input Logic High Input Logic Low Input Current Input Capacitance4 DIGITAL OUTPUTS (SDO and RDY) Output High Voltage Output Low Voltage Tristate Leakage Current Output Capacitance4 POWER SUPPLIES Single-Supply Power Range Dual-Supply Power Range Positive Supply Current Negative Supply Current Logic Supply Range Logic Supply Current Power Dissipation 7 Power Supply Rejection Ratio4 Symbol N R-DNL R-INL R-INL RAB/RAB Conditions Min RWB |VDD - VSS | = 26 V to 33 V |VDD - VSS | = 21 V to 26 V See Table 2 10 -1 -2 -3 -1 Typ 1 0.5 RAB/RAB 7 (RAB/RAB)/T x 106 RW 35 60 N DNL INL (VW/VW)/T x 106 Code = half scale VWFSE VWZSE Code = full scale Code = zero scale VA, VB, VW CA, CB CW ICM 10 -1 -1.5 VOH VOL RPULL_UP = 2.2 k to VLOGIC RPULL_UP = 2.2 k to VLOGIC % 100 0 8 LSB LSB VDD 85 V pF 65 pF -8 0 1 JEDEC compliant 2.0 V V A pF GND + 0.4 +1 V V A pF VLOGIC - 0.4 5 VSS = 0 V VDD/VSS = 16.5 V VDD/VSS = 16.5 V VLOGIC = 5 V; VIH = 5 V or VIL = GND VIH = 5 V or VIL = GND VDD/VSS = 15 V 10% Rev. D | Page 3 of 24 9 9 -2 2.7 0.1 -0.1 1 8 0.103 nA 0.8 1 5 COL ppm/C Bits LSB LSB ppm/C -1 VDD VDD/VSS IDD ISS VLOGIC ILOGIC PDISS PSSR +1 +2 +3 +1 Bits LSB LSB LSB % +1 +1.5 VSS VLOGIC = 2.7 V to 5.5 V VLOGIC = 2.7 V to 5.5 V VIN = 0 V or VLOGIC Unit 5 f = 1 MHz, measured to GND, code = half-scale f = 1 MHz, measured to GND, code = half-scale V A = VB = V W VIH VIL IIL CIL Max 33 16.5 2 5.5 10 110 V V A A V A W %/% AD5293 Parameter DYNAMIC CHARACTERISTICS4, 8 Bandwidth Total Harmonic Distortion VW Settling Time Resistor Noise Density Symbol Conditions BW THDW tS -3 dB VA = 1 V rms, VB = 0 V, f = 1 kHz, VA = 30 V, VB = 0 V, 0.5 LSB error band, initial code = zero scale Code = full scale, R-normal mode Code = full scale, R-perf mode Code = half scale, R-normal mode Code = half scale, R-perf mode RWB = 10 k, TA = 25C, 0 kHz to 200 kHz eN_WB Min Typ 1 Max Unit 520 -93 kHz dB 750 2.5 2.5 5 10 ns s s s nV/Hz 1 Typicals represent average readings at 25C; VDD = +15 V, VSS = -15 V, and VLOGIC = 5 V. Resistor position nonlinearity error. R-INL is the deviation from an ideal value measured between RWB at Code 0x00B to Code 0x3FF or between RWA at Code 0x3F3 to Code 0x000. R-DNL measures the relative step change from ideal between successive tap positions. The specification is guaranteed in resistor performance mode with a wiper current of 1 mA for VA < 12 V and 1.2 mA for VA 12 V. 3 The terms resistor performance mode and R-perf mode are used interchangeably. 4 Guaranteed by design; not subject to production test. 5 INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output DAC. VA = VDD and VB = 0 V. DNL specification limits of 1 LSB maximum are guaranteed monotonic operating conditions. 6 The A, B, and W resistor terminals have no limitations on polarity with respect to each other. Dual-supply operation enables ground-referenced bipolar signal adjustment. 7 PDISS is calculated from (IDD x VDD) + (ISS x VSS) + (ILOGIC x VLOGIC). 8 All dynamic characteristics use VDD = +15 V, VSS = -15 V, and VLOGIC = 5 V. 2 RESISTOR PERFORMANCE MODE CODE RANGE--20 k VERSIONS Table 2. Resistor Tolerance per Code 1% R-Tolerance 2% R-Tolerance 3% R-Tolerance |VDD - VSS| = 30 V to 33 V RWB RWA From 0x15E From 0x000 to 0x3FF to 0x2A1 From 0x8C From 0x000 to 0x3FF to 0x373 From 0x5A From 0x000 to 0x3FF to 0x3A5 RAB = 20 k |VDD - VSS| = 26 V to 30 V |VDD - VSS| = 22 V to 26 V RWB RWA RWB RWA From 0x1F4 From 0x000 From 0x1F4 From 0x000 to 0x3FF to 0x20B to 0x3FF to 0x20B From 0xB4 From 0x000 From 0xFA From 0x000 to 0x3FF to 0x34B to 0x3FF to 0x305 From 0x64 From 0x000 From 0x78 From 0x000 to 0x3FF to 0x39B to 0x3FF to 0x387 Rev. D | Page 4 of 24 |VDD - VSS| = 21 V to 22 V RWB RWA N/A N/A From 0xFA to 0x3FF From 0x78 to 0x3FF From 0x000 to 0x305 From 0x000 to 0x387 AD5293 ELECTRICAL CHARACTERISTICS--50 k AND 100 k VERSIONS VDD = 21 V to 33 V, VSS = 0 V; VDD = 10.5 V to 16.5 V, VSS = -10.5 V to -16.5 V; VLOGIC = 2.7 V to 5.5 V, VA = VDD, VB = VSS, -40C < TA < +105C, unless otherwise noted. Table 3. Parameter DC CHARACTERISTICS, RHEOSTAT MODE Resolution Resistor Differential Nonlinearity 2 Resistor Integral Nonlinearity2 Nominal Resistor Tolerance (R-Perf Mode) 3 Nominal Resistor Tolerance (Normal Mode) Resistance Temperature Coefficient 4 Wiper Resistance DC CHARACTERISTICS, POTENTIOMETER DIVIDER MODE Resolution Differential Nonlinearity 5 Integral Nonlinearity5 Voltage Divider Temperature Coefficient4 Full-Scale Error Zero-Scale Error RESISTOR TERMINALS Terminal Voltage Range 6 Capacitance A, Capacitance B4 Capacitance W4 Common-Mode Leakage Current DIGITAL INPUTS Input Logic High Input Logic Low Input Current Input Capacitance4 DIGITAL OUTPUTS (SDO and RDY) Output High Voltage Output Low Voltage Tristate Leakage Current Output Capacitance4 POWER SUPPLIES Single-Supply Power Range Dual-Supply Power Range Positive Supply Current Negative Supply Current Logic Supply Range Logic Supply Current Power Dissipation 7 Power Supply Rejection Ratio4 Symbol N R-DNL R-INL RAB/RAB Conditions RWB See Table 4 Min 10 -1 -2 -1 Typ 1 Max Unit 0.5 +1 +2 +1 Bits LSB LSB % RAB/RAB 20 (RAB/RAB)/T x 106 RW 35 60 N DNL INL (VW/VW)/T x 106 Code = half scale VWFSE VWZSE Code = full scale Code = zero scale VA, VB, VW CA, CB CW ICM 10 -1 -1.5 VOH VOL RPULL_UP = 2.2 k to VLOGIC RPULL_UP = 2.2 k to VLOGIC Bits LSB LSB ppm/C +1 8 LSB LSB VDD 85 V pF 65 pF -8 0 1 JEDEC compliant 2.0 VDD VDD/VSS IDD ISS VLOGIC ILOGIC PDISS PSSR V V A pF GND + 0.4 +1 V V A pF VLOGIC - 0.4 -1 5 VSS = 0 V VDD/VSS = 16.5 V VDD/VSS = 16.5 V VLOGIC = 5 V; VIH = 5 V or VIL = GND VIH = 5 V or VIL = GND VDD/VSS = 15 V 10% RAB = 50 k RAB = 100 k Rev. D | Page 5 of 24 9 9 -2 2.7 0.1 -0.1 1 8 0.039 0.021 nA 0.8 1 5 COL ppm/C +1 +1.5 VSS VLOGIC = 2.7 V to 5.5 V VLOGIC = 2.7 V to 5.5 V VIN = 0 V or VLOGIC 100 5 f = 1 MHz, measured to GND, code = half-scale f = 1 MHz, measured to GND, code = half-scale V A = VB = V W VIH VIL IIL CIL % 33 16.5 2 5.5 10 110 V V A A V A W %/% %/% AD5293 Parameter DYNAMIC CHARACTERISTICS4, 8 Bandwidth Total Harmonic Distortion VW Settling Time Symbol Conditions BW -3 dB RAB = 50 k RAB = 100 k VA = 1 V rms, VB = 0 V, f = 1 kHz RAB = 50 k RAB = 100 k VA = 30 V, VB = 0 V, 0.5 LSB error band, initial code = zero scale Code = full scale, R-normal mode Code = full scale, R-perf mode Code = half scale, R-normal mode, RAB = 50 k Code = half scale, R-normal mode, RAB = 100 k Code = half scale, R-perf mode, RAB = 50 k Code = half scale, R-perf mode, RAB = 100 k Code = half scale, TA = 25C, 0 kHz to 200 kHz, RAB = 50 k RAB = 100 k THDW tS Resistor Noise Density eN_WB Min Typ 1 Max Unit kHz 210 105 -101 -106 dB dB 750 2.5 7 ns s s 14 s 9 s 16 s 18 27 nV/Hz nV/Hz 1 Typicals represent average readings at 25C; VDD = +15 V, VSS = -15 V, and VLOGIC = 5 V. Resistor position nonlinearity error. R-INL is the deviation from an ideal value measured between RWB at Code 0x00B to Code 0x3FF or between RWA at Code 0x3F3 to Code 0x000. R-DNL measures the relative step change from ideal between successive tap positions. The specification is guaranteed in resistor performance mode with a wiper current of 1 mA for VA < 12 V and 1.2 mA for VA 12 V. 3 The terms resistor performance mode and R-perf mode are used interchangeably. 4 Guaranteed by design; not subject to production test. 5 INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output DAC. VA = VDD and VB = 0 V. DNL specification limits of 1 LSB maximum are guaranteed monotonic operating conditions. 6 The A, B, and W resistor terminals have no limitations on polarity with respect to each other. Dual-supply operation enables ground-referenced bipolar signal adjustment. 7 PDISS is calculated from (IDD x VDD) + (ISS x VSS) + (ILOGIC x VLOGIC). 8 All dynamic characteristics use VDD = +15 V, VSS = -15 V, and VLOGIC = 5 V. 2 RESISTOR PERFORMANCE MODE CODE RANGE--50 k AND 100 k VERSIONS Table 4. Resistor Tolerance per Code 1% R-Tolerance 2% R-Tolerance 3% R-Tolerance RAB = 50 k |VDD - VSS| = 26 V to 33 V |VDD - VSS| = 21 V to 26 V RWA RWB RWA RWB From 0x08C From 0x000 From 0x0B4 From 0x000 to 0x3FF to 0x35F to 0x3FF to 0x31E From 0X03C From 0x000 From 0x050 From 0x000 to 0x3FF to 0x3C3 to 0x3FF to 0x3AF From 0X028 From 0x000 From 0x032 From 0x000 to 0x3FF to 0x3D7 to 0x3FF to 0x3CD Rev. D | Page 6 of 24 RAB = 100 k |VDD - VSS| = 26 V to 33 V |VDD - VSS| = 21 V to 26 V RWB RWA RWB RWA From 0x04B From 0x000 From 0x064 From 0x000 to 0x3FF to 0x3B4 to 0x3FF to 0x39B From 0x028 From 0x000 From 0x028 From 0x000 to 0x3FF to 0x3D7 to 0x3FF to 0x3D7 From 0x019 From 0x000 From 0x019 From 0x000 to 0x3FF to 0x3E6 to 0x3FF to 0x3E6 AD5293 INTERFACE TIMING SPECIFICATIONS VDD = VSS = 15 V, VLOGIC = 2.7 V to 5.5 V, and -40C < TA < +105C. All specifications TMIN to TMAX, unless otherwise noted. Table 5. Parameter t1 2 t2 t3 t4 t5 t6 t7 t8 t9 t10 4 t114 t124 t124 t124 t134 t144 tRESET tPOWER-UP 5 Limit 1 20 10 10 10 5 5 1 400 3 14 1 40 2.4 410 1.5 450 450 20 2 Unit ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min ns max s max ns max ms max ns max ns max ns min ms max Test Conditions/Comments SCLK cycle time SCLK high time SCLK low time SYNC to SCLK falling edge setup time Data setup time Data hold time SCLK falling edge to SYNC rising edge Minimum SYNC high time SYNC rising edge to next SCLK fall ignored RDY rise to SYNC falling edge SYNC rise to RDY fall time RDY low time, RDAC register write command execute time (resistor performance mode) RDY low time, RDAC register write command execute time (normal mode) Software\hardware reset RDY low time, RDAC register read command execute time SCLK rising edge to SDO valid Minimum RESET pulse width (asynchronous) Power-on time to half scale 1 All input signals are specified with tR = tF = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. Maximum SCLK frequency = 50 MHz. Refer to t12 and t13 for RDAC register commands operations. 4 RPULL_UP = 2.2 k to VLOGIC with a capacitance load of 168 pF. 5 Typical power supply voltage slew-rate of 2 V/ms. 2 3 0 0 C3 C2 C1 C0 D9 D8 DB0 (LSB) D7 D6 D5 D4 DATA BITS CONTROL BITS Figure 2. Shift Register Contents Rev. D | Page 7 of 24 D3 D2 D1 D0 07675-002 DB9 (MSB) AD5293 TIMING DIAGRAMS t4 SCLK t2 t7 t1 t9 t3 t8 SYNC t5 t6 X X C3 C2 D7 D6 D2 D1 D0 SDO t11 t10 t12 RDY tRESET 07675-003 DIN RESET Figure 3. Write Timing Diagram, CPOL = 0, CPHA =1 SCLK t9 SYNC DIN X X C3 D0 D0 X X C3 D1 D0 t14 X t11 RDY X t13 Figure 4. Read Timing Diagram, CPOL = 0, CPHA =1 Rev. D | Page 8 of 24 C3 D1 D0 07675-004 SDO AD5293 ABSOLUTE MAXIMUM RATINGS TA = 25C, unless otherwise noted. Table 6. Parameter VDD to GND VSS to GND VLOGIC to GND VDD to VSS VA, VB, VW to GND Digital Input and Output Voltage to GND EXT_CAP Voltage to GND IA, IB, IW Continuous RAB = 20 k RAB = 50 k, 100 k Pulsed 1 Frequency > 10 kHz Frequency 10 kHz Operating Temperature Range Maximum Junction Temperature (TJ max) Storage Temperature Range Reflow Soldering Peak Temperature Time at Peak Temperature Package Power Dissipation Rating -0.3 V to +35 V +0.3 V to -25 V -0.3 V to +7 V 35 V VSS - 0.3 V, VDD + 0.3 V -0.3 V to VLOGIC +0.3 V -0.3 V to +7 V Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. THERMAL RESISTANCE JA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. 3 mA 2 mA Table 7. Thermal Resistance Package Type 14-Lead TSSOP MCC 2 /d 3 MCC2/d3 -40C to +105C 150C -65C to +150C 1 JA 931 JC 20 Unit C/W JEDEC 2S2P test board, still air (from 0 m/sec to 1 m/sec of air flow). ESD CAUTION 260C 20 sec to 40 sec (TJ max - TA)/JA 1 Maximum terminal current is bounded by the maximum current handling of the switches, maximum power dissipation of the package, and maximum applied voltage across any two of the A, B, and W terminals at a given resistance. 2 Maximum continuous current. 3 Pulse duty factor. Rev. D | Page 9 of 24 AD5293 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS RESET 1 14 RDY VSS 2 W 4 B 5 13 SDO AD5293 TOP VIEW Not to Scale 12 SYNC 11 SCLK 10 DIN VDD 6 9 GND EXT_CAP 7 8 VLOGIC 07675-005 A 3 Figure 5. Pin Configuration Table 8. Pin Function Descriptions Pin No. 1 Mnemonic RESET 2 VSS 3 4 5 6 7 8 9 10 A W B VDD EXT_CAP VLOGIC GND DIN 11 SCLK 12 SYNC 13 SDO 14 RDY Description Hardware Reset Pin. Sets the RDAC register to midscale. RESET is activated at the logic high transition. Tie RESET to VLOGIC if not used. Negative Supply. Connect to 0 V for single-supply applications. This pin should be decoupled with 0.1 F ceramic capacitors and 10 F capacitors. Terminal A of RDAC. VSS VA VDD. Wiper Terminal W of RDAC. VSS VW VDD. Terminal B of RDAC. VSS VB VDD. Positive Power Supply. This pin should be decoupled with 0.1 F ceramic capacitors and 10 F capacitors. Connect a 1 F capacitor to EXT_CAP. This capacitor must have a voltage rating of 7 V. Logic Power Supply, 2.7 V to 5.5 V. This pin should be decoupled with 0.1 F ceramic capacitors and 10 F capacitors. Ground Pin, Logic Ground Reference. Serial Data Input. This part has a 16-bit shift register. Data is clocked into the register on the falling edge of the serial clock input. Serial Clock Input. Data is clocked into the shift register on the falling edge of the serial clock input. Data can be transferred at rates up to 50 MHz. Falling Edge Synchronization Signal. This is the frame synchronization signal for the input data. When SYNC goes low, it enables the shift register, and data is transferred in on the falling edges of the following clocks. The selected register is updated on the rising edge of SYNC, following the 16th clock cycle. If SYNC is taken high before the 16th clock cycle, the rising edge of SYNC acts as an interrupt, and the write sequence is ignored by the DAC. Serial Data Output. This open-drain output requires an external pull-up resistor. SDO can be used to clock data from the serial register in daisy-chain mode or in readback mode. Ready Pin. This active-high, open-drain output identifies the completion of a write or read operation to or from the RDAC register. Rev. D | Page 10 of 24 AD5293 TYPICAL PERFORMANCE CHARACTERISTICS 1.0 0.8 0.6 0.4 0.2 0.2 0 -0.2 0 -0.2 -0.4 -0.4 -0.6 -0.6 256 384 512 640 768 896 1023 CODE (Decimal) -1.0 0.4 0.3 0.3 DNL (LSB) 0.4 0.2 0.1 640 768 896 1023 0.2 0.1 0 0 -0.1 -0.1 20k 50k 100k -0.2 -0.2 384 512 640 768 896 1023 CODE (Decimal) -0.3 07675-007 256 +105C +25C -40C 0 128 256 384 512 640 768 896 1023 CODE (Decimal) Figure 10. R-DNL in R-Perf Mode vs. Code vs. Nominal Resistance Figure 7. R-DNL in R-Perf Mode vs. Code vs. Temperature 1.0 1.0 512 TEMPERATURE = 2 5C 0.5 128 384 0.6 0.5 0 256 Figure 9. R-INL in R-Perf Mode vs. Code vs. Nominal Resistance RAB = 20k -0.3 128 CODE (Decimal) Figure 6. R-INL in R-Perf Mode vs. Code vs. Temperature 0.6 0 07675-211 128 07675-106 0 07675-215 -0.8 RAB = 20k -1.0 20k 50k 100k RAB = 20k 0.8 0.6 0.6 0.4 0.4 INL (LSB) 0.8 0.2 TEMPERATURE = 25C 0.2 0 0 -0.2 -0.2 -0.4 -0.4 0 128 256 384 512 640 768 896 1023 CODE (Decimal) 07675-010 -0.6 +105C +25C -40C Figure 8. R-INL in Normal Mode vs. Code vs. Temperature -0.6 0 128 256 384 512 640 768 896 1023 CODE (Decimal) Figure 11. R-INL in Normal Mode vs. Code vs. Nominal Resistance Rev. D | Page 11 of 24 07675-216 DNL (LSB) TEMPERATURE = 25C 0.6 0.4 -0.8 INL (LSB) 20k 50k 100k 0.8 INL (LSB) INL (LSB) 1.0 -40C +25C +105C AD5293 0.15 RAB = 20k 0.10 0.05 0.05 DNL (LSB) 0.10 -0.05 -0.05 -0.10 -0.15 -0.15 256 384 512 640 768 896 1023 CODE (Decimal) -0.20 0.2 INL (LSB) 0.5 0 -0.2 -1.0 -0.6 256 384 512 640 768 896 1023 CODE (Decimal) -0.8 768 896 1023 20k 50k 100k 0 128 256 384 512 640 768 896 1023 CODE (Decimal) Figure 13. INL in R-Perf Mode vs. Code vs. Temperature Figure 16. INL in R-Perf Mode vs. Code vs. Nominal Resistance 0.6 RAB = 20k TEMPERATURE = 25C 0.5 0.4 0.4 0.3 0.3 DNL (LSB) 0.5 0.2 0.1 0.2 0.1 0 0 -0.1 -40C -0.2 0 128 256 +105C +25C 384 512 640 768 20k 50k 100k -0.2 896 CODE (Decimal) 1023 -0.3 0 128 256 384 512 640 768 896 CODE (Decimal) Figure 14. DNL in R-Perf Mode vs. Code vs. Temperature Figure 17. DNL in R-Perf Mode vs. Code vs. Nominal Resistance Rev. D | Page 12 of 24 1023 07675-203 -0.1 07675-015 DNL (LSB) 640 TEMPERATURE = 25C +105C +25C -40C 0.6 512 0 -0.5 07675-014 INL (LSB) 0.6 128 384 0.8 1.0 0 256 Figure 15. R-DNL in Normal Mode vs. Code vs. Nominal Resistance RAB = 20k -1.5 128 CODE (Decimal) Figure 12. R-DNL in Normal Mode vs. Code vs. Temperature 1.5 0 07675-207 128 +105C +25C -40C 0 TEMPERATURE = 25C 0 -0.10 -0.20 20k 50k 100k 07675-213 0 07675-011 DNL (LSB) 0.15 AD5293 0.6 0.4 0.4 0.2 0.2 0 -0.2 -0.4 -0.4 -0.6 -0.6 128 256 384 512 640 768 896 1023 CODE (Decimal) -0.8 07675-018 0 384 512 640 768 896 1023 20k 50k 100k 0.04 0 -0.04 -0.10 -0.08 -0.15 -0.12 RAB = 20k -0.20 128 256 384 512 640 768 896 1023 CODE (Decimal) 0 300 250 200 150 IDD 50 512 640 768 896 1023 VDD = 15V 0.18 ILOGIC 100 384 0.20 SUPPLY CURRENT I LOGIC (mA) 350 256 Figure 22. DNL in Normal Mode vs. Code vs. Temperature VDD/VSS = 15V VLOGIC = +5V 400 128 CODE (Decimal) Figure 19. DNL in Normal Mode vs. Code vs. Temperature 450 TEMPERATURE = 25C -0.16 0 0.16 0.14 0.12 0.1 0.08 0.06 0.04 0.02 10 20 30 40 50 60 70 80 90 100 TEMPERATURE (C) 07675-022 -50 -40 -30 -20 -10 0 ISS Figure 20. Supply Current vs. Temperature 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 DIGITAL INPUT VOLTAGE (V) 4.0 4.5 Figure 23. Supply Current, ILOGIC, vs. Digital Input Voltage. Rev. D | Page 13 of 24 5.0 07675-057 0 07675-205 DNL (LSB) -0.05 07675-019 DNL (LSB) 256 0.08 0 SUPPLY CURRENT (nA) 128 Figure 21. DNL in Normal Mode vs. Code vs. Temperature -40C +25C +105C 0.05 0 CODE (Decimal) Figure 18. INL in Normal Mode vs. Code vs. Temperature 0.10 TEMPERATURE = 25C 0 -0.2 -0.8 20k 50k 100k 0.6 INL (LSB) INL (LSB) 0.8 -40C +25C +105C RAB = 20k 07675-209 0.8 AD5293 700 20k 50k 100k 500 400 300 200 100 0 0 256 512 CODE (Decimal) 768 1023 500 400 300 200 100 0 0 Figure 24. Rheostat Mode Tempco RWB/T vs. Code 512 CODE (Decimal) 768 1023 0 -5 0x200 -10 0x100 0x200 -10 0x100 0x080 -20 0x040 GAIN (dB) 0x080 -20 0x040 -25 0x020 -30 -30 0x010 -40 0x008 0x004 0x010 -35 -50 0x008 -40 -50 10 0x001 100 1k 10k 100k 1M FREQUENCY (Hz) -70 10 07675-025 0x002 100 1k 10k 100k 1M FREQUENCY (Hz) Figure 28. 100 k Gain vs. Frequency vs. Code Figure 25. 20 k Gain vs. Frequency vs. Code 0 0 0x200 -10 -10 0x100 0x080 -20 0x002 -60 0x001 0x004 -45 0x020 07675-201 -15 100k 20k 50k -20 PSRR (dB) 0x040 0x020 -30 0x010 -30 -40 0x008 -50 0x004 -50 -60 0x002 0x001 -60 10 100 1k 10k 100k FREQUENCY (Hz) 1M -70 100 1k 10k 100k 1M FREQUENCY (Hz) Figure 29. Power Supply Rejection Ratio (PSRR) vs. Frequency Figure 26. 50 k Gain vs. Frequency vs. Code Rev. D | Page 14 of 24 07675-026 -40 07674-200 GAIN (dB) 256 Figure 27. Potentiometer Mode Tempco RWB/T vs. Code 0 GAIN (dB) VDD = 30V VSS= 0V 20k 50k 100k 600 07675-024 600 POTENTIOMETER MODE TEMPCO (ppm/C) VDD = 30V, VSS= 0V 07675-023 RHEOSTAT MODE TEMPCO (ppm/C) 700 AD5293 0 -15 -30 -40 -45 -60 -75 -60 -80 -100 -90 100k -140 0.001 FREQUENCY (Hz) 800,000 8 50k - 150pF 50k - 250pF 100k - 0pF 100k - 75pF 100k - 150pF 100k - 250pF 600,000 500,000 400,000 300,000 200,000 6 5 4 20k 3 50k 2 100k 1 8 16 32 64 CODE (Decimal) 128 256 512 07675-222 100,000 0 0 0 Figure 31. Maximum Bandwidth vs. Code vs. Net Capacitance 35 15 10 SYNC 15 14 13 12 11 9 8 0 -8 -16 -24 07675-058 TIME (s) 10 8 7 6 5 4 3 2 1 0 -1 -5 -2 20k 50k 100k 20k 50k 100k VWB, CODE: HALF-SCALE, NORMAL MODE VWB, CODE: HALF-SCALE, R-PERF MODE 1023 16 VOLTAGE (V) VOLTAGE (V) 24 VWB, CODE: FULL SCALE, R-PERF MODE 0 768 VDD/VSS = 15V VA = VDD VB = VSS CODE = HALF CODE 32 VDD/VSS = 30V/0V VLOGIC = 5V VA = VDD VB = VSS 5 512 CODE (Decimal) 40 30 20 256 Figure 34. Theoretical Maximum Current vs. Code VWB, CODE: FULL SCALE, NORMAL MODE 25 10 VDD/VSS = 30V/0V VA = VDD VB = VSS 7 700,000 0 1 Figure 33. Total Harmonic Distortion + Noise (THD + N) vs. Amplitud THEORETICAL IWB_MAX (mA) 20k - 0pF 20k - 75pF 20k - 150pF 20k - 250pF 50k - 0pF 50k - 75pF 900,000 0.1 AMPLITUDE (V rms) Figure 30. Total Harmonic Distortion + Noise (THD + N) vs. Frequency 1,000,000 0.01 07675-029 10k Figure 32. Large Signal Settling Time, Code from Zero Scale to Full Scale Rev. D | Page 15 of 24 -32 -40 -0.5 0 5 10 15 20 25 TIME (s) 30 Figure 35. Digital Feedthrough 35 40 45 07675-221 1k 07675-027 -120 100 07675-220 -120 -105 BANDWIDTH (Hz) VDD/VSS = 15V, CODE = HALF SCALE fIN = 1kHz NOISE BW = 22kHz 20k 50k 100k -20 THD + N (dB) THD + N (dB) 0 VDD/VSS = 15V CODE = HALF SCALE VIN = 1V rms Noise BW = 22kHz 20k 50k 100k AD5293 80 1.2 VDD/VSS = 15V VLOGIC = +5V VA = VDD VB = VSS 0.8 20k 50k 100k 0.6 0.4 0.2 0 -0.2 -0.4 50k 100k 60 50 40 30 20 0 2 4 6 8 10 12 14 16 TIME (s) 0 21 250 VDD/VSS = 15V 20k 50k 100k 200 150 100 10 20 30 40 50 60 70 80 90 100 TEMPERATURE (C) 07675-056 50 0 -40 -30 -20 -10 0 30 VOLTAGE VDD/VSS Figure 38. Code Range > 1% R-Tolerance Error vs. Voltage Figure 36. Maximum Transition Glitch 300 26 Figure 37. Code Range > 1% R-Tolerance Error vs. Temperature Rev. D | Page 16 of 24 33 07675-219 -2 07675-035 -0.8 VA = VDD VB = VSS TEMPERATURE = 25C 20k 10 -0.6 NUMBER OF CODES (AD5293) VOLTAGE (V) NUMBER OF CODES (AD5293) 1.0 70 AD5293 TEST CIRCUITS Figure 39 to Figure 44 define the test conditions used in the Specifications section. NC VA VDD B A V+ ~ VMS W B 07675-030 Figure 39. Resistor Position Nonlinearity Error (Rheostat Operation: R-INL, R-DNL) PSS (%/%) = VMS Figure 42. Power Supply Sensitivity (PSS, PSRR) +15V A DUT V+ = VDD 1LSB = V+/2N VIN W B W DUT VMS 2.5V Figure 40. Potentiometer Divider Nonlinearity Error (INL, DNL) +15V RWB = B + IWB A = NC - RW = 2 0.1V VSS TO VDD -15V -15V GND GND 0.1V IWB RWB VDD DUT A VSS GND B ICM W +15V -15V GND NC 07675-032 CODE = 0x00 W VOUT Figure 43. Gain vs. Frequency NC DUT OP42 B OFFSET GND 07675-031 A V+ VMS% VDD% 07675-036 NC = NO CONNECT V+ = VDD 10% VMS PSRR (dB) = 20 log V DD 07675-033 IW +15V Figure 41. Wiper Resistance GND NC = NO CONNECT -15V Figure 44. Common-Mode Leakage Current Rev. D | Page 17 of 24 07675-037 DUT A W AD5293 THEORY OF OPERATION The AD5293 digital potentiometer is designed to operate as a true variable resistor for analog signals that remain within the terminal voltage range of VSS < VTERM < VDD. The patented 1% resistor tolerance feature helps to minimize the total RDAC resistance error, which reduces the overall system error by offering better absolute matching and improved open-loop performance. The digital potentiometer wiper position is determined by the RDAC register contents. The RDAC register acts as a scratchpad register, allowing as many value changes as necessary to place the potentiometer wiper in the correct position. The RDAC register can be programmed with any position setting via the standard serial peripheral interface (SPI) by loading the 16-bit data-word. SERIAL DATA INTERFACE WRITE PROTECTION On power-up, the serial data input register write command for the RDAC register is disabled. The RDAC write protect bit, C1 of the control register (see Table 12 and Table 13), is set to 0 by default. This disables any change of the RDAC register content, regardless of the software commands, except that the RDAC register can be refreshed to midscale using the software reset command (Command 3, see Table 11) or through hardware, using the RESET pin. To enable programming of the variable resistor wiper position (programming the RDAC register), the write protect bit, C1 of the control register, must first be programmed. This is accomplished by loading the serial data input register with Command 4 (see Table 11). BASIC OPERATION The AD5293 contains a serial interface (SYNC, SCLK, DIN, and SDO) that is compatible with SPI standards, as well as most DSPs. The device allows data to be written to every register via the SPI. SHIFT REGISTER The AD5293 shift register is 16 bits wide (see Figure 2). The 16-bit data-word consists of two unused bits, which are set to 0, followed by four control bits and 10 RDAC data bits. Data is loaded MSB first (Bit 15). The four control bits determine the function of the software command (see Table 11). Figure 3 shows a timing diagram of a typical write sequence. The write sequence begins by bringing the SYNC line low. The SYNC pin must be held low until the complete data-word is loaded from the DIN pin. When SYNC returns high, the serial data-word is decoded according to the instructions in Table 11. The command bits (Cx) control the operation of the digital potentiometer. The data bits (Dx) are the values that are loaded into the decoded register. The AD5293 has an internal counter that counts a multiple of 16 bits (per frame) for proper operation. For example, the AD5293 works with a 32-bit word, but it cannot work properly with a 31- or 33-bit word. The AD5293 does not require a continuous SCLK, when SYNC is high, and all interface pins should be operated close to the supply rails to minimize power consumption in the digital input buffers. The basic mode of setting the variable resistor wiper position (programming the RDAC register) is accomplished by loading the serial data input register with Command 1 (see Table 11) and the desired wiper position data. The RDY pin can be used to monitor the completion of this RDAC register write command. Command 2 can be used to read back the contents of the RDAC register (see Table 11). After issuing the readback command, the RDY pin can be monitored to indicate when the data is available to be read out on SDO in the next SPI operation. Instead of monitoring the RDY pin, a minimum delay can be implemented when executing a write or read command (see Table 5). Table 9 provides an example listing of a sequence of serial data input (DIN) words with the serial data output appearing at the SDO pin in hexadecimal format for an RDAC write and read. Table 9. RDAC Register Write and Read DIN 0x1802 0x0500 SDO 0xXXXX1 0x1802 0x0800 0x0000 0x0500 0x0100 1 RDAC REGISTER The RDAC register directly controls the position of the digital potentiometer wiper. For example, when the RDAC register is loaded with all zeros, the wiper is connected to Terminal B of the variable resistor. The RDAC register is a standard logic register; there is no restriction on the number of changes allowed. The RDY pin can be used to monitor the completion of a write to or read from the RDAC register. The AD5293 presets to midscale on power-up. Action Enable update of wiper position. Write 0x100 to the RDAC register. Wiper moves to 1/4 full-scale position. Prepare data read from RDAC register. NOP (Instruction 0) sends a 16-bit word out of SDO, where the last 10 bits contain the contents of the RDAC register. X = unknown. SHUTDOWN MODE The AD5293 can be placed in shutdown mode by executing the software shutdown command (see Command 6 in Table 11), and setting the LSB to 1. This feature places the RDAC in a special state in which Terminal A is open-circuited and Wiper W is connected to Terminal B. The contents of the RDAC register are unchanged by entering shutdown mode. However, all commands listed in Table 11 are supported while in shutdown mode. Rev. D | Page 18 of 24 AD5293 sequence of the serial data input (DIN). Daisy chaining minimizes the number of port pins required from the controlling IC. As shown in Figure 45, users need to tie the SDO pin of one package to the DIN pin of the next package. Users may need to increase the clock period, because the pull-up resistor and the capacitive loading at the SDO-to-DIN interface may require additional time delay between subsequent devices. RESET A low-to-high transition of the hardware RESET pin loads the RDAC register with midscale. The AD5293 can also be reset through software by executing Command 3 (see Table 11). The control register is restored with default bits (see Table 13). RESISTOR PERFORMANCE MODE This mode activates a new, patented 1% end-to-end resistor tolerance that ensures a 1% resistor tolerance on each code, that is, code = half scale, RWB =10 k 100 . See Table 2 and Table 4 to verify which codes achieve 1% resistor tolerance. The resistor performance mode is activated by programming Bit C2 of the control register (see Table 12 and Table 13). The typical settling time is shown in Figure 32. When two AD5293s are daisy-chained, 32 bits of data are required. The first 16 bits go to U2, and the second 16 bits go to U1. The SYNC pin should be held low until all 32 bits are clocked into their respective serial registers. The SYNC pin is then pulled high to complete the operation. Keep the SYNC pin low until all 32 bits are clocked into their respective serial registers. The SYNC pin is then pulled high to complete the operation. SDO PIN AND DAISY-CHAIN OPERATION The serial data output pin (SDO) serves two purposes: it can be used to read the contents of the wiper setting and control register using Command 2, and Command 5, respectively (see Table 11) or the SDO pin can be used in daisy-chain mode. Data is clocked out of SDO on the rising edge of SCLK. The SDO pin contains an open-drain N-channel FET that requires a pull-up resistor if this pin is used. To place the pin in high impedance and minimize the power dissipation when the pin is used, the 0x8001 data word followed by Command 0 should be sent to the part. Table 10 provides a sample listing for the VLOGIC AD5293 MOSI MICROCONTROLLER SCLK SS DIN AD5293 DIN SDO SCLK U2 SYNC SDO SCLK 07675-039 SYNC U1 RP 2.2k Figure 45. Daisy-Chain Configuration Using SDO Table 10. Minimize Power Dissipation at the SDO Pin SDO1 0xXXXX 0xXXXX High impedance DIN 0xXXXX 0x8001 0x0000 1 Action Last user command sent to the digipot Prepares the SDO pin to be placed in high impedance mode The SDO pin is placed in high impedance X = don't care. Table 11. Command Operation Truth Table Command 0 1 Command Bits[B13:B10] C3 C2 C1 C0 0 0 0 0 0 0 0 1 Data Bits[B9:B0]1 D9 D8 D7 D6 X X X X D9 D8 D7 D6 D5 X D5 D4 X D4 D3 X D3 D2 X D2 D1 X D1 D0 X D0 2 0 0 1 0 X X X X X X X X X X 3 4 0 0 1 1 0 1 0 0 X X X X X X X X X X X X X X X D2 X D1 X X 5 0 1 1 1 X X X X X X X X X X 6 1 0 0 0 X X X X X X X X X D0 1 Operation NOP command. Do nothing. Write contents of serial register data to RDAC. Read RDAC wiper setting from SDO output in the next frame. Reset. Refresh RDAC with midscale code. Write contents of serial register data to control register. Read control register from SDO output in the next frame. Software power-down. D0 = 0 (normal mode). D0 = 1 (device placed in shutdown mode). X = don't care. Table 12. Control Register Bit Map D9 X1 1 D8 X1 D7 X1 D6 X1 D5 X1 D4 X1 X = don't care. Rev. D | Page 19 of 24 D3 X1 D2 C2 D1 C1 D0 X1 AD5293 Table 13. Control Register Function Register Name Control Bit Name C2 Description Calibration enable. 0 = resistor performance mode (default). 1 = normal mode. RDAC register write protect. 0 = locks the wiper position through the digital interface (default). 1 = allows update of wiper position through digital interface. C1 RDAC ARCHITECTURE To achieve optimum performance, Analog Devices, Inc., has patented the RDAC segmentation architecture for all the digital potentiometers. In particular, the AD5293 employs a 3-stage segmentation approach, as shown in Figure 46. The AD5293 wiper switch is designed with transmission gate CMOS topology and with the gate voltage derived from VDD. A The digitally programmed output resistance between the W terminal and the A terminal, RWA, and the W terminal and B terminal, RWB, is calibrated to give a maximum of 1% absolute resistance error over both the full supply and temperature ranges. As a result, the general equation for determining the digitally programmed output resistance between the W terminal and B terminal is D (1) RWB (D ) = x R AB 1024 RL RM RL SW RM RW W where: D is the decimal equivalent of the binary code loaded in the 10-bit RDAC register. RAB is the end-to-end resistance. RW 10-BIT ADDRESS DECODER The nominal resistance between Terminal A and Terminal B, RAB, is available in 20 k, 50 k, and 100 k and has 1024 tap points that are accessed by the wiper terminal. The 10-bit data in the RDAC latch is decoded to select one of the 1024 possible wiper settings. The AD5293 contains an internal 1% resistor tolerance calibration feature that can be enabled or disabled, enabled by default by programming Bit C2 of the control register (see Table 12 and Table 13). RM RL RM RL 07675-040 B Similar to the mechanical potentiometer, the resistance of the RDAC between the W terminal and the A terminal also produces a digitally controlled complementary resistance, RWA. RWA is also calibrated to give a maximum of 1% absolute resistance error. RWA starts at the maximum resistance value and decreases as the data loaded into the latch increases. The general equation for this operation is Figure 46. Simplified RDAC Circuit RWA (D) = PROGRAMMING THE VARIABLE RESISTOR Rheostat Operation--1% Resistor Tolerance The AD5293 operates in rheostat mode when only two terminals are used as a variable resistor. The unused terminal can be left floating or it can be tied to the W terminal, as shown in Figure 47. A W B A W B W B Figure 47. Rheostat Mode Configuration 07675-041 A 1024 - D x R AB 1024 (2) where: D is the decimal equivalent of the binary code loaded in the 10-bit RDAC register. RAB is the end-to-end resistance. In the zero-scale condition, a finite total wiper resistance of 120 is present. Regardless of the setting in which the part is operating, care should be taken to limit the current between the A terminal to B terminal, the W terminal to the A terminal, and the W terminal to the B terminal to the maximum continuous current of 3 mA or to the pulse current specified in Table 6. Otherwise, degradation, or possible destruction of the internal switch contact, can occur. Rev. D | Page 20 of 24 AD5293 PROGRAMMING THE POTENTIOMETER DIVIDER TERMINAL VOLTAGE OPERATING RANGE Voltage Output Operation The positive VDD and negative VSS power supplies of the AD5293 define the boundary conditions for proper 3-terminal, digital potentiometer operation. Supply signals present on the A, B, and W terminals that exceed VDD or VSS are clamped by the internal forward-biased diodes (see Figure 50). The digital potentiometer easily generates a voltage divider at wiper-to-B terminal and wiper-to-A terminal that is proportional to the input voltage at A to B, as shown in Figure 48. Unlike the polarity of VDD to GND, which must be positive, voltage across A to B, W to A, and W to B can be at either polarity. A A VOUT 07675-042 W B W B Figure 48. Potentiometer Mode Configuration If ignoring the effect of the wiper resistance for simplicity, connecting the A terminal to 30 V and the B terminal to ground produces an output voltage at the Wiper W to Terminal B that ranges from 0 V to 30 V - 1 LSB. Each LSB of voltage is equal to the voltage applied across the A terminal and B terminal, divided by the 1024 positions of the potentiometer divider. The general equation defining the output voltage at VW, with respect to ground for any valid input voltage applied to Terminal A and Terminal B, is VW (D) = 1024 - D D xVA + xVB 1024 1024 (3) To optimize the wiper position update rate when in voltage divider mode, it is recommended that the internal 1% resistor tolerance calibration feature be disabled by programming Bit C2 of the control register (see Table 11). Operation of the digital potentiometer in the divider mode results in a more accurate operation over temperature. Unlike rheostat mode, the output voltage is dependent mainly on the ratio of the internal resistors, RWA and RWB, and not on the absolute values. Therefore, the temperature drift reduces to 5 ppm/C. EXT_CAP CAPACITOR A 1 F capacitor to GND must be connected to the EXT_CAP pin (see Figure 49) on power-up and throughout the operation of the AD5293. This capacitor must have a voltage rating of 7 V. VSS Figure 50. Maximum Terminal Voltages Set by VDD and VSS The ground pin of the AD5293 is primarily used as a digital ground reference. To minimize the digital ground bounce, the AD5293 ground pin should be joined remotely to common ground. The digital input control signals to the AD5293 must be referenced to the device ground pin (GND) to satisfy the logic level defined in the Specifications section. Power-Up Sequence Because there are diodes to limit the voltage compliance at the A, B, and W terminals (see Figure 50), it is important to power VDD and VSS first, before applying any voltage to the A, B, and W terminals. Otherwise, the diode is forward-biased such that VDD and VSS are powered up unintentionally. The ideal power-up sequence is GND, VSS, VLOGIC, VDD, the digital inputs, and then VA, VB, and VW. The order of powering up VA, VB, VW, and the digital inputs is not important, as long as they are powered after VDD, VSS, and VLOGIC. Regardless of the power-up sequence and the ramp rates of the power supplies, the power-on preset activates after VLOGIC is powered, restoring midscale to the RDAC register. AD5293 C1 1F 07675-044 VIN VDD EXT_CAP 07675-043 GND Figure 49. Hardware Setup for the EXT_CAP Pin Rev. D | Page 21 of 24 AD5293 APPLICATIONS INFORMATION HIGH VOLTAGE DAC HIGH ACCURACY DAC The AD5293 can be configured as a high voltage DAC, with an output voltage as high as 33 V. The circuit is shown in Figure 51. The output is It is possible to configure the AD5293 as a high accuracy DAC by optimizing the resolution of the device over a specific reduced voltage range. This is achieved by placing external resistors on either side of the RDAC, as shown in Figure 53. The improved 1% resistor tolerance specification greatly reduces error associated with matching to discrete resistors. D x 1.2 V x 1024 R2 1 + R 1 (4) where D is the decimal code from 0 to 1023. VDD U2 U1 AD5293 AD8512 AD5293 U1B 20k V- B R1 R2 20k VOUT AD8512 B 07675-153 VARIABLE GAIN INSTRUMENTATION AMPLIFIER For applications that require high current adjustments, such as a laser diode or turnable laser, a boosted voltage source can be considered (see Figure 52). U3 2N7002 VIN VOUT AD5293 RBIAS CC U2 OP184 SIGNAL The AD8221 in conjunction with the AD5293 and the ADG1207, as shown in Figure 54, make an excellent instrumentation amplifier for use in data acquisition systems. The data acquisition system is low distortion and low noise enable it to condition signals in front of a variety of ADCs. ADG1207 LD VDD +VIN1 IL AD5293 +VIN4 -VIN1 07675-155 U1 B VOUT Figure 53. Optimizing Resolution PROGRAMMABLE VOLTAGE SOURCE WITH BOOSTED OUTPUT W V+ OP1177 R3 Figure 51. High Voltage DAC A U2 1% V- R2 R1 VDD AD8221 -VIN4 Figure 52. Programmable Boosted Voltage Source VSS In this circuit, the inverting input of the op amp forces VOUT to be equal to the wiper voltage set by the digital potentiometer. The load current is then delivered by the supply via the N-channel FET (U3). The N-channel FET power handling must be adequate to dissipate (VIN - VOUT) x IL power. This circuit can source a maximum of 100 mA with a 33 V supply. VOUT 07675-156 U1A V+ D1 (5) R1 + ((1024 - D )1024) x RAB + R3 VDD RBIAS ADR512 R3 + (D 1024 x RAB ) xV DD VOUT (D) = VDD 07675-154 VOUT (D) = Figure 54. Data Acquisition System The gain can be calculated by using Equation 6, as follows: Rev. D | Page 22 of 24 G(D) = 1 + 49.4 k (D 1024) x R AB (6) AD5293 The input is ac-coupled by C1 and attenuated down before feeding into the window comparator formed by U2, U3, and U4B. U6 is used to establish the signal as zero reference. The upper limit of the comparator is set above its offset and, therefore, the output pulses high whenever the input falls between 2.502 V and 2.497 V (or 0.005 V window) in this example. This output is AND'ed with the chip select signal such that the AD5293 updates whenever the signal crosses the window. To avoid a constant update of the device, the chip select signal should be programmed as two pulses, rather than as one. AUDIO VOLUME CONTROL The excellent THD performance and high voltage capability of the AD5293 make it ideal for digital volume control. The AD5293 is used as an audio attenuator; it can be connected directly to a gain amplifier. A large step change in the volume level at any arbitrary time can lead to an abrupt discontinuity of the audio signal, causing an audible zipper noise. To prevent this, a zero-crossing window detector can be inserted to the CS line to delay the device update until the audio signal crosses the window. Because the input signal can operate on top of any dc level, rather than absolute 0 V level, zero crossing in this case means the signal is ac-coupled, and the dc offset level is the signal zero reference point. In Figure 55, the lower trace shows that the volume level changes from a quarter-scale to full-scale when a signal change occurs near the zero-crossing window. The configuration to reduce zipper noise is shown in Figure 56, and the results of using this configuration are shown in Figure 55. 1 2 07675-158 CHANNEL 1 FREQ = 20.25kHz 1.03V p-p Figure 55. Zipper Noise Detector C1 VIN 1F 5V R1 100k R2 200 R4 90k C3 0.1F U2 VCC ADCMP371 GND U6 V+ AD8541 V- U3 VCC ADCMP371 GND R3 100k VDD AD5293 A -15V 4 7408 5 6 1 +15V VSS U4A 7408 2 20k SYNC SCLK SCLK SDIN SDIN SYNC W U5 V+ VOUT V- B -15V GND 07675-157 5V U1 C2 0.1F U4B +5V R5 10k +15V +5V Figure 56. Audio Volume Control with Zipper Noise Reduction. Rev. D | Page 23 of 24 AD5293 OUTLINE DIMENSIONS 5.10 5.00 4.90 14 8 4.50 4.40 4.30 6.40 BSC 1 7 PIN 1 0.65 BSC 1.20 MAX 0.15 0.05 COPLANARITY 0.10 0.30 0.19 0.20 0.09 SEATING PLANE 0.75 0.60 0.45 8 0 061908-A 1.05 1.00 0.80 COMPLIANT TO JEDEC STANDARDS MO-153-AB-1 Figure 57. 14-Lead Thin Shrink Small Outline Package [TSSOP] (RU-14) Dimensions shown in millimeters ORDERING GUIDE Model 1 AD5293BRUZ-20 AD5293BRUZ-20-RL7 AD5293BRUZ-50 AD5293BRUZ-50-RL7 AD5293BRUZ-100 AD5293BRUZ-100-RL7 1 RAB (k) 20 20 50 50 100 100 Resolution 1,024 1,024 1,024 1,024 1,024 1,024 Temperature Range -40C to +105C -40C to +105C -40C to +105C -40C to +105C -40C to +105C -40C to +105C Z = RoHS Compliant Part. (c)2009-2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07675-0-3/11(D) Rev. D | Page 24 of 24 Package Description 14-Lead TSSOP 14-Lead TSSOP 14-Lead TSSOP 14-Lead TSSOP 14-Lead TSSOP 14-Lead TSSOP Package Option RU-14 RU-14 RU-14 RU-14 RU-14 RU-14