1. General description
The 74LVC16244A; 74LVCH162 4 4A are 16 -b it no n- in ver tin g bu ffer/line driver s with
3-state bus compatible outputs. The device can be used as four 4-bit buffers, two 8-bit
buffers or one 16-bit buffer. It features four output enable inputs, (1 OE to 4OE) each
controlling four of the 3-state outputs. A HIGH on nOE causes the outputs to assume a
high-impedance OFF-state.
Inputs can be driven from either 3.3 V or 5 V devices. When disabled, up to 5.5 V can be
applied to the outputs. These features allow the use of these devices in mixed
3.3 Vand 5 V applications.
The 74LVCH16244A bus hold on data inputs eliminates the need for external pull-up
resistors to hold unused inputs.
2. Features and benefits
5 V tolerant inputs/outputs for interfacing with 5 V logic
Wide supply voltage range from 1.2 V to 3.6 V
CMOS low power consumption
Multibyte flow-through standard pin-out architecture
Low inductance multiple power and ground pins for minimum noise and ground
bounce
Direct interface with TTL levels
High-impedance when VCC =0V
All data inputs have bus hold. (74LVCH16244A only)
Complies with JEDEC standard:
JESD8-7A (1.65 V to 1.95 V)
JESD8-5A (2.3 V to 2.7 V)
JESD8-C/JESD36 (2.7 V to 3.6 V)
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-B exceeds 200 V
CDM JESD22-C101E exceeds 1000 V
Specified from 40 Cto+85C and 40 Cto+125C
74LVC16244A; 74LVCH16244A
16-bit buffer/line driver; 5 V input/output tolerant; 3-state
Rev. 12 — 5 March 2012 Product data sheet
74LVC_LVCH16244A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 12 — 5 March 2012 2 of 19
NXP Semiconductors 74LVC16244A; 74LVCH16244A
16-bit buffer/line driver; 5 V input/output tolerant; 3-state
3. Ordering information
4. Functional diagram
Table 1. Ordering information
Type number Temper ature range Package
Name Description Version
74LVC16244ADL 40 C to +125 C SSOP48 plastic shrink small outline package; 48 leads;
body width 7.5 mm SOT370-1
74LVCH16244ADL
74LVC16244ADGG 40 C to +125 C TSSOP48 plastic thin shrink small outline package;
48 leads; body width 6.1 mm SOT362-1
74LVCH16244ADGG
74LVC16244AEV 40 C to +125 C VFBGA56 plastic very thin fine-pitch ball grid array package;
56 balls; body 4.5 70.65 mm SOT702-1
74LVCH16244AEV
74LVC16244ABX 40 C to +125 C HXQFN60 plastic compatible thermal enhanced extremely
thin quad flat package; no leads; 60 terminals;
body 4 6 0.5 mm
SOT1134-2
74LVCH16244ABX
Pin numbers are shown for SSOP48 and TSSOP48
packages only. Pin numbers are shown for SSOP48 and TSSOP48
packages only.
Fig 1. Logic symbol Fig 2. IEC logic symbol
001aae506
47
46
44
43
2
3
5
6
1A0
1A1
1A2
1A3
1Y0
1Y1
1Y2
1Y3
11OE
36
35
33
32
13
14
16
17
3A0
3A1
3A2
3A3
3Y0
3Y1
3Y2
3Y3
25 3OE
30
29
27
26
19
20
22
23
4A0
4A1
4A2
4A3
4Y0
4Y1
4Y2
4Y3
24 4OE
41
40
38
37
8
9
11
12
2A0
2A1
2A2
2A3
2Y0
2Y1
2Y2
2Y3
48 2OE
11
1
1
1
3
2
4
001aae231
33
32
30
29
27
26
16
17
19
20
22
23
47
46
44
43
41
40
38
37
36
35
2
3
5
6
8
9
11
12
13
14
24
25
1A0
1A1
1A2
1A3
2A0
2A1
2A2
2A3
3A0
3A1
3A2
3A3
4A0
4A1
4A2
4A3
1Y0
1Y1
1Y2
1Y3
2Y0
2Y1
2Y2
2Y3
3Y0
3Y1
3Y2
3Y3
4Y0
4Y1
4Y2
4Y3
48
1
4OE
1OE
2OE
3OE
EN1
EN2
EN3
EN4
74LVC_LVCH16244A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 12 — 5 March 2012 3 of 19
NXP Semiconductors 74LVC16244A; 74LVCH16244A
16-bit buffer/line driver; 5 V input/output tolerant; 3-state
5. Pinning information
5.1 Pinning
Fig 3. Bus hold circuit
to internal circuit
mna705
VCC
data input
Fig 4. Pin configuration SOT370-1 (SSOP48) and
SOT362-1 (TSSOP48) Fig 5. Pin configura tio n SOT702-1 (VFBGA56)
74LVC16244A
74LVCH16244A
1OE 2OE
1Y0 1A0
1Y1 1A1
GND GND
1Y2 1A2
1Y3 1A3
VCC VCC
2Y0 2A0
2Y1 2A1
GND GND
2Y2 2A2
2Y3 2A3
3Y0 3A0
3Y1 3A1
GND GND
3Y2 3A2
3Y3 3A3
VCC VCC
4Y0 4A0
4Y1 4A1
GND GND
4Y2 4A2
4Y3 4A3
4OE 3OE
001aaj052
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
001aaj053
74LVC16244A
74LVCH16244A
Transparent top view
K
J
H
G
F
E
C
B
A
D
246135
ball A1
index area
74LVC_LVCH16244A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 12 — 5 March 2012 4 of 19
NXP Semiconductors 74LVC16244A; 74LVCH16244A
16-bit buffer/line driver; 5 V input/output tolerant; 3-state
(1) This is not a supply pin, the substrate is attached to this pad using conductive die attach material. There is no electrical or
mechanical requirement to solder this pad however if it is soldered the solder land should remain floating or be connected to
GND.
Fig 6. Pin configuration SOT1134-2 (HXQFN60)
D1
D3A16A15A14A13A12A11D2
B9 B10 D7 A17
A18
B11
A19
B12
A20
B13
A21
B14
B8
A10 D6
A9
A8
B7
B6
A7
B5
A6
A22
B15
A23
B16
A24
B17
A25
A26
D8
D4A27
B18
A28A29
B19B20
A30A31A32
B4
A5
B3
B2
B1
D5
A4
A3
A2
A1
74LVC16244A
74LVCH16244A
001aaj054
Transparent top view
GND
(1)
terminal 1
index area
74LVC_LVCH16244A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 12 — 5 March 2012 5 of 19
NXP Semiconductors 74LVC16244A; 74LVCH16244A
16-bit buffer/line driver; 5 V input/output tolerant; 3-state
5.2 Pin description
6. Functional description
[1] H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state.
Table 2. Pin description
Symbol Pin Description
SOT370-1 and
SOT362-1 SOT702-1 SOT1134-2
1OE, 2OE,
3OE, 4OE 1, 48, 25, 24 A1, A6, K6, K1 A30, A29, A14, A13 output enable input (active LOW)
1Y0 to 1Y3 2, 3, 5, 6 B2, B1, C2, C1 B20, A31, D5, D1 data output
2Y0 to 2Y3 8, 9, 11, 12 D2, D1, E2, E1 A2, B2, B3, A5 data output
3Y0 to 3Y3 13, 14, 16, 17 F1, F2, G1, G2 A6, B5, B6, A9 data output
4Y0 to 4Y3 19, 20, 22, 23 H1, H2, J1, J2 D2, D6, A12, B8 data output
GND 4, 10, 15, 21, 28,
34, 39, 45 B3, B4, D3, D4, G3 , G4,
J3, J4 A32, A3, A8, A11, A16,
A19, A24, A27 ground (0 V)
VCC 7, 18, 31, 42 C3, C4, H3, H4 A1, A10, A17, A26 supply voltage
1A0 to 1A3 47, 46, 44, 43 B5, B6, C5, C6 B18, A28 , D8, D4 data input
2A0 to 2A3 41, 40, 38, 37 D5, D6, E5, E6 A25, B16, B15, A22 data input
3A0 to 3A3 36, 35, 33, 32 F6, F5, G6, G5 A21, B13, B12, A18 data input
4A0 to 4A3 30, 29, 27, 26 H6, H5, J6, J5 D3, D7, A15, B10 data input
n.c. - A2, A3, A4, A5, K2, K3,
K4, K5 A4, A7, A20, A23, B1,
B4, B7, B9, B11, B14,
B17, B19
not connected
Table 3. Function table[1]
Control Input Output
nOE nAn nYn
LLL
LHH
HXZ
74LVC_LVCH16244A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 12 — 5 March 2012 6 of 19
NXP Semiconductors 74LVC16244A; 74LVCH16244A
16-bit buffer/line driver; 5 V input/output tolerant; 3-state
7. Limiting values
[1] The minimum input voltage ratings may be exceeded if the input current ratings are observed.
[2] The output voltage ratings may be exceeded if the output current ratings are observed.
[3] Above 60 C the value of Ptot derates linearly with 5.5 mW/K.
[4] Above 70 C the value of Ptot derates linearly with 1.8 mW/K.
8. Recommended operating conditions
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Max Unit
VCC supply voltage 0.5 +6.5 V
IIK input clampi n g cu rre nt VI<0V 50 - mA
VIinput voltage [1] 0.5 +6.5 V
IOK output clamping current VO>V
CC or VO<0V - 50 mA
VOoutput voltage output HIGH or LOW [2] 0.5 VCC +0.5 V
output 3-state [2] 0.5 +6.5 V
IOoutput current VO=0V toV
CC -50 mA
ICC supply cur ren t - 100 mA
IGND ground current 100 - mA
Tstg storage temperature 65 +150 C
Ptot total power dissipation Tamb =40 C to +125 C;
(T)SSOP48 package [3] -500mW
VFBGA56 package [4] -1000mW
HXQFN60 package [4] -1000mW
Table 5. Recommended operating con ditions
Symbol Parameter Conditions Min Typ Max Unit
VCC supply voltage 2.7 - 3.6 V
functional 1.2 - 3.6 V
VIinput voltage 0 - 5.5 V
VOoutput voltage output HIGH or LOW 0 - VCC V
output 3-state 0 - 5.5 V
Tamb ambient temperature in free air 40 - +125 C
t/V input transition rise and fall rate VCC = 1.2 V to 2.7 V 0 - 20 ns/V
VCC = 2.7 V to 3.6 V 0 - 10 ns/V
74LVC_LVCH16244A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 12 — 5 March 2012 7 of 19
NXP Semiconductors 74LVC16244A; 74LVCH16244A
16-bit buffer/line driver; 5 V input/output tolerant; 3-state
9. Static characteristics
Table 6. Static characteristics
At recommended operating conditions. V oltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions 40 C to +85 C40 C to +125 CUnit
Min Typ[1] Max Min Max
VIH HIGH-level input
voltage VCC = 1.2 V 1.08 - - 1.08 - V
VCC = 1.65 V to 1.95 V 0.65 VCC - - 0.65 VCC -V
VCC = 2.3 V to 2.7 V 1.7 - - 1.7 - V
VCC = 2.7 V to 3.6 V 2.0 - - 2.0 - V
VIL LOW-level input
voltage VCC = 1.2 V - - 0.12 - 0.12 V
VCC = 1.65 V to 1.95 V - - 0.35 VCC -0.35 VCC V
VCC = 2.3 V to 2.7 V - - 0.7 - 0.7 V
VCC = 2.7 V to 3.6 V - - 0.8 - 0.8 V
VOH HIGH-level
output voltage VI=V
IH or VIL
IO=100 A;
VCC =1.65Vto3.6V VCC 0.2 - - VCC 0.3 - V
IO=4mA; V
CC = 1.65 V 1 .2 - - 1.05 - V
IO=8mA; V
CC = 2.3 V 1.8 - - 1.65 - V
IO=12 mA; VCC = 2.7 V 2.2 - - 2.05 - V
IO=18 mA; VCC = 3.0 V 2.4 - - 2.25 - V
IO=24 mA; VCC = 3.0 V 2.2 - - 2.0 - V
VOL LOW-level
output voltage VI=V
IH or VIL
IO= 100 A;
VCC = 1.65 V to 3.6 V - - 0.2 - 0.3 V
IO=4mA; V
CC = 1.65 V - - 0.45 - 0.65 V
IO=8mA; V
CC = 2.3 V - - 0.6 - 0.8 V
IO=12mA; V
CC = 2.7 V - - 0.4 - 0.6 V
IO=24mA; V
CC = 3.0 V - - 0.55 - 0.8 V
IIinput leakage
current VCC = 3.6 V;
VI=5.5VorGND -0.1 5- 20 A
IOZ OFF-state output
current [2] VI=V
IH or VIL; VCC = 3.6 V;
VO=5.5VorGND; -0.1 5- 20 A
IOFF power-off
leakage current VCC = 0 V; VIor VO= 5 .5 V - 0.1 10 - 20 A
ICC supply current VCC = 3.6 V;
VI=V
CC or GND; IO=0A -0.120-80A
ICC additional supply
current per input pin;
VCC = 2.7 V to 3.6 V;
VI=V
CC 0.6 V; IO=0A
- 5 500 - 5000 A
CIinput
capacitance VCC = 0 V to 3.6 V;
VI=GNDtoV
CC
-5.0---pF
IBHL bus hold LOW
current [3][4] VCC = 1.65; VI = 0.58 V 10 - - 10 - A
VCC = 2.3; VI = 0.7 V 30 - - 25 - A
VCC = 3.0; VI = 0.8 V 75 - - 60 - A
74LVC_LVCH16244A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 12 — 5 March 2012 8 of 19
NXP Semiconductors 74LVC16244A; 74LVCH16244A
16-bit buffer/line driver; 5 V input/output tolerant; 3-state
[1] All typical values are measured at VCC = 3.3 V and Tamb =25C.
[2] The bus hold circuit is switched off when VI>V
CC allowing 5.5 V on the input terminal.
[3] Valid for data inputs only. Control inputs do not have a bus hold circuit.
[4] The specified sustaining current at the data input holds the input below the specified VI level.
[5] The specified overdrive current at the data input forces the data input to the opposite logic input state.
10. Dynamic characteristics
IBHH bus hold HIGH
current [3][4] VCC = 1.65; VI = 1.07 V 10 - - 10 - A
VCC = 2.3; VI = 1.7 V 30 - - 25 - A
VCC = 3.0; VI = 2.0 V 75 - - 60 - A
IBHLO bus hold LOW
overdrive current
[3][5]
VCC = 1.95 V 200 - - 200 - A
VCC = 2.7 V 300 - - 300 - A
VCC = 3.6 V 500 - - 500 - A
IBHHO bus hold HIGH
overdrive current
[3][5]
VCC = 1.95 V 200 - - 200 - A
VCC = 2.7 V 300 - - 300 - A
VCC = 3.6 V 500 - - 500 - A
Table 6. Static characteristics …cont inued
At recommended operating conditions. V oltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions 40 C to +85 C40 C to +125 CUnit
Min Typ[1] Max Min Max
Table 7. Dynamic characteristics
Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 9.
Symbol Parameter Conditions 40 C to +85 C40 C to +125 CUnit
Min Typ[2] Max Min Max
tpd propagation
delay nAntonYn; see Figure 7 [1]
VCC = 1.2 V - 11.0 - - - ns
VCC = 1.65 V to 1.95 V 1.5 4.8 10.7 1.5 11.3 ns
VCC = 2.3 V to 2.7 V 1.0 2.6 5.3 1.0 5.9 ns
VCC = 2.7 V 1.0 2.6 4.7 1.0 6.0 ns
VCC = 3.0 V to 3.6 V 1.1 2.2 4.1 1.1 5.5 ns
ten enable time nOE to nYn; see Figure 8 [1]
VCC = 1.2 V - 15.0 - - - ns
VCC = 1.65 V to 1.95 V 1.5 6.2 12.1 1.5 12 .7 ns
VCC = 2.3 V to 2.7 V 1.0 3.5 6.4 1.0 7.1 ns
VCC = 2.7 V 1.0 3.3 5.8 1.0 7.5 ns
VCC = 3.0 V to 3.6 V 1.0 2.8 4.6 1.0 6.0 ns
tdis disable time nOE to nYn; see Figure 8 [1]
VCC = 1.2 V - 10.0 - - - ns
VCC = 1.65 V to 1.95 V 2.5 4.4 8.7 2.5 9.4 ns
VCC = 2.3 V to 2.7 V 1.0 2.4 4.9 1.0 5.3 ns
VCC = 2.7 V 1.0 3.2 6.2 1.0 8.0 ns
VCC = 3.0 V to 3.6 V 1.8 3.1 5.2 1.8 6.5 ns
74LVC_LVCH16244A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 12 — 5 March 2012 9 of 19
NXP Semiconductors 74LVC16244A; 74LVCH16244A
16-bit buffer/line driver; 5 V input/output tolerant; 3-state
[1] tpd is the same as tPLH and tPHL.
ten is the same as tPZL and tPZH.
tdis is the same as tPLZ and tPHZ.
[2] Typical values are measured at Tamb =25C and VCC = 1.2 V, 1.8 V, 2.5 V, 2.7 V and 3.3 V respectively.
[3] CPD is used to determine the dynamic power dissipation (PDin W).
PD=C
PD VCC2fiN+(CLVCC2fo) where:
fi= input frequency in MHz; fo= output frequency in MHz
CL= output load capacitance in pF
VCC = supply voltage in Volts
N = number of inputs switching
(CLVCC2fo) = sum of the outputs.
11. Waveforms
CPD power
dissipation
capacitance
per input; VI=GNDtoV
CC [3]
VCC = 1.65 V to 1.95 V - 4.8 - - - pF
VCC = 2.3 V to 2.7 V - 8.3 - - - pF
VCC = 3.0 V to 3.6 V - 11.4 - - - pF
Table 7. Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 9.
Symbol Parameter Conditions 40 C to +85 C40 C to +125 CUnit
Min Typ[2] Max Min Max
Measurement points are given in Table 8.
Logic levels: VOL and VOH are typical output voltage levels that occur with the output load.
Fig 7. The input (nAn) to output (nYn) propagation delays
mna171
nAn input
nYn output
tPLH tPHL
GND
VI
VM
VM
VM
VM
VOH
VOL
74LVC_LVCH16244A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 12 — 5 March 2012 10 of 19
NXP Semiconductors 74LVC16244A; 74LVCH16244A
16-bit buffer/line driver; 5 V input/output tolerant; 3-state
Measurement points are given in Table 8.
Logic levels: VOL and VOH are typical output voltage levels that occur with the output load.
Fig 8. 3-state enable and disabl e tim e s.
mna362
tPLZ
tPHZ
outputs
disabled outputs
enabled
VY
VX
outputs
enabled
output
LOW-to-OFF
OFF-to-LOW
output
HIGH-to-OFF
OFF-to-HIGH
nOE input
VI
VOL
VOH
VCC
VM
GND
GND
tPZL
tPZH
VM
VM
Table 8. Measurement points
Supply voltage VMInput
VCC VItr=t
fVXVY
1.2 V 0.5 VCC VCC 2.5 ns VOL + 0.15 V VOH 0.15 V
1.65 V to 1.95 V 0.5 VCC VCC 2.5 ns VOL + 0.15 V VOH 0.15 V
2.3 V to 2.7 V 0.5 VCC VCC 2.5 ns VOL + 0.15 V VOH 0.15 V
2.7V 1.5V 2.7V 2.5 ns VOL + 0.3 V VOH 0.3 V
3.0V to 3.6V 1.5V 2.7V 2.5 ns VOL + 0.3 V VOH 0.3 V
74LVC_LVCH16244A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 12 — 5 March 2012 11 of 19
NXP Semiconductors 74LVC16244A; 74LVCH16244A
16-bit buffer/line driver; 5 V input/output tolerant; 3-state
Test data is given in Table 9.
Definitions for test circuit:
RL = Load resistance.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
VEXT = External voltage for measuring switching times.
Fig 9. Test circuit for measuring switching times
Table 9. Test data
Supply voltage Input Load VEXT
VItr, tfCLRLtPLH, tPHL tPLZ, tPZL tPHZ, tPZH
1.2 V VCC 2 ns 30 pF 1 kopen 2 VCC GND
1.65 V to 1.95 V VCC 2 ns 30 pF 1 kopen 2 VCC GND
2.3 V to 2.7 V VCC 2 ns 30 pF 500 open 2 VCC GND
2.7V 2.7V 2.5 ns 50 pF 500 open 2 VCC GND
3.0Vto3.6V 2.7V 2.5 ns 50 pF 500 open 2 VCC GND
74LVC_LVCH16244A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 12 — 5 March 2012 12 of 19
NXP Semiconductors 74LVC16244A; 74LVCH16244A
16-bit buffer/line driver; 5 V input/output tolerant; 3-state
12. Package outline
Fig 10. Package outline SOT370-1 (SSOP48)
UNIT A1A2A3bpcD
(1) E(1) eH
ELL
pQZywv θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 0.4
0.2 2.35
2.20 0.25 0.3
0.2 0.22
0.13 16.00
15.75 7.6
7.4 0.635 1.4 0.25
10.4
10.1 1.0
0.6 1.2
1.0 0.85
0.40 8
0
o
o
0.18 0.1
DIMENSIONS (mm are the original dimensions)
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
SOT370-1 99-12-27
03-02-19
(1)
wM
bp
D
HE
E
Z
e
c
vMA
X
A
y
48 25
MO-118
24
1
θ
A
A1
A2
Lp
Q
detail X
L
(A )
3
pin 1 index
0 5 10 mm
scale
SSOP48: plastic shrink small outline package; 48 leads; body width 7.5 mm SOT370-1
A
max.
2.8
74LVC_LVCH16244A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 12 — 5 March 2012 13 of 19
NXP Semiconductors 74LVC16244A; 74LVCH16244A
16-bit buffer/line driver; 5 V input/output tolerant; 3-state
Fig 11. Package outline SOT362-1 (TSSOP48)
UNIT A1A2A3bpcD
(1) E(2) eH
ELL
pQZywv θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 0.15
0.05 0.2
0.1 8
0
o
o
0.1
DIMENSIONS (mm are the original dimensions).
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
SOT362-1 99-12-27
03-02-19
wM
θ
A
A1
A2
D
Lp
Q
detail X
E
Z
e
c
L
X
(A )
3
0.25
124
48 25
y
pin 1 index
b
H
1.05
0.85 0.28
0.17 0.2
0.1 12.6
12.4 6.2
6.0 0.5 1 0.25
8.3
7.9 0.50
0.35 0.8
0.4
0.08
0.8
0.4
p
EvMA
A
TSSOP48: plastic thin shrink small outline package; 48 leads; body width 6.1 mm SOT362-1
A
max.
1.2
0
2.5
5 mm
scale
MO-153
74LVC_LVCH16244A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 12 — 5 March 2012 14 of 19
NXP Semiconductors 74LVC16244A; 74LVCH16244A
16-bit buffer/line driver; 5 V input/output tolerant; 3-state
Fig 12. Package outline SOT702-1 (VFBGA56)
0.65
A1bA2
UNIT D ye
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
02-08-08
03-07-01
IEC JEDEC JEITA
mm 10.3
0.2 0.7
0.6 4.6
4.4
y1
7.1
6.9
0.45
0.35 0.08 0.1
e1
3.25
e2
5.85
DIMENSIONS (mm are the original dimensions)
SOT702-1 MO-225
E
0.15
v
0.08
w0 2.5 5 mm
scale
SOT702-1
VFBGA56: plastic very thin fine-pitch ball grid array package; 56 balls; body 4.5 x 7 x 0.65 mm
A
max.
AA2
A1
detail X
y
y1C
e
e
b
X
D
E
C
A
B
C
D
E
F
H
G
J
K
246135
ball A1
index area
BA
e2
e1
1/2 e
1/2 e
AC
CB
vM
wM
ball A1
index area
74LVC_LVCH16244A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 12 — 5 March 2012 15 of 19
NXP Semiconductors 74LVC16244A; 74LVCH16244A
16-bit buffer/line driver; 5 V input/output tolerant; 3-state
Fig 13. Package outline SOT1134-2 (HXQFN60)
References
Outline
version European
projection Issue date
IEC JEDEC JEITA
SOT1134-2 - - -
- - -
- - -
sot1134-2_po
11-08-15
Unit
mm max
nom
min
0.50 0.08
0.05
0.02
0.28
0.23
0.18
1.95
1.85
1.75
6.1
6.0
5.9
3.95
3.85
3.75 1.0 2.5 4.5 0.195
0.145
0.095 0.1
A
Dimensions
HXQFN60: plastic compatible thermal enhanced extremely thin quad flat package; no leads;
60 terminals; body 4 x 6 x 0.5 mm SOT1134-2
A1A2
0.42
0.40
0.38
bD
4.1
4.0
3.9
DhEE
h
0.08 0.1
yy
1
e
0.5
e1e2e3
3.0
e4eT
0.49
eR
0.5
K
0.25
0.20
0.15
L
0.28
0.23
0.18
L1v
0.05
w
0 5 mm
terminal 1
index area
BA
D
E
C
y
C
y1
X
detail X
A A2
A1
terminal 1
index area
e2
e1
eT
eR
eT
eR
e4
e3
e
e
1/2 e
1/2 e
AC B
vC
w
bAC B
vC
w
Dh
K
L
Eh
L1
B1
A1
B7
D5 D8
D6 D7
D1 D4
D2 D3
B20 B18 A27
A26
A17
B11
B17
A11 B8 B10 A16
A32
A10
eR
eT
eR
eT
74LVC_LVCH16244A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 12 — 5 March 2012 16 of 19
NXP Semiconductors 74LVC16244A; 74LVCH16244A
16-bit buffer/line driver; 5 V input/output tolerant; 3-state
13. Abbreviations
14. Revision history
Table 10. Abbreviations
Acronym Description
CDM Charged Device Mo del
CMOS Complementary Metal Oxide Semiconductor
DUT Device Under Test
ESD ElectroStatic Discharge
HBM Human Body Model
MM Machine Mo del
TTL Transistor-Tran s istor Logic
Table 11. Revision history
Document ID Release date Data sheet status Change notice Supersedes
74LVC_LVCH16244A v.12 20120305 Product data sheet - 74LVC_LVCH16244A v.11
Modifications: For type number 74LVC16244ABX and 74LVCH16244ABX the sot code has changed to
SOT1134-2.
74LVC_LVCH16244A v.11 20111027 Product data sheet - 74LVC_LVCH16244A v.10
Modifications: Table 4, Table 5, Table 6, Table 7, and Table 9: values added for lower voltage ranges.
74LVC_LVCH16244A v.10 20110429 Product data sheet - 74LVC_LVCH16244A v.9
Modifications: type numbers 74LVC16244ABQ and 74LVCH16244 ABQ chang ed to 74LVC16244ABX
and 74LVCH16244ABX.
Figure 6: figure note 1 changed.
74LVC_LVCH16244A v.9 20100318 Product data sheet - 74LVC_LVCH16244A v.8
74LVC_LVCH16244A v.8 20081117 Product data sheet - 74LVC_LVCH16244A v.7
74LV C_LVCH16 244A v.7 20031208 Product specification - 74LVC_LVCH16244A v.6
74LV C_LVCH16 244A v.6 20030130 Product specification - 74LVC_LVCH16244A v.5
74LVC_LVCH16244A v.5 20021030 Product specification - 74LVC_H16244A v.4
74LVC_H16244A v.4 19971028 Product specification - 74LVC16244A_
74LVCH16244A v.3
74LVC16244A_
74LVCH16244A v.3 19971028 Product specification - 74LVC16244A v.2
74LVC16244A v.2 19970630 Product specification - 74LVC16244A v.1
74LVC16244A v.1 - - - -
74LVC_LVCH16244A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 12 — 5 March 2012 17 of 19
NXP Semiconductors 74LVC16244A; 74LVCH16244A
16-bit buffer/line driver; 5 V input/output tolerant; 3-state
15. Legal information
15.1 Data sheet status
[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term ‘short data sheet’ is explained in section “Definitions”.
[3] The prod uct sta tus of device (s) descri bed in this d ocument m ay have cha nged since thi s docume nt was publish ed and ma y diffe r in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
15.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liab ility for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and tit le. A short data sh eet is intended
for quick reference only and shou ld not be rel ied u pon to cont ain det ailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall pre vail.
Product specificat ionThe information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to off er functions and qualities beyond tho se described in the
Product data sheet.
15.3 Disclaimers
Limited warr a nty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Se miconductors takes no
responsibility for the content in this document if provided by an inf ormation
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequ ential damages (including - wit hout limitatio n - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggreg ate and cumulative l iability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all informa tion supplied prior
to the publication hereof .
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, lif e-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in perso nal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconducto rs products in such equipment or
applications and ther efore such inclu sion and/or use is at the cu stomer’s own
risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty tha t such application s will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and ope ration of their applications
and products using NXP Semiconductors product s, and NXP Semiconductors
accepts no liability for any assistance with applicati ons or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suit able and fit for the custome r’s applications and
products planned, as well as fo r the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for th e customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanent ly and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individua l agreement. In case an individual
agreement is concluded only the ter ms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
No offer to sell or license — Nothing i n this document may be interpreted or
construed as an of fer t o sell product s that is open for accept ance or t he grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Document status[1][2] Product status[3] Definition
Objective [short] data sheet Development This document contains data fro m the objective specification for product development.
Preliminary [short] dat a sheet Qualification This document contains data from the preliminary specification.
Product [short] dat a sheet Production This document cont ains the product specification.
74LVC_LVCH16244A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 12 — 5 March 2012 18 of 19
NXP Semiconductors 74LVC16244A; 74LVCH16244A
16-bit buffer/line driver; 5 V input/output tolerant; 3-state
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for aut omotive use. It i s neither qua lif ied nor test ed
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
non-automotive qualified products in au tomotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automot ive specifications and standard s, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting f rom customer design an d
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
15.4 Trademarks
Notice: All referenced b rands, produc t names, service names and trademarks
are the property of their respect i ve ow ners.
16. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
NXP Semiconductors 74LVC16244A; 74LVCH16244A
16-bit buffer/line driver; 5 V input/output tolerant; 3-state
© NXP B.V. 2012. All rights reserved.
For more information, please visit: http://www.nxp.co m
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of rele ase: 5 March 2 012
Document identifier: 74LVC_LVCH16244A
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
17. Contents
1 General description. . . . . . . . . . . . . . . . . . . . . . 1
2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1
3 Ordering information. . . . . . . . . . . . . . . . . . . . . 2
4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
5 Pinning information. . . . . . . . . . . . . . . . . . . . . . 3
5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5
6 Functional description . . . . . . . . . . . . . . . . . . . 5
7 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 6
8 Recommended operating conditions. . . . . . . . 6
9 Static characteristics. . . . . . . . . . . . . . . . . . . . . 7
10 Dynamic characteristics . . . . . . . . . . . . . . . . . . 8
11 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 12
13 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 16
14 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 16
15 Legal information. . . . . . . . . . . . . . . . . . . . . . . 17
15.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 17
15.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
15.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 17
15.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 18
16 Contact information. . . . . . . . . . . . . . . . . . . . . 18
17 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19