027252/$ Order this document by MC149571/D REV 3 SEMICONDUCTOR TECHNICAL DATA 0& Advance Information 0XOWL6WDQGDUG9LGHR3URFHVVRU 7KH0&PXOWLVWDQGDUGYLGHRSURFHVVRUSURYLGHVWKHYLGHRFRPSUHVVLRQDQG VFDOLQJIXQFWLRQVIRU4RUXVYLGHRFRQIHUHQFLQJV\VWHPDSSOLFDWLRQV7RVXSSRUWYLGHR FRPPXQLFDWLRQVWKHYLGHRSURFHVVRUFDQHQFRGHHLWKHU+RU+YLGHRELWVWUHDP 7KHSURFHVVRUKDVDGLUHFWLQWHUIDFHWRD176&3$/GHFRGHU,WUHTXLUHV0E\WH('2 '5$0VIRUIUDPHVWRULQJ7KH0&YLGHRSURFHVVRUSHUIRUPVWZRPDMRU LQGHSHQGHQWYLGHRIXQFWLRQV9LGHR3UH3URFHVVLQJ9LGHR(QFRGLQJ7KHIXQFWLRQDO EORFNGLDJUDPLQ)LJXUHVKRZVWKHPDMRUIXQFWLRQDOPRGXOHVWKDWHQDEOHWKH 0&WRSHUIRUPWKHVHIXQFWLRQV Video In (16) Pre- DCT/iDCT/ Motion Rate Processor Quantizer Estimator Control Control System Bus Host Interface Bitstream Encoder Data (8), Address (5), Interrupt (2) DSP (32) EDO DRAM Figure 1. MC149571 Functional Block Diagram 4RUXVLVDUHJLVWHUHGWUDGHPDUNRI0RWRUROD,QF This document contains information on a new product. Specifications and information herein are subject to change without notice. Advance Information (c) 1999MOTOROLA, INC. MC149571 Table of Contents Section 1 Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 Section 2 Signal and Packaging Information . . . . . . . . . . . . . . . . 2-1 Section 3 Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 Section 4 Programmability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 FOR TECHNICAL ASSISTANCE: 7HOHSKRQH ,QWHUQHW KWWSZZZPRWVSVFRPVSVJHQHUDOVDOHVKWPO Data Sheet Conventions 7KLVGDWDVKHHWXVHVWKHIROORZLQJFRQYHQWLRQV OVERBAR Used to indicate a signal that is active when pulled low (For example, the RESET pin is active when low.) asserted Means that a high true (active high) signal is high or that a low true (active low) signal is low deasserted Means that a high true (active high) signal is low or that a low true (active low) signal is high Examples: Note: ii Signal/Symbol Logic State Signal State Voltage PIN True Asserted VIL/VOL PIN False Deasserted VIH/VOH PIN True Asserted VIH/VOH PIN False Deasserted VIL/VOL Values for VIL, VOL, VIH, and VOH are defined by individual product specifications. MC149571 Advance Information MOTOROLA MC149571 Features 0XOWLSOH,789LGHR6WDQGDUGVXSSRUW | ,78+ | ,78+ 9LGHRHQFRGHHQJLQH | (QFRGHV&,)x DQG4&,)x VL]HGLPDJHV | (QFRGHV&,)DWIUDPHVSHUVHFRQGDQG4&,)DWIUDPHVSHUVHFRQG 6XSSRUWVIURPWRNESVYLGHRELWUDWHV 9LGHR3UH3URFHVVLQJ | $FFHSWV176&RU3$/LQSXWYLGHRVLJQDOV | 1RQOLQHDUWHPSRUDOQRLVHFRUHILOWHUUHGXFHVQRLVHDQGLPSURYHVFRGLQJ HIILFLHQF\ | 'DWDLQSXWVWUHDPFRPSOLDQWZLWKELW &&,5VWDQGDUG | *OXHOHVVLQWHUIDFHWRLQGXVWU\VWDQGDUG176&3$/YLGHRGHFRGHUV 0RWLRQ(VWLPDWLRQ | )XOO\VXSSRUWV+$QQH[)$GYDQFHG3UHGLFWLRQ0RGH | )RXUPRWLRQYHFWRUVSHUPDFUREORFNJHQHUDWHGVXSSRUWVRYHUODSSHGEORFN PRWLRQFRPSUHVVLRQIRUEHWWHUSLFWXUHTXDOLW\DWORZHUELWUDWHV | 8QUHVWULFWHGPRWLRQYHFWRUVFDQH[WHQGSDVWSLFWXUHERXQGDULHVWRLPSURYH SHUIRUPDQFH | 0RWLRQHVWLPDWLRQYHFWRUUDQJHH[WHQGVWRYHUWLFDODQGKRUL]RQWDO | IXOOSHOPRWLRQYHFWRUFDQGLGDWHV | +DOISL[HOVHDUFKPRWLRQHVWLPDWLRQ 5DWH&RQWURO | ,QWHOOLJHQWIUDPHUDWHFRQWURO | '\QDPLFWUDGHRIIEHWZHHQWHPSRUDOVSDWLDOTXDOLW\DQGORZODWHQF\IUDPH UDWHDGMXVWPHQWRQXVHULQSXWGXULQJYLGHRFDOOV | 0LQLPXPGHOD\GXHWRIXOO\SLSHOLQHGSURFHVVLQJ 2WKHUIHDWXUHV | ELW+RVW,QWHUIDFHSURYLGHVFKLSFRQWURODQGELWVWUHDPLQWHUIDFH | 7ZHQW\WKUHH2QFKLSUHJLVWHUVDOORZWKHXVHUWRSURJUDPYLGHRSDUDPHWHUV | 2QFKLS'5$0FRQWUROOHULQWHUIDFHV('2'5$0WKURXJKDELW'DWD%XV | 3URJUDPPDEOHRQFKLS3KDVH/RFN/RRS3// WKDWFDQEHSURJUDPPHGWRUXQ IURP0+]WR0+] | 2SHUDWLQJIUHTXHQF\RI0+]ZLWKYLGHRLQSXWIUHTXHQF\RI0+] | 9WROHUDQWLQWHUIDFHRQ,2SLQV | 2SWLPL]HGIRU9RSHUDWLRQIURP&WR&DPELHQWWHPSHUDWXUH | 3ODVWLF4)3SDFNDJH MOTOROLA MC149571 Advance Information iii MC149571 iv MC149571 Advance Information MOTOROLA 6LJQDO'HVFULSWLRQV 6LJQDO*URXSLQJV 7KHLQSXWDQGRXWSXWVLJQDOVRIWKH0&DUHRUJDQL]HGLQWRIXQFWLRQDOJURXSVDV VKRZQLQ7DEOHDQGDVLOOXVWUDWHGLQ)LJXUH7KH0&LVRSHUDWHGIURPD 9VXSSO\KRZHYHUDOOWKHLQSXWDQGELGLUHFWLRQDOSLQVFDQWROHUDWH9 Table 1-1. MC149571 Functional Signal Groupings Number of Signals Detailed Description Power (VCC_xx) and Ground (GND_xx) 55 Table 1-2 Reset 1 Table 1-3 Phase Lock Loop (PLL) and Clock 2 Table 1-4 Operation Mode Select 3 Table 1-5 Host Interface 18 Table 1-6 Video Input 19 Table 1-7 DRAM Interface 45 Table 1-8 Functional Group MOTOROLA MC149571 Advance Information 1-1 MC149571 MC149571 VCC_IO VCC_Q GND_IO/Q VCC_A GND_A VCC_D GND_D 18 6 27 VIPIXCLK VICBLANK VIVSYNC Power/Ground Video In 8 VIY7-VIY0 8 VIC7-VIC0 Reset SYSRESET CLOCKIN SYSPLLBP PLL/Clock MODESEL0 MODESEL1 MODESEL2 Operation Mode Select DCS_L RRAS_L DRD_L RCAS_L DWR_L DADDR4-DADDR0 DDATA7-DDATA0 5 Host Interface RWR_L DRAM Interface 8 DBSEIT_L ROE_L 9 RADDR8- RADDR0 32 RDATA31- RDATA0 DINT_L Figure 1-1. MC149571 Signals Identified by Functional Group 1-2 MC149571 Advance Information MOTOROLA MC149571 3RZHUDQG*URXQG6LJQDOV Table 1-2. MC149571 Power and Ground Signals Signal Name Description VCC_IO I/O Power VCC_Q Core Power GND_IO/Q I/O and Core Ground VCC_A PLL Analog Power GND_A PLL Analog Ground VCC_D PLL Digital Power GND_D PLL Digital Ground 5HVHW6LJQDOV Table 1-3. MC149571 Reset Signal Signal Name SYSRESET Note: Signal Type Input* Detailed Description Chip reset All inputs are 5 V tolerant. MOTOROLA MC149571 Advance Information 1-3 MC149571 3//DQG&ORFN6LJQDOV Table 1-4. MC149571 PLL and Clock Signals Signal Name Signal Type Input1 CLOCKIN SYSPLLBP Input1,2 Detailed Description Clock input to the on-chip PLL (default = 20 MHz) Asserting this signal bypasses the on-chip PLL. This pin must be asserted to bypass the PLL before changing the Operation Mode from Normal to the PLL Programming Mode. Notes: 1. All inputs are 5 V tolerant. 2. See Section 1.5 for information about selecting the Operation Mode and its effect on PLL operation. 2SHUDWLRQ0RGH6LJQDOV Table 1-5. MC149571 Operation Mode Signals Signal Name MODESEL2- MODESEL0 Signal Type Input1 Detailed Description The MODESEL signals combine to define eight operational modes for normal operations and diagnostics.2,3,4 Notes: 1. All inputs are 5 V tolerant. 2. Only two operation modes are available to users: * Normal Operation Mode (all three signals = 0), and * PLL Programming Mode (all three signals = 1). 3. In the Normal Operation Mode, the PLL generates a default internal clock frequency of 2.2 times CLOCKIN. For example, if CLOCKIN = 20 MHz, the internal clock frequency is 44 MHz. 4. To change the ratio between CLOCKIN and the internal clock, select the PLL Programming Mode. See the MC149571 Programming Manual for information about programming the PLL ratio. 1-4 MC149571 Advance Information MOTOROLA MC149571 +RVW,QWHUIDFH6LJQDOV Table 1-6. MC149571 Host Interface Signals Signal Name Signal Type Detailed Description DCS_L Input1 Chip select from Embedded Controller DRD_L Input1 Read enable from Embedded Controller DWR_L Input1 Write enable from Embedded Controller DADDR4-DADDR0 Input1 Emedded Controller Address bus DDATA7-DDATA0 Bidirectional Embedded Controller Interface data bus; 5 V tolerant DBSEIT_L Output Embedded Controller BSE Interrupt DINT_L Output Embedded Controller Interrupt Note: 1. All inputs are 5 V tolerant. 9LGHR,QSXW6LJQDOV Table 1-7. MC149571 Video Input Signals Signal Name Signal Type Detailed Description VIPIXCLK Input1 Pixel clock VICBLANK Input1 Composite BLANK VIVSYNC Input1 Vertical Sync VIY7-VIY0 Input1 Luma data Y in 4:2:2 VIC7-VIC0 Input1 Chroma data Cb/Cr Note: 1. All inputs are 5 V tolerant. MOTOROLA MC149571 Advance Information 1-5 MC149571 '5$0,QWHUIDFH6LJQDOV Table 1-8. MC149571 DRAM Interface Signals Signal Name Signal Type Detailed Description RRAS_L Output Row address strobe to EDO DRAMs RCAS_L Output Column address strobe to EDO DRAMs RWR_L Output Write enable to EDO DRAMs ROE_L Output Output enable for EDO DRAMs RADDR8-RADDR0 Output Address bus to EDO DRAMs RDATA31-RDATA0 Bidirectional 1-6 Memory data bus (5 V tolerant): * RDATA7-RDATA0 = Byte 1 * RDATA15-RDATA8 = Byte 2 * RDATA23-RDATA16 = Byte 3 * RDATA31-RDATA24 = Byte 4 MC149571 Advance Information MOTOROLA MC149571 3LQRXWDQG3DFNDJLQJ,QIRUPDWLRQ ,QWURGXFWLRQ 7KLVVHFWLRQSURYLGHVDWDEOHVKRZLQJKRZWKHVLJQDOVGHVFULEHGLQ6HFWLRQDUH DOORFDWHG7KH0&LVDYDLODEOHLQDSLQ3ODVWLF4)3SDFNDJH 'HWDLOHGSDFNDJHGUDZLQJIRUWKLVGHYLFHLVDYDLDEOHRQWKH0RWRURODZHESDJHDW http://mot-sps.com/cgi-bin/cases 8VHSDFNDJHIRUWKHVHDUFK MOTOROLA MC149571 Advance Information 2-1 MC149571 Table 2-1. MC149571 208 PQFP Package Signal List Pin Name Pin Name Pin Name Pin Name 1 VCC_IO 31 VCC_IO 61 VCC_IO 91 Reserved 2 GND_IO 32 GND_IO 62 DADDR0 92 VCC_IO 3 VIY0 33 Reserved 63 DADDR1 93 GND_IO 4 VIY1 34 Reserved 64 DADDR2 94 Reserved 5 VIY2 35 Reserved 65 DADDR3 95 Reserved 6 VIY3 36 Reserved 66 DADDR4 96 Reserved 7 VIY4 37 Reserved 67 VCC_IO 97 VCC_IO 8 VIY5 38 Reserved 68 GND_IO 98 GND_IO 9 VIY6 39 VCC_IO 69 DDATA0 99 ROE_L 10 VIY7 40 GND_IO 70 DDATA1 100 RWE_L 11 VCC_Q 41 GND_Q 71 DDATA2 101 RRAS_L 12 GND_Q 42 VCC_Q 72 DDATA3 102 VCC_IO 13 GND_IO 43 Reserved 73 VCC_IO 103 GND_IO 14 VCC_IO 44 Reserved 74 GND_IO 104 RADDR0 15 VIC0 45 Reserved 75 DDATA4 105 RADDR1 16 VIC1 46 Reserved 76 DDATA5 106 RADDR2 17 VIC2 47 Reserved 77 DDATA6 107 RADDR3 18 VIC3 48 Reserved 78 DDATA7 108 RADDR4 19 VIC4 49 Reserved 79 VCC_IO 109 RADDR5 20 VIC5 50 Reserved 80 GND_IO 110 RADDR6 21 VIC6 51 VCC_IO 81 GND_Q 111 RADDR7 22 VIC7 52 GND_IO 82 VCC_Q 112 RADDR8 23 VCC_IO 53 GND_IO 83 DBSEIT_L 113 VCC_IO 24 GND_IO 54 GND_IO 84 DINT_L 114 GND_IO 25 Reserved 55 GND_IO 85 DCS_L 115 RDATA0 26 Reserved 56 Reserved 86 VCC_IO 116 RDATA1 27 Reserved 57 Reserved 87 GND_IO 117 RDATA2 28 Reserved 58 VCC_Q 88 DWR_L 118 RDATA3 29 Reserved 59 GND_Q 89 DRD_L 119 RDATA4 30 Reserved 60 GND_IO 90 Reserved 120 RDATA5 2-2 MC149571 Advance Information MOTOROLA MC149571 Table 2-1. MC149571 208 PQFP Package Signal List (Continued) Pin Name Pin Name Pin Name Pin Name 121 RDATA6 144 RDATA23 167 GND_IO 190 Reserved 122 RDATA7 145 RDATA24 168 Reserved 191 Reserved 123 VCC_Q 146 GND_IO 169 Reserved 192 Reserved 124 GND_Q 147 VCC_IO 170 Reserved 193 Reserved 125 RDATA8 148 RDATA25 171 Reserved 194 Reserved 126 RDATA9 149 RDATA26 172 Reserved 195 Reserved 127 RDATA10 150 Reserved 173 Reserved 196 Mode Select 0 128 RDATA11 151 RDATA28 174 Reserved 197 VCC_Q 129 RDATA12 152 RDATA29 175 DDATA4 198 GND_Q 130 RDATA13 153 RDATA30 176 Reserved 199 SYSRESET 131 RDATA14 154 Reserved 177 Reserved 200 Reserved 132 RDATA15 155 RDATA31 178 Reserved 201 SYSPLLBP 133 RCAS_L 156 Mode Select 1 179 GND_A 202 Reserved 134 VCC_IO 157 Mode Select 2 180 VCC_A 203 Reserved 135 GND_IO 158 Reserved 181 CLOCK_IN 204 Reserved 136 RDATA16 159 Reserved 182 VCC_D 205 Reserved 137 RDATA17 160 Reserved 183 GND_D 206 VIPIXCLK 138 RDATA18 161 Reserved 184 Reserved 207 VIVSYNC 139 RDATA19 162 Reserved 185 Reserved 208 VICBLANK 140 RDATA20 163 Reserved 186 Reserved 141 RDATA21 164 Reserved 187 Reserved 142 Reserved 165 Reserved 188 Reserved 143 RDATA22 166 VCC_IO 189 Reserved 1RWHV $OOSLQVPDUNHG5(6(59('VKDOOQRWEHFRQQHFWHGRWKHUZLVHWKHGHYLFHPD\QRW RSHUDWH MOTOROLA MC149571 Advance Information 2-3 6SHFLILFDWLRQV ,QWURGXFWLRQ 7KH0&VSHFLILFDWLRQVDUHSUHOLPLQDU\DQGDUHIURPGHVLJQVLPXODWLRQV7KH\ PD\QRWEHIXOO\WHVWHGRUJXDUDQWHHGDWWKLVHDUO\VWDJHRIWKHSURGXFWOLIHF\FOH )LQDOL]HGVSHFLILFDWLRQVZLOOEHSXEOLVKHGDIWHUIXOOFKDUDFWHUL]DWLRQDQGGHYLFH TXDOLILFDWLRQVDUHFRPSOHWH 0D[LPXP5DWLQJV Table 3-1. Power and Temperature Ratings Rating Symbol Value Unit Supply voltage VCC -0.3 to +4.0 V All input voltage VIN GND to 5.5 V Operating Temperature Range TA 0 to +70 C TSTG -55 to +150 C Storage Temperature Note: Absolute maximum ratings are stress ratings only and functional operation at the maximum limits is not guaranteed. Stress beyond the maximum rating may affect device reliability or cause permanent damage to the device. 7KHUPDO&KDUDFWHULVWLFV Table 3-2. Package Thermal Characteristics Characteristic Junction to Ambient Thermal Resistance MOTOROLA Symbol Value Unit JA 32 C/W MC149571 Advance Information 3-1 MC149571 '&(OHFWULFDO&KDUDFWHULVWLFV Table 3-3. DC Electrical Characteristics Characteristics Symbol Min Typ Max Unit Supply Voltage VCC 3.0 3.3 3.6 V Input High Voltage VIH 2.0 -- 5.5 V Input Low Voltage VIL 0 -- 0.8 V Output High Voltage * DDATA7-DDATA0, RCAS_L (IOH = -8mA) * RDATA31-RDATA0, RADDR8-RADDR0, ROE_L, RRAS_L, RWR_L (IOH = -4 mA) * DBSEIN_L, DINT_L (IOH = -2 mA) VOH 2.4 -- VCC V Output Low Voltage * DDATA7-DDATA0, RCAS_L (IOL = 8mA) * RDATA31-RDATA0, RADDR8-RADDR0, ROE_L, RRAS_L, RWR_L (IOL = 4 mA) * DBSEIN_L, DINT_L (IOL = 2 mA) VOL 0 -- 0.4 V Input Leakage Current (@ 5.5V / Maximum VCC / 0.0V) IIN -10 -- 10(1) A Input Leakage Current (2) (@ Maximum VCC / 0.0V) IIN -10 -- 100 A High Impedance Input Current Itsi -10 -- 10 A Icc in Normal Operation Mode ICC -- -- 450 mA Input Capacitance -- -- 9 pF 1RWHV 1RWLQFOXGLQJWKHIROORZLQJLQSXWSLQVZLWKLQWHUQDOSXOOGRZQUHVLVWRU 0RGH6HOHFW0RGH6HOHFW0RGH6HOHFW6<65(6(76<63//%3 ,QSXW/HDNDJH&XUUHQWIRU 0RGH6HOHFW0RGH6HOHFW0RGH6HOHFW6<65(6(76<63//%3 3-2 MC149571 Advance Information MOTOROLA MC149571 $&(OHFWULFDO&KDUDFWHULVWLFV 7KHWLPLQJZDYHIRUPVVKRZQLQWKLVVHFWLRQDUHWHVWHGZLWKD9LOPD[LPXPRI9DQG 9LKPLQLPXPRI9IRUDOOSLQV$&WLPLQJVSHFLILFDWLRQVZKLFKDUHUHIHUHQFHGWRD GHYLFHLQSXWVLJQDODUHPHDVXUHGLQSURGXFWLRQZLWKUHVSHFWWRWKHSRLQWRIWKH UHVSHFWLYHLQSXWVLJQDOVWUDQVLWLRQ2XWSXWOHYHOVDUHPHDVXUHGZLWKWKHSURGXFWLRQWHVW PDFKLQH9RODQG9RKUHIHUHQFHOHYHOVVHWDW9DQG9UHVSHFWLYHO\ 0&&KLS5HVHW 0&VXSSRUWVDOHYHOVHQVLWLYHUHVHW7RJHQHUDWHDFKLSOHYHOUHVHWDVVHUWWKH 6<65(6(7VLJQDO7KLVUHVHWVWKHUHJLVWHUVDVVRFLDWHGZLWKWKH3//FRQWURO7KHQPV ODWHUGHDVVHUW6<65(6(7$WWKLVWUDQVLWLRQWKHGLYLGHE\WZRFORFNFLUFXLWLVUHVHWDQG WKHLQWHUQDOFKLSUHVHWLVJHQHUDWHGIRUHLJKWV\VWHPFORFNF\FOHVDVVKRZQLQ)LJXUH *LYHQD0+]&/2&.,1DQGWKHGHIDXOWVHWWLQJIRUWKH3//SURJUDPPLQJUHJLVWHU )5UHJLVWHU WKH0&VKRXOGEHDEOHWRDFFHSWSURJUDPPHGYDOXHV&/2&.,1 F\FOHVDIWHUWKHIDOOLQJHGJHRI6<65(6(7 CLOCKIN SYSRESET 1 ms 22 Cycles (CLOCKIN) Figure 3-1. Reset Timing MOTOROLA MC149571 Advance Information 3-3 MC149571 3//3URJUDPPLQJ0RGH 0&HQWHUVWKH3//3URJUDPPLQJPRGHZKHQWKHWKUHHPRGHSLQV02'(6(/ 02'(/6(/DQG02'(6(/ DUHVHWWRDOORQHV ,QWKH3//SURJUDPPLQJPRGH WKHRQFKLS3//LVDXWRPDWLFDOO\E\SDVVHGDQGWKH0&UXQVDWKDOIWKHIUHTXHQF\ RI&/2&.,17KHRQFKLS3//FDQWKHQEHSURJUDPPHGE\ZULWLQJDGHVLUHGUDWLRYDOXH LQWRWKH3//B5B)UHJLVWHU) 1RWHWKDWWKHUDWLRRI)5FDQQRWEHOHVVWKDQ'XHWR DVHWWOHWLPHUHTXLUHPHQWIRUWKH3//WKH3//PXVWVWD\LQWKLVPRGHIRUDWOHDVWP6HF DIWHUZULWLQJWRWKH3//B5B)UHJLVWHU$QLQWHUQDOUHVHWLVWULJJHUHGDVVRRQDV0& H[LWVWKH3//3URJUDPPLQJPRGH7KHLQWHUQDOUHVHWSHUIRUPVWKHVDPHIXQFWLRQDVWKH QRUPDOV\VWHPUHVHWZKLOHUHVHUYLQJWKHQHZ5DQG)YDOXHV :DUQLQJ3HUIRUPLQJDQRUPDOV\VWHPUHVHWDIWHUH[LWLQJWKH3//SURJUDPPLQJPRGH UHWXUQVWKH0&WRWKHGHIDXOWYDOXHV MODESEL0- 000 MODESEL2 111 000 SYSPLLBP DDATA7- DDATA0 PLL_R_F Value 1 ms or longer Figure 3-2. PLL ProgrammingTiming 3-4 MC149571 Advance Information MOTOROLA MC149571 +RVW,QWHUIDFH:ULWH7LPLQJV Table 3-4. Host Interface Write Timings (Host Writes to MC149571) No. Characteristics Min Delay Max Delay Units 1 Address valid to Write Enable Deassertion 9 - ns 2 Write Enable Cycle Time 35 - ns 3 Write Enable Deassertion Time 3 - ns 4 Write Data Setup Time w.r.t Write Enable Deassertion 5 - ns 5 Write Data Hold Time w.r.t. Write Enable Deassertion 2 - ns 6 Previous Read Enable Deassertion to Write Enable Deassertion 35 - ns 7 Write Enable Deassertion to Address Not Valid 2 - ns 8 Chip Select to Write Enable Assertion 0.1 - ns 9 Write Enable Deassertion to Chip Select Inactive 2 - ns DCS_L 8 9 DADDR Write Address 7 1 2 DWR_L 3 DRD_L 4 5 Write Data DDATA 6 Figure 3-3. Host Interface Write Timings MOTOROLA MC149571 Advance Information 3-5 MC149571 +RVW,QWHUIDFH5HDG7LPLQJV Table 3-5. Host Interface Read Timings (Host Read from MC149571) No. Characteristics Min Max Units 16 ns 1 Address valid to Data Active 2 Read Enable Cycle Time 35 - ns 3 Read Enable Deassertion Time 3 - ns 4 Read Enable Assertion to Data Active 9 ns 5 Read Data Hold Time w.r.t. Read Enable Deassertion 1 6 ns 6 Previous Write Enable Deassertion to Read Enable Deassertion 35 - ns 7 Read Enable Deassertion to Address Invalid 2 - ns 8 Chip Select to Read Enable Assertion 0.1 - ns 9 Read Enable De-assertion to Chip Select Inactive 2 - ns 8 9 DCS_L Read Address DADDR 7 1 2 DRD_L 3 DWR_L 4 5 DDATA Read Data 6 Figure 3-4. Host Interface Read Timings 3-6 MC149571 Advance Information MOTOROLA MC149571 ,QWHUUXSW7LPLQJV Table 3-6. Periodic Interrupt Latency Timings Max. Host Response Time after an Interrupt Request Minimum Time Between Interrupts Units Request for transmit of encoded bitstream (DBSEIT_L) 9 25.7 s Request for bits transmitted over channel (DINT_L) 1 33 ms Request for incoming bitstream(DINT_L) not limited 25.7 s Frequency Units 13.5 MHz Periodical Interrupts 7KHUHDUHQRGHILQHGOLPLWVIRUQRQSHULRGLFLQWHUUXSWVVXFKDV 8QVXSSRUWHG+RSWLRQV | 8QUHVWULFWHGPRWLRQ9HFWRUV | &30 | 3%IUDPH | $ULWKPHWLFFRGLQJ ++HUURUV | ,QYDOLG3LFWXUH7\SH | ,OOHJDO9DULDEOH/HQJWK&RGH | 0RUHWKDQFRHIILFLHQWVIRUUXQOHQJWKGHFRGH | 8QH[SHFWHGVWDUWFRGH | ,QFRUUHFW0DFUREORFNV %XIIHU8QGHUIORZ2YHUIORZ | %LWVWUHDPUHFHLYHEXIIHU | %LWVWUHDPWUDQVPLWEXIIHU 9LGHR6LJQDO7LPLQJ Table 3-7. Video Timing Clock Signals VIPIXCLK Note: The standard pixel clock used to interface to NTSC/PAL devices is 13.5 MHz. Other pixel clock rates are possible. Contact Motorola for additional information. MOTOROLA MC149571 Advance Information 3-7 MC149571 ... VIPIXCLK VIVSYNCH 7 VICBLANK 3 4 VIY7-VIY0 Y0 Y1 Y2 VIC7-VIC0 Cb0 Cr0 Cb1 Cr1 6 1 5 2 3 Figure 3-5. Input Video Signals Table 3-8. Video Input Timings No. Characteristics Min Max Units 1 VIVSYNCH Set-up Time 3 - ns 2 VIVSYNCH Hold Time 3 -- ns 3 VICBLANK Active and Inactive Set-upTime 6 - ns 4 VICBLANK Hold Time 3 - ns 5 Data Set-up Time 3 - ns 6 Data Hold Time 3 -- ns 7 VIVSYNCH Pulse Width 1 -- PCLK Cycle 3-8 MC149571 Advance Information MOTOROLA 3URJUDPPDELOLW\ 3URJUDPPLQJ5HJLVWHUV 0&KDVSURJUDPPDEOHUHJLVWHUVDVVKRZQLQ)LJXUH7KHUHJLVWHUVSURYLGH V\VWHPFRQILJXUDELOLW\IRUWKHVXSSRUWHGPDMRUYLGHRIXQFWLRQV Device ID 0x00 ID Register RESERVED RC_Config Pre_Config RESERVED Enc_Par1 Enc_Par2 Enc_Par3 BSE_BPP RC_BitXMT RC_FDTM RC_TBOVR RC_AVGQ RC_QOVR RC_Rate Reset 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0a 0x0b 0x0c 0x0d 0x0e 0x0f 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1a 0x1b 0x1c 0x1d 0x1e 0x1f Reserved Encode Register Pre-Processor Register Reserved Encode Register Encode Register Encode Register Encode Register Encode Register Encode Register Encode Register Encode Register Encode Register Encode Register Control Register Reserved Encode Register Encode Register Reserved Reserved Control Register Control Register Control Register Control Register Reserved Reserved Encode Register Encode Register Encode Register Reserved Control Register RESERVED BSE_Num_Bytes BSE_Data RESERVED RESERVED Int_Status Int_Mask Err_Status Err_Mask RESERVED RESERVED RC_Scale RC_ABPF RC_MBPF RESERVED PLL_R_F Figure 4-1. MC149571 Configuration Register Layout MOTOROLA MC149571 Advance Information 4-1 MC149571 3URJUDPPDEOH)HDWXUHV Table 4-1. MC149571 Programmable Features Video Processing Pre-Processing Encoding PLL Programming 4-2 Feature Value Noise Core Filtering On or Off Picture Format to be captured NTSC or PAL Encode Resolution CIF or QCIF Bitstream Syntax H.261 or H.263 BCH Framing On or Off Advanced Prediction Mode (APM) On or Off Freeze Picture Release On or Off Number of GOB Headers Four options: every other, every fourth, all, and none Adjusted Quantization Target 1-31 Minimum Picture Interval 0-31 Intraframe Count 0-31 Channel Bit Rate (0-8191) * 64 Clock Scalability 27 MHz-44 MHz MC149571 Advance Information MOTOROLA 4RUXVDQG0ID[DUHUHJLVWHUHGWUDGHPDUNVRI0RWRUROD,QF Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. 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