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SEMICONDUCTOR TECHNICAL DATA
© 1999MOTOROLA, INC.
Advance Information
This document contains information on a new product. Specifications and information herein are subject to change without notice.
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Figure 1. MC149571 Functional Block Diagram
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Pre-
Processor DCT/iDCT/
Quantizer Motion
Estimator
Bitstream
Encoder
Rate
Control
EDO
DRAM
DSP
Video
In
Host
Interface
Control
System Bus
(32)
Data (8),
(16)
Address (5),
Interrupt (2)
MC149571
ii MC149571 Advance Information MOTOROLA
Table of Contents
Section 1 Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
Section 2 Signal and Packaging I nformation. . . . . . . . . . . . . . . . 2-1
Sect ion 3 Specificat i ons. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
Section 4 Programmability. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1
FOR TECHNICAL ASSISTANCE:
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Data Sheet Conventions
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OVERBAR Used to indicate a signal that is active when pulled low (For example, the RESET
pin is active when low.)
asserted Means that a high true (active high) signal is high or that a low true (active low)
signal is lo w
deasserted Means that a high true (active high) signal is low or that a low true (active low)
signal is high
Examples: Signal/Symbol Logic State Signal State Voltage
PIN True Asserted VIL/VOL
PIN False Deasserted VIH/VOH
PIN True Asserted VIH/VOH
PIN False Deasserted VIL/VOL
Note: Values for VIL, VOL, VIH, and VOH are defined by individual product specifications.
MC149571
MOTOROLA MC149571 Advance Information iii
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MC149571
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MOTOROLA MC149571 Advance Information 1-1
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Table 1-1. MC149571 Functional Signal Groupings
Functional Group Number of
Signals Detailed
Description
Power (VCC_xx) and Ground (GND_xx) 55 Table 1-2
Reset 1 Table 1-3
Phase Lock Loop (PLL) and Clock 2 Table 1-4
Operation Mode Select 3 Table 1-5
Host Interface 18 Table 1-6
Video Input 19 Table 1-7
DRAM Interface 45 Table 1-8
MC149571
1-2 MC149571 Advance Information MOTOROLA
Figure 1-1. MC149571 Signals Identified by Functional Group
MC149571
CLOCKIN PLL/Clock
SYSPLLBP
Operation
Mode Sele ct
MODESEL0
MODESEL1
MODESEL2
Host Interface
DCS_L
DRD_L
DWR_L
DADDR4–DADDR0
DDATA7–DDATA0 8
5
DBSEIT_L
DINT_L
Video In
DRAM
Interface
RRAS_L
RCAS_L
RWR_L
ROE_L
RADDR8–
RDATA31–
9
32
8
8VIY7–VIY0
VIC7–VIC0
VIPIXCLK
VICBLANK
VIVSYNC
Reset
SYSRESET
RADDR0
RDATA0
Power/Ground
VCC_IO
VCC_Q
VCC_A
GND_A
VCC_D
GND_D
18
6
GND_IO/Q 27
MC149571
MOTOROLA MC149571 Advance Information 1-3
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Table 1-2. MC149571 Power and Ground Signals
Signal Name Description
VCC_IO I/O Po wer
VCC_Q Core Power
GND_IO/Q I/O and Core Ground
VCC_A PLL Analog Power
GND_A PLL Analog Ground
VCC_D PLL Digital Power
GND_D PLL Digital Ground
Table 1-3. MC149571 Reset Signal
Signal Name Signal
Type Detailed Description
SYSRESET Input* Chip reset
Note: All inputs are 5 V tolerant.
MC149571
1-4 MC149571 Advance Information MOTOROLA
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Table 1-4. MC149571 PLL and Clock Signals
Signal Name Signal
Type Detailed Description
CLOCKIN Input1Clock input to the on-chip PLL (default = 20 MHz)
SYSPLLBP Input1,2 Asserting this signal bypasses the on-chip PLL. This pin
must be asserted to bypass the PLL before changing the
Operation Mode from Normal to the PLL Programming
Mode.
Notes: 1. All inputs are 5 V tolerant.
2. See Section 1.5 for information about selecting the Operation Mode and its effect on
PLL operation.
Table 1-5. MC149 571 Op eration Mode Signals
Signal Name Signal
Type Detailed Description
MODESEL2–
MODESEL0 Input1The MODESEL signals combine to define eight
operational modes for normal operations and
diagnostics.2,3,4
Notes: 1. All inputs are 5 V tolerant.
2. Only two operation modes are available to users:
• Normal Operation Mode (all three signals = 0), and
• PLL Programming Mode (all three signals = 1).
3. In the Normal Operation Mode, the PLL generates a default internal clock frequency of
2.2 times CLOCKIN. For example, if CLOCKIN = 20 MHz, the internal clock frequency
is 44 MHz.
4. To change the ratio between CLOCKIN and the internal clock, select the PLL
Programming Mode. See the MC149571 Programming Manual for information about
programming the PLL ratio.
MC149571
MOTOROLA MC149571 Advance Information 1-5
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Table 1-6. MC149571 Host Interface Signals
Signal Name Signal
Type Detailed Description
DCS_L Input1Chip select from Embedded Controller
DRD_L Input1Read enable from Embedded Controller
DWR_L Input1Write enable from Embedded Controller
DADDR4–DADDR0 Input1Emedded Controller Address bus
DDATA7–DDATA0 Bidirectional Embedded Controller Interface data bus; 5 V tolerant
DBSEIT_L Output Embedded Controller BSE Interrupt
DINT_L Output Embedded Controller Interrupt
Note: 1. All inputs are 5 V tolerant.
Table 1-7. MC149571 Video Input Signals
Signal Name Signal
Type Detailed Description
VIPIXCLK Input1Pixel clock
VICBLANK Input1C omp osi te BLA NK
VIVSYNC Input1Ve rt ic al Sy nc
VIY7–VIY0 Input1Luma data Y in 4:2:2
VIC7–VIC0 Input1Chroma data Cb/Cr
Note: 1. All inputs are 5 V tolerant.
MC149571
1-6 MC149571 Advance Information MOTOROLA
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Table 1-8. MC149571 DRAM Interface Signals
Signal Name Signal
Type Detailed Description
RRAS_L Output Row address strobe to EDO DRAMs
RCAS_L Output Column address strobe to EDO DRAMs
RWR_L Output Write enable to EDO DRAMs
ROE_L Output Output enable for EDO DRAMs
RADDR8–RADDR0 Output Address bus to EDO DRAMs
RDATA31–RDATA0 Bidirectional Memory data bus (5 V tolerant):
• RDATA7–RDATA0 = Byte 1
• RDATA15–RDATA8 = Byte 2
• RDATA23–RDATA16 = Byte 3
• RDATA31–RDATA24 = Byte 4
MC149571
MOTOROLA MC149571 Advance Information 2-1
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MC149571
2-2 MC149571 Advance Information MOTOROLA
Table 2-1. MC149571 208 PQFP Package Signal List
Pin Name Pin Name Pin Name Pin Name
1 VCC_IO 31 VCC_IO 61 VCC_IO 91 Reserved
2 GND_IO 32 GND_IO 62 DADDR0 92 VCC_IO
3 VIY0 33 Reserved 63 DADDR1 93 GND_IO
4 VIY1 34 Reserved 64 DADDR2 94 Reserved
5 VIY2 35 Reserved 65 DADDR3 95 Reserved
6 VIY3 36 Reserved 66 DADDR4 96 Reserved
7 VIY4 37 Reserved 67 VCC_IO 97 VCC_IO
8 VIY5 38 Reserved 68 GND_IO 98 GND_IO
9 VIY6 39 VCC_IO 69 DDATA0 99 ROE_L
10 VIY7 40 GND_IO 70 DDATA1 100 RWE_L
11 VCC_Q 41 GND_Q 71 DDATA2 101 RRAS_L
12 GND_Q 42 VCC_Q 72 DDATA3 102 VCC_IO
13 GND_IO 43 Reserved 73 VCC_IO 103 GND_IO
14 VCC_IO 44 Reserved 74 GND_IO 104 RADDR0
15 VIC0 45 Reserved 75 DDATA4 105 RADDR1
16 VIC1 46 Reserved 76 DDATA5 106 RADDR2
17 VIC2 47 Reserved 77 DDATA6 107 RADDR3
18 VIC3 48 Reserved 78 DDATA7 108 RADDR4
19 VIC4 49 Reserved 79 VCC_IO 109 RADDR5
20 VIC5 50 Reserved 80 GND_IO 110 RADDR6
21 VIC6 51 VCC_IO 81 GND_Q 111 RADDR7
22 VIC7 52 GND_IO 82 VCC_Q 112 RADDR8
23 VCC_IO 53 GND_IO 83 DBSEIT_L 113 VCC_IO
24 GND_IO 54 GND_IO 84 DINT_L 114 GND_IO
25 Reserved 55 GND_IO 85 DCS_L 115 RDATA0
26 Reserved 56 Reserved 86 VCC_IO 116 RDATA1
27 Reserved 57 Reserved 87 GND_IO 117 RDATA2
28 Reserved 58 VCC_Q 88 DWR_L 118 RDATA3
29 Reserved 59 GND_Q 89 DRD_L 119 RDATA4
30 Reserved 60 GND_IO 90 Reserved 120 RDATA5
MC149571
MOTOROLA MC149571 Advance Information 2-3
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121 RDATA6 144 RDATA23 167 GND_IO 190 Reserved
122 RDATA7 145 RDATA24 168 Reserved 191 Reserved
123 VCC_Q 146 GND_IO 169 Reserved 192 Reserved
124 GND_Q 147 VCC_IO 170 Reserved 193 Reserved
125 RDATA8 148 RDATA25 171 Reserved 194 Reserved
126 RDATA9 149 RDATA26 172 Reserved 195 Reserved
127 RDATA10 150 Reserved 173 Reserved 196 Mode Select 0
128 RDATA11 151 RDATA28 174 Reserved 197 VCC_Q
129 RDATA12 152 RDATA29 175 DDATA4 198 GND_Q
130 RDATA13 153 RDATA30 176 Reserved 199 SYSRESET
131 RDATA14 154 Reserved 177 Reserved 200 Reserved
132 RDATA15 155 RDATA31 178 Reserved 201 SYSPLLBP
133 RCAS_L 156 Mode Select 1 179 GND_A 202 Reserved
134 VCC_IO 157 Mode Select 2 180 VCC_A 203 Reserved
135 GND_IO 158 Reserved 181 CLOCK_IN 204 Reserved
136 RDATA16 159 Reserved 182 VCC_D 205 Reserved
137 RDATA17 160 Reserved 183 GND_D 206 VIPIXCLK
138 RDATA18 161 Reserved 184 Reserved 207 VIVSYNC
139 RDATA19 162 Reserved 185 Reserved 208 VICBLANK
140 RDATA20 163 Reserved 186 Reserved
141 RDATA21 164 Reserved 187 Reserved
142 Reserved 165 Reserved 188 Reserved
143 RDATA22 166 VCC_IO 189 Reserved
Table 2-1. MC149571 208 PQFP Package Signal List (Continued)
Pin Name Pin Name Pin Name Pin Name
MOTOROLA MC149571 Advance Information 3-1
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Table 3-1. Power an d Tempera ture Ratings
Rating Symbol Value Unit
Supply voltage VCC –0.3 to +4.0 V
All input voltage VIN GND to 5.5 V
Operating Temperature Range TA0 to +70 °C
Sto r age Tempera ture T STG –55 to +150 °C
Note: Absolute maximum ratings are stress ratings only and functional operation at the maximum
limits is not guaranteed. S tress beyond the maximum rating may affect device reliability or
cause permanent damage to the device.
Table 3-2. Package Thermal Characteristics
Characteristic Symbol Value Unit
Junction to Ambient Thermal Resistance θJA 32 °C/W
MC149571
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Table 3-3. DC Electrical Characteristics
Characteristics Symbol Min Typ Max Unit
Supply Voltage VCC 3.0 3.3 3.6 V
Input High Voltage VIH 2.0 —5.5V
Input Low Voltage VIL 0—0.8V
Output High Voltage
• DDATA7–DDATA0, RCAS_L (IOH = -8mA)
• RDATA31–RDATA0, RADDR8–RADDR0, ROE_L,
RRAS_L, RWR_L (IOH = -4 mA)
• DBSEIN_L, DINT_L (IOH = -2 mA)
VOH 2.4 — VCC V
Output Low Voltage
• DDATA7–DDATA0, RCAS_L (IOL = 8mA)
• RDATA31–RDATA0, RADDR8–RADDR0, ROE_L,
RRAS_L, RWR_L (IOL = 4 mA)
• DBSEIN_L, DINT_L (IOL = 2 mA)
VOL 0—0.4V
Input Leakage Current (@ 5.5V / Maximum VCC / 0.0V) IIN –10 — 10(1) µA
Input Leakage Current (2) (@ Maximum VCC / 0.0V) IIN –10 — 100 µA
High Impedance Input Current Itsi –10 — 10 µA
Icc in Normal Operation Mode ICC ——450mA
Input Capacitance ——9 pF
MC149571
MOTOROLA MC149571 Advance Information 3-3
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Figure 3-1. Reset Timing
1 ms
CLOCKIN
SYSRESET 22 Cycles (CL OCKI N)
MC149571
3-4 MC149571 Advance Information MOTOROLA
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Figure 3-2. PLL Prog ra m mi ng Timing
000 111 000MODESEL0–
SYSPLLBP
DDATA7–
1 ms or longer
PLL_R_F Value
MODESEL2
DDATA0
MC149571
MOTOROLA MC149571 Advance Information 3-5
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Figure 3- 3. Host Interface Write Timings
Table 3-4. Host Interface Write Timings (Host Writes to MC149571)
No. Characteristics Min
Delay Max
Delay Units
1 Address valid to Write Enable Deassertion 9-ns
2 Write Enable Cycle Time 35 - ns
3 Write Enable Deassertion Time 3-ns
4 Write Data Setup Time w.r.t Write Enable Deassertion 5-ns
5 Write Data Hold Time w.r.t. Write Enable Deassertion 2-ns
6 Previous Read Enable Deassertion to Write Enable Deassertion 35 - ns
7 Write Enable Deassertion to Address Not Valid 2-ns
8 Chip Select to Write Enable Assertio n 0.1 - ns
9 Write Enable Deassertion to Chip Select Inactive 2-ns
DADDR
DWR_L
DRD_L
DDATA
Write Addre ss
Write Data
1
2
3
45
6
7
DCS_L 89
MC149571
3-6 MC149571 Advance Information MOTOROLA
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Figure 3-4. Host Interface Re ad Timings
Table 3-5. Host Interface Read Timings (Host Read from MC149571)
No. Characteristics Min Max Units
1 Address valid to Data Active 16 ns
2 Read Enable Cycle Time 35 - ns
3 Read Enable Deassertion Time 3-ns
4 Read Enable Assertion to Data Active 9ns
5 Read Data Hold Time w.r.t. Read Enable Deassertion 16ns
6 Previous Write Enable Deassertion to Read Enable Deassertion 35 - ns
7 Read Enable Deassertion to Address Invalid 2-ns
8 Chip Select to Read Enable Assertion 0.1 - ns
9 Read Enable De-assertion to Chip Select Inactive 2-ns
DADDR
DRD_L
DWR_L
DDATA
Read Address
Read Data
1
2
3
4
5
6
7
DCS_L 89
MC149571
MOTOROLA MC149571 Advance Information 3-7
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Table 3-6. Periodic Interrupt Latency Timings
Periodical Interrupts
Max. Host
Response Time
after an Interrupt
Request
Minimum Time
Between
Interrupts Units
Request for transmit of encoded bitstream
(DBSEIT_L) 9 25.7 µs
Request for bits transmitted over channel
(DINT_L) 133
ms
Request for incoming bitstream(DINT_L) not limited 25.7 µs
Table 3-7. Video Timing
Clock Signals Frequency Units
VIPIXCLK 13.5 MHz
Note: The standard pixel clock used to interface to NTSC/PAL devices is 13.5 MHz. Other pixel
clock rates are possible. Contact Motorola for additional information.
MC149571
3-8 MC149571 Advance Information MOTOROLA
Figure 3-5. Input Video Signals
Table 3-8. Video Input Timings
No. Characteristics Min Max Units
1 VIVSYNCH Set-up Time 3-ns
2 VIVSYNCH Hold Time 3—ns
3 VICBLANK Active and Inactive Set-upTime 6-ns
4 VICBLANK Hol d Time 3-ns
5 Data Set-up Time 3-ns
6 Data Hold Time 3—ns
7 VIVSYNCH Pulse Width 1 — PCLK
Cycle
VIPIXCLK
VIVSYNCH
VICBLANK
VIY7-VIY0
1
2
3
53
4
6
7
Y0 Y2Y1
VIC7-VIC0 Cb0 Cr0 Cr1
. . .
Cb1
MOTOROLA MC149571 Advance Information 4-1
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Figure 4-1. MC149571 Configurat ion Register Layout
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0a
0x0b
0x0c
0x0d
0x0e
0x0f
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x17
0x18
0x19
0x1a
0x1b
0x1c
0x1d
0x1e
0x1f
RESERVED
RC_Config
Pre_Config
RESERVED
Enc_Par1
Enc_Par2
Enc_Par3
BSE_BPP
RC_BitXMT
RC_FDTM
RC_TBOVR
RC_AVGQ
RC_QOVR
RC_Rate
Reset
RESERVED
BSE_Num_Bytes
BSE_Data
RESERVED
RESERVED
Int_Status
Int_Mask
Err_Status
Err_Mask
RESERVED
RESERVED
RC_Scale
RC_ABPF
RC_MBPF
RESERVED
PLL_R_F
Encode Register
Reserved
Pre-Processor Register
Reserved
Control Register
0x00
Device ID ID Register
Control Register
Control Register
Control Register
Reserved
Reserved
Control Register
Control Register
Reserved
Encode Register
Encode Register
Encode Register
Encode Register
Encode Register
Encode Register
Encode Register
Encode Register
Encode Register
Encode Register
Encode Register
Encode Register
Encode Register
Encode Register
Encode Register
Reserved
Reserved
Reserved
MC149571
4-2 MC149571 Advance Information MOTOROLA
 3URJUDPPDEOH)HDWXUHV
Table 4-1. MC149571 Programmable Features
Video
Processing Feature Value
Pre -Processi ng Noise Core Filte ring On or Off
Picture Format to be captured NTSC or PAL
Encoding Encode Resolution CIF or QCIF
Bitstream Syntax H.261 or H.263
BCH Framing On or Off
Advanced Prediction Mode (APM) On or Off
Freeze Picture Release On or Off
Number of GOB Headers Four options: every other, every fourth, all,
and none
Adjusted Quantization Target 1–31
Minimum Picture Interval 0–31
Intraframe Count 0–31
Channel Bit Rate (0–8191) * 64
PLL Programming Clock Scalability 27 MHz–44 MHz
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81-3-5487-8488
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any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which
may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual
performance may vary over time. All operating parameters, including “Typicals” must be validated for each
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