LTM4675
1
Rev. C
For more information www.analog.com
TYPICAL APPLICATION
FEATURES DESCRIPTION
Dual 9A or Single 18A
µModule Regulator with Digital
Power System Management
The LT M
®
4675 is a dual 9A or single 18A step-down
µModule
®
(micromodule) DC/DC regulator with 40ms
turn-on time. It features remote configurability and
telemetry-monitoring of power management parameters
over PMBus— an open standard I2C-based digital interface
protocol . The LTM4675 is comprised of fast analog
control loops, precision mixed-signal circuitry, EEPROM,
power MOSFETs, inductors and supporting components.
The LTM4675’s 2-wire serial interface allows outputs to be
margined, tuned and ramped up and down at programmable
slew rates with sequencing delay times. Input and output
currents and voltages, output power, temperatures, uptime
and peak values are readable. Custom configuration of
the EEPROM contents is not required. At start-up, output
voltages, switching frequency, and channel phase angle
assignments can be set by pin-strapping resistors. The
LTpowerPlay
®
GUI and DC1613 USB-to-PMBus converter
and demo kits are available.
The LTM4675 is offered in a 16mm × 11.9mm × 3.51mm
BGA package available with SnPb or RoHS compliant
terminal finish.
APPLICATIONS
n Dual, Fast, Analog Loops with Digital Interface for
Control and Monitoring
n Wide Input Voltage Range: 4.5V to 17V
n Output Voltage Range: 0.5V to 5.5V
n ±0.5% Maximum DC Output Error Over Temperature
n ±2.5% Current Readback Accuracy at 9A Load
n 400kHz PMBus-Compliant I2C Serial Interface
n Integrated 16-Bit ∆Σ ADC
n Supports Telemetry Polling Rates Up to 125Hz
n Constant Frequency Current Mode Control
n Parallel and Current Share Multiple Modules
n All 7-Bit Slave Addresses Supported
n Drop-In Pin-Compatible to Dual 13A LTM4676A and
Dual 18A LTM4677
n 16mm × 11.9mm × 3.51mm BGA Package
Readable Data:
n Input and Output Voltages, Currents, and Temperatures
n Running Peak Values, Uptime, Faults and Warnings
n Onboard EEPROM Fault Log Record with ECC
Writable Data and Configurable Parameters:
n Output Voltage, Voltage Sequencing and Margining
n Digital Soft-Start/Stop Ramp
n OV/UV/OT, UVLO, Frequency and Phasing
n System Optimization in Prototype and Production
All registered trademarks and trademarks are the property of their respective owners. Protected
by U.S. Patents including 5408150, 5481178, 5705919, 5929620, 6144194, 6177787, 6580258,
7420359, 8163643. Licensed under U.S. Patent 7000125 and other related patents worldwide.
Dual 9A µModule Regulator with Digital
Interface for Control and Monitoring*
Using PMBus and LTpowerPlay to Monitor Telemetry and Margin
VOUT0/VOUT1 During Load Pattern Tests. 10Hz Polling Rate. 12VIN
22µF
×2
ON/OFF CONTROL
FAULT INTERRUPTS,
POWER SEQUENCING
PWM CLOCK AND
TIME-BASE
SYNCHRONIZATION
VIN
5.75V TO 17V
VOSNS0–
VOUT0,
ADJUSTABLE
UP TO 9A
100µF
×4
VOSNS0+
VOUT0
VIN0
VIN1
SVIN LOAD0
VOUT1,
ADJUSTABLE
UP TO 9A
100µF
×4
I2C/SMBus I/F WITH
PMBus COMMAND SET
TO/FROM IPMI OR OTHER
BOARD MANAGEMENT
CONTROLLER
LOAD1
RUN0
RUN1
WP
*FOR COMPLETE CIRCUIT, SEE FIGURE 61
LTM4675
GND
4675 TA01a
SGND
SCL
SDA
ALERT
VOSNS1
VOUT1
GPIO0
GPIO1
REGISTER WRITE
PROTECTION
SYNC
SHARE_CLK
1.1
1.0
0.9
VOUT0 (V)
VOUT1 (V)
0.8
1.9
1.8
1.7
1.6
036
TIME (s)
Output Voltage Readback, VOUT Margined 7.5% Low
4675 TA01b
9 12
10
5
IOUT0 (A)
IOUT1 (A)
0
10
5
0
036
TIME (s)
Output Current Readback, Varying Load Pattern
4675 TA01c
9 12
1.0
0.5
IIN0 (A)
IIN1 (A)
0
2.0
1.0
0
036
TIME (s)
Input Current Readback
4675 TA01d
9 12
60
57
54
CHANNEL 0 TEMP (°C)
CHANNEL 1 TEMP (°C)
51
60
57
54
51
036
TIME (SEC)
Power Stage Temperature Readback
4675 TA01e
9 12
Click to view associated Video Design Idea.
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LTM4675
2
Rev. C
For more information www.analog.com
TABLE OF CONTENTS
Features ..................................................... 1
Applications ................................................ 1
Typical Application ........................................ 1
Description.................................................. 1
Absolute Maximum Ratings .............................. 3
Order Information .......................................... 3
Pin Configuration .......................................... 3
Electrical Characteristics ................................. 4
Typical Performance Characteristics .................. 11
Pin Functions .............................................. 13
Simplified Block Diagram ............................... 18
Decoupling Requirements ............................... 18
Functional Diagram ...................................... 19
Test Circuits ............................................... 20
Operation................................................... 21
Power Module Introduction .........................................21
Power Module Configurability and Readback Data ......23
Time-Averaged and Peak Readback Data .................... 25
Power Module Overview .............................................28
EEPROM .....................................................................32
Serial Interface ............................................................33
Device Addressing ......................................................33
Fault Detection and Handling ......................................34
Responses to VOUT and IOUT Faults.............................35
Responses to Timing Faults ........................................ 36
Responses to SVIN OV Faults ......................................36
Responses to OT/UT Faults .........................................36
Responses to External Faults .....................................36
Fault Logging ..............................................................37
Bus Timeout Protection ..............................................37
PMBus Command Summary ............................ 38
PMBus Commands ....................................................38
Applications Information ................................ 45
VIN to VOUT Step-Down Ratios .................................... 48
Input Capacitors ..........................................................48
Output Capacitors .......................................................48
Light Load Current Operation ......................................48
Switching Frequency and Phase .................................49
Minimum On-Time Considerations .............................. 51
Variable Delay Time, Soft-Start and Output Voltage
Ramping ................................................................. 51
Digital Servo Mode .....................................................52
Soft Off (Sequenced Off) ............................................53
Undervoltage Lockout .................................................53
Fault Detection and Handling ......................................54
Open-Drain Pins ..........................................................54
Phase-Locked Loop and Frequency Synchronization ..55
RCONFIG Pin-Straps
(External Resistor Configuration Pins) ....................56
Voltage Selection ........................................................56
Connecting the USB to the I2C/SMBus/PMBus
Controller to the LTM4675 In System ..................... 56
LTpowerPlay: An Interactive GUI for Digital Power
System Management ..............................................60
PMBus Communication and Command Processing ....61
Thermal Considerations and Output Current Derating..... 62
EMI Performance ........................................................ 69
Safety Considerations ................................................. 69
Layout Checklist/Example ...........................................69
Typical Applications ...................................... 71
Appendix A ................................................. 77
Similarity Between PMBus, SMBus and
I2C 2-Wire Interface ................................................ 77
Appendix B ................................................. 78
PMBus Serial Digital Interface ....................................78
Appendix C: PMBus Command Details ................ 82
Addressing and Write Protect .....................................82
General Configuration Registers .................................84
On/Off/Margin .............................................................85
PWM Config ...............................................................87
Voltage ........................................................................89
Current ........................................................................92
Temperature ................................................................95
Timing .........................................................................97
Fault Response ...........................................................99
Fault Sharing ............................................................. 106
Scratchpad ................................................................ 108
Identification ............................................................. 108
Fault Warning and Status .......................................... 109
Telemetry .................................................................. 116
NVM (EEPROM) Memory Commands ....................... 120
Package Description ................................... 127
Package Photograph ................................... 129
Package Description ................................... 130
Revision History ........................................ 131
Typical Application ..................................... 132
Design Resources ...................................... 132
Related Parts ............................................ 132
LTM4675
3
Rev. C
For more information www.analog.com
PIN CONFIGURATIONABSOLUTE MAXIMUM RATINGS
Terminal Voltages:
VINn (Note 4), SVIN ..................................... –0.3V to 20V
VOUTn ........................................................... –0.3V to 6V
VOSNS0+, VORB0+, VOSNS1, VORB1, INTVCC .... –0.3V to 6V
RUNn, SDA, SCL, ALERT ........................... –0.3V to 5.5V
FSWPHCFG, VOUTnCFG, VTRIMnCFG, ASEL .. –0.3V to 2.75V
VDD33, GPIOn, SYNC, SHARE_CLK, WP,
COMPna, VOSNS0–, VORB0– ........................ –0.3V to 3.6V
SGND ........................................................ –0.3V to 0.3V
Temperatures
Internal Operating Temperature Range
(Notes 2, 3) ............................................ –40°C to 125°C
Storage Temperature Range .................. –55°C to 125°C
Peak Solder Reflow Package Body Temperature ... 245°C
(Note 1)
VOUT0
1234567
TOP VIEW
8 9
M
L
K
J
H
G
F
E
D
C
B
A
VIN0
SGND
GND
VOUT1 VIN1
BGA PACKAGE
108-LEAD (16mm × 11.9mm × 3.51mm)
TJMAX = 125°C, θJCtop = 5.9°C/W, θJCbottom = 2.1°C/W, θJB = 2.7°C/W,
θJA = 16°C/W
θ VALUES DETERMINED PER JESD51-12
WEIGHT = 1.7 GRAMS
ORDER INFORMATION
PART NUMBER PAD OR BALL FINISH
PART MARKING* PACKAGE
TYPE
MSL
RATING
TEMPERATURE RANGE
(SEE NOTE 2)DEVICE FINISH CODE
LTM4675EY#PBF SAC305 (RoHS) LTM4675Y e1 BGA 4 –40°C to 125°C
LTM4675IY#PBF SAC305 (RoHS) LTM4675Y e1 BGA 4 –40°C to 125°C
LTM4675IY SnPb (63/37) LTM4675Y e0 BGA 4 –40°C to 125°C
• Contact the factory for parts specified with wider operating temperature
ranges. *Pad or ball finish code is per IPC/JEDEC J-STD-609.
• Recommended LGA and BGA PCB Assembly and Manufacturing
Procedures
• LGA and BGA Package and Tray Drawings
LTM4675
4
Rev. C
For more information www.analog.com
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the specified internal
operating temperature range (Note 2). Specified as each individual output channel (Note 4). TA = 25°C, VIN = 12V, RUNn = 5V,
FREQUENCY_SWITCH = 500kHz and VOUTn commanded to 1.000V unless otherwise noted. Configured with factory-default EEPROM
settings and per Test Circuit 1, unless otherwise noted.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VIN Input DC Voltage Test Circuit 1
Test Circuit 2; VIN_OFF < VIN_ON = 4.25V
l
l
5.75
4.5
17
5.75
V
V
VOUTnRange of Output Voltage
Regulation
VOUT0 Differentially Sensed on VOSNS0+/VOSNS0– Pin-Pair;
VOUT1 Differentially Sensed on VOSNS1/SGND Pin-Pair;
Commanded by Serial Bus or with Resistors Present at Start-Up on
VOUTnCFG and/or VTRIMnCFG
l
l
0.5
0.5
5.5
5.5
V
V
VOUTn(DC) Output Voltage, Total
Variation with Line and
Load
(Note 5
VOUTn Low Range (MFR_PWM_MODEn[1] = 1b),
FREQUENCY_SWITCH = 425kHz )
Digital Servo Engaged (MFR_PWM_MODEn[6] = 1b)
Digital Servo Disengaged (MFR_PWM_MODEn[6] = 0b)
l
0.995
0.985
1.000
1.000
1.005
1.015
V
V
Input Specifications
IINRUSH(VIN) Input Inrush Current at
Start-Up
Test Circuit 1, VOUTn =1V, VIN = 12V; No Load Besides Capacitors;
TON_RISEn = 3ms
400 mA
IQ(SVIN) Input Supply Bias Current Forced Continuous Mode, MFR_PWM_MODEn[0] = 1b
RUNn = 5V, RUN1-n = 0V
Shutdown, RUN0 = RUN1 = 0V
40
20
mA
mA
IS(VINn,PSM) Input Supply Current in
Pulse-Skipping Mode
Operation
Pulse-Skipping Mode, MFR_PWM_MODEn[0] = 0b,
IOUTn = 100mA
20 mA
IS(VINn,FCM) Input Supply Current in
Forced-Continuous Mode
Operation
Forced Continuous Mode, MFR_PWM_MODEn[0] = 1b
IOUTn = 100mA
IOUTn = 9A
40
927
mA
mA
IS(VINn,SHUTDOWN) Input Supply Current in
Shutdown
Shutdown, RUNn = 0V 50 µA
Output Specifications
IOUTnOutput Continuous
Current Range
(Note 6) 0 9 A
∆VOUTn(LINE)
VOUTn
Line Regulation Accuracy Digital Servo Engaged (MFR_PWM_MODEn[6] = 1b)
Digital Servo Disengaged (MFR_PWM_MODEn[6] = 0b)
SVIN and VINn Electrically Shorted Together and INTVCC Open Circuit;
IOUTn = 0A, 5.75V ≤ VIN ≤ 17V, VOUT Low Range
(MFR_PWM_MODEn[1] = 1b) FREQUENCY_SWITCH = 425kHz
(Referenced to 12VIN) (Note 5)
l
0.03
0.03
±0.2
%
%/V
∆VOUTn(LOAD)
VOUTn
Load Regulation
Accuracy
Digital Servo Engaged (MFR_PWM_MODEn[6] = 1b)
Digital Servo Disengaged (MFR_PWM_MODEn[6] = 0b)
0A ≤ IOUTn ≤ 9A, VOUT Low Range, (MFR_PWM_MODEn[1] = 1b)
FREQUENCY_SWITCH = 425kHz (Note 5)
l
0.03
0.2
0.5
%
%
VOUTn(AC) Output Voltage Ripple 10 mVP-P
fS (Each Channel) VOUTn Ripple Frequency FREQUENCY_SWITCH Set to 500kHz (0xFBE8) l462.5 500 537.5 kHz
∆VOUTn(START) Turn-On Overshoot TON_RISEn = 3ms (Note 12) 8 mV
tSTART Turn-On Start-Up Time Time from VIN Toggling from 0V to 12V to Rising Edge of GPIOn.
TON_DELAYn = 0ms, TON_RISEn = 3ms,
MFR_GPIO_PROPAGATEn = 0x0100,
MFR_GPIO_RESPONSEn = 0x0000
l35 40 ms
LTM4675
5
Rev. C
For more information www.analog.com
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the specified internal
operating temperature range (Note 2). Specified as each individual output channel (Note 4). TA = 25°C, VIN = 12V, RUNn = 5V,
FREQUENCY_SWITCH = 500kHz and VOUTn commanded to 1.000V unless otherwise noted. Configured with factory-default EEPROM
settings and per Test Circuit 1, unless otherwise noted.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
tDELAY(0ms) Turn-On Delay Time Time from First Rising Edge of RUNn to Rising Edge of GPIOn.
TON_DELAYn = 0ms, TON_RISEn = 3ms,
MFR_GPIO_PROPAGATEn = 0x0100,
MFR_GPIO_RESPONSEn = 0x0000.
VIN Having Been Established for at Least 40ms
l2.75 3.1 3.5 ms
∆VOUTn(LS) Peak Output Voltage
Deviation for Dynamic
Load Step
Load: 0A to 4.5A and 4.5A to 0A at 4.5A/µs, Figure 61 Circuit,
VOUTn = 1V, VIN = 12V (Note 12)
50 mV
tSETTLE Settling Time for
Dynamic Load Step
Load: 0A to 4.5A and 4.5A to 0A at 4.5A/µs, Figure 61 Circuit,
VOUTn = 1V, VIN = 12V (Note 12)
35 µs
IOUTn(OCL_PK) Output Current Limit,
Peak
Cycle-by-Cycle Inductor Peak Current Limit Inception 15.8 A
IOUTn(OCL_AVG)Output Current Limit,
Time Averaged
Time-Averaged Output Inductor Current Limit Inception Threshold,
Commanded by IOUT_OC_FAULT_LIMITn (Note 12)
10.8A; See IO-RB-ACC
Specification (Output Current
Readback Accuracy)
Control Section
VFBCM0 Channel 0 Feedback Input
Common Mode Range
VOSNS0– Valid Input Range (Referred to SGND)
VOSNS0+ Valid Input Range (Referred to SGND)
l
l
–0.1 0.3
5.7
V
V
VFBCM1 Channel 1 Feedback Input
Common Mode Range
SGND Valid Input Range (Referred to GND)
VOSNS1 Valid Input Range (Referred to SGND)
l
l
–0.3 0.3
5.7
V
V
VOUT-RNG0 Full-Scale Command
Voltage, Range 0
(Notes 7, 15)
VOUTn Commanded to 5.500V, MFR_PWM_MODEn[1] = 0b
Resolution
LSB Step Size
5.422
12
1.375
5.576
V
Bits
mV
VOUT-RNG1 Full-Scale Command
Voltage, Range 1
(Notes 7, 15)
VOUTn Commanded to 2.750V, MFR_PWM_MODEn[1] = 1b
Resolution
LSB Step Size
2.711
12
0.6875
2.788
V
Bits
mV
RVOSNS0+VOSNS0+ Impedance to
SGND
0.05V ≤ VVOSNS0+ – VSGND ≤ 5.5V 41 kΩ
RVOSNS1 VOSNS1 Impedance to
SGND
0.05V ≤ VVOSNS1 – VSGND ≤ 5.5V 37 kΩ
tON(MIN) Minimum On-Time (Note 8 ) 45 ns
Analog OV/UV (Overvoltage/Undervoltage) Output Voltage Supervisor Comparators (VOUT_OV/UV_FAULT_LIMIT and VOUT_OV/UV_WARN_LIMIT Monitors)
NOV/UV_COMP Resolution, Output
Voltage Supervisors
(Note 15) 8 Bits
VOV-RNG Output OV Comparator
Threshold Detection
Range
(Note 15)
High Range Scale, MFR_PWM_MODEn[1] = 0b
Low Range Scale, MFR_PWM_MODEn[1] = 1b
1
0.5
5.6
2.7
V
V
VOU-STP Output OV and UV
Comparator Threshold
Programming LSB Step
Size
(Note 15)
High Range Scale, MFR_PWM_MODEn[1] = 0b
Low Range Scale, MFR_PWM_MODEn[1] = 1b
22
11
mV
mV
LTM4675
6
Rev. C
For more information www.analog.com
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the specified internal
operating temperature range (Note 2). Specified as each individual output channel (Note 4). TA = 25°C, VIN = 12V, RUNn = 5V,
FREQUENCY_SWITCH = 500kHz and VOUTn commanded to 1.000V unless otherwise noted. Configured with factory-default EEPROM
settings and per Test Circuit 1, unless otherwise noted.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VOV-ACC Output OV Comparator
Threshold Accuracy
(See Note 14)
2V ≤ VVOSNS0+ – VVOSNS0– ≤ 5.6V, MFR_PWM_MODE0[1] = 0b
1V ≤ VVOSNS0+ – VVOSNS0– ≤ 2.7V, MFR_PWM_MODE0[1] = 1b
0.5V ≤ VVOSNS0+ – VVOSNS0– < 1V, MFR_PWM_MODE0[1] = 1b
2V ≤ VVOSNS1 – VSGND ≤ 5.6V, MFR_PWM_MODE1[1] = 0b
1.5V ≤ VVOSNS1 – VSGND ≤ 2.7V, MFR_PWM_MODE1[1] = 1b
0.5V ≤ VVOSNS1 – VSGND < 1.5V, MFR_PWM_MODE1[1] = 1b
l
l
l
l
l
l
±2
±2
±20
±2
±2
±30
%
%
mV
%
%
mV
VUV-RNG Output UV Comparator
Threshold Detection
Range
(Note 15)
High Range Scale, MFR_PWM_MODEn[1] = 0b
Low Range Scale, MFR_PWM_MODEn[1] = 1b
1
0.5
5.4
2.7
V
V
VUV-ACC Output UV Comparator
Threshold Accuracy
(See Note 14)
2V ≤ VVOSNS0+ – VVOSNS0– ≤ 5.4V, MFR_PWM_MODE0[1] = 0b
1V ≤ VVOSNS0+ – VVOSNS0– ≤ 2.7V, MFR_PWM_MODE0[1] = 1b
0.5V ≤ VVOSNS0+ – VVOSNS0– < 1V, MFR_PWM_MODE0[1] = 1b
2V ≤ VVOSNS1 – VSGND ≤ 5.4V, MFR_PWM_MODE1[1] = 0b
1.5V ≤ VVOSNS1 – VSGND ≤ 2.7V, MFR_PWM_MODE1[1] = 1b
0.5V ≤ VVOSNS1 – VSGND < 1.5V, MFR_PWM_MODE1[1] = 1b
l
l
l
l
l
l
±2
±2
±20
±2
±2
±30
%
%
mV
%
%
mV
tPROP-OV Output OV Comparator
Response Times
Overdrive to 10% Above Programmed Threshold 35 µs
tPROP-UV Output UV Comparator
Response Times
Underdrive to 10% Below Programmed Threshold 50 µs
Analog OV/UV SVIN Input Voltage Supervisor Comparators (Threshold Detectors for VIN_ON and VIN_OFF)
NSVIN-OV/UV-COMP SVIN OV/UV Comparator
Threshold-Programming
Resolution
(Note 15) 8 Bits
SVIN-OU-RANGE SVIN OV/UV Comparator
Threshold-Programming
Range
l4.5 20 V
SVIN-OU-STP SVIN OV/UV Comparator
Threshold-Programming
LSB Step Size
(Note 15) 82 mV
SVIN-OU-ACC SVIN OV/UV Comparator
Threshold Accuracy
9V < SVIN ≤ 20V
4.5V ≤ SVIN ≤ 9V
l
l
±2.5
±225
%
mV
tPROP-SVIN-HIGH-VIN
SVIN OV/UV Comparator
Response Time, High VIN
Operating Configuration
Test Circuit 1, and:
VIN_ON = 9V; SVIN Driven from 8.775V to 9.225V
VIN_OFF = 9V; SVIN Driven from 9.225V to 8.775V
l
l
35
35
µs
µs
tPROP-SVIN-LOW-VIN SVIN OV/UV Comparator
Response Time, Low VIN
Operating Configuration
Test Circuit 2, and:
VIN_ON = 4.5V; SVIN Driven from 4.225V to 4.725V
VIN_OFF = 4.5V; SVIN Driven from 4.725V to 4.225V
l
l
35
35
µs
µs
Channels 0 and 1 Output Voltage Readback (READ_VOUTn)
NVO-RB Output Voltage Readback
Resolution and LSB Step
Size
(Note 15) 16
244
Bits
µV
VO-F/S Output Voltage Full-Scale
Digitizable Range
VRUNn = 0V (Notes 7, 15) 8 V
VO-RB-ACC Output Voltage Readback
Accuracy
Channel 0: 1V ≤ VVOSNS0+ – VVOSNS0– ≤ 5.5V
Channel 0: 0.6V ≤ VVOSNS0+ – VVOSNS0– < 1V
Channel 1: 1V ≤ VVOSNS1 – VSGND ≤ 5.5V
Channel 1: 0.6V ≤ VVOSNS1 – VSGND < 1V
l
l
l
l
Within ±0.5% of Reading
Within ±5mV of Reading
Within ±0.5% of Reading
Within ±5mV of Reading
LTM4675
7
Rev. C
For more information www.analog.com
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the specified internal
operating temperature range (Note 2). Specified as each individual output channel (Note 4). TA = 25°C, VIN = 12V, RUNn = 5V,
FREQUENCY_SWITCH = 500kHz and VOUTn commanded to 1.000V unless otherwise noted. Configured with factory-default EEPROM
settings and per Test Circuit 1, unless otherwise noted.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
tCONVERT-VO-RB Output Voltage Readback
Update Rate
MFR_ADC_CONTROL=0x00 (Notes 9, 15)
MFR_ADC_CONTROL=0x0D (Notes 9, 15)
MFR_ADC_CONTROL=0x05 or 0x09 (Notes 9, 15)
90
27
8
ms
ms
ms
Input Voltage (SVIN) Readback (READ_VIN)
NSVIN-RB Input Voltage Readback
Resolution and LSB Step
Size
(Notes 10, 15) 10
15.625
Bits
mV
SVIN-F/S Input Voltage Full-Scale
Digitizable Range
(Notes 11, 15) 38.91 V
SVIN-RB-ACC Input Voltage Readback
Accuracy
READ_VIN, 4.5V ≤ SVIN ≤ 17V lWithin ±2% of Reading
tCONVERT-SVIN-RB Input Voltage Readback
Update Rate
MFR_ADC_CONTROL=0x00 (Notes 9, 15)
MFR_ADC_CONTROL=0x01 (Notes 9, 15)
90
8
ms
ms
Channels 0 and 1 Output Current (READ_IOUTn), Duty Cycle (READ_DUTY_CYCLEn), and Computed Input Current (MFR_READ_IINn) Readback
NIO-RB Output Current Readback
Resolution and LSB Step
Size
(Notes 10, 12) 10
15.6
Bits
mA
IO-F/S, II-F/S Output Current Full-Scale
Digitizable Range and
Input Current Range of
Calculation
(Note 12) ±40 A
IO-RB-ACC Output Current, Readback
Accuracy
READ_IOUTn, Channels 0 and 1, 0 ≤ IOUTn ≤ 9A,
Forced-Continuous Mode, MFR_PWM_MODEn[0]=1b
lWithin 225mA of Reading
IO-RB(9A) Full Load Output Current
Readback
IOUTn = 9A (Note 12). See Histograms in Typical Performance
Characteristics
9 A
NII-RB Computed Input Current,
Readback Resolution and
LSB Step Size
(Notes 10, 12) 10
1.95
Bits
mA
II-RB-ACC Computed Input Current,
Readback Accuracy,
Neglecting ISVIN
MFR_READ_IINn, Channels 0 and 1, 0 ≤ IOUTn ≤ 9A,
Forced-Continuous Mode, MFR_PWM_MODEn[0]=1b,
MFR_IIN_OFFSETn = 0mA
l
Within 140mA of Reading
tCONVERT-IO-RB Output Current Readback
Update Rate
MFR_ADC_CONTROL=0x00 (Notes 9, 15)
MFR_ADC_CONTROL=0x0D (Notes 9, 15)
MFR_ADC_CONTROL=0x06 or 0x0A (Notes 9, 15)
90
27
8
ms
ms
ms
tCONVERT-II-RB Computed Input Current,
Readback Update Rate
MFR_ADC_CONTROL=0x00 (Notes 9, 15) 90 ms
NDUTY-RB Resolution, Duty Cycle
Readback
(Notes 10, 15) 10 Bits
DRB-ACC Duty Cycle TUE READ_DUTY_CYCLEn, 16.3% Duty Cycle (Note 15) ±3 %
tCONVERT-DUTY-RB Duty Cycle Readback
Update Rate
MFR_ADC_CONTROL=0x00 (Notes 9, 15) 90 ms
Temperature Readback for Channel 0, Channel 1, and Controller (Respectively: READ_TEMPERATURE_10, READ_TEMPERATURE_11,
and READ_TEMPERATURE_2)
TRES-RB Temperature Readback
Resolution
Channel 0, Channel 1, and Controller (Note 15) 0.0625 °C
TRB-CH-ACC(72mV) Channel Temperature
TUE, Switching Action Off
Channels 0 and 1, PWM Inactive, RUNn = 0V,
∆VTSNSna = 72mV
lWithin ±3°C of Reading
LTM4675
8
Rev. C
For more information www.analog.com
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the specified internal
operating temperature range (Note 2). Specified as each individual output channel (Note 4). TA = 25°C, VIN = 12V, RUNn = 5V,
FREQUENCY_SWITCH = 500kHz and VOUTn commanded to 1.000V unless otherwise noted. Configured with factory-default EEPROM
settings and per Test Circuit 1, unless otherwise noted.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
TRB-CH-ACC(ON) Channel Temperature
TUE, Switching Action On
READ_TEMPERATURE_1n, Channels 0 and 1,
PWM Active, RUNn = 5V (Note 12)
Within ±3°C of Reading
TRB-CTRL-ACC(ON) Control IC Die
Temperature TUE,
Switching Action On
READ_TEMPERATURE_2, PWM Active, RUN0 = RUN1 = 5V
(Note 12)
Within ±1°C of Reading
tCONVERT-TEMP-RB Temperature Readback
Update Rate
MFR_ADC_CONTROL=0x00 (Notes 9, 15)
MFR_ADC_CONTROL=0x06 or 0x0A (Notes 9, 15)
90
8
ms
ms
INTVCC Regulator
VINTVCC Internal VCC Voltage No
Load
6V ≤ VIN ≤ 17V 4.8 5 5.2 V
∆VINTVCC(LOAD)
VINTVCC
INTVCC Load Regulation 0mA ≤ IINTVCC ≤ 50mA 0.5 ±2 %
VDD33 Regulator
VVDD33 Internal VDD33 Voltage 3.2 3.3 3.4 V
ILIM(VDD33) VDD33 Current Limit VDD33 Electrically Short-Circuited to GND 70 mA
VVDD33_OV VDD33 Overvoltage
Threshold
(Note 15) 3.5 V
VVDD33_UV VDD33 Undervoltage
Threshold
(Note 15) 3.1 V
VDD25 Regulator
VVDD25 Internal VDD25 Voltage 2.5 V
ILIM(VDD25) VDD25 Current Limit VDD25 Electrically Short-Circuited to GND 50 mA
Oscillator and Phase-Locked Loop (PLL)
fOSC Oscillator Frequency
Accuracy
FREQUENCY_SWITCH = 500kHz (0xFBE8)
250kHz ≤ FREQUENCY_SWITCH ≤ 1MHz (Note 15)
l±7.5
±7.5
%
%
fSYNC PLL SYNC Capture Range (Note 16) l225 1100 kHz
VTH,SYNC SYNC Input Threshold VSYNC Rising (Note 15)
VSYNC Falling (Note 15)
1.5
1
V
V
VOL,SYNC SYNC Low Output
Voltage
ISYNC = 3mA l0.3 0.4 V
ISYNC SYNC Leakage Current in
Frequency Slave Mode
0V ≤ VSYNC ≤ 3.6V
MFR_CONFIG_ALL[4]=1b
l±5 µA
θSYNC-θ0 SYNC-to-Channel 0
Phase Relationship, Lag
from Falling Edge of Sync
to Rising Edge of Top
MOSFET (MT0) Gate
(Note 15)
MFR_PWM_CONFIG[2:0] = 000b, 01Xb
MFR_PWM_CONFIG[2:0] = 101b
MFR_PWM_CONFIG[2:0] = 001b
MFR_PWM_CONFIG[2:0] = 1X0b
0
60
90
120
Deg
Deg
Deg
Deg
θSYNC-θ1 SYNC-to-Channel 1
Phase Relationship, Lag
from Falling Edge of Sync
to Rising Edge of Top
MOSFET (MT1) Gate
(Note 15)
MFR_PWM_CONFIG[2:0] = 011b
MFR_PWM_CONFIG[2:0] = 000b
MFR_PWM_CONFIG[2:0] = 010b, 10Xb
MFR_PWM_CONFIG[2:0] = 001b
MFR_PWM_CONFIG[2:0] = 110b
120
180
240
270
300
Deg
Deg
Deg
Deg
Deg
LTM4675
9
Rev. C
For more information www.analog.com
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the specified internal
operating temperature range (Note 2). Specified as each individual output channel (Note 4). TA = 25°C, VIN = 12V, RUNn = 5V,
FREQUENCY_SWITCH = 500kHz and VOUTn commanded to 1.000V unless otherwise noted. Configured with factory-default EEPROM
settings and per Test Circuit 1, unless otherwise noted.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
EEPROM Characteristics
Endurance (Note 13) 0°C ≤ TJ ≤ 85°C During EEPROM Write Operations (Note 3) l10,000 Cycles
Retention (Note 13) TJ < TJ(MAX), with Most Recent EEPROM Write Operation Having
Occurred at 0°C ≤ TJ ≤ 85°C (Note 3)
l10 Years
Mass_Write Mass Write Operation
Time
Execution of STORE_USER_ALL Command, 0°C ≤ TJ ≤ 85°C
(ATE-Tested at TJ = 25°C) (Notes 3, 13)
440 4100 ms
Digital I/Os
VIH Input High Threshold
Voltage
SCL, SDA, RUNn, GPIOn (Note 15)
SHARE_CLK, WP (Note 15)
1.35
1.8
V
V
VIL Input Low Threshold
Voltage
SCL, SDA, RUNn, GPIOn (Note 15)
SHARE_CLK, WP (Note 15)
0.8
0.6
V
V
VHYST Input Hysteresis SCL, SDA (Note 15) 80 mV
VOL Output Low Voltage SCL, SDA, ALERT, RUNn, GPIOn, SHARE_CLK:
ISINK = 3mA
l
0.3
0.4
V
IOL Input Leakage Current SDA, SCL, ALERT, RUNn: 0V ≤ VPIN ≤ 5.5V
GPIOn and SHARE_CLK: 0V ≤ VPIN ≤ 3.6V
l
l
±5
±2
µA
µA
tFILTER Input Digital Filtering RUNn (Note 15)
GPIOn (Note 15)
10
3
µs
µs
CPIN Input Capacitance SCL, SDA, RUNn, GPIOn, SHARE_CLK, WP (Note 15) 10 pF
PMBus Interface Timing Characteristics
fSMB Serial Bus Operating
Frequency
(Note 15) 10 400 kHz
tBUF Bus Free Time Between
Stop and Start
(Note 15) 1.3 μs
tHD,STA Hold Time After Repeated
Start Condition
Time Period After Which First Clock Is Generated (Note 15) 0.6 µs
tSU,STA Repeated Start Condition
Setup Time
(Note 15) 0.6 μs
tSU,STO Stop Condition Setup
Time
(Note 15) 0.6 μs
tHD,DAT Data Hold Time Receiving Data (Note 15)
Transmitting Data (Note 15)
0
0.3
0.9
µs
µs
tSU,DAT Data Setup Time Receiving Data (Note 15) 0.1 μs
tTIMEOUT_SMB Stuck PMBus Timer
Timeout
Measured from the Last PMBus Start Event:
Block Reads, MFR_CONFIG_ALL[3]=0b (Note 15)
Non-Block Reads, MFR_CONFIG_ALL[3]=0b (Note 15)
MFR_CONFIG_ALL[3]=1b (Note 15)
150
32
250
ms
ms
ms
tLOW Serial Clock Low Period (Note 15) 1.3 10000 μs
tHIGH Serial Clock High Period (Note 15) 0.6 μs
LTM4675
10
Rev. C
For more information www.analog.com
ELECTRICAL CHARACTERISTICS
Note 1: Stresses beyond those listing under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating conditions for extended periods may affect device
reliability and lifetime.
Note 2: The LTM4675 is tested under pulsed-load conditions such that
TJ ≈ TA. The LTM4675E is guaranteed to meet performance specifications
over the 0°C to 125°C internal operating temperature range. Specifications
over the –40°C to 125°C internal operating temperature range are assured
by design, characterization and correlation with statistical process
controls. The LTM4675I is guaranteed to meet specifications over the
full –40°C to 125°C internal operating temperature range. Note that the
maximum ambient temperature consistent with these specifications is
determined by specific operating conditions in conjunction with board
layout, the rated package thermal resistance and other environmental
factors.
Note 3: The LTM4675’s EEPROM temperature range for valid write
commands is 0°C to 85°C. To achieve guaranteed EEPROM data retention,
execution of the “STORE_USER_ALL” command—i.e., uploading RAM
contents to NVM—outside this temperature range is not recommended.
However, as long as the LTM4675’s EEPROM temperature is less than
130°C, the LTM4675 will obey the STORE_USER_ALL command. Only
when EEPROM temperature exceeds 130°C, the LTM4675 will not act
on any STORE_USER_ALL transactions: instead, the LTM4675 NACKs
the serial command and asserts its relevant CML (communications,
memory, logic) fault bits. EEPROM temperature can be queried
prior to commanding STORE_USER_ALL; see the Applications
Informationsection.
Note 4: The two power inputs—VIN0 and VIN1—and their respective power
outputs—VOUT0 and VOUT1—are tested independently in production. A
shorthand notation is used in this document that allows these parameters
to be refered to by “VINn” and “VOUTn”, where n is permitted to take on a
value of 0 or 1. This italicized, subscripted “n” notation and convention
is extended to encompass all such pin names, as well as register names
with channel-specific, i.e., paged data. For example, VOUT_COMMANDn
refers to the VOUT_COMMAND command code data located in Pages 0
and1, which in turn relate to Channels 0 (VOUT0) and Channel 1 (VOUT1).
Registers containing non-page-specific data, i.e., whose data is “global” to
the module or applies to both of the module's Channels lack the italicized,
subscripted “n”, e.g., FREQUENCY_SWITCH.
Note 5: VOUTn(DC) and line and load regulation tests are performed in
production with digital servo disengaged (MFR_PWM_MODEn[6]=0b)
and low VOUTn range selected (MFR_PWM_MODEn[1]) = 1b. The digital
servo control loop is exercised in production (setting MFR_PWM_
MODEn[6] = 1b), but convergence of the output voltage to its final settling
value is not necessarily observed in final test—due to potentially long
time constants involved—and is instead guaranteed by the output voltage
readback accuracy specification. Evaluation in application demonstrates
capability; see the Typical Performance Characteristics section.
Note 6: See output current derating curves for different VIN, VOUT, and TA,
located in the Applications Information section.
Note 7: Even though VOUT0 and VOUT1 are specified for 6V absolute
maximum, the maximum recommended regulation-command voltage is:
5.5V for a high-VOUT range setting of MFR_PWM_MODEn[1]=0b; 2.5V for
a low-VOUT range setting of MFR_PWM_MODEn[1]=1b.
Note 8: Minimum on-time is tested at wafer sort.
Note 9: Data conversion is performed in round-robin (cyclic) fashion.
All telemetry signals are continuously digitized, and reported data is
based on measurements not older than 90ms, typical. Some telemetry
parameters can be digitized at a faster update rate by configuring MFR_
ADC_CONTROL.
Note 10: The following telemetry parameters are formatted in PMBus-
defined “Linear Data Format”, in which each register contains a word
comprised of 5 most significant bits—representing a signed exponent, to
be raised to the power of 2—and 11 least significant bits—representing
a signed mantissa: input voltage (on SVIN), accessed via the READ_VIN
command code; output currents (IOUTn), accessed via the READ_IOUTn
command codes; module input current (IVIN0 + IVIN1 + ISVIN), accessed via
the READ_IIN command code; channel input currents (IVINn + 1/2 • ISVIN),
accessed via the MFR_READ_IINn command codes;and duty cycles of
channel 0 and channel 1 switching power stages, accessed via the
READ_DUTY_CYCLEn command codes. This data format limits the
resolution of telemetry readback data to 10 bits even though the internal
ADC is 16 bits and the LTM4675’s internal calculations use 32-bit words.
Note 11: The absolute maximum rating for the SVIN pin is 20V. Input
voltage telemetry (READ_VIN) is obtained by digitizing a voltage scaled
down from the SVIN pin.
Note 12: These typical parameters are based on bench measurements and
are not production tested.
Note 13: EEPROM endurance and retention are guaranteed by wafer-level
testing for data retention. The minimum retention specification applies
for devices whose EEPROM has been cycled less than the minimum
endurance specification, and whose EEPROM data was written to at
0°C ≤ TJ ≤ 85°C. Downloading NVM contents to RAM by executing
the RESTORE_USER_ALL or MFR_RESET commands is valid over the
entire operating temperature range and does not influence EEPROM
characteristics.
Note 14: Channel 0 OV/UV comparator threshold accuracy for
MFR_PWM_MODE0[1] = 1b tested in ATE at VVOSNS0+ – VVOSNS0– =
0.5V and 2.7V. 1V condition tested at IC-Level, only. Channel 1 OV/UV
comparator threshold accuracy for MFR_PWM_MODE1[1] = 1b tested
in ATE with VVOSNS1-VSGND = 0.5V and 2.7V. 1.5V condition tested at
IC-level, only.
Note 15: Tested at IC-level ATE.
Note 16: PLL SYNC capture range tested with FREQUENCY_SWITCH set to
frequency slave mode (0x0000), with MFR_CONFIG_ALL[4] = 1b, and with
SYNC driven by external clock. Low end of SYNC capture range (225kHz)
verified at VIN = 5.75V and VOUTn = 2.5V. High end of SYNC capture range
(1.1MHz) verified at VIN = 12V and VOUTn = 3.3V.
LTM4675
11
Rev. C
For more information www.analog.com
TYPICAL PERFORMANCE CHARACTERISTICS
Efficiency vs Load Current at 5VIN Efficiency vs Load Current at 8VIN Efficiency vs Load Current at 12VIN
TA = 25°C, 12VIN to 1VOUT, unless otherwise noted.
OUTPUT CURRENT (A)
024
80
90
18
70
65 6810 12 14 16
100
75
85
95
EFFICIENCY (%)
4675 G01
3.3VOUT, 650kHz
2.5VOUT, 650kHz
1.8VOUT, 650kHz
1.5VOUT, 575kHz
1.2VOUT, 500kHz
1.0VOUT, 500kHz
0.9VOUT, 425kHz
OUTPUT CURRENT (A)
024
80
90
18
70
65 6810 12 14 16
100
75
85
95
EFFICIENCY (%)
4675 G02
5.0VOUT, 1MHz
3.3VOUT, 1MHz
2.5VOUT, 1MHz
1.8VOUT, 750kHz
1.5VOUT, 650kHz
1.2VOUT, 575kHz
1.0VOUT, 500kHz
0.9VOUT, 525kHz
Single Phase Single Output
Pulse-Skipping (Discontinuous)
Mode Efficiency,
VIN = SVIN = VINn, INTVCC Open,
MFR_PWM_MODEn[0] = 0b
OUTPUT CURRENT (A)
012
50
70
9
4675 G04
40 345678
90
60
80
12VIN TO 1.5VOUT, 650kHz
EFFICIENCY (%)
Dual Phase Single OutputLoad
Transient Response,12VIN to 1VOUT
Single Phase Single OutputLoad
Transient Response,12VIN to 1VOUT
Dual Phase Single OutputLoad
Transient Response, 5VIN to 1VOUT
VOUT
20mV/DIV
AC-COUPLED
IOUT
10A/DIV
50µs/DIV
FIGURE 27 CIRCUIT AT 12VIN, INTVCC PIN
OPEN CIRCUIT AND VOUT_COMMANDn SET
TO 1.000V. 8A TO 18A LOAD STEP AT 10A/µs
4675 G05
VOUT0
50mV/DIV
AC-COUPLED
IOUT
5A/DIV
40µs/DIV
FIGURE 61 CIRCUIT AT 12VIN
0A TO 5A LOAD STEP AT 5A/µs
4675 G06
VOUT
20mV/DIV
AC-COUPLED
IOUT
10A/DIV
50µs/DIV
FIGURE 27 CIRCUIT AT 5VIN,
VOUT_COMMANDn SET TO 1.000V.
8A TO 18A LOAD STEP AT 10A/µs
4675 G07
Dual Output Concurrent Rail
Start-Up/Shutdown
Dual Output Start-Up/Shutdown
with a Pre-Biased Load
VOUT0,
VOUT1
500mV/DIV
IOUT0
5A/DIV
RUN0, RUN1
5V/DIV
2ms/DIV
FIGURE 61 CIRCUIT AT 12VIN, 112mΩ LOAD
ON VOUT0, NO LOAD ON VOUT1.
TON_RISE0 = 3ms, TON_RISE1 = 5.297ms,
TOFF_DELAY1 = 0ms, TOFF_DELAY0 = 2.43ms,
TOFF_FALL1 = 5.328ms, TOFF_FALL0 = 3ms,
ON_OFF_CONFIGn = 0x1E
4675 G08
VOUT0, VOUT1
500mV/DIV
IDIODE
1mA/DIV
RUN0, RUN1
5V/DIV
2ms/DIV
FIGURE 61 CIRCUIT AT 12VIN, 112mΩ LOAD ON
VOUT0, 500Ω ON VOUT1. VOUT1 PRE-BIASED
THROUGH A DIODE. TON_RISE0 = 3ms,
TON_RISE1 = 5.297ms, TOFF_DELAY1 = 0ms,
TOFF_DELAY0 = 2.43ms, TOFF_FALL1 = 5.328ms,
TOFF_FALL0 = 3ms, ON_OFF_CONFIG1 = 0x1F,
ON_OFF_CONFIG0 = 0x1E
4675 G09
OUTPUT CURRENT (A)
024
80
90
18
70
65 6810 12 14 16
100
75
85
95
EFFICIENCY (%)
4675 G03
5.0VOUT, 1MHz
3.3VOUT, 1MHz
2.5VOUT, 1MHz
1.8VOUT, 750kHz
1.5VOUT, 650kHz
1.2VOUT, 575kHz
1.0VOUT, 500kHz
0.9VOUT, 525kHz
LTM4675
12
Rev. C
For more information www.analog.com
READ_TEMPERATURE_2
(Control IC Temperature Error) vs
Junction Temperature, RUNn = 0V
READ_VIN (Input Voltage
Readback Telemetry) Error vs
SVIN, RUNn = 0V
MFR_READ_IINn (Input Current
Readback) Error vs (IVINn + ISVIN),
MFR_PWM_MODEn[0]=1b,
IOUTn Swept from 0A to 9A, One
Channel at a Time, RUN1-n = 0V
Single Phase Single Output Short-
Circuit Protection at Full Load
READ_VOUTn (Output Voltage
Readback) Error vs VOUTn
IOUTn = No Load, RUN1-n = 0V
READ_IOUTn (Output Current
Readback) Error vs IOUTn
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, 12VIN to 1VOUT, unless otherwise noted.
Single Phase Single Output
Short-Circuit Protection at No Load
ACTUAL TEMPERATURE (°C)
–45
–1.0
MEASUREMENT ERROR (°C)
–0.8
–0.4
–0.2
0
1.0
0.4
–5 35 55
4675 G14
–0.6
0.6
0.8
0.2
–25 15 75 95 115
VOUT0
200mV/DIV
IIN0
1A/DIV
10µs/DIV
FIGURE 61 CIRCUIT AT 12VIN,
NO LOAD ON VOUT0 PRIOR TO APPLICATION
OF SHORT CIRCUIT
4675 G10
VOUT0
200mV/DIV
IIN0
1A/DIV
10µs/DIV
FIGURE 61 CIRCUIT AT 12VIN,
112mΩ LOAD ON VOUT0 PRIOR TO
APPLICATION OF SHORT CIRCUIT
4675 G11
VOUT (V)
0.5
MEASUREMENT ERROR (mV)
0
20
30
4.5
4675 G12
–20
–10
10
–30 1.5 2.5 3.5 5.5
SPECIFIED UPPER LIMIT
SPECIFIED LOWER LIMIT
CHANNEL 0
CHANNEL 1
SVIN (V)
4
–400
MEASUREMENT ERROR (mV)
–200
0
200
400
8 12 16 20
SPECIFIED UPPER LIMIT
SPECIFIED LOWER LIMIT
4675 G15
IINn + ISVIN (A)
0
–160
MEASUREMENT ERROR (mA)
–120
–80
–40
0
120
80
40
160
0.2 0.4 0.6 0.8
4675 G16
1.0
CHANNEL 1
CHANNEL 0
SPECIFIED UPPER LIMIT
SPECIFIED LOWER LIMIT
IOUT (A)
0
–300
MEASUREMENT ERROR (mA)
–200
–100
0
100
CHANNEL 0
CHANNEL 1
200
300
369
SPECIFIED UPPER LIMIT
SPECIFIED LOWER LIMIT
4675 G13
LTM4675
13
Rev. C
For more information www.analog.com
PIN FUNCTIONS
PACKAGE ROW AND COLUMN LABELING MAY VARY
AMONG µModule PRODUCTS. REVIEW EACH PACKAGE
LAYOUT CAREFULLY.
GND (A2-8, B2-7, C2, C4-8, D2, D5, E1, E9, F1, F8, G1,
G8-9, H1, H8-9, J2, J8, K2, K5-8, L2-7, M2-8): Power
Ground of the LTM4675. Power return for VOUT0 and VOUT1.
VOUT0 (A1, B1, C1, D1): Channel 0 Output Voltage.
VOSNS0+ (D7): Channel 0 Positive Differential Voltage Sense
Input. Together, VOSNS0+ and VOSNS0– serve to kelvin-sense
the VOUT0 output voltage at VOUT0’s point of load (POL)
and provide the differential feedback signal directly to
Channel 0’s control loop and voltage supervisor circuits.
VOUT0 can regulate up to 5.5V output. Command VOUT0’s
target regulation voltage by serial bus. Its initial command
value at SVIN power-up is dictated by NVM (non-volatile
memory) contents (factory default: 1.000V)—or, option-
ally, may be set by configuration resistors; see VOUT0CFG,
VTRIM0CFG and the
Applications Information
section.
VOSNS0– (E7): Channel 0 Negative Differential Voltage
Sense Input. See VOSNS0+.
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, 12VIN to 1VOUT, unless otherwise noted.
READ_IOUT of 26 LTM4675s
(DC2053) 12VIN, 1VOUT,
TJ = –40°C, IOUTn = 9A, System
Having Reached Thermally
Steady-State Condition, No Airflow
READ_IOUT of 26 LTM4675s
(DC2053) 12VIN, 1VOUT,
TJ = 25°C, IOUTn = 9A, System
Having Reached Thermally
Steady-State Condition, No Airflow
READ_IOUT of 26 LTM4675s
(DC2053) 12VIN, 1VOUT,
TJ = 125°C, IOUTn = 9A, System
Having Reached Thermally
Steady-State Condition, No Airflow
READ_IOUT CHANNEL READBACK (A)
NUMBER OF CHANNELS
4675 G17
0
2
4
6
8
10
12
14
9.00000
9.03125
9.06250
9.09375
9.12500
9.15625
9.18750
9.21875
9.25000
READ_IOUT CHANNEL READBACK (A)
NUMBER OF CHANNELS
4675 G18
0
2
4
6
8
10
12
14
8.87500
8.90625
8.93750
8.96875
9.00000
9.03125
9.06250
9.09375
9.12500
READ_IOUT CHANNEL READBACK (A)
NUMBER OF CHANNELS
4675 G19
0
2
4
6
8
10
12
14
8.81250
8.84375
8.87500
8.90625
8.93750
8.96875
9.00000
9.03125
9.06250
VORB0+ (D8): Channel 0 Positive Readback Pin. Shorted to
VOSNS0+ internal to the LTM4675. If desired, place a test
point on this node and measure its impedance to VOUT0
on one’s hardware (e.g., motherboard, during in circuit
test (ICT) post-assembly process) to provide a means of
verifying the integrity of the feedback signal connection
between VOSNS0+ and VOUT0.
VORB0– (E8): Channel 0 Negative Readback Pin. Shorted
to VOSNS0– internal to the LTM4675. If desired, place a
test point on this node and measure its impedance to
GND on one’s hardware (e.g., motherboard, during ICT
post-assembly process) to provide a means of verifying
the integrity of the feedback signal connection between
VOSNS0– and GND (VOUT0 power return).
VOUT1 (J1, K1, L1, M1): Channel 1 Output Voltage.
VOSNS1 (H7): Channel 1 Positive Voltage Sense Input.
Connect VOSNS1 to VOUT1 at the POL. This provides the
feedback signal for Channel 1’s control loop and voltage
supervisor circuits. VOUT1 can regulate up to 5.5V output.
Command VOUT1’s target regulation voltage by serial bus.
Its initial command value at SVIN power-up is dictated by
LTM4675
14
Rev. C
For more information www.analog.com
PIN FUNCTIONS
NVM (non-volatile memory) contents (factory default:
1.000V)—or, optionally, may be set by configuration
resistors; see VOUT1CFG, VTRIM1CFG and the Applications
Information section.
SGND (F5-6, G5-6): Channel 1 Negative Voltage Sense Input.
See VOSNS1. Additionally, SGND is the signal ground return
path of the LTM4675. If desired, one may place a test point
on one of the four SGND pins and measure its impedance
to GND on one’s hardware (e.g., motherboard, during ICT
post-assembly process) to provide a means of verifying
the integrity of the feedback signal connection between
the other three SGND pins and GND (VOUT1 power return).
SGND is not electrically connected to GND internal to the
LTM4675. Connect SGND to GND local to the LTM4675.
VORB1 (J7): Channel 1 Positive Readback Pin. Shorted to
VOSNS1 internal to the LTM4675. At one’s option, place
a test point on this node and measure its impedance to
VOUT1 on one’s hardware (e.g., motherboard, during ICT
post-assembly process) to provide a means of verifying
the integrity of the feedback signal connection between
VOUT1 and VOSNS1.
VIN0 (A9, B9, C9, D9): Positive Power Input to Channel 0
Switching Stage. Provide sufficient decoupling capacitance
in the form of multilayer ceramic capacitors (MLCCs) and
low ESR electrolytic (or equivalent) to handle reflected
input current ripple from the step-down switching stage.
MLCCs should be placed as close to the LTM4675 as
physically possible. See Layout Recommendations in the
Applications Information section.
VIN1 (J9, K9, L9, M9): Positive Power Input to Channel
1 Switching Stage. Provide sufficient decoupling capaci-
tance in the form of MLCCs and low ESR electrolytic (or
equivalent) to handle reflected input current ripple from the
step-down switching stage. MLCCs should be placed as
close to the LTM4675 as physically possible. See Layout
Recommendations in the Applications Information section.
SW0 (B8): Switching Node of Channel 0 Step-Down Con-
verter Stage. Used for test purposes or EMI-snubbing. May
be routed a short distance to a local test point to monitor
switching action of Channel 0, if desired, but do not route
near any sensitive signals; otherwise, leave electrically
isolated (open).
SW1 (L8): Switching Node of Channel 1 Step-Down Con-
verter Stage. Used for test purposes or EMI-snubbing. May
be routed a short distance to a local test point to monitor
switching action of Channel 1, if desired, but do not route
near any sensitive signals; otherwise, leave open.
SVIN (F9): Input Supply for LTM4675’s Internal Control IC.
In most applications, SVIN connects to VIN0 and/or VIN1,
in which case no external decoupling beyond that already
allocated for VIN0/VIN1 is required. If SVIN is operated from
an auxiliary supply separate from VIN0/VIN1, decouple this
pin to GND with a capacitor (0.1μF to 1μF).
INTVCC (F7, G7): Internal Regulator, 5V Output. When
operating the LTM4675 from 5.75V ≤ SVIN ≤ 17V, an LDO
generates INTVCC from SVIN to bias internal control circuits
and the MOSFET drivers of the LTM4675. No external
decoupling is required. INTVCC is regulated regardless of
the RUNn pin state. When operating the LTM4675 with
4.5V ≤ SVIN < 5.75V, INTVCC must be electrically shorted
to SVIN.
VDD33 (J5): Internally Generated 3.3V Power Supply
Output Pin. This pin should only be used to provide ex-
ternal current for the pull-up resistors required for GPIOn,
SHARE_CLK, and SYNC, and may be used to provide
external current for pull-up resistors on RUNn, SDA, SCL
and ALERT. No external decoupling is required.
VDD25 (J4): Internally Generated 2.5V Power Supply Output
Pin. Do not load this pin with external current; it is used
strictly to bias internal logic and provides current for the
internal pull-up resistors connected to the configuration-
programming pins. No external decoupling is required.
ASEL (G2): Serial Bus Address Configuration Pin. On any
given I2C/SMBus serial bus segment, every device must
have its own unique slave address. If this pin is left open,
the LTM4675 powers up to its default slave address of
0x4F (hexadecimal), i.e., 1001111b (industry standard
convention is used throughout this document: 7-bit
slave addressing). The lower four bits of the LTM4675’s
slave address can be altered from this default value by
connecting a resistor from this pin to SGND. Minimize
capacitance—especially when the pin is left open—to
assure accurate detection of the pin state.
LTM4675
15
Rev. C
For more information www.analog.com
PIN FUNCTIONS
FSWPHCFG (H2): Switching Frequency, Channel Phase-
Interleaving Angle and Phase Relationship to SYNC
Configuration Pin. If this pin is left open—or, if the LTM4675
is configured to ignore pin-strap (RCONFIG) resistors,
i.e., MFR_CONFIG_ALL[6] = 1b—then the LTM4675’s
switching frequency (FREQUENCY_SWITCH) and channel
phase relationships (with respect to the SYNC clock;
MFR_PWM_CONFIG[2:0]) are dictated at SVIN power-
up according to the LTM4675’s NVM contents. Default
factory values are: 500kHz operation; Channel 0 at 0°; and
Channel 1 at 180°C (convention throughout this document:
a phase angle of 0° means the channel’s switch node
rises coincident with the falling edge of the SYNC pulse).
Connecting a resistor from this pin to SGND (and using the
factory-default NVM setting of MFR_CONFIG_ALL[6] = 0b)
allows a convenient way to configure multiple LTM4675s
with identical NVM contents for different switching frequen-
cies of operation and phase interleaving angle settings of
intra- and extra-module-paralleled channels—all, without
GUI intervention or the need to “custom pre-program”
module NVM contents. (See the Applications Information
section.) Minimize capacitance—especially when the pin
is left open—to assure accurate detection of the pin state.
VOUT0CFG (G3): Output Voltage Select Pin for VOUT0,
Coarse Setting. If the VOUT0CFG and VTRIM0CFG pins are
both left open—or, if the LTM4675 is configured to ignore
pin-strap (RCONFIG) resistors, i.e., MFR_CONFIG_ALL[6]
= 1b—then the LTM4675’s target VOUT0 output voltage
setting (VOUT_COMMAND0) and associated power-
good and OV/UV warning and fault thresholds are
dictated at SVIN power-up according to the LTM4675’s
NVM contents. A resistor* connected from this pin to
SGND—in combination with resistor pin settings on
VTRIM0CFG, and using the factory-default NVM setting
of MFR_CONFIG_ALL[6] = 0b—can be used to config-
ure the LTM4675’s Channel 0 output to power-up to a
VOUT_COMMAND value (and associated output voltage
monitoring and protection/fault-detection thresholds)
different from those of NVM contents. (See the Applications
Information section.) Connecting resistor(s) from VOUT0CFG
to SGND and/or VTRIM0CFG to SGND in this manner
allows a convenient way to configure multiple LTM4675s
with identical NVM contents for different output voltage
settings—all without GUI intervention or the need to
“custom-pre-program” module NVM contents. Minimize
capacitance—especially when the pin is left open—to
assure accurate detection of the pin state. Note that use of
RCONFIGs* on VOUT0CFG/VTRIM0CFG can affect the VOUT0
range setting (MFR_PWM_MODE0[1]) and loop gain.
VTRIM0CFG (H3): Output Voltage Select Pin for VOUT0, Fine
Setting. Works in combination with VOUT0CFG to affect
the VOUT_COMMAND (and associated output voltage
monitoring and protection/fault-detection thresholds)
of Channel0, at SVIN power-up. (See VOUT0CFG and the
Applications Information section.) Minimize capacitance—
especially when the pin is left open—to assure accurate
detection of the pin state. Note that use of RCONFIGs*
on VOUT0CFG/VTRIM0CFG can affect the VOUT0 range setting
(MFR_PWM_MODE0[1]) and loop gain.
VOUT1CFG (G4): Output Voltage Select Pin for VOUT1,
Coarse Setting. If the VOUT1CFG and VTRIM1CFG pins are
both left open—or, if the LTM4675 is configured to ignore
pin-strap (RCONFIG) resistors, i.e., MFR_CONFIG_ALL[6]
= 1b—then the LTM4675’s target VOUT1 output voltage
setting (VOUT_COMMAND1) and associated OV/UV
warning and fault thresholds are dictated at SVIN power-up
according to the LTM4675’s NVM contents, in precisely
the same fashion that the VOUT0CFG and VTRIM0CFG pins
affect the respective settings of VOUT0 /Channel 0. (See
VOUT0CFG, VTRIM0CFG and the Applications Information
section.) Minimize capacitance—especially when the pin
is left open—to assure accurate detection of the pin state.
Note that use of RCONFIGs* on VOUT1CFG/VTRIM1CFG can
affect the VOUT1 range setting (MFR_PWM_MODE1[1])
and loop gain.
VTRIM1CFG (H4): Output Voltage Select Pin for VOUT1, Fine
Setting. Works in combination with VOUT1CFG to affect
the VOUT_COMMAND (and associated output voltage
monitoring and protection/fault-detection thresholds)
of Channel1, at SVIN power-up. (See VOUT1CFG and the
Applications Information section.) Minimize capacitance—
especially when the pin is left open—to assure accurate
detection of the pin state. Note that use of RCONFIGs*
on VOUT1CFG/VTRIM1CFG can affect the VOUT1 range setting
(MFR_PWM_MODE1[1]) and loop gain.
*In applications where VOUT0 and VOUT1 are paralleled, the respective VOUTnCFG and VTRIMnCFG
pin-pairs can be electrically connected together; common RCONFIG resistors can be applied,
whose values are half of what is prescribed in Table 2 and Table 3. See Figure 34, for example.
LTM4675
16
Rev. C
For more information www.analog.com
PIN FUNCTIONS
SYNC (E5): PWM Clock Synchronization Input and Open-
Drain Output Pin. The setting of the FREQUENCY_SWITCH
command dictates whether the LTM4675 is a “sync master”
or “sync slave” module. When the LTM4675 is a sync
master, FREQUENCY_SWITCH contains the commanded
switching frequency of Channels 0 and 1—in PMBus
linear data format—and it drives its SYNC pin low for
500ns at a time, at this commanded rate. In contrast, a
sync slave uses MFR_CONFIG_ALL[4]=1b and does not
pull its SYNC pin low. The LTM4675’s PLL synchronizes
the LTM4675’s PWM clock to the waveform present on
the SYNC pin—and therefore, a resistor pull-up to 3.3V
is required in the application, regardless of whether the
LTM4675 is a sync master or slave. EXCEPTION: driving
the SYNC pin with an external clock is permissible; see
the Applications Information section for details.
SCL (E4): Serial Bus Clock Open-Drain Input (Can Be
an Input and Output, if Clock Stretching is Enabled). A
pull-up resistor to 3.3V is required in the application
for digital communication to the SMBus master(s) that
nominally drive this clock. The LTM4675 will never
encounter scenarios where it would need to engage clock
stretching unless SCL communication speeds exceed
100kHz—and even then, LTM4675 will not clock stretch
unless clock stretching is enabled by means of setting
MFR_CONFIG_ALL[1] = 1b. The factory-default NVM
configuration setting has MFR_CONFIG_ALL[1] = 0b:
clock stretching disabled. If communication on the bus at
clock speeds above 100kHz is required, the user’s SMBus
master(s) need to implement clock stretching support to
assure solid serial bus communications, and only then
should MFR_CONFIG_ALL[1] be set to 1b. When clock
stretching is enabled, SCL becomes a bidirectional, open-
drain output pin on LTM4675.
SDA (D4): Serial Bus Data Open-Drain Input and Output.
A pull-up resistor to 3.3V is required in the application.
ALERT (E3): Open-Drain Digital Output. A pull-up resistor
to 3.3V is required in the application only if SMBALERT
interrupt detection is implemented in one’s SMBus system.
SHARE_CLK (H5): Share Clock, Bidirectional Open-
Drain Clock Sharing Pin. Nominally 100kHz. Used for
synchronizing the time base between multiple LTM4675s
(and any other Analog Devices devices with a SHARE_CLK
pin)—to realize well-defined rail sequencing and rail
tracking. Tie the SHARE_CLK pins of all such devices
together; all devices with a SHARE_CLK pin will synchronize
to the fastest clock. A pull-up resistor to 3.3V is required
when synchronizing the time base between multiple
devices. If synchronizing the time base between multiple
devices is not needed and MFR_CHAN_CONFIGn[2]=0b,
only then is a pull-up resistor not required.
GPIO0, GPIO1 (E2 and F2, Respectively):
Digital,
Programmable General Purpose Inputs and Outputs.
Open-drain outputs and/or high impedance inputs. The
LTM4675’s factory-default NVM configurations for
MFR_GPIO_PROPAGATEn—0x6893—and MFR_GPIO_
RESPONSEn—0xC0—are such that: (1) when a channel-
specific fault condition is detected—such as channel OT
(overtemperature) or output UV/OV—the respective GPIOn
pin pulls logic low; (2) when a non-channel specific fault
condition is detected—such as input OV or control IC
OT—both GPIOn pins pull logic low; (3) the LTM4675
ceases switching action on Channel 0 and 1 when its
respective GPIOn pin is logic low. Most significantly, this
default configuration provides for graceful integration and
inter-operation of LTM4675 with paralleled channel(s) of
other LTM4675(s)—in terms of properly coordinating
efforts in starting, ceasing, and resuming switching
action and output voltage regulation, in unison—all
without GUI intervention or the need to “custom-
preprogram” module NVM contents. Pull-up resistors
from GPIOn to 3.3V are required for proper operation in
the vast majority of applications. (Only if the LTM4675’s
MFR_GPIO_RESPONSEn value were set to 0x00 might
pull-ups be unnecessary. See the Applications Information
section for details.)
LTM4675
17
Rev. C
For more information www.analog.com
PIN FUNCTIONS
WP (K4): Write Protect Pin, Active High. An internal
10μA current source pulls this pin to VDD33. If WP is
open circuit or logic high, only I2C writes to PAGE,
OPERATION, CLEAR_FAULTS, MFR_CLEAR_PEAKS and
MFR_EE_UNLOCK are supported. Additionally, individual
faults can be cleared by writing 1b’s to bits of interest in
registers prefixed with “STATUS”. If WP is low, I2C writes
are unrestricted.
RUN0, RUN1 (F3 and F4, Respectively): Enable Run Input
for Channels 0 and 1, Respectively. Open-drain input and
output. Logic high on these pins enables the respective
outputs of the LTM4675. These open-drain output pins
hold the pin low until the LTM4675 is out of reset and
SVIN is detected to exceed VIN_ON. A pull-up resistor to
3.3V is required in the application. Do not pull RUN logic
high with a low impedance source.
TSNS0 (C3 and D3): Temperature Sensor Node for Chan-
nel0. Pads C3 and D3 are connected to each other inter-
nal to the module. It is permissible to leave these pads
electrically open circuit and to only solder these pins to
mounting pads on the PC board for mechanical integrity
purposes. However, it is acceptable to electrically connect
C3 to D3 on the PC board.
TSNS1a, TSNS1b (J3 and K3, Respectively): Channel 1
Temperature Excitation/Measurement and Thermal Sensor
Pins, Respectively. In most applications, connect TSNS1a
to TSNS1b. This allows the LTM4675 to monitor the Power
Stage Temperature of Channel 1. See the
Applications
Information
section for information on how to use TSNS1a
to monitor a temperature sensor external to the module,
e.g., a PN junction on the die of a microprocessor.
COMP0a, COMP1a (E6 and H6, Respectively): Current
Control Threshold and Error Amplifier Compensation Nodes
for Channels 0 and 1, Respectively. The trip threshold
of each channel’s current comparator increases with a
respective rise in COMPna voltage. Small filter capacitors
(22pF) internal to the LTM4675 on these COMP pins (ter-
minated to SGND) introduce high frequency roll off of the
error-amplifier response, yielding good noise rejection in
the control loop. See COMP0b/COMP1b.
COMP0b, COMP1b (D6 and J6, Respectively): Internal
Loop Compensation Networks for Channels 0 and 1, Re-
spectively. For the vast majority of applications, the internal,
default loop compensation of the LTM4675 is suitable to
apply “as is”, and yields very satisfactory results: apply the
default loop compensation to the control loops of Chan-
nels 0 and 1 by simply connecting COMP0a to COMP0b
and COMP1a to COMP1b, respectively. In contrast, when
more specialized applications require a personal touch the
optimization of control loop response, this can be easily
accomplished by connecting (an) R-C network(s) from
COMP0a and/or COMP1a—terminated to SGND—and
leaving COMP0b and/or COMP1b open, as desired.
LTM4675
18
Rev. C
For more information www.analog.com
SIMPLIFIED BLOCK DIAGRAM
DECOUPLING REQUIREMENTS
Figure 1. Simplified LTM4675 Block Diagram
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
CINH External High Frequency Input Capacitor Requirement
(5.75V ≤ VIN ≤ 17V, VOUTn Commanded to 1.000V)
IOUT0 = 9A, 2 × 22μF, or 3 × 10μF
IOUT1 = 9A, 2 × 22μF, or 3 × 10μF
30 44 µF
COUTnHF External High Frequency Output Capacitor Requirement
(5.75V ≤ VIN ≤ 17V, VOUTn Commanded to 1.000V)
IOUT0 = 9A
IOUT1 = 9A
400
400
µF
µF
TA = 25°C. Using Figure 1 configuration.
+
+
VIN0
VOUT0
VIN
5.75V TO 17V
SW0
GND
TSNS0
VOSNS0+
VORB0+
VOSNS0–
LOCAL
HIGH
FREQ
MLCCs
x1
VORB0–
COMP0a
COMP0b
VOUT1
SW1
GND
TSNS1b
TSNS1a
VOSNS1[+]
SGND [VOSNS1–]
COMP1a
CONTROLLER SIGNAL GND
COMP1b
SYNC
ASEL
4675 F01
VDD25
VOUT0CFG
VTRIM0CFG
VTRIM1CFG
VOUT1CFG
FSWPHCFG
SCL
5V TOLERANT; PULL-UP
RESISTORS NOT SHOWN
5V TOLERANT; PULL-UP
RESISTORS NOT SHOWN
3.3V TOLERANT; PULL-UP
RESISTOR NOT NEEDED
SDA
ALERT
WP
RUN0
RUN1
GPIO0
GPIO1
SHARE_CLK
COUT0LF COUT1LF COUT1HF
COUT0HF
VOUT0
ADJUSTABLE
UP TO 5.5V
UP TO 9A
SVIN
1µF 1µF
MT0
360nH 360nH
THERMAL
SENSOR
THERMAL
SENSOR
MB0
MT1
MB1
2.2µF 2.2µF
INTVCC VDD33 VIN1
CINH
CINL
THERMAL
SENSOR
ANALOG
READBACK
SIGNALS
TO ERROR
AMPLIFIER
POWER CONTROL
ANALOG SECTION
POWER MANAGEMENT
DIGITAL SECTION
+
–
LOAD0
LOCAL
HIGH
FREQ
MLCCs
LOAD1
+
VORB1[+]
VOUT1
ADJUSTABLE
UP TO 5.5V
UP TO 9A
INTERNAL
COMP
SPI
SLAVE
SPI
MASTER
SYNC
DRIVER
OSC
(32MHz)
DIGITAL ENGINE
EEPROM
ROM
RAM
INTERNAL
COMP
ADC
3.3V TOLERANT; PULL-UP
RESISTORS NOT SHOWN
3.3V TOLERANT; PULL-UP
RESISTOR NOT SHOWN
CONFIGURATION
RESISTORS TERMINATING
TO SGND NOT SHOWN
LTM4675
19
Rev. C
For more information www.analog.com
FUNCTIONAL DIAGRAM
+
VIN0
CINH
CINL
+
COUT0LF
(Computed Total Input Current, IVINO + IVIN1 + ISVIN: READ_IIN)
(Computed Channel 0 Input Current, IVIN0 + 1/2 • ISVIN: MFR_READ_IIN0) (Computed Channel 1 Input Current, IVIN1 + 1/2 • ISVIN: MFR_READ_IIN1)
VIN
5.75V TO 17V
(SVIN Telemetry:
READ_VIN and MFR_VIN_PEAK)
(PWM0 Telemetry:
READ_DUTY_CYCLE0)
(PWM1 Telemetry:
READ_DUTY_CYCLE1)
(IOUT0 Telemetry: READ_IOUT0
and MFR_IOUT_PEAK0)
(IOUT1 Telemetry: READ_IOUT1
and MFR_IOUT_PEAK1)
Channel 0 Thermal Sensor
(Telemetry: READ_TEMPERATURE_10
and MFR_TEMPERATURE_1_PEAK0)
Channel 1 Thermal Sensor
(Telemetry: READ_TEMPERATURE_11
and MFR_TEMPERATURE_1_PEAK1)
+
+ + ––
–
SVIN INTVCC VDD33 VIN1
INT
FILTER
MT0 MT1
MB1
MB0
POWER CONTROL
ANALOG SECTION
VOUT0
GND
COUT0HF COUT1LF COUT1HF
VOUT0
ADJUSTABLE
UP TO 5.5V
UP TO 9A
VOUT1
ADJUSTABLE
UP TO 5.5V
UP TO 9A
SW0
ZISNS0b–
VOUT1
GND
SW1
ZISNS0b+
TSNS0
∆ISNS0, Channel 0 Current Sense Signal Channel 1 Current Sense Signal, ∆ISNS1
Channel 1 (VOUT1) Voltage Feedback Signal
(Differential when Terminating SGND at LOAD1 as Shown)
∆VOSNS0, Differential Feedback Signal
Channel 0 (VOUT0) Voltage Feedback Signal
Channel 0 Current Demand Signal
Channel 1 Current Demand Signal
Channel 0 Internal Loop Compensation
Channel 1 Internal Loop Compensation
Power Controller Thermal Sensor
(Telemetry: READ_TEMPERATURE_2)
ZISNS0a
ZCOMP0b
TSNS1b
TSNS1a
VORB1[+]
VOSNS0+
VORB0+
VOSNS0–
VOSNS1[+]
SGND [VOSNS1–]
VORB0–
COMP0a
COMP0b
SCL
SDA
WP
RUN0
RUN1
GPIO0
GPIO1
SHARE_CLK
ALERT
COMP1a
COMP1b
TMUX
2µA 30µA
CURRENT MODE
PWM CTRL. LOOPS,
LIN. REGULATORS,
DACs ADC, UV/OV
COMPARATORS,
VCO AND PLL,
MOSFET DRIVERS
AND POWER
SWITCH LOGIC
+
–
∆VOSNS0
VOSNS1
∆ISNS0a
∆ISNS1a
SVIN÷39
PWM0
PWM1
8:1 MUX
VTSNS
DACs, OV/UV
Comparators,
Other
POWER MANAGEMENT
DIGITAL SECTION
DIGITAL ENGINE, INCLUDING:
ROM, RAM, NVM AND OSCILLATOR
16-BIT
ADC SPI
SLAVE
R
R
TO E/A
22pF
22pF
1nF + 20kΩ
1nF + 20kΩ
A = 1
R
R
LOCAL
HIGH
FREQ
MLCCs
LOCAL
HIGH
FREQ
MLCCs
(VOUT0 Telemetry:
READ_VOUT0 and
MFR_VOUT_PEAK0)
(VOUT1 Telemetry:
READ_VOUT1 and
MFR_VOUT_PEAK1)
(LOAD0 Power Consumption
Telemetry: READ_POUT0)
LOAD0
ZCOMP1b
+
ZISNS1a
(LOAD1 Power Consumption
Telemetry: READ_POUT1)
LOAD1
Controller Signal GND
(Switching Frequency Telemetry:
READ_FREQUENCY) SYNC
VDD25
ASEL
FSWPHCFG
VOUT0CFG
VTRIM0CFG
Configuration
Resistors Terminating
to SGND Not Shown
VOUT1CFG
VTRIM1CFG
4675 FD
14.3k
×6
3.3V Tolerant; Pull-Up
Resistor Not Shown
SPI
MASTER
DIGITAL ENGINE, MAIN CONTROL
EEPROMRAM
SYNC
DRIVER
ROM
PROGRAM
VDD33
COMPARE
I2C-BASED SMBus
INTERFACE WITH PMBus
COMMAND SET
(10kHz TO 400kHz
COMPATIBLE)
CHANNEL TIMING
MANAGEMENT
UVLO
OSC
(32MHz)
CONFIG
DETECT
SINC3
VDD33
VDD33
10µA
5V Tolerant; Pull-Up
Resistors Not Shown
5V Tolerant; Pull-Up
Resistors Not Shown
3.3V Tolerant; Pull-Up
Resistor Not Needed
3.3V Tolerant; Pull-Up
Resistors Not Shown
ZISNS1b–
ZISNS1b+
LTM4675
20
Rev. C
For more information www.analog.com
TEST CIRCUITS
Test Circuit 1. LTM4675 ATE High V
IN
Operating Range Configuration, 5.75V ≤ VIN ≤ 17V
CINH
10µF
×6
CINL
150µF
VIN
5.75V TO 17V COUTH0
100µF
×4
VOUT0
1V ADJUSTABLE
UP TO 9A
VOUT1
1V ADJUSTABLE
UP TO 9A
VIN0
VIN1
SVIN
VDD33
SCL
SDA
ALERT
RUN0
RUN1
GPIO0
GPIO1
SYNC
SHARE_CLK
WP
VOUT0
TSNS0
VORB0+
VOSNS0+
VOSNS0–
VORB0–
VORB1
VOUT1
TSNS1a
TSNS1b
VOSNS1
SGND
INTVCC
VDD25
SW0
SW1
COMP0a
COMP0b
COMP1a
COMP1b
ASEL
FSWPHCFG
VOUT0CFG
VTRIM0CFG
VOUT1CFG
VTRIM1CFG
GND
+COUTL0
OPT*
+
COUTL1
OPT*
+
LOAD0
COUTH1
100µF
×4
LTM4675
LOAD1
SMBus INTERFACE WITH
PMBus COMMAND SET
ON/OFF CONTROL,
FAULT MANAGEMENT AND
POWER SEQUENCING
PWM CLOCK SYNCH
TIME BASE SYNCH
(PULL-UP RESISTORS ON DIGITAL
I/O PINS NOT SHOWN)
RTH1
30.1k *COUTL0, COUTL1 NOT USED IN ATE TESTING
RTH0
30.1k
4675 TC01
CTH1
470pF
CTH0
470pF
Test Circuit 2. LTM4675 ATE Low V
IN
Operating Range Configuration, 4.5V ≤ VIN ≤ 5.75V
RTH1
30.1k *COUTL0, COUTL1 NOT USED IN ATE TESTING
RTH0
30.1k
CTH1
470pF
CTH0
470pF
CINH
10µF
×6
CINL
150µF
VIN
4.5V TO 5.75V COUTH0
100µF
×4
VOUT0
1V ADJUSTABLE
UP TO 9A
VOUT1
1V ADJUSTABLE
UP TO 9A
VIN0
VIN1
SVIN
VDD33
SCL
SDA
ALERT
RUN0
RUN1
GPIO0
GPIO1
SYNC
SHARE_CLK
WP
INTVCC
VDD25
SW0
SW1
COMP0a
COMP0b
COMP1a
COMP1b
ASEL
FSWPHCFG
VOUT0CFG
VTRIM0CFG
VOUT1CFG
VTRIM1CFG
GND
+
LOAD0
COUTH1
100µF
×4
LTM4675
LOAD1
SMBus INTERFACE WITH
PMBus COMMAND SET
ON/OFF CONTROL,
FAULT MANAGEMENT AND
POWER SEQUENCING
PWM CLOCK SYNCH
TIME BASE SYNCH
(PULL-UP RESISTORS ON DIGITAL
I/O PINS NOT SHOWN)
4675 TC02
COUTL0
OPT*
+
COUTL1
OPT*
+
VOUT0
TSNS0
VORB0+
VOSNS0+
VOSNS0–
VORB0–
VORB1
VOUT1
TSNS1a
TSNS1b
VOSNS1
SGND
LTM4675
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Rev. C
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OPERATION
POWER MODULE INTRODUCTION
The LTM4675 is a highly configurable dual 9A output
standalone nonisolated switching mode step-down
DC/DC power supply with built-in EEPROM NVM (non-
volatile memory) with ECC and I2C-based PMBus/SMBus
2-wire serial communication interface capable of 400kHz
SCL bus speed. Tw o output voltages can be regulated (VOUT0,
VOUT1—collectively, VOUTn) with a few external input and
output capacitors and pull-up resistors. Readback telemetry
data of average input and output voltages and currents,
Channel PWM duty cycles, and module temperatures are
continually digitized cyclically by an integrated 16-bit ADC
(analog-to-digital converter). Many fault thresholds and
responses are customizable. Data can be autonomously
saved to EEPROM when a fault occurs, and the resulting
fault log can be retrieved over I2C at a later time, for analysis.
The LTM4675 provides precisely regulated output voltages
between 0.6VDC to 5.5VDC (±0.5% above 1VDC, ±5mV below
1VDC). The target output voltage can be set according to pin-
strapping resistors (VOUTnCFG and VTRIMnCFG pins), NVM/
register settings, and altered on the fly via the I2C interface.
The output voltage can be modified by the user at any time
with a write to PMBus VOUT_COMMAND. Executing this
command has a typical latency less than 10ms. Writes to
PMBus OPERATION have a typical latency less than 1ms.
The NVM factory-default switching frequency is 500kHz and
the phase-interleaving angle between its two channels is
180°. Channel switching frequency, phase angle, and phase
relationship with respect to the falling edge of the SYNC pin
waveform can be configured according to a pin-strap resistor
(FSWPHCFG pin) and NVM/register settings—though, not on the
fly during regulation. The 7-bit I2C slave address of the module
defaults to the value retrieved from MFR_ADDRESS[6:0] at
power-up (factory default: 0x4F), but the least significant
four bits of the address are set by resistor pin-strapping the
ASEL pin. Bits[6:4] of MFR_ADDRESS can be written and
stored to EEPROM. Between the ASEL resistor pin-strap and
user-configurable MFS_ADDRESS[6:4], the LTM4675 can
take on any 7-bit slave address desired. With the exception
of the ASEL pin, the module can be configured to ignore all
pin-strap resistors, if desired (see MFR_CONFIG_ALL[6]).
Table 1 provides a summary of LTM4675’s supported PMBus
commands. For details on the supported commands, payloads
and data formats see Appendix C: PMBus Command Details.
For introductory information about the PMBus Specifica-
tion, see Appendix A: Similarity Between PMBus, SMBus
and I2C 2-Wire Interface. For information about the data
communication link layer and timing diagrams, see Ap-
pendix B: PMBus Serial Digital Interface.
Major features of the LTM4675 strictly from a DC/DC
converter power delivery point of view are as follows:
n Up to 9A Output Current Delivery from Each of Tw o
Integrated Power Stages (See Front Page Figure)—
or Up to 18A Output, Combined (See Figure 27 and
Figure 34).
n Wide Input Voltage Range: DC/DC Step-Down Con-
version from 5.75V to 17V Input (See Figure 61).
n DC/DC Step-Down Conversion from 4.5V to 5.75V Input,
Connecting SVIN to INTVCC (See Figure 27).
n DC/DC Step-Down Conversion Possible from Less Than
4.5V Input When an Auxiliary 5V Bias Supply Powers
SVIN and INTVCC (See Figure 29).
n Output Voltage Range: 0.5V to 5.5V on both VOUT0 and
VOUT1.
n Differential Remote Sensing of VOUT0 (VOSNS0+/
VOSNS0–). For paralleled outputs, the VOSNS0+/VOSNS0–
pin-pair can be configured as the feedback path for
both VOUT0 and VOUT1 (see Figure 34 and, optionally,
MFR_PWM_CONFIG[7]).
n Start-Up Into a Pre-Biased Load Without Sinking
Current.
n Four LTM4675s Can Be Paralleled to Deliver Up to ~70A
(See Figure 31).
n One LTM4675 Can Be Paralleled with Three LTM4620A
or LTM4630 Modules to Deliver Up to 122A; Infer
Rail Status and Telemetry of Paralleled LTM4620A or
LTM4630 via the Sole LTM4675 (See Figure 32).
n Discontinuous Mode Operation Available for Higher
Light-Load Efficiency (MFR_PWM_MODEn[0]).
n Output Current Limit and Overvoltage Protection.
n Three Integrated Temperature Sensors, Over/Under-
temperature Protection.
n Constant Frequency Peak Current Mode Control.
LTM4675
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OPERATION
n Configurable Switching Frequency, 250kHz to 1MHz;
Synchronizable to External Clock; Seven Configurable
Channel Phase Interleaving Settings.
n Internal Loop Compensation Provided; External Loop
Compensation Can Be Applied, if Preferred.
n Low Profile (16mm × 11.9mm × 3.51mm) BGA Pack-
age Power Solution Requires Only Input and Output
Capacitors; at Most, Nine Pull-Up Resistors for Open-
Drain Digital Signals; at Most, Six Pull-Down Resistors
to Configure All Possible Pin-Strapping Options.
Features of the LTM4675 that enable power system
management, rail sequencing, and fault monitoring and
reporting are as follows:
n I2C-based PMBus/SMBus 2-Wire Serial Communication
Interface (SDA, SCL) with ALERT Interrupt Pin, SCL
Clock Capable of 400kHz Bus Communication Speeds
with Clock Low Extending—or 100kHz, Otherwise.
n Configurable Output Voltage.
n Configurable Input Undervoltage Comparators
(UVLO Rising, UVLO Falling).
n Configurable Switching Frequency.
n Configurable Current Limit.
n Configurable Output Over/Undervoltage Comparators.
n Configurable Turn-On and Turn-Off Delay Times.
n Configurable Output Ramp Rise and Fall Times.
n Non-Volatile Configuration Memory (NVM EEPROM)
with ECC to Configure Aforementioned Settings, and
More—Yielding Standalone Operation, if Desired, and
Also Enabling In-Situ Changes to the LTM4675’s Con-
figuration in Embedded Designs.
n Monitoring and Reporting of Telemetry Data: Average
Output and Input Currents and Voltages, Internal Tem-
peratures, and Power Stage Duty Cycles—Continuously
Digitized Cyclically by a 16-Bit ADC.
• Peak Observed Output Current and Voltage, Input
Voltage, and Module Temperatures Can Be Polled
and Cleared/Reset.
• ADC Latency Not Greater Than 90ms, Nominal.
• Option to Monitor One External Temperature in Lieu of
Channel 1 (VOUT1) Module Power Stage Temperature.
n Monitoring, Reporting, and Configurable Response
to Latching and Non-Latching Individual Fault and/or
Warning Status, Including but Not Limited to:
• Output Over/Undervoltages.
• Input (SVIN) Over/Undervoltages.
• Module Input and Power Stage Output Overcurrents.
• Module Power Stage Over/Under Temperatures.
• Internal Control IC Overtemperature.
• Communication, Memory and Logic (CML) Faults.
n Fault Logging Upon Detection of a Fault Condition. The
LTM4675 Can Be Configured to Automatically Upload a
Fault Log to Its NVM, Consisting of: an Uptime Counter,
Peak Observed Telemetry, Telemetry Gathered from the Six
Most Recent Rounds of Cyclical ADC Data Leading Up to
the Detection of the Fault That Triggered Fault Log Writing,
and Fault Status Associated with That ADC History.
n Tw o Configurable Open-Drain General Purpose Input/
Output Pins (GPIO0, GPIO1), Which Can Be Used for:
• Fault Reporting, e.g., as a System Interrupt Signal.
• Coordinating Turn-On/Off of the LTM4675 in Multi-
phase/Multirail Systems.
• Propagating an Unfiltered Power Good Signal (Output
of a VOUTn Undervoltage Comparator) to Command
Turn-On/Off of a Downstream Rail.
n A Write Protect (WP) Pin and Configurable WRITE_
PROTECT Register to Protect the Internal Configuration
of RAM and NVM Against Unintended Changes via I2C.
n Time-Base Interconnect (SHARE_CLK, 100kHz Heart-
beat) for Synchronization in the Time Domain Between
Multiple LTM4675s.
n Optional External Configuration Resistors (RCONFIGs)
for Setting Start-Up Output Voltages, Switching Fre-
quency and Channel-to-Channel Phase Interleaving
Angle.
n Any 7-Bit Slave Address Can Be Assigned to the LTM4675
(0x4F Default), Configured by Resistor Pin Strapping
the ASEL Pin and User-Editable Bits [6:4] of MFR_AD-
DRESS.
LTM4675
23
Rev. C
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OPERATION
POWER MODULE CONFIGURABILITY AND
READBACK DATA
This section of the data sheet describes all the configurable
features and readable data of the LTM4675 accessible
via I2C. The relevant command code name(s) are
indicatedby use of all capital letters, e.g., “VIN_ON”. Refer
to Table 1 and Appendix C: PMBus Command Details of
this data sheet for details of the command code, payload
size, data format and factory-default value. Specific
register bits of some registers are indicated with the use
of brackets, i.e., “[” and “]”. The least significant bit (LSB)
of a register is bit number zero, indicated by “[0]”. The
most significant bit of a byte-long (8-bit-long) register is bit
number seven, indicated by “[7]”. The most significant bit
(MSB) of a word-long (16-bit-long) register is bit number
fifteen, indicated by “[15]”. Multiple bits of a register can
be alluded to with the use of a colon, e.g., bits 2, 1 and
0 of the MFR_PWM_CONFIG register are indicated by
“MFR_PWM_CONFIG[2:0]”. Bits can take on values of 0b
or 1b. The subscripted “b” suffix indicates the number’s
value is in binary. Values in hexadecimal are indicated with
a “0x” prefix. For example, decimal value “89” is indicated
by 0x59 and 01011001b (8-bit-long values), as well as
0x0059 and 0000000001011001b (16-bit-long values).
One further shorthand notion the reader will notice is the
italicized “n” or “n”. “n” can take on a value of 0 or 1—and
provides an easy way to refer to registers which are paged
commands, i.e., register names which have the same
command code value but can be configured independently
(or yield channel-specific telemetry) for Channel 0 (Page
0, or 0x00) vs Channel 1 (Page 1, or 0x01). Registers
lacking an “n” are therefore easily identified as being
global in nature, i.e., common to both Channels/Outputs.
For example, the switching frequency setting commanded
by register FREQUENCY_SWITCH is common to both
channels, and lacks “n”. Another example: the READ_VIN
register contains the digitized input voltage as seen at
the SVIN pin, and SVIN is unique, i.e., common to both
Channels. In contrast, the nominal commanded output
voltage is indicated by the register VOUT_COMMANDn.
The “n” indicates that VOUT_COMMAND can be set dif-
ferently for Channel 0 vs Channel 1. Executing the PAGE
Command (Command Code 0x00) with payload 0x00 sets
the LTM4675 to write/read data pertaining to Channel 0 in
all subsequent I2C transactions until the Page is changed.
Executing the PAGE Command with payload 0x01 sets the
LTM4675 to write/read data pertaining to Channel 1 in all
subsequent I2C transactions until the Page is changed.
Executing the PAGE Command with payload 0xFF sets
the LTM4675 to write data pertaining to Channels 0 and1
in all subsequent I2C write transactions until the Page is
changed. Reads from and writes to global registers do
not require setting the Page to 0xFF. Reads from channel-
specific (i.e., non-global) registers when the Page is set to
0xFF result in the LTM4675 reporting the value on Page
0x00 (i.e., Channel 0-specific data).
The list below itemizes aspects of the LTM4675 relating
to power supply functions that are configurable by I2C
communications—provided the state of the WP (write
protect) pin and the WRITE_PROTECT register value permit
the I2C writes—and by EEPROM settings:
n Output start-up voltages (VOUT_COMMANDn), the
maximum commandable output voltages (VOUT_MAXn),
output margin high (VOUT_MARGIN_HIGHn) and margin
low (VOUT_MARGIN_LOWn) command voltages, and
output over/undervoltage warning and fault thresholds
(VOUT_OV_WARN_LIMITn, VOUT_OV_FAULT_LIMITn,
VOUT_UV_WARN_LIMITn, and VOUT_UV_FAULT_
LIMITn). Additionally, these values can be configured
at SVIN power-up according to resistor-pin strapping of
the VOUT0CFG, VTRIM0CFG, VOUT1CFG and/or VTRIM1CFG
pins, provided MFR_CONFIG_ALL[6] = 0b.
n Output voltages, on the fly, including transition rate
(∆V/∆t), VOUT_TRANSITION_RATEn— either by I2C
writes to the VOUT_COMMANDn, VOUT_MARGIN_
HIGHn, or VOUT_MARGIN_LOWn registers, and/or to
the OPERATIONn register.
n Input undervoltage-lockout, rising (VIN_ON) and input
undervoltage lockout, falling (VIN_OFF), based on the
SVIN pin voltage.
n
Switching frequency (FREQUENCY_SWITCH) and channel
phase-interleaving angle (MFR_PWM_CONFIG[2:0]).
However, these parameters can be changed via I2C
communications only when the LTM4675’s channels
are off, i.e., not switching. The LTM4675 synchronizes
LTM4675
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OPERATION
its switching frequency to a clock signal supplied to
its SYNC pin when MFR_CONFIG_ALL[4]=1b. These
parameters can be configured at SVIN power-up according
to resistor-pin strapping of the FSWPHCFG pin, provided
MFR_CONFIG_ALL[6] = 0b.
n Output voltage turn-on and turn-off sequencing and
associated watchdog timers, namely:
• Output voltage turn-on delay time (the time delay from
the LTM4675 being commanded to turn on, e.g., by
the RUNn pin toggling from logic low to high, before
switching action commences. TON_DELAYn).
• Output voltage soft-start ramp-up time (TON_RISEn).
• The amount of time (TON_MAX_FAULT_LIMITn)
permitted to elapse after the LTM4675 is commanded
to turn on, e.g., by the RUNn pin toggling from logic
low to high, after which, if the output voltage fails
to exceed the output undervoltage fault threshold
(VOUT_UV_FAULT_LIMITn), the LTM4675’s output
(VOUTn) is declared to have not come up in a timely
manner.
• The LTM4675’s response to any such afore-
mentioned TON_MAX_FAULT_LIMITn event
(TON_MAX_FAULT_RESPONSEn).
• Output voltage soft-stop ramp-down time
(TOFF_FALLn).
• Output voltage turn-off delay time (the time delay from
the LTM4675 being commanded to turn off, e.g., by
the RUNn pin toggling from logic high to low, before
switching action ceases. TOFF_DELAYn).
• When commanded to turn off its output—or,
when turning off its output in response to a fault—
configuring whether the LTM4675's output (VOUTn)
becomes high impedance (“High-Z” or “three
state”—turning off both MTn and MBn in the power
stage). (“Immediate Off”, ON_OFF_CONFIGn[0] =
1b vs configuring the output voltage to be ramped
down according to TOFF_FALLn and/or TOFF_DELAYn
settings, ON_OFF_CONFIGn[0] = 0b).
• The amount of time (TOFF_MAX_WARN_LIMITn)
permitted to elapse after the LTM4675 is supposed
to have turned off its output, i.e., at the end of the
period dictated by TOFF_FALLn, after which, If the
output voltage has not fallen below 12.5% of the
former target voltage of regulation, the LTM4675’s
output (VOUTn) is declared to have not powered down
in a timely manner.
n Configurable output voltage restart time. Subsequent to
the RUNn pin being pulled low, the LTM4675 pulls RUNn
logic low, itself, and the output cannot be restarted until a
minimum time has elapsed—the restart delay time. This
delay assures proper sequencing of all system rails. The
minimum restart delay processed by the LTM4675 is the
longer of (TOFF_DELAYn + TOFF_FALLn + 136ms) vs the
commanded MFR_RESTART_DELAYn register value. At
the end of this delay, the LTM4675 releases its RUNn pin.
n Configurable fault-hiccup retry delay time. When a fault
occurs in which the LTM4675’s fault response behavior
to that fault is to reattempt power-up of its output voltage
after said fault ceases to be present (e.g., “Infinite Retry”),
the delay time for the LTM4675 to re-engage switching
action is the longer of the MFR_RETRY_DELAYn time vs
the time required for the output to decay below 12.5% of
the formerly commanded output voltage value (unless this
lattermost criteria, i.e., requiring the output to decay below
12.5% is negated by the setting of MFR_CHAN_CON-
FIGn[0] to “1b”—which is the LTM4675’s factory-NVM
default setting).
n Output over/undervoltage fault responses (VOUT_OV_
FAULT_RESPONSEn, VOUT_UV_FAULT_RESPONSEn).
n Time-averaged current limit warning and instantaneous
peak (cycle-by-cycle) fault thresholds, and fault response
(IOUT_OC_WARN_LIMITn, IOUT_OC_FAULT_LIMITn,
IOUT_OC_FAULT_RESPONSEn).
n Channel (VOUT0, VOUT1) overtemperature warning and
fault thresholds, and fault response (OT_WARN_LIMITn,
OT_FAULT_LIMITn, OT_FAULT_RESPONSEn).
n Channel (VOUT0, VOUT1) undertemperature fault
thresholds and fault response (UT_FAULT_LIMITn,
UT_FAULT_RESPONSEn).
n Input overvoltage fault threshold and response
(VIN_OV_FAULT_LIMIT, VIN_OV_FAULT_RESPONSE),
based on the SVIN pin voltage.
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OPERATION
n Input undervoltage warning threshold (VIN_UV_WARN_
LIMIT) based on the SVIN pin voltage.
n Module input overcurrent warning threshold
(IIN_OC_WARN_LIMIT)
The control IC within the LTM4675 module ceases
switching action if control IC temperature exceeds 160°C
(Note 12). The control IC resumes operation after a 10°C
cool-down hysteresis. Note that these typical parameters
are based on measurements in a lab oven and are not
production tested. This overtemperature protection is
intended to protect the device during momentary overload
conditions. The maximum rated junction temperature will
be exceeded when this protection is active. Continuous
operation above the specified absolute maximum operat-
ing junction temperature may impair device reliability or
permanently damage the device.
TIME-AVERAGED AND PEAK READBACK D ATA
Time-averaged telemetry readback data accessible via I2C
communications follow:
n Channel output current (READ_IOUTn) and peak
observed value of READ_IOUTn (MFR_IOUT_PEAKn).
n Channel output voltage (READ_VOUTn) and peak
observed value of READ_VOUTn (MFR_VOUT_PEAKn).
n Channel output power (READ_POUTn).
n Channel input current (MFR_READ_IINn) and module
input current (READ_IIN).
n Channel temperatures (READ_TEMPERATURE_1n) and
peak observed values of READ_TEMPERATURE_1n
(MFR_TEMPERATURE_1_PEAKn).
n Control IC temperature (READ_TEMPERATURE_2) and
peak observed value (MFR_TEMPERATURE_2_PEAK).
n Input voltage (READ_VIN), based on the voltage of
the SVIN pin, and peak observed value of READ_VIN
(MFR_VIN_PEAK).
n Channel topside power MOSFET (MTn) duty cycle
(READ_DUTY_CYCLEn)
Digitized cyclical telemetry is available at a 10Hz update
rate, typical. Through the use of the MFR_ADC_CONTROL
command, some signals of interest can be digitized more
frequently—up to a 125Hz update rate, typical. Availability
of newly digitized telemetry data can be made known via
the MFR_ADC_TELEMETRY_STATUS command.
Peak observed values of telemetry readback data can
be cleared with the MFR_CLEAR_PEAKS I2C command,
provided the WRITE_PROTECT register value permits it.
(Executing MFR_CLEAR_PEAKS can be performed regard-
less of the state of the WP pin.)
Details on the LTM4675’s Fault Log Feature follow:
n Fault logging is enabled when MFR_CONFIG_ALL[7] = 1b.
n A fault log is present in NVM when STATUS_MFR_
SPECIFICn[3]Reports “1b”, which is propagated to the
MFR Bit (Bit 12) of the STATUS_WORD register.
n Retrieving fault log data, if present, is performed with
the MFR_FAULT_LOG command. 147 bytes of data
are retrieved using the PMBus-defined variant to the
SMBus block read protocol.
n The fault log contents in NVM, if present, are cleared
by executing the MFR_FAULT_LOG_CLEAR command.
n The fault log will not be written if a fault log is already
present in NVM.
n The LTM4675 can be forced to write a fault log to
its NVM by executing the MFR_FAULT_LOG_STORE
command; the LTM4675 will behave as if a channel
faulted off. Note the command is NACKed and a CML
fault is reported if a fault log is already present at the
time of executing MFR_FAULT_LOG_STORE.
When an external stimulus pulls the LTM4675’s GPIOn
pin(s) logic low, the respective channel (VOUTn) ei-
ther: takes no action on it, i.e., ignores it completely—
if MFR_GPIO_RESPONSEn = 0x00; or, turns off immediately,
i.e., the power stage(s) become high impedance (“inhibited”)—
if MFR_GPIO_RESPONSEn = 0xC0.
LTM4675
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OPERATION
The MFR_GPIO_PROPAGATEn register contents config-
ure which fault(s) cause the LTM4675 to pull its GPIOn
pin(s) logic low.
I2C communications are originated by the user’s (system’s)
I2C master device. Writes/reads to/from Channel 0 of the
LTM4675 (VOUT0: PAGE 0x00), to/from Channel 1 of the
LTM4675 (VOUT1: PAGE 0x01), or writes to both Channels
0 and 1 of the LTM4675 (VOUT0 and VOUT1: PAGE 0xFF) are
possible. The target channel(s) of interest are selected by the
I2C master by executing the PAGE command and sending
the appropriate argument (0x00, 0x01, 0xFF) in the payload.
The PAGE command is unrestricted, i.e., not affected by
the WP pin or WRITE_PROTECT register settings.
The LTM4675 always responds to its global slave ad-
dresses, 0x5A and 0x5B. Commands sent to the global
address 0x5A act the same as if the PAGE command were
set to 0xFF, i.e., received commands are written to both
channels simultaneously. Commands sent to the global
address 0x5B are applied to the PAGE active at the time of
the global address transaction, i.e., allows channel-specific
command of all LTM4675 devices on the bus.
I2C commands not listed above that relate to Fault Status
and EEPROM NVM Operations follow. Writing of the
following is possible provided the state of the WP (write
protect) pin and the WRITE_PROTECT register value
permits the I2C writes:
n Soliciting (reading) module fault status and clearing
(writing) module fault status (CLEAR_FAULTS, STATUS_
BYTEn, STATUS_WORDn, STATUS_VOUTn, STATUS_
IOUTn, STATUS_INPUT, STATUS_TEMPERATUREn,
STATUS_CML [communications, memory, and/or
logic], and STATUS_MFR_SPECIFICn [miscellaneous]).
n Storing the LTM4675’s user-writable RAM register data
to the EEPROM NVM (STORE_USER_ALL).
n An alternate means to the STORE_USER_ALL command
to directly erase and write the LTM4675’s EEPROM
contents, protected by unlock keys, to facilitate
programming of the LTM4675 EEPROM in environments
such as ICT (in-circuit test) and bulk programming by, e.g.,
embedded hardware or by the LTpowerPlay GUI. Also, a
means to directly read the LTM4675 EEPROM contents
(MFR_EE_UNLOCK, MFR_EE_ERASE, MFR_EE_DATA).
n Instigating a soft reset of the LTM4675 without power-
cycling SVIN power (MFR_RESET). The MFR_RESET
command triggers the download of EEPROM NVM data
to RAM registers, as if SVIN power had been cycled.
n Forcing a download of EEPROM NVM data to
RAM registers (RESTORE_USER_ALL). This is
indistinguishable from executing MFR_RESET.
Other data that can be obtained from the LTM4675 via I2C
communications are as follows:
n Soliciting the LTM4675 for its PMBus capabilities, as
defined by PMBus (CAPABILITY):
• PEC (packet error checking). Note, the LTM4675
requires valid PEC in I2C communications when
MFR_CONFIG_ALL[2] = 1b. The NVM factory-default
configuration is MFR_CONFIG_ALL[2] = 0b, i.e., PEC
not required.
• I2C communications can be supported at up to
400kHz SCL bus speed. Note, clock low extending
(clock stretching) must be enabled on the LTM4675
to ensure robust communications above 100kHz SCL
bus speeds, i.e., MFR_CONFIG_ALL[1] = 1b. The
NVM factory-default configuration is MFR_CONFIG_
ALL[1] = 0b, i.e. Clock stretching is disabled.
• The LTM4675 has an SMBALERT (ALERT) pin and
does support the SMBus ARA (alert response ad-
dress) protocol.
n Soliciting the module for the maximum output voltage
it can be commanded to produce (MFR_VOUT_MAXn).
n Soliciting the device for the data format of its output
voltage-related registers (VOUT_MODEn).
n Soliciting the device for the revisions of PMBus specifica-
tions that it supports (Part I: Rev. 1.2; Part II: Rev 1.2).
n Soliciting the device for the identification of the
manufacturer of the LTM4675, “LTC” (MFR_ID) and
the manufacturer code representing the LTM4675 and
revision, 0x47AX (MFR_SPECIAL_ID).
n Soliciting the device for its part number, “LTM4675 ”
(MFR_MODEL).*
n Soliciting the module for its serial umber
(MFR_SERIAL).
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OPERATION
n The digital status of the LTM4675’s I/O pads and
validity of the ADC (MFR_PADS) and WP pin status
(MFR_COMMON[0]).
The following list indicates other aspects of the LTM4675
relating to power system management and power
sequencing that are configurable by I2C communications—
provided the state of the WP (write protect) pin and the
WRITE_PROTECT register value permit the I2C writes—and
by EEPROM settings:
n Providing multiple means to read/write data directly
to a particular channel of the LTM4675 by assigning
additional slave address for channels 0 and 1 (MFR_
RAIL_ADDRESSn), the benefit of which is that it reduces
page command usage and associated I2C traffic. It
also facilitates altering the same register of multiple
LTM4675 in unison without invoking the PMBus group
command protocol. See also PAGE_PLUS_READ and
PAGE_PLUS_WRITE.
n Configuring the output voltage to be on or off by means
other than the RUNn pin (ON_OFF_CONFIGn[3], OPERA-
TION commands).
n Configuring whether the LTM4675 performs a
CLEAR_FAULTS command upon itself when either
RUNn pin toggles from logic low to logic high.
(MFR_CONFIG_ALL[0]).
n Configuring whether the LTM4675 pulls RUNn logic low
when the LTM4675 is commanded off by other means
(MFR_CHAN_CONFIGn[4]).
n Configuring the response of the LTM4675 when it is
commanded to turn on its output prior to the completion
of processing TOFF_DELAYn and TOFF_FALLn power-
down sequencing (MFR_CHAN_CONFIGn[3]).
n Configuring whether the LTM4675’s output is
disabled when SHARE_CLK is held low (MFR_CHAN_
CONFIGn[2]).
n Configuring whether the ALERT pin is pulled low when
GPIOn is pulled low by external stimulus (MFR_CHAN_
CONFIGn[1]).
n Setting the value of the MFR_IIN_OFFSETn registers,
representing an estimate of the current drawn by the
SVIN pin. The SVIN pin current is not measured by
the LTM4675 but the MFR_IIN_OFFSETn is used in
computing and reporting channel and total module
input currents (MFR_READ_IINn, READ_IIN).
n Three words (six bytes) of the LTM4675’s EEPROM that
are available for storing user data. (USER_DATA_03n,
USER_DATA_04).
n Invoking or releasing several levels of I2C write protection
(WRITE_PROTECT).
n Configuring the bus timeout for 255ms (MFR_CONFIG_
ALL[3]=1b) if the host needs more time to complete
I2C transactions.
n Determining whether the user-editable RAM register
values are identical to the contents of the user NVM
(MFR_COMPARE_USER_ALL).
n Setting the programmable output voltage range of VOUT
to a narrower range (0.5V to 2.75V) in order to achieve
a higher resolution of VOUT adjustment than is available
by default (MFR_PWM_MODEn[1]). MFR_PWM_MODE
cannot be changed on the fly; switching action must
be off. Note that altering the VOUT range alters the gain
of the control loop and may therefore require loop
compensation to be adjusted.
n Altering the temperature coefficient of the LTM4675’s
current sensing elements, if needed (MFR_IOUT_CAL_
GAIN_TCn) (uncommon to alter this parameter from its
NVM-Factory default setting).
n Altering the gain or offset of the power stage sensors
(MFR_TEMP_1_GAINn and MFR_TEMP_1_OFFSETn)—
or that of the external temperature sensor, when an
external temperature sensor is used on the TSNS1a
pin. (Uncommon to alter this parameter from its NVM-
factory default setting).
n Configuring whether the LTM4675 Pulls SHARE_CLK
logic low when SVIN has fallen outside Its UVLO
thresholds (MFR_PWM_CONFIG[4]). MFR_PWM_
CONFIG cannot be changed on the fly; switching action
must be off (uncommon to alter this parameter from
its NVM-factory default setting).
* The MFR_MODEL value is “LT M 4675 ". The value consists of 8 ASCII characters and the last
character is a blank space punctuation character (" "), i.e., ASCII code 0x20 or 32d.
LTM4675
28
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OPERATION
n Configuring whether the LTM4675’s output voltage
digital servos are active vs disengaged (MFR_PWM_
MODEn[6]. Uncommon to alter this parameter from its
NVM-factory default settings).
n Configuring whether the LTM4675’s current limit
range is set to high range vs low range. (MFR_PWM_
MODEn[7]. Not recommended to alter this parameter
from its NVM-factory default settings).
Remaining LTM4675 status that can be queried over I2C
communications follow:
n Access to three “hand-shaking” status bits (MFR_COM-
MON[6:4]) to ease implementation of PMBus busy
protocols, i.e., enabling fast and robust system level
communication through polling of these bits to infer
LTM4675’s readiness to act on subsequent I2C writes.
(See PMBus communication and command processing,
in the Applications Information section.)
n Providing a means to determine whether the LTM4675
NVM download to RAM has occurred (“NVM Initialized,”
MFR_COMMON[3]).
n Providing a means other than ARA protocol to de-
termine whether the LTM4675 is pulling ALERT low
(MFR_COMMON[7]).
n Detecting a SHARE_CLK timeout event
(MFR_COMMON[1]).
n Verifying or Altering the Slave Address of the LTM4675
(MFR_ADDRESS).
POWER MODULE OVERVIEW
A dedicated remote-sense amplifier precisely kelvin-senses
VOUT0’s load via the differential pin-pair formed by VOSNS0+
and VOSNS0–. VOUT0 can be commanded to between 0.5VDC
and 5.5VDC. VOUT1 is sensed via the pin-pair formed by
VOSNS1 and signal ground of the module’s SGND. VOUT1
can be commanded to between 0.5VDC and 5.5VDC.
Output voltage readback telemetry is available over I2C
(READ_VOUTn registers). Peak output voltage readback
telemetry is accessible in the MFR_READ_VOUT_PEAKn
registers. If VOSNS0– exceeds VOSNS0+, no phase reversal
of the differentially-sensed output voltage feedback signal
occurs (Note 12). Similarly, no phase reversal occurs when
SGND exceeds VOSNS1(Note 12). For added flexibility, the
VOSNSO+/VOSNSO– feedback pins can be configured as the
control loop feedback path for both VOUT0 and VOUT1 by
setting MFR_PWM_CONFIG[7]=1b. (See Figure 34).
The typical application schematic is shown in Figure 61
on the back page of this data sheet.
The LTM4675 can operate from input voltages between
5.75V and 17V (see front page figure). In this configura-
tion, INTVCC MOSFET driver and control IC bias is gener-
ated internally by an LDO fed from SVIN to produce 5V
at up to 100mA peak output current. Additional internal
LDOs—3.3V (VDD33), derived from INTVCC, and 2.5V
(VDD25), derived from VDD33—bias the LTM4675’s digital
circuitry. When INTVCC is connected to SVIN, the LTM4675
can operate from input voltages between 4.5V and 5.75V
(see Figure 27). Control IC bias (SVIN) is routed indepen-
dent of the inputs to the power stages (VIN0, VIN1); this
enables step-down DC/DC conversion from less than 4.5V
input (see Figure 29), so long as auxiliary power (4.5V
~ 17V) is available to bias the control IC appropriately.
Furthermore, the inputs of the two power stages are not
connected together internal to the module; therefore, DC/
DC step-down conversion from two different source power
supplies can be performed.
Per Note 6 of the Electrical Characteristics section, the
output current may require derating for some operating
scenarios. Detailed derating guidance is provided in the
Applications Information section.
The LTM4675 contains dual integrated constant frequency
current mode control buck regulators (Channel 0 and Channel
1) whose built-in power MOSFETs are capable of fast switching
speed. The factory NVM-default switching frequency clocks
SYNC at 500kHz, to which the regulators synchronize their
switching frequency. The default phase-interleaving angle
between the channels is 180°. A pin-strapping resistor on FSW-
PHCFG configures the frequency of the SYNC clock (switching
frequency) and the channel phase relationship of the channels
to each other and with respect to the falling edge of the SYNC
signal. (Not all possible combinations of switching frequency
and phase-angle assignments are settable by resistor pin
programming; see Table 4. Configure the LTM4675’s NVM
LTM4675
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OPERATION
to implement settings not available by resistor-pin strapping.)
When a FSWPHCFG pin-strap resistor sets the channel phase
relationship of the LTM4675’s channels, the SYNC clock is
not driven by the module; instead, SYNC becomes strictly a
high impedance input and channel switching frequency is then
synchronized to SYNC provided by an externally-generated
clock or sibling LTM4675 with pull-up resistor to VDD33.
Switching frequency and phase relationship can be altered
via the I2C interface, but only when switching action is off,
i.e., when the module is not regulating either output. See the
Applications Information section for details.
Internal feedback loop compensation for Regulator 0 is
available by connecting COMP0a to COMP0b. (For Regula-
tor1, the connection is from COMP1a to COMP1b.) With
current mode control and internal feedback loop compensa-
tion, the LTM4675 module has sufficient stability margins
and good transient performance with a wide range of output
capacitors—even all-ceramic MLCCs. Table 20 provides
guidance on input and output capacitors recommended for
many common operating conditions. The Analog Devices
μModule Power Design Tool is available for transient and
stability analysis. Furthermore, expert users who prefer
to not make use of the module’s internal feedback loop
compensation—but instead, tailor the feedback loop com-
pensation specifically for his/her application—may do so
by not connecting COMPna to COMPnb: the personalized
loop compensation network can be applied externally, i.e.,
from COMPna to SGND, and leaving COMPnb open circuit.
The LTM4675 has two general purpose input/output pins,
named GPIO0 and GPIO1. The behavior of these pins is
configurable via registers MFR_GPIO_PROPAGATEn and
MFR_GPIO_RESPONSEn. The GPIOn pins are high impedance
during NVM-download-to-RAM initialization. These pins
are intended to perform one of two primary functions, or a
hybrid of the two: behave as open- drain, active low fault/
warning indicators; and/or, behave as auxiliary RUN pins
for their respective VOUTs. In the former case, the pins can
be configured as interrupt pins, pulling active low when
output under/overvoltage, input under/overvoltage, input/
output overcurrent, overtemperature, and/or communication,
memory or logic (CML) fault or warning events are detected
by the LTM4675. Factory NVM-default settings configure the
LTM4675 for the latter case, enabling the GPIOn to be bussed
to paralleled siblings (paralleled LTM4675 channels and/or
modules), for purposes of coordinating orderly power-up and
power-down, i.e., in unison. The LTM4675 DC/DC regulator
does not feature a traditional “power good” (PGOOD) indicator
pin to indicate when the output voltage is within a few percent
of the target regulation point. However, the GPIOn pin can be
configured as a PGOOD indicator. If used for event-based
sequencing of downstream rails, configure GPIOn as the
unfiltered output of the VOUT_UV_FAULT_LIMITn comparator,
setting Bit 12 of MFR_GPIO_PROPAGATEn to “1b”; do not set
Bits 9 and 10 of MFR_GPIO_PROPAGATEn for this purpose,
since the propagation of power good in those latter instances
is subject to supervisor filtering and comparator latency. If it is
necessary to have the desired PGOOD polarity appear on the
GPIOn pin immediately upon SVIN power-up—given that the
pin will initially be high impedance, until NVM contents have
downloaded to RAM—a pull-down Schottky diode is needed
between the RUNn pin of the LTM4675 and the respective
GPIOn pin. (see Figure 2). If the GPIOn pin is configured as a
PGOOD indicator, the MFR_GPIO_RESPONSEn must be set
to “ignore” (0x00), or else the LTM4675 cannot start up due
to the latch-off conditions imposed.
The RUNn pin is a bidirectional open-drain pin. This means
it should never be driven logic high from a low impedance
source. Instead, simply provide a 10k pull-up resistor from
the RUNn pins to VDD33. The LTM4675 pulls its RUNn pin
logic low during NVM-download-to-RAM initialization,
when SVIN is below the commanded undervoltage lockout
voltage (VIN_ON, rising and VIN_OFF, falling), and
subsequent to external stimulus pulling RUN low—for
a minimum time dictated by MFR_RESTART_DELAYn.
Bussing the respective RUNn and GPIOn pins to sibling
LTM4675 modules enables coordinated power-up/power-
down to be well orchestrated, i.e., performing turn-on and
turn-off in a unified fashion.
When RUNn exceeds 1.35V, the LTM4675 initially idles
for a time dictated by the TON_DELAYn register. After the
TON_DELAYn time expires, the module begins ramping
up the respective control loop’s internal reference,
starting from 0V. In the absence of a pre-biased VOUTn
condition, the output voltage is ramped linearly from 0V
to the commanded target voltage, with a ramp-up time
dictated by the TON_RISEn register. In the presence of a
LTM4675
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OPERATION
pre-biased VOUTn condition, the output voltage is brought
into regulation in the same manner as aforementioned,
with the exception that inductor current is prevented from
going negative (the module’s controller is operated in
discontinuous mode operation during start-up). In both
cases, the output voltage reaches regulation in a consistent
time, as measured with respect to RUNn toggling high.
See start-up oscilloscope shots in the Typical Performance
Characteristics section.
Pulling the RUNn pin below 0.8V turns off the DC/DC
converter, i.e., forces the respective regulator into a
shutdown state. Factory NVM-default settings configure the
LTM4675 to turn off its power stage MOSFETs immediately,
thereby becoming high impedance. The output voltage then
decays according to whatever output capacitance and load
impedance is present. Alternatively, NVM/register settings
can configure the LTM4675 to actively discharge VOUTn
when RUNn is pulled logic low, according to prescribed
TOFF_DELAYn delay and TOFF_FALLn ramp-down times.
See the Applications Information section for details. The
LTM4675 does not feature an explicit, analog TRACK pin.
Rail-to-rail tracking and sequencing is handled digitally,
as explained previously.
Bussing the open-drain SHARE_CLK pins of all LTM4675s
(and providing a pull-up resistor to VDD33) provides a
means for all LTM4675s in the system to synchronize
their time-base (or “heartbeat”) to the fastest SHARE_CLK
clock. Sharing the heartbeat amongst all LTM4675 ensures
that all rails are sequenced according to expectations; it
negates timing errors that could otherwise materialize
due to SHARE_CLK (time-base) tolerance and part-to-
part variation.
Current sense information is derived from across the power
inductors internal to the LTM4675 and made available to
the internal control IC’s current control loops and ADC
sensors. Output current readback telemetry is available over
I2C (READ_IOUTn registers). Peak output current readback
telemetry is available in the MFR_READ_IOUT_PEAKn
registers.
Output power readback is computed by the LTM4675
according to:
READ_POUTn = READ_VOUTn • READ_IOUTn
Alternating excitation currents of 2µA and 30µA are sourced
from the TSNS1a pin. Connecting TSNS1a to TSNS1b,
temperature sensing of the Channel 1 power stage is
realized by the LTM4675 digitizing the voltages that appear
at the PNP transistor temperature sensor that resides at
the TSNS1b pin. Analogous activity occurs on the TSNS0
node, from which Channel 0 power stage temperature is
derived. The LTM4675 performs what is known in the
industry as delta VBE (∆VBE) computations and makes
channel (power stage) temperature telemetry available
over I2C (READ_TEMPERATURE_1n). The junction
temperature of the control IC within the LTM4675 is also
available over I2C (READ_TEMPERATURE_2). Observed
peak Channel temperatures can be read back in registers
READ_MFR_TEMPERATURE_1_PEAKn. Observed peak
temperature of the control IC can be read back in register
MFR_READ_TEMPERATURE_2_PEAK.
For a fixed load current, the amplitude of the current
sense information changes over temperature due to the
temperature coefficient of copper (inductor DCR), which is
approximately 3900ppm/°C. This would introduce signifi-
cant current readback error over the operating range of the
module if not for the fact that the LTM4675’s temperature
Figure 2. Event (Voltage) Based Sequencing
LTM4675
Voltage Based Sequencing by Cascading GPIOn Pins Into RUNn Pins
(MFR_GPIO_PROPAGATE = XXX1X00XX00XXXXXb and MFR_GPIO_RESPONSE = 0x00)
GPIO0 = VOUT0_UVUF
GPIO1 = VOUT1_UVUF
RUN1
NOTE: RESISTOR OR RC PULL-UPS ON RUNn AND GPIOn PINS NOT SHOWN
*OPTIONAL SIGNAL SCHOTTKY DIODE. ONLY NEEDED WHEN ACCURATE PGOOD
(POWER GOOD) INDICATION IS REQURED BY THE SYSTEM/USER IMMEDIATELY
AT SVIN POWER UP
RUN0
START
LTM4675
4675 F02
RUN0GPIO0 = VOUT0_UVUF
GPIO1 = VOUT1_UVUF
TO NEXT CHANNEL
IN THE SEQUENCE
RUN1
*
*
*
*
LTM4675
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OPERATION
readback information is used in conjunction with the per-
ceived current sense signal to yield temperature-corrected
current readback data.
If desired, it is possible to use only the temperature
readback information derived by the TSNS0 pin to
yield temperature-corrected current readback data for
both Channels 0 and 1. This frees up the Channel 1
temperature sensor to monitor a temperature sensor
external to the LTM4675. This is achieved by setting
MFR_PWM_MODE0[4] = 1b (the NVM-factory default
value is 0b). This degrades the current readback accuracy
of Channel 1—more so when Channel 0 and Channel1
are not paralleled outputs. However, the TSNS1a pin
becomes available to be connected to an external diode-
connected small-signal PNP transistor (such as 2N3906)
and 10nF X7R capacitor, i.e., an external temperature
sensor, whose temperature readback data and peak value
are available over I2C (READ_TEMPERATURE_11, MFR_
READ_TEMPERATURE_1_PEAK1). Implementation of the
aforementioned is as follows: (1) local to the LTM4675,
electrically connect a 10nF X7R capacitor directly from
TSNS1a to SGND; (2) differentially route a pair of traces
from the LTM4675's TSNS1a and SGND pins to the target
PNP transistor; (3) electrically connect the emitter of the
PNP transistor to TSNS1a; (4) electrically connect the col-
lector and base of the PNP transistor to SGND.
Power stage duty cycle readback telemetry is available over
I2C (READ_DUTY_CYCLEn registers). Computed channel
input current readback is computed by the LTM4675 as:
MFR_READ_IINn = READ_DUTY_CYCLEn • READ_IOUTn
+ MFR_IIN_OFFSETn
Computed module input current readback is computed
by the LTM4675 as:
READ_IIN
=
MFR_READ_IIN
0+
MFR_READ_IIN
1
where MFR_IIN_OFFSETn is a register value representing
the SVIN input bias current. The SVIN current is not dig-
itized by the module. The factory NVM-default value of
MFR_IIN_OFFSETn is 29.56mA, representing the
contribution of current drawn by each of the module’s
channels on the SVIN pin, when the power stages are
operating in forced continuous mode at the factory-
default switching frequency of 500kHz. See Table 8 in
the Applications Information section for recommended
MFR_IIN_OFFSETn setting vs Switching Frequency. The
aforementioned method by which input current is calculated
yields an accurate current readback value even at light load
currents, but only as long as the module is configured for
forced continuous operation (NVM-factory default). SVIN
and peak SVIN readback telemetry is accessible via I2C in
the READ_VIN and MFR_VIN_PEAK registers, respectively.
The power stage switch nodes are brought out on the SWn
pin for functional operation monitoring and for optional
installation of a resistor-capacitor snubber circuit (termi-
nated to GND) for reduced EMI.
The LTM4675 features a write protect (WP) pin. If WP is
open circuit or logic high, I2C writes are severely restricted:
only I2C writes to the PAGE, OPERATION, CLEAR_FAULTS,
MFR_CLEAR_PEAKS, and MFR_EE_UNLOCK commands
are supported, with the exception that individual fault bits
can be cleared by writing a “1b” to the respective bits in the
STATUS_* registers. Register reads are never restricted.
Not to be confused with the WP pin, the LTM4675 features
a WRITE_PROTECT register, which is also used to restrict
I2C writes to register contents. Refer to Appendix C:
PMBus Command Details for details. The WP pin and the
WRITE_PROTECT register provide a level of protection
against accidental changes to RAM and EEPROM contents.
The LTM4675 supports all possible 7-bit slave addresses.
The factory NVM-default slave address is 0x4F. The lower
four bits of the LTM4675’s slave address can be altered
from this default value by connecting a resistor from
the ASEL pin to SGND. See Table 5 in the Applications
Information section for details. Bits[6:4] can be altered by
writing to the SLAVE_ADDRESS command. The value of
the SLAVE_ADDRESS command can be stored to NVM,
however, the lower four bits of the SLAVE_ADDRESS is
always dictated by the ASEL resistor pin-strap setting.
Up to four LTM4675 modules (8 channels) can be par-
alleled, suitable for powering ~70A loads such as CPUs and
GPUs. (See Figure 31) The LTM4675 can be paralleled with
LTM4620A or LTM4630 modules, as well (see Figure 32
and Figure 33).
LTM4675
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OPERATION
EEPROM
The LTM4675’s control IC contains an internal EEPROM
(non-volatile memory, NVM) with Error Correction Coding
(ECC) to store configuration settings and fault log informa-
tion. EEPROM endurance retention and mass write opera-
tion time are specified in the Electrical Characteristics and
Absolute Maximum Ratings sections. Write operations at
TJ < 0°C or at TJ > 85°C are possible although the Electri-
cal Characteristics are not guaranteed and the EEPROM
retention characteristics may be degraded. Read opera-
tions performed at junction temperatures between –40°C
and 125°C do not degrade the EEPROM. The fault logging
function, which is useful in debugging system problems
that may occur at high temperatures, only writes to fault
log-specific EEPROM locations (partitions). If occasional
writes to these registers occur above 85°C junction, the
slight degradation in the data retention characteristics of
the fault log does not undermine the usefulness of the
function.
It is recommended that the EEPROM not be written when
the control IC die temperature is greater than 85°C. If the
die temperature exceeds 130°C, the LTM4675’s control
IC disables all EEPROM write operations. EEPROM write
operations are subsequently re-enabled when the die
temperature drops below 125°C.
The degradation in EEPROM retention for temperatures
>125°C can be approximated by calculating the dimen-
sionless acceleration factor using the following equation:
AF =e
Ea
k
⎛
⎝
⎜⎞
⎠
⎟•1
T
USE+273–1
T
STRESS+273
⎛
⎝
⎜⎞
⎠
⎟
⎡
⎣
⎢⎤
⎦
⎥
where:
AF = acceleration factor
Ea = activation energy = 1.4eV
k = 8.617 • 10–5 eV/°K
TUSE = 125°C specified junction temperature
TSTRESS = actual junction temperature in °C
Example: Calculate the effect on retention when operating
at a junction temperature of 135°C for 10 hours.
TSTRESS = 130°C
TUSE = 125°C
AF= e[(1.4/8.617 • 10–5) • (1/398 – 1/403)] = 1.66
The equivalent operating time at 125°C = 16.6 hours.
Thus the overall retention of the EEPROM was degraded
by 6.6 hours as a result of operating at a junction tempera-
ture of 130°C for 10 hours. The effect of the overstress
is negligible when compared to the overall EEPROM
retention rating of 87,600 hours at a maximum junction
temperature of 125°C.
The integrity of the EEPROM is checked with a CRC
calculation each time its data is read, such as after a
power-on reset or execution of a RESTORE_USER_ALL or
MFR_RESET command. If CRC error occurs, the MFR bit is
set in the STATUS_BYTE and STATUS_WORD commands.
The NVM CRC error bit in the STATUS_MFR_SPECIFIC
command is set and the ALERT and RUN pins are pulled
low disabling the output as a safety measure. The device
will only respond at special address 0x7C or global ad-
dresses 0x5A and 0x5B.
Internal EEPROM with CRC Protection and ECC
The LTM4675 contains internal EEPROM with Error Correc-
tion Coding (ECC) to store user configuration settings and
fault log information. EEPROM endurance and retention for
user space and fault log pages are specified in the Absolute
Maximum Ratings and Electrical Characteristics table.
The integrity of the EEPROM memory is checked with a CRC
calculation each time its data is to be read, such as after a
power-on reset. A CRC error will prevent the controller from
leaving the OFF state. If a CRC error occurs, the CML bit is
set in the STATUS_BYTE and STATUS_WORD commands,
the appropriate bit is set in the STATUS_MFR_SPECIFIC
command, and the ALERT and RUN pins will be pulled
low. At that point the device will respond at special address
0x7C, which is only activated after an invalid CRC has
been detected. The module will also respond to global
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OPERATION
addresses 0x5A and 0x5B, but all LTC PSM modules and
ICs will respond to these addresses so users must be
careful when using global addresses. EEPROM repair can
be attempted by writing the desired configuration to the
controller and executing a STORE_USER_ALL command
followed by a CLEAR_FAULTS command. Contact the
factory if EEPROM repair is unsuccessful.
See the Applications Information section and Application
Note 145, or contact the factory for details on efficient in-
system EEPROM programming, including bulk EEPROM
programming, which the
LTM4675
also supports.
SERIAL INTERFACE
The LTM4675 serial interface is a PMBus compliant slave
device and can operate at any frequency between 10kHz
and 400kHz. The address is configurable using either the
EEPROM or an external resistor divider. In addition the
LTM4675 always responds to the global broadcast address
of 0x5A (7 bit) or 0x5B (7 bit). Address 0x5A is not paged
and is performed on both channels. 0x5B respects the
page command. Because address 0x5A does not support
page, it can not be used for any paged reading commands.
The serial interface supports the following protocols
defined in the PMBus specifications: 1) send command,
2) write byte, 3) write word, 4) group, 5) read byte, 6)
read word and 7) read block 8) PAGE_PLUS_READ,
9) PAGE_PLUS_WRITE 10) SMBALERT_MASK read,
11) SMBALERT_MASK write. All read operations will
return a valid PEC if the PMBus master requests it. If
the PEC_REQUIRED bit is set in the MFR_CONFIG_ALL
command, the PMBus write operations will not be acted
upon until a valid PEC has been received by the LTM4675.
Communication Protection
PEC write errors (if PEC_REQUIRED is active), attempts
to access unsupported commands, or writing invalid data
to supported commands will result in a CML fault. The
CML bit is set in the STATUS_BYTE and STATUS_WORD
commands, the appropriate bit is set in the STATUS_CML
command, and the ALERT pin is pulled low.
DEVICE ADDRESSING
The LTM4675 offers four different types of addressing
over the PMBus interface, specifically: 1) global, 2) device,
3) rail addressing and 4) alert response address (ARA).
Global addressing provides a means of the PMBus master
to address all LTM4675 devices on the bus. The LTM4675
global address is fixed 0x5A (7 bit) or 0xB4 (8 bit) and cannot
be disabled. Commands sent to the global address act the
same as if PAGE is set
to a value of 0xFF. Commands sent are
written to both channels simultaneously. Global command
0x5B (7 bit) or 0xB6 (8 bit) is paged and allows channel
specific command of all LTM4675 devices on the bus. Other
ADI device types may respond at one or both of these global
addresses; therefore do not read from global addresses.
Rail addressing provides a means for the bus master to
simultaneously communicate with all channels connected
together to produce a single output voltage (PolyPhase
®
).
While similar to global addressing, the rail address can be
dynamically assigned with the paged MFR_RAIL_ADDRESS
command, allowing for any logical grouping of channels that
might be required for reliable system control. Do not read from
rail addresses because multiple ADI devices may respond.
Device addressing provides the standard means of the
PMBus master communicating with a single instance
of an LTM4675. The value of the device address is set
by a combination of the ASEL configuration pin and the
MFR_ADDRESS command. When this addressing means
is used, the PAGE command determines the channel being
acted upon. Device addressing can be disabled by writing
a value of 0x80 to the MFR_ADDRESS.
All four means of PMBus addressing require the user to
employ disciplined planning to avoid addressing conflicts.
Communication to LTM4675 devices at global and rail ad-
dresses should be limited to command write operations.
FAULT DETECTION AND HANDLING
A variety of fault and warning reporting and handling
mechanisms are available. Fault and warning detection
capabilities include:
n Input OV/FAULT Protection and UV Warning
n Average Input OC Warn
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OPERATION
n Output OV/UV Fault and Warn Protection
n Output OC Fault and Warn Protection
n Internal and External Overtemperature Fault and Warn
Protection
n External Undertemperature Fault Protection
n CML Fault (Communication, Memory or Logic)
n External Fault Detection via the Bidirectional GPIOn Pins.
In addition, the LTM4675 can map any combination of fault
indicators to their respective GPIOn pin using the propagate
GPIOn response commands, MFR_GPIO_PROPAGATEn.
Typical usage of a GPIO pin is as a driver for an external
crowbar device, overtemperature alert, overvoltage alert or
as an interrupt to cause a microcontroller to poll the fault
commands. Alternatively, the GPIOn pins can be used as
inputs to detect external faults downstream of the controller
that require an immediate response. The GPIO0 and/or GPIO1
pins can also be configured as power good outputs. Power
good indicates the controller output is within the OV/UV fault
thresholds. At power-up the pin will initially be three-state. If it
is necessary to have the desired polarity on the pin at power-
up in this configuration, attach a Schottky diode between the
RUN pin of the propagated power good signal and the GPIO
pin. The Cathode must be attached to RUN and the Anode to
the GPIO pin (see Figure 2). If the GPIO pin is set to a power
good status, the MFR_GPIO_RESPONSE must be ignore
otherwise a latched off condition exists.
As described in the Soft-Start section, it is possible to control
start-up through concatenated events. If GPIOn is used to drive
the RUN pin of another controller, the unfiltered VOUT_UV
fault limit should be mapped to the GPIO pin.
Any fault or warning event will cause the ALERT pin to assert
low unless the ALERT is masked by the SMBALERT_MASK
command. The pin will remain asserted low until the
CLEAR_FAULTS command is issued, the fault bit is written
to a 1, the PMBus master successfully reads the device
ARA register, bias power is cycled or a MFR_RESET or
RESTORE_USER_ALL command is issued. Channel specific
faults are cleared if the RUN pins are toggled OFF/ON or
the part is commanded OFF/ON via PMBus. If bit 0 of MFR_
CONFIG_ALL is set to a 1, toggling the RUN pins OFF/ON or
commanding the part OFF/ON via PMBus clears all faults.
The MFR_GPIO_PROPAGATEn command determines if the
GPIO pins are pulled low when a fault is detected; however,
the ALERT pin is always pulled low if a fault or warning is
detected and the status bits are updated unless the ALERT
pin is masked using the SMBALERT_MASK command.
Output and input fault event handling is controlled by the
corresponding fault response byte as specified in Table 24 to
Table 28. Shutdown recovery from these types of faults can
either be autonomous or latched. For autonomous recovery,
the faults are not latched, so if the fault condition is not
present after the retry interval has elapsed, a new soft-start is
attempted. If the fault persists, the controller will continue to
retry. The retry interval is specified by the MFR_RETRY_DELAY
command and prevents damage to the regulator components
by repetitive power cycling. The MFR_RETRY_DELAY must
be greater than 120ms. It can not exceed 83.88 seconds.
Channel-to-channel fault dependencies can be created by
connecting GPIOn pins together. In the event of an internal fault,
one or more of the channels is configured to pull the bussed
GPIOn pins low. The other channels are then configured to shut
down when the GPIOn pins are pulled low. For autonomous
group retry, the faulted channel is configured to release the
GPIOn pin(s) after a retry interval, assuming the original
fault has cleared. All the channels in the group then begin
a soft-start sequence. If the fault response is LATCH_OFF,
the GPIO pin remains asserted low until either the RUN pin
is toggled OFF/ON or the part is commanded OFF/ON. The
toggling of the RUN either by the pin or OFF/ON command
will clear faults associated with the channel. If it is desired to
have all faults cleared when either RUN pin is toggled, set bit 0
of MFR_CONFIG_ALL to a 1.
The status of all faults and warnings is summarized in the
STATUS_WORD and STATUS_BYTE commands.
RESPONSES TO VOUT AND IOUT FAULTS
VOUT OV and UV conditions are monitored by comparators.
The OV and UV limits are set in three ways.
n As a Percentage of the VOUT if Using the Resistor Con-
figuration Pins
n In EEPROM if Either Programmed at the Factory or
Through the GUI
n By PMBus Command
LTM4675
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OPERATION
The IIN and IOUT overcurrent monitors are performed by
ADC readings and calculations. Thus these values are
based on average currents and can have a nominal time
latency of up to 90ms. The IOUT calculation accounts for
the power inductor DCR and the temperature coefficient of
the inductor's copper winding. The input current is equal to
the sum of output current times the respective channel duty
cycle plus the input offset current for each channel. If this
calculated input current exceeds the IIN_OC_WARN_LIMIT
the ALERT pin is pulled low and the IIN_OC_WARN bit is
asserted in the STATUS_INPUT register.
The LTM4675 provides the ability to ignore the fault, shut
down and latch off or shut down and retry indefinitely
(hiccup). The retry interval is set in MFR_RETRY_DELAYn
and can be from 120ms to 83.88 seconds in 1ms incre-
ments. The shutdown for OV/UV and OC can be done
immediately or after a user selectable deglitch time.
Output Overvoltage Fault Response
A programmable overvoltage comparator (OV) guards
against transient overshoots as well as long-term over-
voltages at the output. In such cases, the top MOSFET is
turned off and the bottom MOSFET is turned on until the
overvoltage condition is cleared regardless of the PMBus
VOUT_OV_FAULT_RESPONSEn command byte value. This
hardware level fault response delay is typically 2µs from
the overvoltage condition to BG asserted high. Using the
VOUT_OV_FAULT_RESPONSEn command, the user can
select any of the following behaviors:
n OV Pull-Down Only (OV cannot be ignored)
n Shut Down (Stop Switching) Immediately—Latch Off
n Shut Down Immediately—Retry Indefinitely using the
Time Interval Specified in MFR_RETRY_DELAYn
Either the Latch Off or Retry fault responses can be de-
glitched in increments of (0 to 7) • 10µs. See Table 24.
Output Undervoltage Response
The response to an undervoltage comparator output can
be either:
n Ignore
n Shut Down Immediately—Latch Off
n Shut Down Immediately—Retry Indefinitely using the
Time Interval Specified in MFR_RETRY_DELAYn
Either the Latch Off or Retry fault responses can be de-
glitched in increments of (0 to 7) • 10µs. See Table 25.
Peak Output Overcurrent Fault Response
Due to the current mode control algorithm, peak inductor
current is always limited on a cycle by cycle basis. The
value of the peak current limit is specified in the Electrical
Characteristics table. The current limit circuit operates by
limiting the COMPna maximum voltage. DCR sensing is
used so the COMPna maximum voltage has a temperature
dependency directly proportional to the TC of the DCR
of the inductor. The LTM4675 automatically monitors
the power stage temperature sensors and modifies the
maximum allowed COMPna to compensate for this term.
The overcurrent fault processing circuitry can execute the
following behaviors:
n Current Limit Indefinitely
n Shut Down Immediately—Latch Off
n Shut Down Immediately—Retry Indefinitely using the
Time Interval Specified in MFR_RETRY_DELAYn
The overcurrent responses can be deglitched in increments
of (0 to 7) • 16ms. See Table 26.
RESPONSES TO TIMING FAULTS
TON_MAX_FAULT_LIMITn is the time allowed for VOUT to
rise and settle at start-up. The TON_MAX_FAULT_LIMITn
condition is predicated upon detection of the VOUT_UV_
FAULT_LIMITn as the output is undergoing a SOFT_START
sequence. The TON_MAX_FAULT_LIMITn time is started
after TON_DELAYn has been reached and a SOFT_START
sequence is started. The resolution of the TON_MAX_
FAULT_LIMITn is 10µs. If the VOUT_UV_FAULT_LIMITn
is not reached within the TON_MAX_FAULT_LIMITn time,
the response of this fault is determined by the value of
the TON_MAX_FAULT_RESPONSEn command value. This
response may be one of the following:
n Ignore
n Shut Down (Stop Switching) Immediately—Latch Off
LTM4675
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OPERATION
n Shut Down Immediately—Retry Indefinitely using the
Time Interval Specified in MFR_RETRY_DELAYn
This fault response is not deglitched. A value of 0 in
TON_MAX_FAULT_LIMITn means the fault is ignored. The
TON_MAX_FAULT_LIMITn should be set longer than the
TON_RISEn time. It is recommended TON_MAX_FAULT_
LIMITn always be set to a non-zero value, otherwise the
output may never come up and no flag will be set to the
user.
See Table 28.
RESPONSES TO SVIN OV FAULTS
SVIN overvoltage is measured with the ADC; therefore,
the response is naturally deglitched by up to the 90ms
typical response time of the ADC. The fault responses are:
n Ignore
n Shut Down Immediately—Latch Off
n Shut Down Immediately—Retry Indefinitely using the
Time Interval Specified in MFR_RETRY_DELAYn
See Table 28.
RESPONSES TO OT/UT FAULTS
Internal Overtemperature Fault/Warn Response
An internal temperature sensor protects against EEPROM
damage. Above 85°C, no writes to EEPROM are recom-
mended. Above 130°C, the internal over temperature warn
threshold is exceeded and the part disables EEPROM writes
and does not re-enable until the temperature has dropped
to 125°C. When the die temperature exceed 160°C the
internal over temperature fault response is enabled and
the PWM is disabled until the die temperature drops below
150°C. Temperature is measured by the ADC. Internal
temperature faults cannot be ignored. Internal temperature
limits cannot be adjusted by the user.
See Table 27.
External Overtemperature and Undertemperature
Fault Response
Two temperature sensors within the LTM4675 are used
to sense power stage temperature. The OT_FAULT_
RESPONSEn and UT_FAULT_RESPONSEn commands are
used to determine the appropriate response to an over-
temperature and undertemperature condition, respectively.
The fault responses are:
n Ignore
n Shut Down Immediately—Latch Off
n Shut Down Immediately—Retry Indefinitely using the
Time Interval Specified in MFR_RETRY_DELAYn
See Table 28.
RESPONSES TO EXTERNAL FAULTS
When either GPIOn pin is pulled low, the OTHER bit is set
in the STATUS_WORD command, the appropriate bit is set
in the STATUS_MFR_SPECIFC command, and the ALERT
pin is pulled low. Responses are not deglitched. Each
channel can be configured to ignore or shut down then
retry in response to its GPIOn pin going low by modifying
the MFR_GPIO_RESPONSEn command. To avoid the
ALERT pin asserting low when GPIO is pulled low, assert
bit 1 of MFR_CHAN_CONFIGn, or mask the ALERT using
the SMBALERT_MASK command.
FAULT LOGGING
The LTM4675 has fault logging capability. Data is logged
into memory in the order shown in Table 30. The data to
be stored in the fault log is being continuously stored in
internal volatile memory. When a fault event occurs, the
recording into internal volatile memory is halted, the fault
log information is available from the MFR_FAULT_LOG
command, and the contents of the internal memory
are copied into EEPROM. Fault logging is allowed at
temperatures above 85°C; however, retention of 10 years is
LTM4675
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not guaranteed. When the die temperature exceeds 130°C
the fault logging is delayed until the die temperature drops
below 125°C. After the fault condition that created the fault
log event has been removed, clear the fault before the fault
log data is erased, or else the part will immediately issue
another fault log.
When the LTM4675 powers-up, it checks the
EEPROM
for a valid fault log. If a valid fault log exists in
EEPROM
,
the “Valid Fault Log” bit in the STATUS_MFR_SPECIFIC
command will be set and an ALERT event will be generated.
Also, fault logging will be blocked until the LTM4675 has
received a MFR_FAULT_LOG_CLEAR command before
fault logging will be re-enabled.
The information is stored in EEPROM in the event of any fault
that disables the controller on either channel. An external
GPIOn pulling low will not trigger a fault logging event.
OPERATION
BUS TIMEOUT PROTECTION
The LTM4675 implements a timeout feature to avoid
hanging the serial interface. The data packet timer begins
at the first START event before the device address write
byte. Data packet information must be completed within
25ms or the LTM4675 will three-state the bus and ignore
the given data packet. If more time is required, assert
bit 3 of MFR_CONFIG_ALL to allow typical bus timeouts
of 255ms. Data packet information includes the device
address byte write, command byte, repeat start event
(if a read operation), device address byte read (if a read
operation), all data bytes and the PEC byte if applicable.
The LTM4675 allows longer PMBus timeouts for block
read data packets. This timeout is proportional to the
length of the block read. The additional block read timeout
applies primarily to the MFR_FAULT_LOG command. In
no circumstances will the timeout period be less than the
tTIMEOUT_SMB specification of 32ms (typical).
The user is encouraged to use as high a clock rate as possible
to maintain efficient data packet transfer between all devices
sharing the serial bus interface. The LTM4675 supports the
full PMBus frequency range from 10kHz to 400kHz.
LTM4675
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PMBUS COMMAND SUMMARY
PMBUS COMMANDS
Table 1 lists supported PMBus commands and
manufacturer specific commands. A complete description
of these commands can be found in the “PMBus Power
System Management Protocol Specification – Part
II – Revision 1.2." Users are encouraged to reference
this specification. Exceptions or manufacturer specific
implementations are listed in Table 1.
All commands from 0xD0 through 0xFF not listed in this
table are implicitly reserved by the manufacturer. Users
should avoid blind writes within this range of commands
to avoid undesired operation of the part. All commands
from 0x00 through 0xCF not listed in this table are implicitly
not supported by the manufacturer. Attempting to access
non-supported or reserved commands may result in a CML
command fault event. All output voltage settings and
measurements are based on the VOUT_MODE setting of
0x14. This translates to an exponent of 2–12.
If PMBus commands are received faster than they are being
processed, the part may become too busy to handle new
commands. In these circumstances the part follows the
protocols defined in the PMBus Specification v1.2, Part
II, Section 10.8.7, to communicate that it is busy.
The part includes handshaking features to eliminate busy
errors and simplify error handling software while ensuring
robust communication and system behavior. Please refer
to the PMBus Communication and Command Processing
subsection in the Applications Information section for details.
Table 1. Summary of Supported Commands
PMBus COMMAND
NAME, OR FEATURE
CMD CODE
(REGISTER)
COMMAND OR FEATURE
DESCRIPTION LTM4675 NVM FACTORY-DEFAULT VALUE AND/OR ATTRIBUTES PAGE
PAGE 0x00 Channel or page currently targeted
for paged communications.
0x00, read/write, non-paged, not stored in NVM. 82
OPERATIONn0x01 Operating mode control. On/off,
margin high and margin low.
0x80, read/write, paged, stored in user-editable NVM. 86
ON_OFF_CONFIGn0x02 RUNn pin and On/Off
Configuration.
0x1F, read/write, paged, stored in user-editable NVM. 85
CLEAR_FAULTS 0x03 Clear any fault bits that have been
set.
Default value not applicable, send byte only, non-paged, not stored in
NVM.
109
PAGE_PLUS_WRITE 0x05 Write a command directly to a
specified page.
Default value not applicable, write-only, non-paged, not stored in NVM. 82
PAGE_PLUS_READ 0x06 Read a command directly from a
specified page.
Default value not applicable, read/write, non-paged, not stored in NVM. 83
WRITE_PROTECT 0x10 Level of protection provided by the
device against accidental changes.
0x00, read/write, non-paged, stored in user-editable NVM. 83
STORE_USER_ALL 0x15 Store user operating memory to
EEPROM (user-editable NVM).
Default value not applicable, send byte only, non-paged, not stored in
NVM.
120
RESTORE_USER_
ALL
0x16 Restore user operating memory
from EEPROM.
Default value not applicable, send byte only, non-paged, not stored in NVM.
Identical to MFR_RESET command (0xFD).
121
CAPABILITY 0x19 Summary of PMBus optional
communication protocols
supported by this device.
0xB0, read-only, non-paged, not stored in NVM. 108
SMBALERT_MASKn0x1B Mask ALERT activity. Default mask values: STATUS_VOUTn=0x00, STATUS_IOUTn=0x00,
STATUS_INPUT=0x00, STATUS_TEMPERATUREn=0x00, STATUS_
CML=0x00, STATUS_MFR_SPECIFICn=0x11.
Read/write, paged as indicated, 10 bytes total, stored in NVM
110
VOUT_MODEn0x20 Output voltage format/exponent. 0x14 (2–12), read-only, paged, not stored in NVM. 90
VOUT_COMMANDn0x21 Nominal output voltage set point. 0x1000 (1.000V), read/write, paged, stored in user-editable NVM. 91
LTM4675
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For more information www.analog.com
PMBUS COMMAND SUMMARY
Table 1. Summary of Supported Commands
PMBus COMMAND
NAME, OR FEATURE
CMD CODE
(REGISTER)
COMMAND OR FEATURE
DESCRIPTION LTM4675 NVM FACTORY-DEFAULT VALUE AND/OR ATTRIBUTES PAGE
VOUT_MAXn0x24 The upper limit on the
commandable output voltage.
Page 0x00: 0x599A (5.600V)
Page 0x01: 0x599A (5.600V)
Read/write, paged, stored in user-editable NVM.
90
VOUT_MARGIN_
HIGHn
0x25 Margin high output voltage set
point. Must be greater than
VOUT_COMMANDn.
0x10CD (1.050V), read/write, paged, stored in user-editable NVM. 91
VOUT_MARGIN_
LOWn
0x26 Margin low output voltage set
point. Must be less than
VOUT_COMMANDn.
0x0F33 (0.950V), read/write, paged, stored in user-editable NVM. 92
VOUT_TRANSITION_
RATEn
0x27 The rate at which the output
voltage changes when VOUTn is
commanded to a new value via
I2C.
0x8042 (0.001V/ms), read/write, paged, stored in user-editable NVM. 97
FREQUENCY_
SWITCH
0x33 The switching frequency setting. 0xFBE8 (500kHz), read/write, non-paged, stored in user-editable NVM. 89
VIN_ON 0x35 The undervoltage lockout (UVLO)-
rising threshold.
0xCAC0 (5.500V), as monitored on the “SVIN” pin, read/write, non-paged,
stored in user-editable NVM.
90
VIN_OFF 0x36 The undervoltage lockout (UVLO)-
falling threshold.
0xCAA0 (5.250V) , as monitored on the “SVIN” pin, read/write, non-paged,
stored in user-editable NVM.
90
IOUT_CAL_GAINn0x38 The ratio of the voltage at the
control IC’s current-sense pins
to the sensed current, in mΩ, at
25°C.
Trimmed at ATE, read/write, paged, stored in factory-only NVM. Writes to
this register not recommended.
93
VOUT_OV_FAULT_
LIMITn
0x40 Output overvoltage fault limit. 0x119A (1.100V), read/write, paged, stored in user-editable NVM. 91
VOUT_OV_FAULT_
RESPONSEn
0x41 Action to be taken by the device
when an output overvoltage fault
is detected.
0x7A (20µs glitch filter; non-latching shutdown; autonomous restart upon
fault removal), read/write, paged, stored in user-editable NVM.
100
VOUT_OV_WARN_
LIMITn
0x42 Output overvoltage warning
threshold.
0x1133 (1.075V), read/write, paged, stored in user-editable NVM. 91
VOUT_UV_WARN_
LIMITn
0x43 Output undervoltage warning
threshold.
0x0ECD (0.925V), read/write, paged, stored in user-editable NVM. 92
VOUT_UV_FAULT_
LIMITn
0x44 Output undervoltage fault limit. 0x0E66 (0.900V), read/write, paged, stored in user-editable NVM. 92
VOUT_UV_FAULT_
RESPONSEn
0x45 Action to be taken by the device
when an output undervoltage fault
is detected.
0xB8 (non-latching shutdown; autonomous restart upon fault removal),
read/write, paged, stored in user-editable NVM.
101
IOUT_OC_FAULT_
LIMITn
0x46 Output overcurrent fault threshold
(cycle-by-cycle inductor peak
current).
0xD3F3 (15.80A), read/write, paged, stored in user-editable NVM. 94
IOUT_OC_FAULT_
RESPONSEn
0x47 Action to be taken by the device
when an output overcurrent fault
is detected.
0x00 (try to regulate through the fault condition/event; limit the cycle-by-
cycle peak of the inductor current to not exceed the commanded IOUT_
OC_FAULT_LIMIT), read/write, paged, stored in user-editable NVM.
103
IOUT_OC_WARN_
LIMITn
0x4A Output overcurrent warning
threshold (time-averaged inductor
current).
0xD2B3 (10.80A), read/write, paged, stored in user-editable NVM. 95
OT_FAULT_LIMITn0x4F Overtemperature fault threshold. 0xF200 (128°C), read/write, paged, stored in user-editable NVM. 96
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PMBUS COMMAND SUMMARY
Table 1. Summary of Supported Commands
PMBus COMMAND
NAME, OR FEATURE
CMD CODE
(REGISTER)
COMMAND OR FEATURE
DESCRIPTION LTM4675 NVM FACTORY-DEFAULT VALUE AND/OR ATTRIBUTES PAGE
OT_FAULT_
RESPONSEn
0x50 Action to be taken by the device
when an overtemperature fault is
detected via TSNSna.
0xB8 (non-latching shutdown; autonomous restart upon fault removal),
read/write, paged, stored in user-editable NVM.
105
OT_WARN_LIMITn0x51 Overtemperature warning
threshold.
0xEBE8 (125°C), read/write, paged, stored in user-editable NVM. 96
UT_FAULT_LIMITn0x53 Undertemperature fault threshold. 0xE530 (–45°C), read/write, paged, stored in user-editable NVM. 96
UT_FAULT_
RESPONSEn
0x54 Response to undertemperature
fault events.
0x00 (ignore; continue without interruption), read/write, paged, stored in
user-editable NVM, read/write, paged, stored in user-editable NVM.
105
VIN_OV_FAULT_
LIMIT
0x55 Input supply (SVIN) overvoltage
fault limit.
0xDA2E (17.44V), read/write, non-paged, stored in user-editable NVM. 89
VIN_OV_FAULT_
RESPONSEn
0x56 Response to input overvoltage
fault events.
0xB8 (non-latching shutdown; autonomous restart upon fault removal),
read/write, paged, stored in user-editable NVM.
99
VIN_UV_WARN_
LIMIT
0x58 Input undervoltage warning
threshold.
0xCAA6 (5.297V), read/write, non-paged, stored in user-editable NVM. 89
IIN_OC_WARN_
LIMIT
0x5D Input supply overcurrent warning
threshold.
0xD220 (8.5A), read/write, non-paged, stored in user-editable NVM. 93
TON_DELAYn0x60 Time from RUNn and/or
OPERATIONn on to output rail
turn-on.
0x8000 (0ms), read/write, paged, stored in user-editable NVM. 97
TON_RISEn0x61 Time from when the output
voltage reference starts to rise
until it reaches its commanded
setting.
0xC300 (3ms), read/write, paged, stored in user-editable NVM. 97
TON_MAX_FAULT_
LIMITn
0x62 Turn-on watchdog timeout fault
threshold (time permitted for
VOUTn to reach or exceed VOUT_
UV_FAULT_LIMITn after turn-on
command is received).
0xCA80 (5ms), read/write, paged, stored in user-editable NVM. 97
TON_MAX_FAULT_
RESPONSEn
0x63 Action to be taken by the device
when a TON_MAX_FAULTn event
is detected.
0xB8 (non-latching shutdown; autonomous restart upon fault removal),
read/write, paged, stored in user-editable NVM.
102
TOFF_DELAYn0x64 Time from RUN and/or Operation
off to the start of TOFF_FALLn
ramp.
0x8000 (0ms), read/write, paged, stored in user-editable NVM. 98
TOFF_FALLn0x65 Time from when the output
voltage reference starts to fall until
it reaches 0V.
0xC300 (3ms), read/write, paged, stored in user-editable NVM. 98
TOFF_MAX_WARN_
LIMITn
0x66 Turn-off watchdog timeout fault
threshold (time permitted for
VOUTn to decay to or below
12.5% of the commanded VOUTn
value at the time of receiving a
turn-off command).
0x8000 (no limit; warning is disabled), read/write, paged, stored in user-
editable NVM.
98
STATUS_BYTEn0x78 One byte summary of the unit’s
fault condition.
Default value not applicable, read/write, paged, not stored in NVM. 111
STATUS_WORDn0x79 Tw o byte summary of the unit’s
fault condition.
Default value not applicable, read/write, paged, not stored in NVM. 111
STATUS_VOUTn0x7A Output voltage fault and warning
status.
Default value not applicable, read/write, paged, not stored in NVM. 112
LTM4675
41
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PMBUS COMMAND SUMMARY
Table 1. Summary of Supported Commands
PMBus COMMAND
NAME, OR FEATURE
CMD CODE
(REGISTER)
COMMAND OR FEATURE
DESCRIPTION LTM4675 NVM FACTORY-DEFAULT VALUE AND/OR ATTRIBUTES PAGE
STATUS_IOUTn0x7B Output current fault and warning
status.
Default value not applicable, read/write, paged, not stored in NVM. 112
STATUS_INPUT 0x7C Input supply (SVIN) fault and
warning status.
Default value not applicable, read/write, non-paged, not stored in NVM. 112
STATUS_
TEMPERATUREn
0x7D TSNSna-sensed temperature fault
and warning status for READ_
TEMERATURE_1n.
Default value not applicable, read/write, paged, not stored in NVM. 113
STATUS_CML 0x7E Communication and memory fault
and warning status.
Default value not applicable, read/write, non-paged, not stored in NVM. 113
STATUS_MFR_
SPECIFICn
0x80 Manufacturer specific fault and
state information.
Default value not applicable, read/write, paged, not stored in NVM. 113
READ_VIN 0x88 Measured input supply (SVIN)
voltage.
Default value not applicable, read-only, non-paged, not stored in NVM. 117
READ_IIN 0x89 Calculated total input supply
current.
Default value not applicable, read-only, non-paged, not stored in NVM. 117
READ_VOUTn0x8B Measured output voltage. Default value not applicable, read-only, paged, not stored in NVM. 117
READ_IOUTn0x8C Measured output current. Default value not applicable, read-only, paged, not stored in NVM. 117
READ_
TEMPERATURE_1n
0x8D Measurement of TSNSna-sensed
temperature.
Default value not applicable, read-only, paged, not stored in NVM. 117
READ_
TEMPERATURE_2
0x8E Measured control IC junction
temperature.
Default value not applicable, read-only, non-paged, not stored in NVM. 118
READ_DUTY_
CYCLEn
0x94 Measured duty cycle of MTn. Default value not applicable, read-only, paged, not stored in NVM. 118
READ_POUTn0x96 Calculated output power. Default value not applicable, read-only, paged, not stored in NVM. 118
PMBUS_REVISION 0x98 PMBus revision supported by this
device.
0x22 (Revision 1.2 of Part I and Revision 1.2 of Part II of PMBus
Specification documents), read-only, non-paged, not stored in NVM.
108
MFR_ID 0x99 Manufacturer identification, in
ASCII
“LT C ”, read-only, non-paged. 108
MFR_MODEL 0x9A Manufacturer’s part number, in
ASCII
LTM4675, read-only, non-paged. 109
MFR_SERIAL 0x9E Serial number of this specific unit. Up to nine bytes of custom-formatted data that identify the unit’s
configuration, read-only, non-paged.
109
MFR_VOUT_MAXn0xA5 Maximum allowed output voltage. 0x5B34 (5.700V) on both channels. Read-only, paged, not stored in user-
editable NVM.
92
USER_DATA_00 0xB0 OEM reserved data. Read/write, non-paged, stored in user-editable NVM. Recommended
against altering.
108
USER_DATA_01n0xB1 OEM reserved data. Read/write, paged, stored in user-editable NVM. Recommended against
altering.
108
USER_DATA_02 0xB2 OEM reserved data. Read/write, non-paged, stored in user-editable NVM. Recommended
against altering.
108
USER_DATA_03n0xB3 User-editable words available for
the user.
0x0000, read/write, paged, stored in user-editable NVM. 108
USER_DATA_04 0xB4 A user-editable word available for
the user.
0x0000, read/write, non-paged, stored in user-editable NVM. 108
MFR_INFO 0xB6 Manufacturing specific
information
Default value not applicable, read only, non-paged, not stored in NVM.
Bit 5 is 0b when ECC has made a correction to data derived from the
EEPROM user space.
116
LTM4675
42
Rev. C
For more information www.analog.com
Table 1. Summary of Supported Commands
PMBus COMMAND
NAME, OR FEATURE
CMD CODE
(REGISTER)
COMMAND OR FEATURE
DESCRIPTION LTM4675 NVM FACTORY-DEFAULT VALUE AND/OR ATTRIBUTES PAGE
MFR_EE_UNLOCK 0xBD Unlock user EEPROM for access
by MFR_EE_ERASE and MFR_EE_
DATA commands.
Default value not applicable, read/write, non-paged, not stored in NVM. 126
MFR_EE_ERASE 0xBE Initialize user EEPROM for bulk
programming by MFR_EE_DATA.
Default value not applicable, read/write, non-paged, not stored in NVM. 126
MFR_EE_DATA 0xBF Data transferred to and from
EEPROM using sequential PMBus
word reads or writes. Supports
bulk programming.
Default value not applicable, read/write, non-paged, not stored in NVM. 126
MFR_CHAN_
CONFIG_*n
0xD0 Channel-specific configuration
bits.
0x1F, read/write, paged, stored in user-editable NVM. Register is named
“MFR_CHAN_CONFIG” and referred to as “MFR_CHAN_CONFIG_
LTM467X” in LTpowerPlay.
84
MFR_CONFIG_ALL_* 0xD1 Global configuration bits, i.e.,
common to both VOUT channels
0 and 1.
0x09, read/write, non-paged, stored in user-editable NVM. Bit 4
configures whether the SYNC drive circuit is active (0b) or inactive (1b);
Bit 3 configures whether the Stuck PMBus Timer Timeout is 150ms for
Block Reads and 32ms for Non-Block Reads (0b) or 250ms for all
Reads (1b).
Register is named "MFR_CONFIG_ALL_LTM467X” in LTpowerPlay.
85
MFR_GPIO_
PROPAGATE_*n
0xD2 Configuration bits for propagating
faults to the GPIOn pins.
0x6893, read/write, paged, stored in user-editable NVM. Register is
named “MFR_GPIO_PROPAGATE” and referred to as “MFR_GPIO_
PROPAGATE_LTM467X” in LTpowerPlay.
106
MFR_PWM_
MODE_*n
0xD4 Configuration for the PWM engine
of each VOUT channel.
0xC1, read/write, paged, stored in user-editable NVM. Bit 1 commands
whether the output is in high range (0b) or low range (1b). Bit 0
commands whether the output is operating in Forced Continuous
Conduction Mode (1b) or Discontinuous Mode (0b).
Command is named MFR_PWM_MODE and referred to as MFR_PWM_
MODE_LTM467X in LTpowerPlay.
87
MFR_GPIO_
RESPONSEn
0xD5 Action to be taken by the device
when the GPIOn pin is asserted
low by circuitry external to the
unit.
0xC0 (make the respective output’s power stage high impedance, i.e.,
three-stated; autonomous restart upon fault removal),
read/write, paged, stored in user-editable NVM.
107
MFR_OT_FAULT_
RESPONSE
0xD6 Action to be taken by the device
when a control IC junction
overtemperature fault is detected.
0xC0 (make the respective output’s power stage high impedance, i.e.,
three-stated; autonomous restart upon fault removal), read-only, non-
paged, not stored in user-editable NVM.
104
MFR_IOUT_PEAKn0xD7 Maximum measured value of
READ_IOUTn since the last MFR_
CLEAR_PEAKS.
Default value not applicable, read-only, paged, not stored in NVM. 119
MFR_ADC_
CONTROL
0xD8 ADC telemetry parameter for
repeated fast ADC readback.
0x00, read/write, not paged, not stored in NVM. Allows telemetry
readback rates up to 125Hz instead of 10Hz, nominal.
119
MFR_ADC_
TELEMETRY_
STATUS
0xDA ADC status during short-loop. Default value not applicable, read/write, not paged, not stored in NVM.
ADC status indicating most recently digitized telemetry when engaged in
short round-robin loop (MFR_ADC_CONTROL=0x0D)
120
MFR_RETRY_
DELAYn
0xDB Retry interval during fault-retry
mode.
0xF3E8 (250ms), read/write, paged, stored in user-editable NVM. 99
MFR_RESTART_
DELAYn
0xDC Minimum interval (nominal) the
RUNn pin is pulled logic low by
internal circuitry.
0xFA58 (300ms), read/write, paged, stored in user-editable NVM. 99
MFR_VOUT_PEAKn0xDD Maximum measured value of
READ_VOUTn since the last
MFR_CLEAR_PEAKS.
Default value not applicable, read-only, paged, not stored in NVM. 118
PMBUS COMMAND SUMMARY
LTM4675
43
Rev. C
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PMBUS COMMAND SUMMARY
Table 1. Summary of Supported Commands
PMBus COMMAND
NAME, OR FEATURE
CMD CODE
(REGISTER)
COMMAND OR FEATURE
DESCRIPTION LTM4675 NVM FACTORY-DEFAULT VALUE AND/OR ATTRIBUTES PAGE
MFR_VIN_PEAK 0xDE Maximum measured value of
READ_VIN since the last MFR_
CLEAR_PEAKS.
Default value not applicable, read-only, non-paged, not stored in NVM. 118
MFR_
TEMPERATURE_1_
PEAKn
0xDF Maximum value of TSNSna
measured temperature since the
last MFR_CLEAR_PEAKS.
Default value not applicable, read-only, paged, not stored in NVM. 118
MFR_CLEAR_PEAKS 0xE3 Clears all peak values. Default value not applicable, send byte only, non-paged, not stored in
NVM.
110
MFR_PADS 0xE5 Digital status of the I/O pads. Default value not applicable, read-only, non-paged, not stored in NVM. 114
MFR_ADDRESS 0xE6 LTM4675's I2C slave address,
right-justified.
0x4F, read/write, non-paged, stored in user-editable NVM. Bits[6:4]
represent the user-configurable upper 3 bits of the 7-bit slave address of
the device. Bits[3:0] are dictated by the ASEL resistor pin-strap setting.
Setting this command to 0x80 disables device-specific addressing.
84
MFR_SPECIAL_ID 0xE7 Manufacturer code representing IC
silicon and revision
0x47AX, read-only, non-paged. 109
MFR_IIN_OFFSETn0xE9 Coefficient used in calculations of
READ_IIN and MFR_READ_IINn,
representing the contribution of
input current drawn by the control
IC, including the MOSFET drivers.
0x8BC9 (0.02956A), read/write, paged, stored in user-editable NVM. 93
MFR_FAULT_LOG_
STORE
0xEA Commands a transfer of the fault
log from RAM to EEPROM. This
causes the part to behave as if a
channel has faulted off.
Default value not applicable, send byte only, non-paged, not stored in
NVM.
126
MFR_FAULT_LOG_
CLEAR
0xEC Initialize the EEPROM block
reserved for fault logging and
clear any previous fault logging
locks.
Default value not applicable, send byte only, non-paged, not stored in
NVM.
126
MFR_READ_IINn0xED Calculated input current, by
channel.
Default value not applicable, read-only, paged, not stored in NVM. 117
MFR_FAULT_LOG 0xEE Fault log data bytes. This
sequentially retrieved data is used
to assemble a complete fault log.
Default value not applicable, read-only, non-paged, stored in fault-log
NVM.
125
MFR_COMMON 0xEF Manufacturer status bits that are
common across multiple ADI ICs/
modules.
Default value not applicable, read-only, non-paged, not stored in NVM. 114
MFR_COMPARE_
USER_ALL
0xF0 Compares current command
contents (RAM) with NVM.
Default value not applicable, send byte only, non-paged, not stored in
NVM.
121
MFR_
TEMPERATURE_2_
PEAK
0xF4 Maximum measured control IC
junction temperature since last
MFR_CLEAR_PEAKS.
Default value not applicable, read-only, non-paged, not stored in NVM. 118
MFR_PWM_
CONFIG_*
0xF5 Configuration bits for setting
the phase interleaving angles of
Channels 0 and 1, SHARE_CLK
behavior in UVLO, and using
the fully differential amplifier
to regulate paralleled output
channels.
0x10, read/write, non-paged, stored in user-editable NVM. When bit 7 is
0b, Channel 1's output is regulated by the VOSNS1 and SGND feedback
signals. When bit 7 is 1b, Channel 1's output is regulated by the VOSNS0+
and VOSNS0– feedback signals. Only set bit 7 to 1b for PolyPhase rail
applications. The command is named MFR_PWM_CONFIG and referred to
as MFR_PWM_CONFIG_LTM467X in LTpowerPlay.
88
MFR_IOUT_CAL_
GAIN_TCn
0xF6 Temperature coefficient of the
current sensing element.
0x0F14 (3860ppm/°C), read/write, paged, stored in user-editable NVM. 93
LTM4675
44
Rev. C
For more information www.analog.com
Table 1. Summary of Supported Commands
PMBus COMMAND
NAME, OR FEATURE
CMD CODE
(REGISTER)
COMMAND OR FEATURE
DESCRIPTION LTM4675 NVM FACTORY-DEFAULT VALUE AND/OR ATTRIBUTES PAGE
MFR_TEMP_1_
GAINn
0xF8 Sets the slope of the temperature
sensors that interface to TSNSna.
0x3FAE (0.995, in custom units), read/write, paged, stored in user-
editable NVM.
95
MFR_TEMP_1_
OFFSETn
0xF9 Sets the offset of the TSNSna
temperature sensor with respect
to –273.1°C.
0x8000 (0.0), read/write, paged, stored in NVM. 95
MFR_RAIL_
ADDRESSn
0xFA Common address for PolyPhase
outputs to adjust common
parameters.
0x80, read/write, paged, stored in NVM. 84
MFR_RESET 0xFD Commanded reset without
requiring a power down.
Default value not applicable, send byte only, non-paged, not stored in
NVM. Identical to RESTORE_USER_ALL.
87
PMBUS COMMAND SUMMARY
LTM4675
45
Rev. C
For more information www.analog.com
APPLICATIONS INFORMATION
Table 2. VOUTnCFG Pin Strapping Look-Up Table for the
LTM4675's Output Voltage, Coarse Setting (Not Applicable if
MFR_CONFIG_ALL[6] = 1b)
RVOUTnCFG*,**
(kΩ)
VOUTn (V) SETTING
COARSE MFR_PWM_MODEn[1] BIT
Open NVM NVM
32.4 See Table 3 See Table 3
22.6 3.3 0
18.0 3.1 0
15.4 2.9 0
12.7 2.7 0
10.7 2.5 0, if VTRIMn > 0mV
1, if VTRIMn ≤ 0mV
9.09 2.3 1
7.68 2.1 1
6.34 1.9 1
5.23 1.7 1
4.22 1.5 1
3.24 1.3 1
2.43 1.1 1
1.65 0.9 1
0.787 0.7 1
0 0.5 1
*RVOUTnCFG value indicated is nominal. Select RVOUTnCFG from a resistor
vendor such that its value is always within 3% of the value indicated in
the table. Take into account resistor initial tolerance, T.C.R. and resistor
operating temperatures, soldering heat/IR reflow, and endurance of the
resistor over its lifetime. Thermal shock/cycling, moisture (humidity) and
other effects (depending on one’s specific application) could also affect
RVOUTnCFG’s value over time. All such effects must be taken into account
in order for resistor pin strapping to yield the expected result at every
SVIN power-up and/or every execution of MFR_RESET or RESTORE_
USER_ALL, over the lifetime of one’s product.
**In applications where VOUT0 and VOUT1 are paralleled, the respective
VOUTnCFG and VTRIMnCFG pin-pairs can be electrically connected together;
common RCONFIG resistors can be applied, whose values are half of
what is prescribed in Table 2 and Table 3. See Figure 34, for example.
Table 3. VTRIMnCFG Pin Strapping Look-Up Table for the
LTM4675's Output Voltage, Fine Adjustment Setting (Not
Applicable if MFR_CONFIG_ALL[6] = 1b)
RVTRIMnCFG*,**
(kΩ)
VTRIM (mV) FINE
ADJUSTMENT
TO VOUTn
SETTING WHEN
RESPECTIVE
RVOUTnCFG ≠
32.4kΩ
VOUTn OUTPUT
VOLTAGE
SETTING
(V) WHEN
VOUTnCFG PIN
USES RCFG =
32.4kΩ
MFR_PWM_
MODEn[1] BIT
Open 0 NVM 0, if VOUT_OV_
FAULT_LIMITn
> 2.75V
1, if VOUT_OV_
FAULT_LIMITn
≤ 2.75V
32.4 99
22.6 86.625
18.0 74.25
15.4 61.875
12.7 49.5
10.7 37.125 5.50 0
9.09 24.75 5.25 0
7.68 12.375 5.00 0
6.34 –12.375 4.75 0
5.23 –24.75 4.50 0
4.22 –37.125 4.25 0
3.24 –49.5 4.00 0
2.43 –61.875 3.75 0
1.65 –74.25 3.63 0
0.787 –86.625 3.50 0
0 –99 3.46 0
*RVTRIMnCFG value indicated is nominal. Select RVTRIMnCFG from a
resistor vendor such that its value is always within 3% of the value
indicated in the table. Take into account resistor initial tolerance,
T.C.R. and resistor operating temperatures, soldering heat/IR reflow,
and endurance of the resistor over its lifetime. Thermal shock/cycling,
moisture (humidity) and other effects (depending on one’s specific
application) could also affect RVTRIMnCFG’s value over time. All such
effects must be taken into account in order for resistor pin strapping to
yield the expected result at every SVIN power-up and/or every execution
of MFR_RESET or RESTORE_USER_ALL, over the lifetime of one’s
product.
**In applications where VOUT0 and VOUT1 are paralleled, the respective
VOUTnCFG and VTRIMnCFG pin-pairs can be electrically connected together;
common RCONFIG resistors can be applied, whose values are half of
what is prescribed in Table 2 and Table 3. See Figure 34, for example.
LTM4675
46
Rev. C
For more information www.analog.com
APPLICATIONS INFORMATION
Table 4. FSWPHCFG Pin Strapping Look-Up Table to Set the LTM4675's Switching Frequency and Channel Phase-Interleaving Angle
(Not Applicable if MFR_CONFIG_ALL[6] = 1b)
RFSWPHCFG*
(kΩ)
SWITCHING
FREQUENCY (kHz) θSYNC TO θ0θSYNC TO θ1
BITS [2:0] OF
MFR_PWM_CONFIG
BIT [4] OF
MFR_CONFIG_ALL
Open NVM; LTM4675
Default = 500
NVM; LTM4675
Default = 0°
NVM; LTM4675
Default = 180°
NVM; LTM4675
Default = 000b
NVM; LTM4675
Default = 0b
32.4 250 0° 180° 000b0b
22.6 350 0° 180° 000b0b
18.0 425 0° 180° 000b0b
15.4 575 0° 180° 000b0b
12.7 650 0° 180° 000b0b
10.7 750 0° 180° 000b0b
9.09 1000 0° 180° 000b0b
7.68 500 120° 240° 100b0b
6.34 500 90° 270° 001b0b
5.23 Sync Slave** 0° 240° 010b1b
4.22 Sync Slave** 0° 120° 011b1b
3.24 Sync Slave** 60° 240° 101b1b
2.43 Sync Slave** 120° 300° 110b1b
1.65 Sync Slave** 90° 270° 001b1b
0.787 Sync Slave** 0° 180° 000b1b
0 Sync Slave** 120° 240° 100b1b
* RFSWPHCFG value indicated is nominal. Select RFSWPHCFG from a resistor vendor such that its value is always within 3% of the value indicated
in the table. Take into account resistor initial tolerance, T.C.R. and resistor operating temperatures, soldering heat/IR reflow, and endurance of
the resistor over its lifetime. Thermal shock/cycling, moisture (humidity) and other effects (depending on one’s specific application) could also
affect RFSWPHCFG’s value over time. All such effects must be taken into account in order for resistor pin-strapping to yield the expected result at
every SVIN power-up and/or every execution of MFR_RESET or RESTORE_USER_ALL, over the lifetime of one’s product.
** The "Sync Slave" setting results in MFR_CONFIG_ALL[4] being set to 1b and FREQUENCY_SWITCH being set according to user-configurable
EEPROM contents corresponding to Command 0x33 (factory default: 500kHz). In this configuration, the module's switching frequency
synchronizes to the SYNC signal, provided that the SYNC pin is driven in a manner consistent with specifications (see Switching Frequency and
Phase subsection of the Applications Information section for details).
LTM4675
47
Rev. C
For more information www.analog.com
APPLICATIONS INFORMATION
Table 5. ASEL Pin Strapping Look-Up Table to Set the
LTM4675's MFR_ADDRESS (Applicable Regardless of
MFR_CONFIG_ALL[6] Setting)
RASEL* (kΩ) SLAVE ADDRESS
BITS[6:4] BITS[3:0]
Open NVM NVM_R/W
32.4 NVM 1111_R/W
22.6 NVM 1110_R/W
18.0 NVM 1101_R/W
15.4 NVM 1100_R/W
12.7 NVM 1011_R/W
10.7 NVM 1010_R/W
9.09 NVM 1001_R/W
7.68 NVM 1000_R/W
6.34 NVM 0111_R/W
5.23 NVM 0110_R/W
4.22 NVM 0101_R/W
3.24 NVM 0100_R/W
2.43 NVM 0011_R/W
1.65 NVM 0010_R/W
0.787 NVM 0001_R/W
0 NVM 0000_R/W
where:
R/W = Read/Write bit in control byte.
All PMBus device addresses listed in the specification are 7 bits wide
unless otherwise noted.
Note: The LTM4675 will always respond to slave address 0x5A and 0x5B
regardless of the NVM or ASEL resistor configuration values.
*RASEL value indicated is nominal. Select RASEL from a resistor vendor
such that its value is always within 3% of the value indicated in the
table. Take into account resistor initial tolerance, T.C.R. and resistor
operating temperatures, soldering heat/IR reflow, and endurance of the
resistor over its lifetime. Thermal shock cycling, moisture (humidity)
and other effects (depending on one’s specific application) could also
affect RASEL’s value over time. All such effects must be taken into
account in order for resistor pin-strapping to yield the expected result
at every SVIN power-up and/or every execution of MFR_RESET or
RESTORE_USER_ALL, over the lifetime of one’s product.
Table 6. LTM4675 MFR_ADDRESS Command Examples
Expressed in 7- and 8-Bit Addressing
DESCRIPTION
HEX DEVICE
ADDRESS BIT
7
BIT
6
BIT
5
BIT
4
BIT
3
BIT
2
BIT
1
BIT
0 R/W7 BIT 8 BIT
Rail40x5A 0xB4 0 1 0 1 1 0 1 0 0
Global40x5B 0xB6 0 1 0 1 1 0 1 1 0
Default 0x4F 0x9E 0 1 0 0 1 1 1 1 0
Example 1 0x40 0x80 0 1 0 0 0 0 0 0 0
Example 2 0x41 0x82 0 1 0 0 0 0 0 1 0
Disabled2,3 10000000 0
Note 1: This table can be applied to the MFR_RAIL_ADDRESSn command,
but not the MFR_ADDRESS command.
Note 2: A disabled value in one command does not disable the device, nor
does it disable the Global address.
Note 3: A disabled value in one command does not inhibit the device from
responding to device addresses specified in other commands.
Note 4: It is not recommended to write the value 0x00, 0x0C
(7 bit), 0x5A (7 bit), 0x5B (7 bit), or 0x7C (7 bit) to the MFR_RAIL_
ADDRESSn or MFR_ADDRESS commands.
LTM4675
48
Rev. C
For more information www.analog.com
APPLICATIONS INFORMATION
VIN TO VOUT STEP-DOWN RATIOS
There are restrictions in the maximum VIN and VOUT step-
down ratio that can be achieved for a given input voltage.
Each output of the LTM4675 is capable of 95% duty cycle
at 500kHz, but the VIN to VOUT minimum dropout is still
a function of its load current and will limit output current
capability related to high duty cycle on the topside switch.
Minimum on-time tON(MIN) is another consideration in
operating at a specified duty cycle while operating at a
certain frequency due to the fact that tON(MIN) < D/fSW,
where D is duty cycle and fSW is the switching frequency.
tON(MIN) is specified in the electrical parameters as 45ns.
See Note 6 in the Electrical Characteristics section for
output current guideline.
INPUT CAPACITORS
The LTM4675 module should be connected to a low AC-
impedance DC source. For the regulator input four 22µF
input ceramic capacitors are used to handle the RMS
ripple current. A 47µF to 100µF surface mount aluminum
electrolytic bulk capacitor can be used for more input bulk
capacitance. This bulk input capacitor is only needed if
the input source impedance is compromised by long in-
ductive leads, traces or not enough source capacitance.
If low impedance power planes are used, then this bulk
capacitor is not needed.
For a buck converter, the switching duty-cycle can be
estimated as:
D
n
=
V
OUT
n
VIN
n
Without considering the inductor current ripple, for each
output, the RMS current of the input capacitor can be
estimated as:
ICIN
n
(RMS) =
I
OUT
n
(MAX)
η%• D
n
• 1−D
n
( )
In the above equation, η% is the estimated efficiency of the
power module. The bulk capacitor can be a switcher-rated
electrolytic aluminum capacitor, or a Polymer capacitor.
OUTPUT CAPACITORS
The LTM4675 is designed for low output voltage ripple
noise and good transient response. The bulk output
capacitors defined as COUT are chosen with low enough
effective series resistance (ESR) to meet the output volt-
age ripple and transient requirements. COUT can be a low
ESR tantalum capacitor, a low ESR polymer capacitor or
ceramic capacitor. The typical output capacitance range
for each output is from 400µF to 700µF. Additional output
filtering may be required by the system designer, if further
reduction of output ripple or dynamic transient spikes
is required. Table 20 shows a matrix of different output
voltages and output capacitors to minimize the voltage
droop and overshoot during a 4.5A/µs transient. The table
optimizes total equivalent ESR and total bulk capacitance
to optimize the transient performance. Stability criteria are
considered in the Table 20 matrix, and the Analog Devices
µModule Power Design Tool will be provided for stability
analysis. Multiphase operation reduces effective output
ripple as a function of the number of phases. Application
Note 77 discusses this noise reduction versus output
ripple current cancellation, but the output capacitance
should be considered carefully as a function of stability and
transient response. The Analog Devices µModule Power
Design Tool can calculate the output ripple reduction as
the number of implemented phases increases by N times.
A small value 10Ω resistor can be placed in series from
VOUTn to the VOSNS0+ or VOSNS1 pin to allow for a bode
plot analyzer to inject a signal into the control loop and
validate the regulator stability.
LIGHT LOAD CURRENT OPERATION
The LTM4675 has two modes of operation: high efficiency,
discontinuous conduction mode or forced continuous
conduction mode. The mode of operation is configured by
bit 0 of the MFR_PWM_MODEn command (discontinuous
conduction is always the start-up mode, forced continuous
is the default running mode).
LTM4675
49
Rev. C
For more information www.analog.com
APPLICATIONS INFORMATION
If a channel is enabled for discontinuous mode operation,
the inductor current is not allowed to reverse. The reverse
current comparator, IREV
, turns off the bottom MOSFET
(MBn) just before the inductor current reaches zero,
preventing it from reversing and going negative. Thus, the
controller can operate in discontinuous (pulse-skippng)
operation. In forced continuous operation, the inductor
current is allowed to reverse at light loads or under
large transient conditions. The peak inductor current
is determined solely by the voltage on the COMPna pin.
In this mode, the efficiency at light loads is lower than
discontinuous mode operation. However, continuous mode
exhibits lower output ripple and less interference with audio
circuitry. Forced continuous conduction mode may result
in reverse inductor current, which can cause the input
supply to boost. The VIN_OV_FAULT_LIMIT can detect
this (if SVIN is connected to VIN0 and/or VIN1) and turn off
the offending channel. However, this fault is based on an
ADC read and can nominally take up to 90ms to detect. If
there is a concern about the input supply boosting, keep
the part in discontinuous conduction operation.
SWITCHING FREQUENCY AND PHASE
The switching frequency of the LTM4675’s channels is
established by its analog phase-locked-loop (PLL) locking
on to the clock present at the module’s SYNC pin. The
clock waveform on the SYNC pin can be generated by
the LTM4675’s internal circuitry when an external pull-up
resistor to 3.3V (e.g., VDD33) is provided, in combination
with the LTM4675 control IC’s FREQUENCY_SWITCH
command being set to one of the following supported
values: 250kHz, 350kHz, 425kHz, 500kHz, 575kHz,
650kHz, 750kHz, 1MHz (see Table 8 for hexadecimal
values). In this configuration, the module is called a
“sync master”: using the factory-default setting of
MFR_CONFIG_ALL[4]=0b, SYNC becomes a bidirectional
open-drain pin, and the LTM4675 pulls SYNC logic low
for nominally 500ns at a time, at the prescribed clock
rate. The SYNC signal can be bused to other LTM4675
modules (configured as “sync slaves”), for purposes of
synchronizing switching frequencies of multiple modules
within a system—but only one LTM4675 should be
configured as a “sync master”; the other LTM4675(s)
should be configured as “sync slaves”.
There are two recommended ways to configure an
LTM4675 as a “sync slave”:
• Apply an appropriate pin-strap resistor setting on the
FSWPHCFG pin (see Table 4), and use the factory-default
setting MFR_CONFIG_ALL[6] = 0b. This configures
MFR_CONFIG_ALL[4] = 1b and FREQUENCY_SWITCH
according to EEPROM settings (0xFBE8 factory default,
corresponding to 500kHz). The LTM4675’s SYNC pin
thus becomes a high impedance input and the module
synchronizes its frequency to that of the externally
applied clock, provided that the frequency of the
externally applied clock exceeds ~45% of the target
frequency (FREQUENCY_SWITCH). If the SYNC clock is
absent, the module responds by operating at its target
frequency, indefinitely. If and when the SYNC clock is
restored, the module automatically phase-locks to the
SYNC clock as normal.
• Set FREQUENCY_SWITCH to 0x0000 and MFR_
CONFIG_ALL[4]=1b. Using MFR_CONFIG_ALL[4]=1b,
the LTM4675’s SYNC pin becomes a high impedance
input, only—i.e., it does not drive SYNC low. The module
synchronizes its frequency to that of the clock applied
to its SYNC pin. The only shortcoming of this approach
is: in the absence of an externally applied clock, the
switching frequency of the module will default to the
low end of its frequency-synchronization capture range
(~225kHz).
The FREQUENCY_SWITCH command can be altered
via I2C commands, but only when switching action is
disengaged, i.e., the module’s outputs are turned off. The
FREQUENCY_SWITCH command takes on the value stored
in NVM at SVIN power-up, but is overridden according
to a resistor pin-strap applied between the FSWPHCFG pin
and SGND only if the module is configured to respect
resistor pin-strap settings (MFR_CONFIG_ALL[6] = 0b).
LTM4675
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Table 4 highlights available resistor pin-strap and
corresponding FREQUENCY_SWITCH settings.
The relative phasing of all active channels in a PolyPhase
rail should be optimally phased. The relative phasing of
each rail is 360°/n, where n is the number of phases in
the rail. MFR_PWM_CONFIG[2:0] configures channel
relative phasing with respect to the SYNC pin. Phase
relationship values are indicated with 0° corresponding
to the falling edge of SYNC being coincident with the
turn-on of the top MOSFETs, MTn.
The MFR_PWM_CONFIG command can be altered
via I2C commands, but only when switching action is
disengaged, i.e., the module’s outputs are turned off. The
MFR_PWM_CONFIG command takes on the value stored
in NVM at SVIN power-up, but is overridden according to
a resistor pin-strap applied between the FSWPHCFG pin and
SGND only if the module is configured to respect resistor
pin-strap settings (MFR_CONFIG_ALL[6] = 0b). Table 4
highlights available resistor pin-strap and corresponding
MFR_PWM_CONFIG[2:0] settings.
Some combinations of FREQUENCY_SWITCH and
MFR_PWM_CONFIG[2:0] are not available by resistor
pin-strapping the FSWPHCFG pin. All combinations
of supported values for FREQUENCY_SWITCH and
MFR_PWM_CONFIG[2:0] can be configured by NVM
programming—or, I2C transactions, provided switching
action is disengaged, i.e., the module’s outputs are
turned off.
Care must be taken to minimize capacitance on SYNC
to assure that the pull-up resistor versus the capacitor
load has a low enough time constant for the application
to form a “clean” clock. (See “Open-Drain Pins”, later
in this section.)
When an LTM4675 is configured as a sync slave, it is
permissible for external circuitry to drive the SYNC pin
from a current-limited source (less than 10mA), rather
than using a pull-up resistor. Any external circuitry must
not drive high with arbitrarily low impedance at SVIN
power-up, because the SYNC output can be low impedance
until NVM contents have been downloaded to RAM.
Recommended LTM4675 switching frequencies of
operation for many common VIN-to-VOUT applications
are indicated in Table 7. When the two channels of an
LTM4675 are stepping input voltage(s) down to output
voltages whose recommended switching frequencies
in Table 7 are significantly different, operation at the
higher of the two recommended switching frequencies
is preferable, but minimum on-time must be considered.
(See Minimum On-Time Considerations section.) For
example, consider an application in which it is desired for
an LTM4675 to step-down 12VIN to 1VOUT on Channel 0,
and 12VIN to 3.3VOUT on Channel 1: according to Table 7,
the recommended switching frequency is 500kHz and
1MHz, respectively. However, the switching frequency
setting of the LTM4675 is common to both channels.
Based on the aforementioned guidance, operation at
1MHz would be preferred—in order to keep inductor
ripple currents reasonable—however, it is then realized
that the on-time for a 12VIN-to-1VOUT condition at 1MHz
is only 83ns, shy of the 90ns guardband recommendation.
Therefore, for this particular example, the recommended
switching frequency becomes 750kHz.
Table 7. Recommended Switching Frequency for Various
VIN-to-VOUT Step-Down Scenarios
5VIN 8VIN ~ 12VIN
0.9VOUT 425kHz 425kHz
1.0VOUT 500kHz 500kHz
1.2VOUT 500kHz 575kHz
1.5VOUT 575kHz 650kHz
1.8VOUT 650kHz 750kHz
2.5VOUT 650kHz 1MHz
3.3VOUT 650kHz 1MHz
5.0VOUT N/A 1MHz
The current drawn by the SVIN pin of the LTM4675 is not
digitized or computed. A value representing the estimated
SVIN current is located in the MFR_IIN_OFFSETn command,
and is used in the computations of input current readback
telemetry, namely READ_IIN and and MFR_READ_IINn.
The recommended setting of MFR_IIN_OFFSETn is
found in Table 8. The same value should be used for
MFR_IIN_OFFSET0 and MFR_IIN_OFFSET1 (i.e., Pages
0x00 and 0x01).
LTM4675
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MINIMUM ON-TIME CONSIDERATIONS
Minimum on-time, tON(MIN), is the smallest time duration
that the LTM4675 is capable of turning on the top MOSFET.
It is determined by internal timing delays and the gate
charge required to turn on the top MOSFET. Low duty
cycle applications may approach this minimum on-time
limit and care should be taken to ensure that:
tON(MIN) <
V
OUT
n
V
IN
n
• f
OSC
If the duty cycle falls below what can be accommodated
by the minimum on-time, the controller will begin to skip
cycles. The output voltage will continue to be regulated,
but the ripple voltage and current will increase.
The minimum on-time for the LTM4675 is 45ns, nominal,
guardband to 90ns.
VARIABLE DELAY TIME, SOFT-START AND OUTPUT
VOLTAGE RAMPING
The LTM4675 must enter its run state prior to soft-start.
The RUNn pins are released after the part initializes and
SVIN is greater than the VIN_ON threshold. If multiple
LTM4675s are used in an application, they should be
configured to share the same RUNn pins. They all hold
their respective RUNn pins low until all devices initialize
and SVIN exceeds the VIN_ON threshold for all devices.
The SHARE_CLK pin assures all the devices connected to
the signal use the same time base.
After the RUNn pin releases, the controller waits for the
user-specified turn-on delay (TON_DELAYn) prior to
initiating an output voltage ramp. Multiple LTM4675s and
other ADI parts can be configured to start with variable
delay times. To work correctly, all devices use the same
timing clock (SHARE_CLK) and all devices must share
the RUNn pin. This allows the relative delay of all parts
to be synchronized. The actual variation in the delay will
be dependent on the highest clock rate of the devices
connected to the SHARE_CLK pin (all Analog Devices ICs
are configured to allow the fastest SHARE_CLK signal to
control the timing of all devices). The SHARE_CLK signal
can be ±7.5% in frequency, thus the actual time delays
will have some variance.
Soft-start is performed by actively regulating the load voltage
while digitally ramping the target voltage from 0V to the
commanded voltage set point. The rise time of the voltage
ramp can be programmed using the TON_RISEn command
to minimize inrush currents associated with the start-up
voltage ramp. The soft-start feature is disabled by setting
TON_RISEn to any value less than 0.250ms. The LTM4675
performs the necessary math internally to assure the voltage
ramp is controlled to the desired slope. However, the voltage
slope can not be any faster than the fundamental limits of
the power stage. The number of steps in the ramp is equal
to TON_RISE/0.1ms. Therefore, the shorter the TON_RISEn
time setting, the more jagged the soft-start ramp appears.
The LTM4675 PWM always operates in discontinuous
mode during the TON_RISEn operation. In discontinuous
mode, the bottom MOSFET (MBn) is turned off as soon
as reverse current is detected in the inductor. This allows
the regulator to start up into a pre-biased load.
There is no analog tracking feature in the LTM4675;
however, two outputs can be given the same TON_RISEn and
TON_DELAYn times to achieve ratiometric rail tracking.
Because the RUNn pins are released at the same time and
both units use the same time base (SHARE_CLK), the
outputs track very closely. If the circuit is in a PolyPhase
configuration, all timing parameters must be the same.
Table 8. Recommended MFR_IIN_OFFSET
n
Setting vs
Switching Frequency Setting
SWITCHING
FREQUENCY
(kHz)
FREQUENCY_
SWITCH
COMMAND
VALUE (HEX.)
RECOMMENDED
MFR_IIN_
OFFSETn
SETTING (mA)
RECOMMENDED
MFR_IIN_
OFFSETn
SETTING (HEX.)
250 0xF3E8 20.26 0x8A98
350 0xFABC 23.98 0x8B12
425 0xFB52 26.77 0x8B6D
500 0xFBE8 29.56 0x8BC9
575 0x023F 32.35 0x9212
650 0x028A 35.14 0x9240
750 0x02EE 38.86 0x927D
1000 0x03E8 48.16 0x9315
Sync. to
External Clock,
fSYNC
N/A 0.372 • fSYNC +
10.96
*
*See Appendix C: PMBus Command Details, L11 data format.
LTM4675
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DAC VOLTAGE
ERROR (NOT
TO SCALE)
TIME DELAY OF
MANY SECONDS
DIGITAL SERVO
MODE ENABLED FINAL OUTPUT
VOLTAGE REACHED
TON_MAX_FAULT_LIMITn
TON_RISEnTIME 4675 F03
TON_DELAY
n
VOUTn
RUNn
VOUT_UV_FAULT_LIMITn
Figure 3. Timing Controlled VOUT Rise
APPLICATIONS INFORMATION
Coincident rail tracking can be achieved by setting two
outputs to have the same turn-on/off slew rates, identical
turn-on delays, and appropriately chosen turn-off delays:
VOUT _COMMANDRAIL1
TON_RISERAIL1
=VOUT _COMMANDRAIL2
TON_RISERAIL2
and
VOUT _COMMANDRAIL1
TOFF _FALL
RAIL1
=VOUT _COMMANDRAIL2
TOFF _FALL
RAIL2
and
TON_DELAYRAIL1 = TON_DELAYRAIL2
and (if VOUT_COMMANDRAIL2 ≥ VOUT_COMMANDRAIL1)
TOFF _DELAY
RAIL1 =
TOFF _DELAY
RAIL2 +1– VOUT _COMMANDRAIL1
VOUT _COMMANDRAIL2
⎛
⎝
⎜⎞
⎠
⎟
•TOFF _FALL
RAIL2
or else (VOUT_COMMANDRAIL2 < VOUT_COMMANDRAIL1)
TOFF _DELAY
RAIL2 =
TOFF _DELAY
RAIL1 +1– VOUT _COMMANDRAIL2
VOUT _COMMANDRAIL1
⎛
⎝
⎜⎞
⎠
⎟
•TOFF _FALL
RAIL1
The described method of start-up sequencing is time based.
For concatenated events it is possible to control the RUN
pin based on the GPIOn pin of a different controller (see
Figure 2). The GPIOn pin can be configured to release
when the output voltage of the converter is greater than
the VOUT_UV_FAULT_LIMITn. It is recommended to use
the unfiltered VOUT UV fault limit because there is little
appreciable time delay between the converter crossing the
UV threshold and the GPIOn pin releasing. The unfiltered
output can be enabled by the MFR_GPIO_PROPAGATEn[12]
setting. (Refer to the MFR section of the PMBus commands
in Appendix C: PMBus Command Details). The unfiltered
signal may have some glitching as the VOUT signal
transitions through the comparator threshold. A small
digital filter of 250µs internally deglitches the GPIOn pins.
If the TON_RISE time is greater than 100ms, the deglitch
filter should be complimented with an externally applied
capacitor between GPIOn and ground—to further filter
the waveform. The RC time-constant of the filter should
be set sufficiently fast to assure no appreciable delay is
incurred. For most applications, a value of 300µs to 500µs
will provide sufficient filtering without significantly delay-
ing the trigger event.
DIGITAL SERVO MODE
For maximum accuracy in the regulated output voltage,
enable the digital servo loop by asserting bit 6 of the
MFR_PWM_MODEn command. In digital servo mode,
the LTM4675 adjusts the regulated output voltage based
on the ADC voltage reading. Every 90ms the digital servo
loop steps the LSB of the DAC (nominally 1.375mV
or 0.6875mV depending on the voltage range bit,
MFR_PWM_MODEn[1]) until the output is at the correct
ADC reading. At power-up this mode engages after TON_
MAX_FAULT_LIMITn unless the limit is set to0 (infinite).
If the TON_MAX_FAULT_LIMITn is set to 0 (infinite), the
servo begins after TON_RISEn is complete and VOUTn has
exceeded VOUT_UV_FAULT_LIMITn and IOUT_OCn is
not present. This same point in time is when the output
changes from discontinuous to the mode commanded by
MFR_PWM_MODEn[0]. Refer to Figure 3 for details on
the VOUTn waveform under time based sequencing.
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If the TON_MAX_FAULT_LIMITn is set to a value greater
than 0 and the TON_MAX_FAULT_RESPONSEn is set to
ignore (0x00), the servo begins:
1. After the TON_RISEn sequence is complete
2. After the TON_MAX_FAULT_LIMITn time is reached;
and
3. After the VOUT_UV_FAULT_LIMITn has been exceed
or the IOUT_OC_FAULT_LIMITn is no longer active.
If the TON_MAX_FAULT_LIMITn is set to a value greater
than 0 and the TON_MAX_FAULT_RESPONSEn is not set
to ignore (0X00), the servo begins:
1. After the TON_RISEn sequence is complete;
2. After the TON_MAX_FAULT_LIMITn time has expired
and both VOUT_UV_FAULTn and IOUT_OC_FAULTn are
not present.
The maximum rise time is limited to 1.3 seconds.
In a PolyPhase configuration it is recommended only one
of the control loops have the digital servo mode enabled.
This will assure the various loops do not work against each
other due to slight differences in the reference circuits.
SOFT OFF (SEQUENCED OFF)
In addition to a controlled start-up, the LTM4675 also
supports controlled turn-off. The TOFF_DELAYn and
TOFF_FALLn functions are shown in Figure 4. TOFF_FALLn
is processed when the RUNn pin goes low or if the module
is commanded off. If the module faults off or GPIOn is
pulled low externally and the module is programmed to
respond to this (MFR_GPIO_RESPONSEn = 0xC0), the
output three-states (becomes high impedance) rather than
exhibiting a controlled ramp. The output then decays as
a function of the load.
The output voltage operates as shown in Figure 4 so long as
the part is in forced continuous mode and the TOFF_FALLn
time is sufficiently slow that the power stage can achieve
the desired slope. The TOFF_FALLn time can only be met if
the power stage and controller can sink sufficient current
to assure the output is at zero volts by the end of the fall
time interval. If the TOFF_FALLn time is set shorter than
the time required to discharge the load capacitance, the
output will not reach the desired zero volt state. At the end
of TOFF_FALLn, the controller ceases to sink current and
VOUTn decays at the natural rate determined by the load
impedance. If the controller is in discontinuous mode, the
controller does not pull negative current and the output
becomes pulled low by the load, not the power stage. The
maximum fail time is limited to 1.3 seconds. The number of
steps in the ramp is equal to TOFF_FALL/0.1ms.Therefore,
the shorter the TOFF_FALLn setting, the more jagged the
TOFF_FALLn ramp appears.
UNDERVOLTAGE LOCKOUT
The LTM4675 is initialized by an internal threshold-
based UVLO where SVIN must be approximately 4V and
INTVCC, VDD33, VDD25 must be within approximately
20% of the regulated values. In addition, VDD33 must
be within approximately 7% of the targeted value before
the LTM4675 releases its RUNn pins. After the part has
initialized, an additional comparator monitors SVIN. The
VIN_ON threshold must be exceeded before the power
sequencing can begin. When SVIN drops below the VIN_OFF
threshold, the LTM4675 ceases PWM action and SVIN must
increase above the VIN_ON threshold before the controller
will restart. The normal start-up sequence will be allowed
after the VIN_ON threshold is crossed.
It is possible to program the contents of the NVM in
the application if the VDD33 supply is externally driven.
This activates the digital portion of the LTM4675
without engaging the high voltage sections. PMBus
communications are valid in this supply configura-
tion. If SVIN has not been applied to the LTM4675,
Figure 4. TOFF_DELAYn and TOFF_FALLn
TOFF_FALLn
TOFF_DELAYnTIME 4675 F04
VOUTn
RUNn
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MFR_COMMON[3] will be asserted low, indicating that
NVM has not initialized. If this condition is detected, the
part will only respond to addresses 0x5A and 0x5B. To
initialize the part issue the following set of commands:
global address 0x5B command 0xBD data 0x2B followed
by global address 0x5B command 0xBD and data 0xC4.
The part will now respond to the correct address. Configure
the part as desired then issue a STORE_USER_ALL. When
SVIN is applied a MFR_RESET or RESTORE_USER_ALL,
command must be issued to allow the PWM to be enabled
and valid ADC conversions to be read.
FAULT DETECTION AND HANDLING
The LTM4675 GPIOn pins are configurable to indicate a
variety of faults including OV/UV, OC, OT, timing faults,
peak overcurrent faults. In addition the GPIOn pins can be
pulled low by external sources to indicate to the LTM4675
the presence of a fault in some other portion of the system.
The fault response is configurable via PMBus Command
Code names with a _RESPONSE suffix and allows the
following options:
n Ignore
n Shut Down Immediately—Latch Off
n Shut Down Immediately—Retry Indefinitely at the Time
Interval Specified in MFR_RETRY_DELAYn
Refer to Appendix C and the PMBus specification for
more details.
The OV response is automatic and rapid. If an OV is de-
tected, MTn is turned off and BGn is turned on, until the
OV condition clears.
Fault logging is available on the LTM4675. The fault log-
ging is configurable to automatically store data when a
fault occurs that causes the unit to fault off. The header
portion of the fault logging table contains peak values. It
is possible to read these values at any time. This data will
be useful while troubleshooting the fault.
If the LTM4675 internal temperature is in excess of 85°C
or below 0°C, the write into the NVM is not recommended.
The data will still be held in RAM, unless the 3.3V supply
UVLO threshold is reached. If the die temperature exceeds
130°C all NVM communication is disabled until the die
temperature drops below 125°C, with the exception of
the RESTORE_USER_ALL command, which is valid at
any temperature.
OPEN-DRAIN PINS
Note that up to nine pull-up resistors are required for
proper operation of the LTM4675:
• Three for the SMBus/I2C interface (the SCL, SDA, and
ALERT pins); two, only if the system SMBus host does
not make use of the ALERT interrupt. (These are 5V
tolerant).
• One each for the RUN0 and RUN1 pins (or, just one
to RUN0 and RUN1, if RUN0 and RUN1 are electrically
connected together). (These are 5V tolerant).
• One each for GPIO0 and GPIO1 (or, just one to GPIO0
and GPIO1, if GPIO0 and GPIO1 are electrically connected
together). (These are 3.3V tolerant).
• One on SHARE_CLK, required, for the LTM4675 to
establish a heartbeat time base for timing-related op-
erations and functions (output voltage ramp-up timing,
voltage margining transition timing, SYNC open-drain
drive frequency). (SHARE CLK is 3.3V tolerant).
• One on SYNC, in order for the LTM4675 to phase lock
to the frequency generated by the open-drain output
of its digital engine. EXCEPTION: in some applications,
it is desirable to drive the LTM4675’s SYNC pin with
a hard-driven (low impedance) external clock. This
is the only scenario where the LTM4675 does not
require a pull-up resistor on SYNC. However, be aware
that the SYNC pin can be low impedance during NVM
initialization, i.e., during download of EEPROM contents
to RAM (for ~50ms [Note 12] after SVIN power is
applied). Therefore, the hard-driven clock signal should
only be applied to the LTM4675 SYNC pin through a
series resistor whose impedance limits current into the
SYNC pin during NVM initialization to less than 10mA.
If FREQUENCY_SWITCH=0x0000, any clock signal
should be provided prior to the RUNn pins toggle from
logic low to logic high, or else the switching frequency
of the LTM4675 will start off at the low end of its PLL-
capture range (~225kHz) until the SYNC clock becomes
established. (SYNC is 3.3V tolerant).
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All the above pins interface to pull-down transistors within
the module that can sink 3mA at 0.4V. The low threshold
on the pins is 0.8V; thus, plenty of margin on the digital
signals with 3mA of current. For 3.3V pins, 3mA of current
is a 1.1k resistor. Unless there are transient speed issues
associated with the RC time constant of the resistor pull-
up and parasitic capacitance to ground, a 10k resistor or
larger is generally recommended.
For high speed signals such as the SDA, SCL and SYNC,
a lower value resistor may be required. The RC time con-
stant should be set to 1/3 to 1/5 the required rise time
to avoid timing issues. For a 100pF load and a 400kHz
PMBus communication rate, the rise time must be less
than 300ns. The resistor pull-up on the SDA and SCL pins
with the time constant set to 1/3 the rise time:
RPULLUP =
t
RISE
3•100pF =1k
Be careful to minimize parasitic capacitance on the SDA and
SCL pins to avoid communication problems. To estimate
the loading capacitance, monitor the signal in question
and measure how long it takes for the desired signal to
reach approximately 63% of the output value. This is one
time constant.
The SYNC pin interfaces to a pull-down transis-
tor within the module whose output is held low for
nominally 500ns per switching period. If the internal
oscillator is set for 500kHz and the load is 100pF and a
3x time constant is required, the resistor calculation is
as follows:
RPULLUP =
2µs – 500ns
3•100pF =5k
The closest 1% resistor is 4.99k.
If timing errors are occurring or if the SYNC frequency is
not as fast as desired, monitor the waveform and determine
if the RC time constant is too long for the application. If
possible reduce the parasitic capacitance. If not reduce
the pull up resistor sufficiently to assure proper timing.
PHASE-LOCKED LOOP AND FREQUENCY
SYNCHRONIZATION
The LTM4675 has a phase-locked loop (PLL) comprised
of an internal voltage-controlled oscillator (VCO) and a
phase detector. The PLL is locked to the falling edge of
the SYNC pin. The phase relationship between channel 0,
channel 1 and the falling edge of SYNC is controlled by
the lower 3 bits of the MFR_PWM_CONFIG command. For
PolyPhase applications, it is recommended all the phases
be spaced evenly. Thus for a 2-phase system the signals
should be 180° out of phase and a 4-phase system should
be spaced 90°.
The phase detector is an edge-sensitive digital type that
provides a known phase shift between the external and
internal oscillators. This type of phase detector does not
exhibit false lock to harmonics of the external clock.
The output of the phase detector is a pair of complemen-
tary current sources that charge or discharge the internal
filter network. The PLL lock range is guaranteed between
225kHz and 1.1MHz.
The PLL has a lock detection circuit. If the PLL should lose
lock during operation, bit 4 of the STATUS_MFR_SPECIFIC
command is asserted and the ALERT pin is pulled low.
The fault can be cleared by writing a 1 to the bit. If the
user does not wish to see the PLL_FAULT, even if a
synchronization clock is not available at power up, bit 3
of the MFR_CONFIG_ALL command must be asserted.
If the SYNC signal is not clocking in the application, the
PLL runs at the lowest free running frequency of the VCO.
This will be well below the intended PWM frequency of
the application and may cause undesirable operation of
the converter.
If the PWM (SWn) signal appears to be running at too
high a frequency, monitor the SYNC pin. Extra transitions
on the falling edge will result in the PLL trying to lock on
to noise instead of the intended signal. Review routing
of digital control signals and minimize crosstalk to the
SYNC signal to avoid this problem. Multiple LTM4675s
are required to share the SYNC pin in PolyPhase
LTM4675
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configurations; for other configurations, it is optional.
If the SYNC pin is shared between LTM4675s, only one
LTM4675 can be programmed with a frequency output.
All the other LTM4675s must be configured for external
clock (MFR_CONFIG_ALL[4]=1b, and/or see Table 4).
RCONFIG PIN-STRAPS (EXTERNAL RESISTOR
CONFIGURATION PINS)
The LTM4675 default NVM is programmed to respect
the RCONFIG pins. If a user wishes the output voltage,
PWM frequency and phasing and the address to be set
without programming the part or purchasing specially
programmed parts, the RCONFIG pins can be used to
establish these parameters—provided MFR_CONFIG_
ALL[6] = 0b. The RCONFIG pins only require a resistor
terminating to SGND of the LTM4675. The RCONFIG pins
are only monitored at initial power up and during a reset
(MFR_RESET or RESTORE_USER_ALL) so modifying their
values perhaps using a DAC after the part is powered will
have no effect. To assure proper operation, the value of
RCONFIG resistors applied to the LTM4675 pin-strapping
pins must not deviate more than ±3% away from the target
nominal values indicated in lookup Table 2 to Table 5,
over the lifetime of the product. Thin film, 1% tolerance
(or better), ±50ppm/°C-T.C.R. rated (or better) resistors
from vendors such as KOA Speer, Panasonic, Vishay and
Yageo are good candidates. Noisy clock signals should
not be routed near these pins. Note that bits [3:0] of
MFR_ADDRESS are dictated by the ASEL pin-strap resistor
regardless of the setting of MFR_CONFIG_ALL[6].
VOLTAGE SELECTION
When an output voltage is set using the RCONFIG pins on
VOUTn_CFG and VTRIMn_CFG (MFR_CONFIG_ALL[6] =
0b), the following parameters are set as a percentage of
the output voltage:
• VOUT_OV_FAULT_LIMIT +10%
• VOUT_OV_WARN +7.5%
• VOUT_MAX +7.5%
• VOUT_MARGIN_HI +5%
• VOUT_MARGIN_LO –5%
• VOUT_UV_WARN –6.5%
• VOUT_UV_FAULT_LIMIT –7%
CONNECTING THE USB TO THE I2C/SMBus/PMBus
CONTROLLER TO THE LTM4675 IN SYSTEM
The ADI USB to I2C/SMBus/PMBus controller can be
interfaced to the LTM4675 on the user’s board for pro-
gramming, telemetry and system debug. The controller,
when used in conjunction with LTpowerPlay, provides a
powerful way to debug an entire power system. Faults are
quickly diagnosed using telemetry, fault status registers
and the fault log. The final configuration can be quickly
developed and stored to the LTM4675 EEPROM.
LTM4675
57
Rev. C
For more information www.analog.com
APPLICATIONS INFORMATION
Figure 5 and Figure 6 illustrate the application schematics
for powering, programming and communicating with
one or more
LTM4675
s via the ADI I2C/SMBus/PMBus
controller regardless of whether or not system power is
present. If system power is not present the dongle will
power the
LTM4675
through the VDD33 supply pin. To
initialize the part when SVIN is not applied and the VDD33
pin is powered use global address 0x5B command 0xBD
data 0x2B followed by address 0x5B command 0xBD data
0xC4. The part can now be communicated with, and the
project file updated. To write the updated project file to
the NVM issue a STORE_USER_ALL command. When
SVIN is applied, a MFR_RESET or RESTORE_USER_ALL
must be issued to allow the PWM to be enabled and valid
ADCs to be read.
Because of the controllers limited current sourcing capabil-
ity, only the LTM4675s, their associated pull-up resistors
and the I2C pull-up resistors should be powered from the
ORed 3.3V/3.4V supply. In addition, any device sharing
the I2C bus connections with the LTM4675 must not have
body diodes between the SDA/SCL pins and their respec-
tive VDD node because this will interfere with bus com-
munication in the absence of system power. In Figure 5,
the dongle will not bias the LTM4675s when SVIN is
present. It is recommended the RUNn pins be held low
to avoid providing power to the load until the part is fully
configured.
The ADI controller/adapter I2C connections are opto-
isolated from the PC USB. The 3.3V/3/4V from the control-
ler/adapter and the LTM4675 VDD33 pin must be driven to
each LTM4675 with a separate PFET or diode, according to
Figure 5 and Figure 6. Only when SVIN is not applied is it
permissible for the VDD33 pins to be electrically in parallel
because the INTVCC LDO is off. The DC1613’s 3.3V current
limit is 100mA but typical VDD33 currents are under 15mA.
The VDD33 does back drive the INTVCC pin. Normally this
is not an issue if SVIN is open. The DC2086 is capable of
delivering 3.4V at 2A.
Using a 4-pin header in Figure 5 or Figure 6 maximizes
flexibility to alter the LTM4675’s NVM contents at any stage
of the user’s product development and production cycles.
If the LTM4675’s NVM is “pre-programmed”, i.e., contains
its finalized configuration, prior to being soldered to the
user’s PCB/motherboard—or, if other means have been
provided for altering the LTM4675's NVM contents in the
user’s system—then the 3.3V/3.4V pin on the header is
not needed, and a 3-pin header is sufficient to establish
GUI communications. The LTM4675 can be purchased
with customized NVM contents; consult factory for details.
Alternatively, the NVM contents of the LTM4675 can be
configured in a mass production environment by design-
ing for it in ICT (in-circuit test), or by providing a means
of applying SVIN while holding the LTM4675’s RUN pins
low. Communication to the module must be made possible
via the SCL and SDA pins/nets in all NVM programming
scenarios. Recommended headers are found in Table 9
and Table 10.
LTM4675
58
Rev. C
For more information www.analog.com
APPLICATIONS INFORMATION
Figure 6. Circuit Suitable for Programming EEPROM/NVM of LTM4675 and Other ADI PSM
Modules/ICs in Vast Systems, Even When VIN Power is Absent, TA > 20°C and TJ < 85°C
Figure 5. Circuit Suitable for Programming EEPROM/NVM of LTM4675 and Other ADI
PSM Modules/ICs in Vast Systems, Even When VIN Power is Absent, 0°C < TJ ≤ 85°C
SVIN
VIN
VDD33 VDD25
SDA
VGS MAX ON THE TP0101K IS 8V. IF VIN > 16V,
CHANGE THE RESISTOR DIVIDER ON THE PFET GATE
ALTERNATE PFETS/PACKAGES:
SOT-723: GOOD-ARK SEMI SSF2319GE
ON SEMI NTK3139PT1G
ROHM RZM002P02T2L
SOT-523: DIODES INC. DMG1013T-7
GOOD-ARK SEMI SSF2319GD
SOT-563: DIODES INC. DMP2104V-7
ON SEMI NTZS3151PT1G
SOT-323: DIODES INC. DMG1013UW-7
ON SEMI NTS2101PT1G
VISHAY Si1303DL-T1-E3
4675 F05
10k
100k
TP0101K
SOT-23
SEE TABLES 9-13 FOR
CONNECTOR AND
PINOUT OPTIONS
ISOLATED 3.4V
(USUALLY NEEDED)
SCL
SDA
TP0101K
SOT-23
100k
TO LTC DC2086 DIGITAL
POWER PROGRAMMING
ADAPTER (REQUIRES LTC
DC1613 USB TO I2C/SMBus/
PMBus CONTROLLER)
MODULE PROGRAMMING
AND COMMUNICATION
INTERFACE HEADER
SCL
WP SGND
LTM4675
SVIN
VDD33
SDA
SCL
WP SGND
LTM4675
•
•
•
•
•
•
10k
VDD25
SVIN
VIN
VDD33 VDD25
SDA
D1, D2: NXP PMEG2005AEL OR PMEG2005AELD.
DIODE SELECTION IS NOT ARBITRARY.
USE VF < 210mV AT IF = 20mA
4675 F06
10k
SEE TABLES 9-13 FOR
CONNECTOR AND
PINOUT OPTIONS
ISOLATED 3.4V
(USUALLY NEEDED)
SCL D1
SOD882
SDA
MODULE PROGRAMMING
AND COMMUNICATION
INTERFACE HEADER
TO LTC DC2086 DIGITAL
POWER PROGRAMMING
ADAPTER (REQUIRES LTC
DC1613 USB TO I2C/SMBus/
PMBus CONTROLLER)
SCL
WP SGND
LTM4675
SVIN
VDD33
SDA
SCL
WP SGND
LTM4675
•
•
•
•
•
•
10k
VDD25
D2
SOD882
LTM4675
59
Rev. C
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APPLICATIONS INFORMATION
Table 9. 4-Pin Headers, 2mm Pin-to-Pin Spacing, Gold Flash or Plating, Compatible with DC2086 Cables
MOUNTING
STYLE
INSERTION
ANGLE INTERFACE STYLE VENDOR PART NUMBER PINOUT STYLE (SEE TABLE 11)
Surface Mount
Vertical
Shrouded and Keyed Header Hirose DF3DZ-4P-2V(51)
DF3DZ-4P-2V(50)
DF3Z-4P-2V(50)
Type A
Non Shrouded, Non-Keyed Header 3M 951104-2530-AR-PR Type A and B Supported. Reversible/Not Keyed
Right Angle
Shrouded and Keyed Header Hirose DF3DZ-4P-2H(51)
DF3DZ-4P-2H(50)
Type A
Non Shrouded. Cable-to-Header/PCB
Mechanics Yield Keying Effect
FCI 10112684-G03-04ULF Type B. Keying Achieved by PCB Surface
Through-Hole
Vertical
Shrouded and Keyed Header Hirose DF3-4P-2DSA(01) Type A
Non Shrouded, Non-Keyed Header Harwin M22-2010405 Type A and B Supported. Reversible/Not Keyed
Samtec TMM-104-01-LS
Sullins NRPN041PAEN-RC
Right Angle
Shrouded and Keyed Header Hirose DF3-4P-2DS(01) Type A
Non Shrouded. Cable-to-Header/PCB
Mechanics Yield Keying Effect
Norcomp 27630402RP2 Type B. Keying Achieved by Intentional PCB
Interference
Harwin M22-2030405
Samtec TMM-104-01-L-S-RA
Table 10. 3-Pin Headers, 2mm Pin-to-Pin Spacing, Gold Flash or Plating, Compatible with DC2086 Cables
MOUNTING
STYLE
INSERTION
ANGLE INTERFACE STYLE VENDOR PART NUMBER PINOUT STYLE (SEE TABLE 12)
Surface Mount
Vertical
Shrouded and Keyed Header Hirose DF3DZ-3P-2V(51)
DF3DZ-3P-2V(50)
DF3Z-3P-2V(50)
Type A
Non Shrouded, Non-Keyed Header 3M 951103-2530-AR-PR Type A and B Supported. Reversible/Not Keyed
Right Angle
Shrouded and Keyed Header Hirose DF3DZ-3P-2H(51)
DF3DZ-3P-2H(50)
Type A
Non Shrouded. Cable-to-Header/PCB
Mechanics Yield Keying Effect
FCI 10112684-G03-03LF Type B. Keying Achieved by PCB Surface
Through-Hole
Vertical
Shrouded and Keyed Header Hirose DF3-3P-2DSA(01) Type A
Non Shrouded, Non-Keyed Header Harwin M22-2010305 Type A and B Supported. Reversible/Not Keyed
Samtec TMM-103-01-LS
Sullins NRPN031PAEN-RC
Right Angle
Shrouded and Keyed Header Hirose DF3-3P-2DS(01) Type A
Non Shrouded. Cable-to-Header/PCB
Mechanics Yield Keying Effect
Norcomp 27630302RP2 Type B. Keying Achieved by Intentional PCB
Interference
Harwin M22-2030305
Samtec TMM-103-01-L-S-RA
Table 11. Recommended 4-Pin Header Pinout (Pin Numbering
Scheme Adheres to Hirose Conventions). Interfaces to DC2086
Cables
PIN NUMBER
PINOUT STYLE “A”
(SEE TABLE 9)
PINOUT STYLE “B”
(SEE TABLE 9)
1 SDA Isolated 3.3V/3.4V
2 GND SCL
3 SCL GND
4 Isolated 3.3V/3.4V SDA
Table 12. Recommended 3-Pin Header Pinout (Pin Numbering
Scheme Adheres to Hirose Conventions). Interfaces to DC2086
Cables
PIN NUMBER PINOUT STYLE “A”
(SEE TABLE 10)
PINOUT STYLE “B”
(SEE TABLE 10)
1 SDA SCL
2 GND GND
3 SCL SDA
LTM4675
60
Rev. C
For more information www.analog.com
APPLICATIONS INFORMATION
LTpowerPlay: AN INTERACTIVE GUI FOR DIGITAL
POWER SYSTEM MANAGEMENT
LTpowerPlay is a powerful Windows-based development
environment that supports Analog Devices digital power
ICs including the LTM4675. The software supports a variety
of different tasks. LTpowerPlay can be used to evaluate
Analog Devices ICs by connecting to a demo board or the
user application. LTpowerPlay can also be used in an offline
mode (with no hardware present) in order to build multiple
Figure 7. LTPowerPlay
IC configuration files that can be saved and reloaded at a
later time. LTpowerPlay provides unprecedented diagnostic
and debug features. It becomes a valuable diagnostic tool
during board bring-up to program or tweak the power
system or to diagnose power issues when bringing up
rails. LTpowerPlay utilizes Analog Devices’s USB-to-I2C/
SMBus/PMBus controller to communication with one of
the many potential targets including the DC2053 (single
LTM4675), DC1811 (single LTM4676A) or DC1989B (dual,
triple, quad LTM4676A) demo boards, or a customer target
system. The software also provides an automatic update
feature to keep the revisions current with the latest set of
device drivers and documentation. A great deal of context
sensitive help is available with LTpowerPlay along with
several tutorial demos. Complete information is available at
LTpowerPlay.
Table 13. 4-Pin Male-to-Male Shrouded and Keyed Adapter
(Optional. Eases Creation of Adapter Cables, if Deviating from
Recommended Connectors/Connector Pinouts). Interfaces to
DC2086 Cables
VENDOR PART NUMBER WEBSITE
Hirose DF3-4EP-2A www.hirose.com, www.hirose.co.jp
LTM4675
61
Rev. C
For more information www.analog.com
APPLICATIONS INFORMATION
PMBus COMMUNICATION AND COMMAND PROCESSING
The LTM4675 has one deep buffer to hold the last data
written for each supported command prior to processing
as shown in Figure 8; Write Command Data Processing.
When the part receives a new command from the bus,
it copies the data into the Write Command Data Buffer,
indicates to the internal processor that this command
data needs to be fetched, and converts the command to
its internal format so that it can be executed.
Tw o distinct parallel blocks manage command buffering
and command processing (fetch, convert, and execute)
to ensure the last data written to any command is never
lost. Command data buffering handles incoming PM-
Bus writes by storing the command data to the Write
Command Data Buffer and marking these commands for
future processing. The internal processor runs in parallel
and handles the sometimes slower task of fetching, con-
verting and executing commands marked for processing.
Some computationally intensive commands (e.g., timing
parameters, temperatures, voltages and currents) have
internal processor execution times that may be long
relative to PMBus timing. If the part is busy processing a
command, and new command(s) arrive, execution may
be delayed or processed in a different order than received.
The part indicates when internal calculations are in process
via bit5 of MFR_COMMON (‘calculations not pending’).
When the part is busy calculating, bit 5 is cleared. When
this bit is set, the part is ready for another command. An
example polling loop is provided in Figure 8 which ensures
that commands are processed in order while simplifying
error handling routines.
When the part receives a new command while it is busy,
it will communicate this condition using standard PMBus
protocol. Depending on part configuration it may either
NACK the command or return all ones (0xFF) for reads. It
may also generate a BUSY fault and ALERT notification,
or stretch the SCL clock low. For more information refer
to PMBus Specification v1.2, Part II, Section 10.8.7 and
SMBus v2.0 section 4.3.3. Clock stretching can be enabled
by asserting bit 1 of MFR_CONFIG_ALL. Clock stretching
will only occur if enabled and the bus communication
speed exceeds 100kHz.
PMBus busy protocols are well accepted standards, but
can make writing system level software somewhat com-
plex. The part provides three ‘hand shaking’ status bits
which reduce complexity while enabling robust system
level communication.
The three hand shaking status bits are in the MFR_
COMMON register. When the part is busy executing an
internal operation, it will clear bit 6 of MFR_COMMON
(‘module not busy’). When the part is busy specifically
because it is in a transitional VOUT state (margining hi/lo,
power off/on, moving to a new output voltage set point,
etc.) it will clear bit 4 of MFR_COMMON (‘output not in
transition’). When internal calculations are in process, the
part will clear bit5 of MFR_COMMON (‘calculations not
pending’). These three status bits can be polled with a
PMBus read byte of the MFR_COMMON register until all
three bits are set. A command immediately following the
status bits being set will be accepted without NACKing or
generating a BUSY fault/ALERT notification. The part can
NACK commands for other reasons, however, as required
by the PMBus spec (for instance, an invalid command or
data). An example of a robust command write algorithm
for the VOUT_COMMANDn register is provided in Figure 9.
DECODER
CMD
INTERNAL
PROCESSOR
WRITE COMMAND
DATA BUFFER
PAGE
CMDS
0x00
0x21
0xFD
4675 F08
x1
•
•
•
•
•
•
MFR_RESET
VOUT_COMMAND
S
CALCULATIONS
PENDING
PMBus
WRITE
R
FETCH,
CONVERT
DATA
AND
EXECUTE
DATA
MUX
Figure 8. Write Command Data Processing
Figure 9. Example of a Command Write of VOUT_COMMAND
// wait until bits 6, 5, and 4 of MFR_COMMON are all set
do
{
mfrCommonValue = PMBUS_READ_BYTE(0xEF);
partReady = (mfrCommonV
alue & 0x68) == 0x68;
}while (!partReady)
// now the part is ready to receive the next command
PMBUS_WRITE_WORD(0x21, 0x2000); //write VOUT_COMMAND to 2V
LTM4675
62
Rev. C
For more information www.analog.com
APPLICATIONS INFORMATION
It is recommended that all command writes (write byte,
write word, etc.) be preceded with a polling loop to avoid
the extra complexity of dealing with busy behavior and
unwanted ALERT notification. A simple way to achieve this
is by creating SAFE_WRITE_BYTE() and SAFE_WRITE_
WORD() subroutines. The above polling mechanism allows
one’s software to remain clean and simple while robustly
communicating with the part. For a detailed discussion
of these topics and other special cases please refer to the
application note section.
When communicating using bus speeds at or below
100kHz, the polling mechanism shown here provides a
simple solution that ensures robust communication without
clock stretching. At bus speeds in excess of 100kHz, it is
strongly recommended that the part be configured to en-
able clock stretching. This requires a PMBus master that
supports clock stretching. System software that detects
and properly recovers from the standard PMBus NACK/
BUSY faults as described in the PMBus Specification v1.2,
Part II, Section 10.8.7 is required to communicate above
100kHz without clock stretching. Clock stretching will not
extend the PMBus speed beyond the specified 400kHz.
THERMAL CONSIDERATIONS AND
OUTPUT CURRENT DERATING
The thermal resistances reported in the Pin Configuration
section of this data sheet are consistent with those pa-
rameters defined by JESD51-12 and are intended for use
with finite element analysis (FEA) software modeling tools
that leverage the outcome of thermal modeling, simula-
tion, and correlation to hardware evaluation performed on
a µModule package mounted to a hardware test board.
The motivation for providing these thermal coefficients is
found in JESD51-12 (“Guidelines for Reporting and Using
Electronic Package Thermal Information”).
Many designers may opt to use laboratory equipment
and a test vehicle such as the demo board to predict the
µModule regulator’s thermal performance in their appli-
cation at various electrical and environmental operating
conditions to compliment any FEA activities. Without FEA
software, the thermal resistances reported in the Pin Con-
figuration section are, in and of themselves, not relevant to
providing guidance of thermal performance; instead, the
derating curves provided in this data sheet can be used
in a manner that yields insight and guidance pertaining to
one’s application-usage, and can be adapted to correlate
thermal performance to one’s own application.
The Pin Configuration section gives four thermal coeffi-
cients explicitly defined in JESD51-12; these coefficients
are quoted or paraphrased below:
1. θJA, the thermal resistance from junction to ambient, is
the natural convection junction-to-ambient air thermal
resistance measured in a one cubic foot sealed enclo-
sure. This environment is sometimes referred to as
“still air” although natural convection causes the air to
move. This value is determined with the part mounted
to a JESD51-9 defined test board, which does not reflect
an actual application or viable operating condition.
2. θJCbottom, the thermal resistance from junction to the
bottom of the product case, is determined with all of
the component power dissipation flowing through the
bottom of the package. In the typical µModule regulator,
the bulk of the heat flows out the bottom of the pack-
age, but there is always heat flow out into the ambient
environment. As a result, this thermal resistance value
may be useful for comparing packages but the test
conditions don’t generally match the user’s application.
3. θJCtop, the thermal resistance from junction to top of
the product case, is determined with nearly all of the
component power dissipation flowing through the top of
the package. As the electrical connections of the typical
µModule regulator are on the bottom of the package, it
is rare for an application to operate such that most of
the heat flows from the junction to the top of the part.
As in the case of θJCbottom, this value may be useful
for comparing packages but the test conditions don’t
generally match the user’s application.
4. θJB, the thermal resistance from junction to the printed
circuit board, is the junction-to-board thermal resis-
tance where almost all of the heat flows through the
bottom of the µModule regulator and into the board,
and is really the sum of the θJCbottom and the thermal
resistance of the bottom of the part through the solder
joints and through a portion of the board. The board
LTM4675
63
Rev. C
For more information www.analog.com
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temperature is measured a specified distance from the
package, using a two sided, two layer board. This board
is described in JESD51-9.
A graphical representation of the aforementioned thermal
resistances is given in Figure 10; blue resistances are
contained within the µModule regulator, whereas green
resistances are external to the µModule package.
As a practical matter, it should be clear to the reader that
no individual or sub-group of the four thermal resistance
parameters defined by JESD51-12 or provided in the Pin
Configuration section replicates or conveys normal op-
erating conditions of a µModule regulator. For example,
in normal board-mounted applications, never does 100%
of the device’s total power loss (heat) thermally conduct
exclusively through the top or exclusively through bot-
tom of the µModule package—as the standard defines
for θJCtop and θJCbottom, respectively. In practice, power
loss is thermally dissipated in both directions away from
the package—granted, in the absence of a heat sink and
airflow, a majority of the heat flow is into the board.
Within the LTM4675, be aware there are multiple power
devices and components dissipating power, with a con-
sequence that the thermal resistances relative to different
junctions of components or die are not exactly linear with
respect to total package power loss. To reconcile this
complication without sacrificing modeling simplicity—but
also not ignoring practical realities—an approach has been
taken using FEA software modeling along with laboratory
testing in a controlled-environment chamber to reason-
ably define and correlate the thermal resistance values
supplied in this data sheet: (1) Initially, FEA software is
used to accurately build the mechanical geometry of the
LTM4675 and the specified PCB with all of the correct
material coefficients along with accurate power loss
source definitions; (2) this model simulates a software-
defined JEDEC environment consistent with JESD51-9 and
JESD51-12 to predict power loss heat flow and temperature
readings at different interfaces that enable the calculation
of the JEDEC-defined thermal resistance values; (3) the
model and FEA software is used to evaluate the LTM4675
with heat sink and airflow; (4) having solved for and
analyzed these thermal resistance values and simulated
various operating conditions in the software model, a
thorough laboratory evaluation replicates the simulated
conditions with thermocouples within a controlled envi-
ronment chamber while operating the device at the same
power loss as that which was simulated. The outcome of
this process and due diligence yields the set of derating
curves provided in later sections of this data sheet, along
with well-correlated JESD51-12-defined θ values provided
in the Pin Configuration section of this data sheet.
The 1V, 1.8V and 3.3V power loss curves in Figure 11,
Figure 12 and Figure 13 respectively can be used in
coordination with the load current derating curves in
Figures 14 to 25 for calculating an approximate θJA
thermal resistance for the LTM4675 with various heat
sinking and air flow conditions. These thermal resistances
represent demonstrated performance of the LTM4675
on DC2053A hardware; a 4-layer FR4 PCB measuring
4675 F10
µMODULE DEVICE
JUNCTION-TO-CASE (TOP)
RESISTANCE
JUNCTION-TO-BOARD RESISTANCE
JUNCTION-TO-AMBIENT THERMAL RESISTANCE COMPONENTS
CASE (TOP)-TO-AMBIENT
RESISTANCE
BOARD-TO-AMBIENT
RESISTANCE
JUNCTION-TO-CASE
(BOTTOM) RESISTANCE
JUNCTION AMBIENT
CASE (BOTTOM)-TO-BOARD
RESISTANCE
Figure 10. Graphical Representation of JESD51-12 Thermal Coefficients
LTM4675
64
Rev. C
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APPLICATIONS INFORMATION
99mm × 133mm × 1.6mm using outer and inner copper
weights of 2oz and 1oz, respectively. The power loss
curves are taken at room temperature, and are increased
with multiplicative factors with ambient temperature.
These approximate factors are listed in Table 14.
(Compute the factor by interpolation, for intermediate
temperatures.) The derating curves are plotted with the
LTM4675’s paralleled outputs initially sourcing up to 18A
and the ambient temperature at 30°C. The output voltages
are 1V, 1.8V and 3.3V. These are chosen to include the lower
and higher output voltage ranges for correlating the thermal
resistance. Thermal models are derived from several
temperature measurements in a controlled temperature
chamber along with thermal modeling analysis. The
junction temperatures are monitored while ambient
temperature is increased with and without air flow, and with
and without a heat sink attached with thermally conductive
adhesive tape. The power loss increase with ambient
temperature change is factored into the derating curves.
The junctions are maintained at 120°C maximum while
lowering output current or power while increasing ambient
temperature. The decreased output current decreases the
internal module loss as ambient temperature is increased.
The monitored junction temperature of 120°C minus the
ambient operating temperature specifies how much module
temperature rise can be allowed. As an example in Figure 19,
the load current is derated to ~12A at ~65°C ambient with
200LFM airflow and no heat sink and the room temperature
(25°C) power loss for this 12VIN to 1VOUT at 12AOUT
condition is ~3.6W. A 4.05W loss is calculated by multiplying
the ~3.6W room temperature loss from the 12VIN to
1.8VOUT power loss curve at 12A (Figure 12), withthe 1.125
multiplying factor at 65°C ambient (from Table 14). If the
65°C ambient temperature is subtracted from the 120°C
junction temperature, then the difference of 55°C divided
by 4.05W yields a thermal resistance, θJA, of 13.6°C/W—
in good agreement with Table 16. Table 15, Table 16 and
Table 17 provide equivalent thermal resistances for 1V, 1.8V
and 3.3V outputs with and without air flow and heat sinking.
The derived thermal resistances in Table 15, Table 16
and Table 17 for the various conditions can be multiplied
by the calculated power loss as a function of ambient
temperature to derive temperature rise above ambient,
thus maximum junction temperature. Room temperature
power loss can be derived from the efficiency curves
in the Typical Performance Characteristics section and
adjusted with ambient temperature multiplicative factors
from Table 14.
Table 14. Power Loss Multiplicative Factors vs Ambient
Temperature
AMBIENT TEMPERATURE
POWER LOSS MULTIPLICATIVE
FACTOR
Up to 40°C 1.00
50°C 1.05
60°C 1.10
70°C 1.15
80°C 1.20
90°C 1.25
100°C 1.30
110°C 1.35
120°C 1.40
LTM4675
65
Rev. C
For more information www.analog.com
APPLICATIONS INFORMATION
Table 15. 1.0V Output
DERATING CURVE VIN (V) POWER LOSS CURVE AIRFLOW (LFM) HEAT SINK θJA (°C/W)
Figures 14, 15 5, 12 Figure 11 0 None 16.1
Figures 14, 15 5, 12 Figure 11 200 None 12.3
Figures 14, 15 5, 12 Figure 11 400 None 11.2
Figures 16, 17 5, 12 Figure 11 0 BGA Heat Sink 14.8
Figures 16, 17 5, 12 Figure 11 200 BGA Heat Sink 11.4
Figures 16, 17 5, 12 Figure 11 400 BGA Heat Sink 10.3
Table 16. 1.8V Output
DERATING CURVE VIN (V) POWER LOSS CURVE AIRFLOW (LFM) HEAT SINK θJA (°C/W)
Figures 18, 19 5, 12 Figure 12 0 None 16.4
Figures 18, 19 5, 12 Figure 12 200 None 13.4
Figures 18, 19 5, 12 Figure 12 400 None 12.3
Figures 20, 21 5, 12 Figure 12 0 BGA Heat Sink 15.4
Figures 20, 21 5, 12 Figure 12 200 BGA Heat Sink 12.6
Figures 20, 21 5, 12 Figure 12 400 BGA Heat Sink 11.4
Table 17. 3.3V Output
DERATING CURVE VIN (V) POWER LOSS CURVE AIRFLOW (LFM) HEAT SINK θJA (°C/W)
Figure 22, 23 5, 12 Figure 13 0 None 15.9
Figure 22, 23 5, 12 Figure 13 200 None 13.1
Figure 22, 23 5, 12 Figure 13 400 None 11.8
Figure 24, 25 5, 12 Figure 13 0 BGA Heat Sink 15.0
Figure 24, 25 5, 12 Figure 13 200 BGA Heat Sink 12.2
Figure 24, 25 5, 12 Figure 13 400 BGA Heat Sink 11.1
Table 18. Heat Sink Manufacturer (Thermally Conductive Adhesive Tape Pre-Attached)
HEAT SINK MANUFACTURER PART NUMBER WEBSITE
Cool Innovations 3-0504035UT411 www.coolinnovations.com
Table 19. Thermally Conductive Adhesive Tape Vendor
THERMALLY CONDUCTIVE ADHESIVE
TAPE MANUFACTURER PART NUMBER WEBSITE
Chomerics T411 www.chomerics.com
LTM4675
66
Rev. C
For more information www.analog.com
APPLICATIONS INFORMATION
Table 20. LTM4675 Channel Output Voltage Response vs Component Matrix. 4.5A Load-Stepping at 4.5A/µs. Typical Measured Values
COUTH VENDORS PART NUMBER
COUTL
VENDORS PART NUMBER
AVX 12106D107MAT2A (100μF, 6.3V, 1210 Case Size) Sanyo POSCAP 6TPF330M9L (330μF, 6.3V, 9mΩ ESR, D3L Case Size)
Murata GRM32ER60J107ME20L (100μF, 6.3V, 1210 Case Size) Sanyo POSCAP 6TPD470M (470μF, 6.3V, 10mΩ ESR, D4D Case Size)
Taiyo Yuden JMK325BJ107MM-T (100μF, 6.3V, 1210 Case Size) Sanyo POSCAP 2R5TPE470M9 (470μF, 2.5V, 9mΩ ESR, D2E Case Size)
TDK C3225X5R0J107MT (100μF, 6.3V, 1210 Case Size) Sanyo POSCAP 6TPF470MAH (470μF, 6.3V, 10mΩ ESR, D4 Case Size)
VOUTn
(V)
VINn
(V)
REF.
CIRCUIT*
COUTHn
(CERAMIC
OUTPUT
CAP)
COUTLn
(BULK
OUTPUT
CAP)
CONNECT
COMPna TO
COMPnb?
(INTERNAL LOOP
COMP)
RTHn
(EXT
LOOP
COMP)
(kΩ)
CTHn
(EXT
LOOP
COMP)
(nF)
fSW
(kHz)
FSWPHCFG
PIN-
STRAP,
RESISTOR
TO SGND
(Table 4)
(kΩ)
VOUTnCFG
PIN-
STRAP
RESISTOR
TO SGND
(Table 2)
(kΩ)
VTRIMnCFG
PIN-
STRAP,
RESISTOR
TO SGND
(Table 3)
(kΩ)
TRANS-
IENT
DROOP
(0A TO
4.5A)
(mV)
PK-PK
DEVI-
ATION
(0A TO
4.5A
TO 0A)
(mV)
RECOV-
ERY
TIME
(µs)
0.9 5 Test Ckt. 2 100µF × 4 None Yes, cf. Figure 61 N/A N/A 425 18.0 1.65 None 37 76 45
0.9 5 Test Ckt. 2 100µF × 3 470µF Yes, cf. Figure 61 N/A N/A 425 18.0 1.65 None 30 63 50
0.9 12 Test Ckt. 1 100µF × 4 None Yes, cf. Figure 61 N/A N/A 425 18.0 1.65 None 37 76 45
0.9 12 Test Ckt. 1 100µF × 3 470µF Yes, cf. Figure 61 N/A N/A 425 18.0 1.65 None 30 63 50
1 5 Test Ckt. 2 100µF × 4 None Yes, cf. Figure 61 N/A N/A 500 None 2.43 0 39 79 45
1 5 Test Ckt. 2 100µF × 3 470µF Yes, cf. Figure 61 N/A N/A 500 None 2.43 0 31 63 50
1 12 Test Ckt. 1 100µF × 4 None Yes, cf. Figure 61 N/A N/A 500 None 2.43 0 39 79 45
1 12 Test Ckt. 1 100µF × 3 470µF Yes, cf. Figure 61 N/A N/A 500 None 2.43 0 31 63 50
1.2 5 Test Ckt. 2 100µF × 4 None Yes, cf. Figure 61 N/A N/A 500 None 3.24 0 40 80 45
1.2 5 Test Ckt. 2 100µF × 3 470µF Yes, cf. Figure 61 N/A N/A 500 None 3.24 0 32 64 50
1.2 12 Test Ckt. 1 100µF × 4 None Yes, cf. Figure 61 N/A N/A 575 15.4 3.24 0 40 80 45
1.2 12 Test Ckt. 1 100µF × 3 470µF Yes, cf. Figure 61 N/A N/A 575 15.4 3.24 0 32 64 50
1.5 5 Test Ckt. 2 100µF × 4 None Yes, cf. Figure 61 N/A N/A 575 15.4 4.22 None 41 81 45
1.5 5 Test Ckt. 2 100µF × 3 470µF Yes, cf. Figure 61 N/A N/A 575 15.4 4.22 None 32 65 50
1.5 12 Test Ckt. 1 100µF × 4 None Yes, cf. Figure 61 N/A N/A 650 12.7 4.22 None 41 81 45
1.5 12 Test Ckt. 1 100µF × 3 470µF Yes, cf. Figure 61 N/A N/A 650 12.7 4.22 None 32 65 50
1.8 5 Test Ckt. 2 100µF × 4 None Yes, cf. Figure 61 N/A N/A 650 12.7 6.34 0 41 82 45
1.8 5 Test Ckt. 2 100µF × 3 470µF Yes, cf. Figure 61 N/A N/A 650 12.7 6.34 0 32 65 50
1.8 12 Test Ckt. 1 100µF × 4 None Yes, cf. Figure 61 N/A N/A 750 10.7 6.34 0 41 82 45
1.8 12 Test Ckt. 1 100µF × 3 470µF Yes, cf. Figure 61 N/A N/A 750 10.7 6.34 0 32 65 50
2.5 5 Test Ckt. 2 100µF × 4 None Yes, cf. Figure 61 N/A N/A 650 12.7 10.7 None 42 87 45
2.5 5 Test Ckt. 2 100µF × 3 470µF Yes, cf. Figure 61 N/A N/A 650 12.7 10.7 None 32 65 50
2.5 12 Test Ckt. 1 100µF × 4 None Yes, cf. Figure 61 N/A N/A 1000 9.09 10.7 None 42 87 45
2.5 12 Test Ckt. 1 100µF × 3 470µF Yes, cf. Figure 61 N/A N/A 1000 9.09 10.7 None 32 65 50
3.3 5 Test Ckt. 2 100µF × 4 None Yes, cf. Figure 61 N/A N/A 650 12.7 22.6 None 70 147 50
3.3 5 Test Ckt. 2 100µF ×3 470µF Yes, cf. Figure 61 N/A N/A 650 12.7 22.6 None 54 104 60
3.3 12 Test Ckt. 1 100µF × 4 None Yes, cf. Figure 61 N/A N/A 1000 9.09 22.6 None 70 147 50
3.3 12 Test Ckt. 1 100µF × 3 470µF Yes, cf. Figure 61 N/A N/A 1000 9.09 22.6 None 54 105 60
5 12 Test Ckt. 1 100µF × 3 470µF Yes, cf. Figure 61 N/A N/A 1000 9.09 32.4 7.68 56 113 60
*For all conditions: CINH input capacitance is 10µF × 2, per channel (VIN0, VIN1). CINL bulk input capacitance of 150µF is optional if VIN has very low input
impedance.
LTM4675
67
Rev. C
For more information www.analog.com
Figure 11. 1VOUT Power Loss Curve Figure 12. 1.8VOUT Power Loss Curve Figure 13. 3.3VOUT Power Loss Curve
OUTPUT CURRENT (A)
024
POWER LOSS (W)
4
6
4675 F11
2
068 10 12 14 16 18
7
5VIN
3
5
1
8VIN
12VIN
OUTPUT CURRENT (A)
024
POWER LOSS (W)
4
6
4675 F12
2
068 10 12 14 16 18
7
5VIN
3
5
1
8VIN
12VIN
OUTPUT CURRENT (A)
024
POWER LOSS (W)
4
6
4675 F13
2
068 10 12 14 16 18
7
5VIN
3
5
1
8VIN
12VIN
APPLICATIONS INFORMATION-DERATING CURVES
AMBIENT TEMPERATURE (°C)
30
0
MAXIMUM LOAD CURRENT (A)
2
6
8
10
18
14
40 50 60 70
4675 F17
4
16
12
80 12090 100 110
400LFM
200LFM
0LFM
Figure 14. 5V to 1V Derating
Curve, No Heat Sink
Figure 15. 12V to 1V Derating Curve,
No Heat Sink
AMBIENT TEMPERATURE (°C)
30
0
MAXIMUM LOAD CURRENT (A)
2
6
8
10
18
14
40 50 60 70
4675 F14
4
16
12
80 12090 100 110
400LFM
200LFM
0LFM
AMBIENT TEMPERATURE (°C)
30
0
MAXIMUM LOAD CURRENT (A)
2
6
8
10
18
14
40 50 60 70
4675 F15
4
16
12
80 12090 100 110
400LFM
200LFM
0LFM
AMBIENT TEMPERATURE (°C)
30
0
MAXIMUM LOAD CURRENT (A)
2
6
8
10
18
14
40 50 60 70
4675 F16
4
16
12
80 12090 100 110
400LFM
200LFM
0LFM
See also Figure 35, 12VIN to 5VOUT Derating Curves.
Figure 16. 5V to 1V Derating
Curve, with Heat Sink
Figure 17. 12V to 1V Derating
Curve, with Heat Sink
AMBIENT TEMPERATURE (°C)
30
0
MAXIMUM LOAD CURRENT (A)
2
6
8
10
18
14
40 50 60 70
4675 F18
4
16
12
80 12090 100 110
400LFM
200LFM
0LFM
AMBIENT TEMPERATURE (°C)
30
0
MAXIMUM LOAD CURRENT (A)
2
6
8
10
18
14
40 50 60 70
4675 F19
4
16
12
80 12090 100 110
400LFM
200LFM
0LFM
Figure 18. 5V to 1.8V Derating
Curve, No Heat Sink
Figure 19. 12V to 1.8V Derating
Curve, No Heat Sink
LTM4675
68
Rev. C
For more information www.analog.com
APPLICATIONS INFORMATION-DERATING CURVES
AMBIENT TEMPERATURE (°C)
30
0
MAXIMUM LOAD CURRENT (A)
2
6
8
10
18
14
40 50 60 70
4675 F20
4
16
12
80 12090 100 110
400LFM
200LFM
0LFM
AMBIENT TEMPERATURE (°C)
30
0
MAXIMUM LOAD CURRENT (A)
2
6
8
10
18
14
40 50 60 70
4675 F21
4
16
12
80 12090 100 110
400LFM
200LFM
0LFM
Figure 20. 5V to 1.8V Derating
Curve, with Heat Sink
Figure 21. 12V to 1.8V Derating
Curve, with Heat Sink
AMBIENT TEMPERATURE (°C)
30
0
MAXIMUM LOAD CURRENT (A)
2
6
8
10
18
14
40 50 60 70
4675 F23
4
16
12
80 12090 100 110
400LFM
200LFM
0LFM
AMBIENT TEMPERATURE (°C)
30
0
MAXIMUM LOAD CURRENT (A)
2
6
8
10
18
14
40 50 60 70
4675 F24
4
16
12
80 12090 100 110
400LFM
200LFM
0LFM
AMBIENT TEMPERATURE (°C)
30
0
MAXIMUM LOAD CURRENT (A)
2
6
8
10
18
14
40 50 60 70
4675 F25
4
16
12
80 12090 100 110
400LFM
200LFM
0LFM
AMBIENT TEMPERATURE (°C)
30
0
MAXIMUM LOAD CURRENT (A)
2
6
8
10
18
14
40 50 60 70
4675 F22
4
16
12
80 12090 100 110
400LFM
200LFM
0LFM
Figure 22. 5V to 3.3V Derating
Curve, No Heat Sink
Figure 23. 12V to 3.3V Derating
Curve, No Heat Sink
Figure 24. 5V to 3.3V Derating
Curve, with Heat Sink
Figure 25. 12V to 3.3V Derating
Curve, with Heat Sink
LTM4675
69
Rev. C
For more information www.analog.com
APPLICATIONS INFORMATION
EMI PERFORMANCE
The SWn pin provides access to the midpoint of the power
MOSFETs in LTM4675’s power stages.
Connecting an optional series RC network from SWn to
GND can dampen high frequency (~30MHz+) switch node
ringing caused by parasitic inductances and capacitances
in the switched-current paths. The RC network is called
a snubber circuit because it dampens (or “snubs”) the
resonance of the parasitics, at the expense of higher
power loss.
To use a snubber, choose first how much power to allocate
to the task and how much PCB real estate is available to
implement the snubber. For example, if PCB space al-
lows a low inductance 1W resistor to be used—derated
conservatively to 600mW (PSNUB)—then the capacitor in
the snubber network (CSW) is computed by:
CSW =
P
SNUB
V
IN
n
(MAX)
2• f
SW
where VINn(MAX) is the maximum input voltage that the
input to the power stage (VINn) will see in the application,
and fSW is the DC/DC converter’s switching frequency
of operation. CSW should be NPO, C0G or X7R-type (or
better) material.
The snubber resistor (RSW) value is then given by:
RSW =5nH
CSW
The snubber resistor should be low ESL and capable of
withstanding the pulsed currents present in snubber cir-
cuits. A value between 0.7Ω and 4.2Ω is normal.
SAFETY CONSIDERATIONS
The LTM4675 modules do not provide galvanic isolation
from VIN to VOUT. There is no internal fuse. If required,
a slow blow fuse with a rating twice the maximum input
current needs to be provided to protect each unit from
catastrophic failure.
The fuse or circuit breaker should be selected to limit the
current to the regulator during overvoltage in case of an
internal top MOSFET fault. If the internal top MOSFET fails,
then turning it off will not resolve the overvoltage, thus the
internal bottom MOSFET will turn on indefinitely trying to
protect the load. Under this fault condition, the input volt-
age will source very large currents to ground through the
failed internal top MOSFET and enabled internal bottom
MOSFET. This can cause excessive heat and board dam-
age depending on how much power the input voltage can
deliver to this system. A fuse or circuit breaker can be used
as a secondary fault protector in this situation. The device
does support over current and overtemperature protection.
LAYOUT CHECKLIST/EXAMPLE
The high integration of LTM4675 makes the PCB board
layout very simple and easy. However, to optimize its
electrical and thermal performance, some layout consid-
erations are still necessary.
• Use large PCB copper areas for high current paths,
including VINn, GND and VOUTn. It helps to minimize
the PCB conduction loss and thermal stress.
• Place high frequency ceramic input and output capaci-
tors next to the VINn, GND and VOUTn pins to minimize
high frequency noise.
• Place a dedicated power ground layer underneath the
module.
• To minimize the via conduction loss and reduce module
thermal stress, use multiple vias for interconnection
between top layer and other power layers.
LTM4675
70
Rev. C
For more information www.analog.com
• Do not put vias directly on pads, unless they are capped
or plated over.
• Use a separate SGND copper plane for components
connected to signal pins. Connect SGND to GND local
to the LTM4675.
• For parallel modules, tie the VOUTn, VOSNS0+/VOSNS– and/
or VOSNS1/SGND voltage-sense differential pair lines,
APPLICATIONS INFORMATION
Figure 26. Recommended PCB Layout Package Top View
RUNn, GPIOn, COMPna, SYNC and SHARE_CLK pins
together—as shown in Figure 31.
• Bring out test points on the signal pins for monitoring.
Figure 26 (a) shows a good example of the LTM4675’s
recommended layout. For flexibility, the LTM4675 is drop-
in pin-compatible to its taller, larger dual 13A LTM4676A
and dual 18A LTM4677 sibling modules—as seen in the
layout recommended by Figure 26 (b).
1
2
3
4
5
6
7
8
9
MLKJHGFEDCBA
SGND
9
8
7
6
5
COUT0
GND
COUT1
CIN1
CIN0 VIN0 VIN1
GND
GND
4
3
2
1
A B C D E F G
GND VOUT1
VOUT0
H J K L M
VOUT0
VIN0
GND
GND
GND
SGND
GND
GND
GND
GND
GND
VOUT1
VIN1
SGND
9
8
7
6
5
COUT0
GND
COUT1
CIN1
CIN0
VIN0 VIN1
GND
GND
4
3
2
1
A B C D E F G
CNTRL VOUT1
4675 F26ab
VOUT0
H J K L M
(a) PCB Layout for LTM4675, Package Top View
9
8
7
6
5
4
3
2
1
(b) PCB Layout to Accommodate Any of LTM4675 or LTM4676A or LTM4677 Modules
VIN0 VIN1
VOUT0 VOUT1
A B C D E F G H J K L M
GND GND
GND GND
GND
LTM4675
71
Rev. C
For more information www.analog.com
TYPICAL APPLICATIONS
Figure 27. 18A, 1.5V Output DC/DC µModule Regulator with I2C/SMBus/PMBus Serial Interface
(28a) 5VIN, Figure 27 Circuit (28b) 12VIN, Figure 27 Circuit with INTVCC
Open and VOUT Commanded to 1V
TOTAL OUTPUT CURRENT (A)
0
CHANNEL OUTPUT CURRENT (A)
6
4675 F28a
6
2
2 4 8
0
–2
10
IOUT0
IOUT1
8
4
10 12 14 18
TOTAL OUTPUT CURRENT (A)
0
CHANNEL OUTPUT CURRENT (A)
6
4675 F28b
6
2
2 4 8
0
–2
10
IOUT0
IOUT1
8
4
10 12 14 18
Figure 28. Current Sharing Performance of the LTM4675's Channels
CINH
22µF
×3
CINL
220µF
10k
×7
VIN
4.5V to 5.75V
PWM CLOCK SYNCH.
TIME BASE SYNCH.
• SLAVE ADDRESS = 1001010_R/W (0X4A)
• 575kHz SWITCHING FREQUENCY
• NO GUI CONFIGURATION AND
NO PART-SPECIFIC PROGRAMMING REQUIRED EXCEPT:
VIN_OFF < VIN_UV_WARN_LIMIT < VIN_ON < 4.3V
IN MULTI-MODULE SYSTEMS, CONFIGURING RAIL_ADDRESS
IS RECOMMENDED
• SETTING MFR_PWM_CONFIG[7]=1b,
CONFIGURES THE VOUT1 CONTROL LOOP
TO USE THE VOSNS0+/VOSNS0– DIFFERENTIAL-
SENSE PIN-PAIR AS THE FEEDBACK SIGNAL
FOR REGULATING VOUT1.
COUT
100µF
×6
470µF
10mΩ
ESR
×2
VOUT, 1.5V
ADJUSTABLE
UP TO 18A
VIN0
VIN1
SVIN
VDD33
LOAD
SCL
SDA
ALERT
RUN0
RUN1
GPIO0
GPIO1
SYNC
SHARE_CLK
VOUT0CFG
VTRIM0CFG
VOUT1CFG
VTRIM1CFG
INTVCC
VDD25
SW0
SW1
COMP0a
COMP0b
COMP1a
COMP1b
GND
WP
10.7k
1%
±50ppm/°C
15.4k
1%
±50ppm/°C
LTM4675
4675 F27
+
2.1k
1%
±50ppm/°C
SMBus INTERFACE WITH
PMBus COMMAND SET
ON/OFF CONTROL, FAULT
MANAGEMENT, POWER
SEQUENCING
FSWPHCFG
ASEL
VOUT0
TSNS0
VORB0+
VOSNS0+
VOSNS0–
VORB0–
VORB1
VOUT1
TSNS1a
TSNS1b
VOSNS1
SGND
+
LTM4675
72
Rev. C
For more information www.analog.com
TYPICAL APPLICATIONS
Figure 29. 9A, 1.2V and 2.5V Outputs Generated from 3.3V Power Input and Providing I2C/SMBus/PMBus Serial Interface
Figure 30. Output Voltage Margining, Figure 29 Circuit
VOUT1, 2.5V
ADJUSTABLE
UP TO 9A
CINH
22µF
×3
CINL
220µF
10k
×9
3.3VIN
NOMINAL
5V
LOW POWER BIAS
<100mA
PWM CLOCK SYNCH.
TIME BASE SYNCH.
• SLAVE ADDRESS = 1001111_R/W (0X4F)
• 500kHz SWITCHING FREQUENCY
• NO GUI CONFIGURATION AND
NO PART-SPECIFIC PROGRAMMING REQUIRED EXCEPT:
VIN_OFF < VIN_UV_WARN_LIMIT < VIN_ON < 4.5V
IN MULTI-MODULE SYSTEMS, CONFIGURING RAIL_ADDRESS
IS RECOMMENDED
COUT0
100µF
×5
COUT1
100µF
×5
VOUT0, 1.2V
ADJUSTABLE
UP TO 9A
VIN0
VIN1
SVIN
VDD33
LOAD0
SCL
SDA
ALERT
RUN0
RUN1
GPIO0
GPIO1
SYNC
SHARE_CLK
VOUT0CFG
VTRIM0CFG
VOUT1CFG
VTRIM1CFG
INTVCC
VDD25
SW0
SW1
COMP0a
COMP0b
COMP1a
COMP1b
GND
WP
3.24k
1%
±50ppm/°C
LTM4675
4675 F29
+
10.7k
1%
±50ppm/°C
SMBus INTERFACE WITH
PMBus COMMAND SET
ON/OFF CONTROL, FAULT
MANAGEMENT, POWER
SEQUENCING
LOAD1
FSWPHCFG
ASEL
VOUT0
TSNS0
VORB0+
VOSNS0+
VOSNS0–
VORB0–
VORB1
VOUT1
TSNS1a
TSNS1b
VOSNS1
SGND
(30a) PMBus Operation (Reg. 0x01): 0x80 → 0xA8 (Margin High)
(30c) PMBus Operation (Reg. 0x01): 0x80 → 0x98 (Margin Low)
(30b) PMBus Operation (Reg. 0x01): 0xA8 → 0x80 (Margin Off)
(30d) PMBus Operation (Reg. 0x01): 0x98 → 0x80 (Margin Off)
VOUT1
50mV/DIV
VOUT0
50mV/DIV
SCL
5V/DIV
SDA
5V/DIV
4ms/DIV 4675 F30a
VOUT1
50mV/DIV
VOUT0
50mV/DIV
SCL
5V/DIV
SDA
5V/DIV
4ms/DIV 4675 F30b
VOUT1
50mV/DIV
VOUT0
50mV/DIV
SCL
5V/DIV
SDA
5V/DIV
4ms/DIV 4675 F30c
VOUT1
50mV/DIV
VOUT0
50mV/DIV
SCL
5V/DIV
SDA
5V/DIV
4ms/DIV 4675 F30d
LTM4675
73
Rev. C
For more information www.analog.com
TYPICAL APPLICATIONS
CIN1
10µF
×4
CIN5
150µF
10k
×7
VIN
5.75V TO 16V
PWM CLOCK SYNCH.
TIME BASE SYNCH.
COUT(MLCC)
100µF
×10
COUT(BULK)
330µF
×10
VOUT, 1V
ADJUSTABLE
UP TO 70A
VOUT0
TSNS0
VOSNS0+
VOSNS0–
VINO
VIN1
SVIN
VDD33
LOAD
SCL
SDA
ALERT
RUN0
RUN1
GPIO0
GPIO1
SYNC
SHARE_CLK
ASEL
FSWPHCFG
VOUT0CFG
VTRIM0CFG
VOUT1CFG
VTRIM1CFG
INTVCC
VDD25
SW0
SW1
COMP0a
COMP0b
COMP1a
COMP1b
GND
WP
U1
LTM4675
+
SMBus INTERFACE WITH
PMBus COMMAND SET
U1: SLAVE ADDRESS = 1000000_R/W (0X40)
U2: SLAVE ADDRESS = 1000001_R/W (0X41)
U3: SLAVE ADDRESS = 1000010_R/W (0X42)
U4: SLAVE ADDRESS = 1000011_R/W (0X43)
500kHz SWITCHING FREQUENCY WITH
INTERLEAVING
NO GUI CONFIGURATION AND NO PART-SPECIFIC
PROGRAMMING REQUIRED
IN MULTI-MODULE SYSTEMS, CONFIGURING
RAIL_ADDRESS IS RECOMMENDED
ELECTRICALLY UNCONNECTED PINS
VORB0+, VORB0– AND VORB1 NOT SHOWN
SETTING MFR_PWM_CONFIG[7] = 1b,
CONFIGURES THE VOUT1 CONTROL LOOP
TO USE THE VOSNS0+/VOSNS0– DIFFERENTIAL-
SENSE PIN-PAIR AS THE FEEDBACK SIGNAL
FOR REGULATING VOUT1.
ON/OFF CONTROL, FAULT
MANAGEMENT, POWER
SEQUENCING
CIN2
10µF
×4
VOUT0
TSNS0
VOSNS0+
VOSNS0–
VINO
VIN1
SVIN
VDD33
SCL
SDA
ALERT
RUN0
RUN1
GPIO0
GPIO1
SYNC
SHARE_CLK
FSWPHCFG
VOUT0CFG
VTRIM0CFG
VOUT1CFG
VTRIM1CFG
INTVCC
VDD25
SW0
SW1
COMP0a
COMP0b
COMP1a
COMP1b
GND
WP
1.65k
1%
±50ppm/°C
787Ω
1%
±50ppm/°C
U2
LTM4675
ASEL
CIN3
10µF
×4
VOUT0
TSNS0
VOSNS0+
VOSNS0–
VINO
VIN1
SVIN
VDD33
SCL
SDA
ALERT
RUN0
RUN1
GPIO0
GPIO1
SYNC
SHARE_CLK
FSWPHCFG
VOUT0CFG
VTRIM0CFG
VOUT1CFG
VTRIM1CFG
INTVCC
VDD25
SW0
SW1
COMP0a
COMP0b
COMP1a
COMP1b
GND
WP
3.24k
1%
±50ppm/°C
1.65k
1%
±50ppm/°C
U3
LTM4675
ASEL
CIN4
10µF
×4
VOUT0
TSNS0
VOSNS0+
VOSNS0–
VINO
VIN1
SVIN
VDD33
SCL
SDA
ALERT
RUN0
RUN1
GPIO0
GPIO1
SYNC
SHARE_CLK
FSWPHCFG
VOUT0CFG
VTRIM0CFG
VOUT1CFG
VTRIM1CFG
INTVCC
VDD25
SW0
SW1
COMP0a
COMP0b
COMP1a
COMP1b
GND
WP
1.21k
1%
±50ppm/°C
4675 F31
CTHP
220pF
CTH
3.3nF
RTH
1.65k
U4
LTM4675
ASEL
VOUT1
TSNS1a
TSNS1b
VOSNS1
SGND
VOUT1
TSNS1a
TSNS1b
VOSNS1
SGND
VOUT1
TSNS1a
TSNS1b
VOSNS1
SGND
VOUT1
TSNS1a
TSNS1b
VOSNS1
SGND
Figure 31. Four Paralleled LTM4675 Producing 1VOUT at Up to 70A. Integrated Power System Management Features Accessible Over
2-Wire I2C/SMBus/PMBus Serial Interface. Evaluated on DC1989B-C, Custom-Stuffed with LTM4675 Modules
LTM4675
74
Rev. C
For more information www.analog.com
TYPICAL APPLICATIONS
CIN1
10µF
×4
CIN5
150µF
10k
×6
12VIN ±20%
CIN2
10µF
×4
COUT(MLCC)
100µF
×20
COUT(BULK)
470µF
×10
VOUT, 1V
ADJUSTABLE
UP TO 92A~122A
VOUT0
TSNS0
VOSNS0+
VOSNS0–
VINO
VIN1
SVIN
VDD33
LOAD
SCL
SDA
ALERT
RUN0
RUN1
GPIO0
GPIO1
SYNC
SHARE_CLK
ASEL
FSWPHCFG
VOUT0CFG
VTRIM0CFG
VOUT1CFG
VTRIM1CFG
INTVCC
VDD25
SW0
SW1
COMP0a
COMP0b
COMP1a
COMP1b
GND
WP
U1
LTM4675
U2*
+
VOUT1
TSNS1a
TSNS1b
VOSNS1
SGND
PWM CLOCK SYNCH.
TIME BASE SYNCH.
SMBus INTERFACE WITH
PMBus COMMAND SET
ON/OFF CONTROL, FAULT
MANAGEMENT, POWER
SEQUENCING
RTH*
CTH*
CINTVCC2
4.7µF
U1: SLAVE ADDRESS = 1000000_R/W (0x40)
500kHz SWITCHING FREQUENCY WITH INTERLEAVING
NO GUI CONFIGURATION AND NO PART-SPECIFIC
PROGRAMMING REQUIRED EXCEPT:
IOUT_OC_WARN_LIMITn =18A
MFR_GPIO_RESPONSEn = 0x00
IN MULTI-MODULE SYSTEMS, CONFIGURING
RAIL_ADDRESS IS RECOMMENDED
ELECTRICALLY UNCONNECTED PINS
VORB0+, VORB0– AND VORB1 NOT SHOWN
SETTING MFR_PWM_CONFIG[7] = 1b,
CONFIGURES THE VOUT1 CONTROL LOOP
TO USE THE VOSNS0+/VOSNS0– DIFFERENTIAL-
SENSE PIN-PAIR AS THE FEEDBACK SIGNAL
FOR REGULATING VOUT1.
RCLK
200Ω
M1
2N7002A
1.2k
1%
±50ppm/°C
6.34k
1%
±50ppm/°C
RTEMP2
121k
RVFB
8.25k
RFSET2
121k
RDIV1*
RDIV2*
CIN3
10µF
×4
CIN4
10µF
×4
–
+
U5A
1/2 LT1801
VIN
TEMP
EXTVCC
PHASMD
RUN1
RUN2
TRACK1
TRACK2
PGOOD1
VOUT1
VOUTS1
VFB1
VOUT2
VOUTS2
VFB2
DIFFP
DIFFN
DIFFOUT
MODE_PLLIN
SW1
SW2
INTVCC
CLKOUT
SGND
GND
PGOOD2
COMP1
COMP2
fSET
U3*
CINTVCC3
4.7µF
RTEMP3
121k
RFSET3
121k
TEMP
EXTVCC
PHASMD
RUN1
RUN2
TRACK1
TRACK2
PGOOD1
VOUT1
VOUTS1
VFB1
VOUT2
VOUTS2
VFB2
DIFFP
DIFFN
DIFFOUT
MODE_PLLIN
SW1
SW2
INTVCC
CLKOUT
SGND
GND
PGOOD2
COMP1
COMP2
fSET
U4*
CINTVCC4
4.7µF
RTEMP4
121k
RFSET4
121k
TEMP
EXTVCC
PHASMD
RUN1
RUN2
TRACK1
TRACK2
PGOOD1
VOUT1
VOUTS1
VFB1
VOUT2
VOUTS2
VFB2
DIFFP
DIFFN
DIFFOUT
MODE_PLLIN
SW1
SW2
INTVCC
CLKOUT
SGND
GND
PGOOD2
4675 F32
COMP1
COMP2
fSET
–
+U5B
1/2 LT1801
DEMO BOARD
DC2106A-A
DC2106A-B
OUTPUT CURRENT
UP TO 92A
UP TO 122A
U2, U3, U4
LTM4620A
LTM4630
U1
LTM4675
LTM4675
RDIV1
28k
23.2k
RDIV2
90.9k
95.3k
RTH
13.3k
8.87k
CTH
4.7nF
4.7nF
*STUFFING OPTIONS
Figure 32. One LTM4675 Operating In Parallel with 3xLTM4620A or 3xLTM4630 (See Demo Boards DC2106A-A, DC2106A-B, Custom-Stuffed with
LTM4675 Modules for U1) Producing 1VOUT at up to 92A ~ 122A. Power System Management Features Accessible Through LTM4675. See Figure 33
LTM4675
75
Rev. C
For more information www.analog.com
TYPICAL APPLICATIONS
(33a) LTM4675 Paralleled with 3x LTM4620A (Up to 92A Output)
(33b) LTM4675 Paralleled with 3x LTM4630 (Up to 122A Output)
Figure 33. Current Sharing Performance of Figure 32 Circuit at 12VIN
TOTAL OUTPUT CURRENT (A)
0
CHANNEL OUTPUT CURRENT (A)
6
8
10
9080
4675 F33a
4
2
–2 20 40 60
10 100
30 50 70
0
14
12
U1-LTM4675-IOUT0
U1-LTM4675-IOUT1
U2-LTM4620A-IOUT1
U2-LTM4620A-IOUT2
U3-LTM4620A-IOUT1
U3-LTM4620A-IOUT2
U4-LTM4620A-IOUT1
U4-LTM4620A-IOUT2
TOTAL OUTPUT CURRENT (A)
0
CHANNEL OUTPUT CURRENT (A)
18
60
4675 F33b
9
3
20 40 80
0
–3
21
15
12
6
100 120 140
U1-LTM4675-IOUT0
U1-LTM4675-IOUT1
U2-LTM4630-IOUT1
U2-LTM4630-IOUT2
U3-LTM4630-IOUT1
U3-LTM4630-IOUT2
U4-LTM4630-IOUT1
U4-LTM4630-IOUT2
LTM4675
76
Rev. C
For more information www.analog.com
TYPICAL APPLICATIONS
CINH
22µF
×3
CINL
220µF
10k
×7
VIN
5.75V to 17V
PWM CLOCK SYNCH.
TIME BASE SYNCH.
• SLAVE ADDRESS = 1000101_R/W (0X45)
• 1MHz SWITCHING FREQUENCY
• NO GUI CONFIGURATION AND NO
PART-SPECIFIC PROGRAMMING REQUIRED
IN MULTI-MODULE SYSTEMS, CONFIGURING
RAIL_ADDRESS IS RECOMMENDED.
• SETTING MFR_PWM_CONFIG[7]=1b,
CONFIGURES THE VOUT1 CONTROL LOOP
TO USE THE VOSNS0+/VOSNS0– DIFFERENTIAL-
SENSE PIN-PAIR AS THE FEEDBACK SIGNAL
FOR REGULATING VOUT1.
COUT
100µF
×10
VOUT, 5V
ADJUSTABLE
UP TO 18A
OPTIONAL: INSTALLING U2 AWAY FROM HEAT SOURCES
ALLOWS INTVCC LDO LOSSES NORMALLY INCURRED BY
THE LTM4675 TO BE DISSIPATED INSTEAD BY THE LT3060.
THERMAL-DERATING CAN THUS BE IMPROVED
VIN0
VIN1
SVIN
VDD33
LOAD
SCL
SDA
ALERT
RUN0
RUN1
GPIO0
GPIO1
SYNC
SHARE_CLK
VOUT0CFG
VTRIM0CFG
VOUT1CFG
VTRIM1CFG
INTVCC
VDD25
SW0
SW1
COMP0a
COMP0b
COMP1a
COMP1b
GND
WP
4.22k
1%
±50ppm/°C
9.09k
1%
±50ppm/°C
U1
LTM4675
4675 F34
+
3.83k
1%
±50ppm/°C
SMBus INTERFACE WITH
PMBus COMMAND SET
ON/OFF CONTROL, FAULT
MANAGEMENT, POWER
SEQUENCING
FSWPHCFG
ASEL
IN
RSET1
13.3k
RSET2
1.62k
OUT
SHDN ADJ
U2
LT3060
GND REF/BYP
16.2k
1%
±50ppm/°C
VOUT0
TSNS0
VORB0+
VOSNS0+
VOSNS0–
VORB0–
VORB1
VOUT1
TSNS1a
TSNS1b
VOSNS1
SGND
Figure 34. 18A, 5V Output DC/DC µModule Regulator with Serial Interface
Figure 35. Output Derating Curve of Figure 34 Circuit Tested on DC2053, 12VIN, No Heat Sink
AMBIENT TEMPERATURE (°C)
20 30
0
MAXIMUM LOAD CURRENT (A)
2
6
8
10
18
14
40 60
4675 F35
4
16
12
80 90 100
50 70
400LFM, WITH U2, RSET1 AND RSET2 INSTALLED: θJA = 7.9°C/W
0LFM, WITH U2, RSET1 AND RSET2 INSTALLED: θJA = 9.2°C/W
400LFM, WITH U2, RSET1 AND RSET2 NOT USED: θJA = 9.5°C/W
0LFM, WITH U2, RSET1 AND RSET2 NOT USED: θJA = 13°C/W
LTM4675
77
Rev. C
For more information www.analog.com
APPENDIX A
SIMILARITY BETWEEN PMBUS, SMBUS AND I2C
2-WIRE INTERFACE
The PMBus 2-wire interface is an incremental extension
of the SMBus. SMBus is built upon I2C with some minor
differences in timing, DC parameters and protocol. The
PMBus/SMBus protocols are more robust than simple I2C
byte commands because PMBus/SMBus provide time-outs
to prevent bus errors and optional packet error checking
(PEC) to ensure data integrity. In general, a master device
that can be configured for I2C communication can be
used for PMBus communication with little or no change
to hardware or firmware. Repeat start (restart) is not
supported by all I2C controllers but is required for SMBus/
PMBus reads. If a general purpose I2C controller is used,
check that repeat start is supported.
For a description of the minor extensions and exceptions
PMBus makes to SMBus, refer to PMBus Specification
Part 1 Revision 1.2: Paragraph 5: Transport.
For a description of the differences between SMBus and
I2C, refer to System Management Bus (SMBus) Speci-
fication Version 2.0: Appendix B—Differences Between
SMBus and I2C.
PMBus data format terminology and abbreviations used in
ADI data sheets (see Appendix C, for example), application
notes, and the LTpowerPlay GUI are indicated in Table 21.
Table 21. Data Format Terminology
PMBus TERMINOLOGY MEANING
TERMINOLOGY FOR: SPECS, GUI,
APPLICATION NOTES
ABBREVIATIONS FOR SUMMARY
COMMAND TABLE
Linear Linear Linear_5s_11s L11
Linear (for Voltage Related
Commands)
Linear Linear_16u L16
Direct Direct-Manufacturer Customized DirectMfr CF
Hex Hex I16
ASCII ASCII ASC
Register Fields Reg Reg
Handshaking features are included to ensure robust system communication. Please refer to the PMBus Communication and Command Processing
subsection of the Applications Information section for further details.
LTM4675
78
Rev. C
For more information www.analog.com
APPENDIX B
PMBUS SERIAL DIGITAL INTERFACE
The LTM4675 communicates with a host (master) using the
standard PMBus serial bus interface. The Timing Diagram,
Figure 36, shows the timing relationship of the signals on
the bus. The two bus lines, SDA and SCL, must be high
when the bus is not in use. External pull-up resistors or
current sources are required on these lines.
The LTM4675 is a slave device. The master can com-
municate with the LTM4675 using the following formats:
n Master transmitter, slave receiver
n Master receiver, slave transmitter
The following PMBus protocols are supported:
n Write Byte, Write Word, Send Byte, Block Write
n Read Byte, Read Word, Block Read
n Block Write -- Block Read Process Call
n Alert Response Address
Figure 38 to Figure 54 illustrate the aforementioned PMBus
protocols. All transactions support PEC (parity error check)
and GCP (group command protocol). The Block Read
supports 255 bytes of returned data. For this reason, the
PMBus timeout may be extended when reading the fault log.
Figure 37 is a key to the protocol diagrams in this section.
PEC is optional.
A value shown below a field in the following figures is a
mandatory value for that field.
The data formats implemented by PMBus are:
n Master transmitter transmits to slave receiver. The
transfer direction in this case is not changed.
n Master reads slave immediately after the first byte. At
the moment of the first acknowledgment (provided by
the slave receiver) the master transmitter becomes a
master receiver and the slave receiver becomes a slave
transmitter.
n Combined format. During a change of direction within
a transfer, the master repeats both a start condition
and the slave address but with the R/W bit reversed.
In this case, the master receiver terminates the transfer
by generating a NACK on the last byte of the transfer
and a STOP condition.
Figure 36. Timing Diagram
SDA
SCL
tHD(STA) tHD(DAT)
tSU(STA) tSU(STO)
tSU(DAT)
tLOW
tHD(SDA) tSP tBUF
START
CONDITION
STOP
CONDITION
REPEATED START
CONDITION
START
CONDITION
tr
tftr
tf
tHIGH 4675 F36
LTM4675
79
Rev. C
For more information www.analog.com
APPENDIX B
Figure 37. PMBus Packet Protocol Diagram Element Key
Figure 38. Quick Command Protocol
Figure 39. Send Byte Protocol
Figure 40. Send Byte Protocol with PEC
Figure 41. Write Byte Protocol
Figure 42. Write Byte Protocol with PEC
SLAVE ADDRESS DATA BYTEWr A A P
4675 F37
S
7
S START CONDITION
Sr REPEATED START CONDITION
Rd READ (BIT VALUE OF 1)
Wr WRITE (BIT VALUE OF 0)
x SHOWN UNDER A FIELD INDICATES THAT THAT
FIELD IS REQUIRED TO HAVE THE VALUE OF x
A ACKNOWLEDGE (THIS BIT POSITION MAY BE 0
FOR AN ACK OR 1 FOR A NACK)
P STOP CONDITION
PEC PACKET ERROR CODE
MASTER TO SLAVE
SLAVE TO MASTER
CONTINUATION OF PROTOCOL
81 1 1
x x
11
...
SLAVE ADDRESS Rd/Wr A P
4675 F38
S
7 1 1 11
SLAVE ADDRESS COMMAND CODEWr A A P
4675 F39
S
7 81 1 1 11
SLAVE ADDRESS COMMAND CODE PECWr A A A P
4675 F40
S
7 8 81 1 1 1 11
SLAVE ADDRESS COMMAND CODE DATA BYTEWr A A A P
4675 F41
S
7 8 81 1 1 1 11
SLAVE ADDRESS COMMAND CODE DATA BYTEWr A A A P
4675 F42
S
7 8 8 1
PEC
81 1 1 1 11
A
LTM4675
80
Rev. C
For more information www.analog.com
APPENDIX B
SLAVE ADDRESS COMMAND CODE DATA BYTE LOWWr A A A P
4675 F43
S
7 8 8 1
DATA BYTE HIGH
81 1 1 1 11
A
SLAVE ADDRESS COMMAND CODE DATA BYTE LOWWr A A A P
4675 F44
S
7 8 8 1
DATA BYTE HIGH
8
PEC
811 1 1 1 11
A A
SLAVE ADDRESS COMMAND CODE SLAVE ADDRESSWr A A Sr P
4675 F45
S
7 8 7 11
DATA BYTE
8 11 1 1 11 1
ARd NA
SLAVE ADDRESS COMMAND CODE SLAVE ADDRESSWr A A Sr P
4675 F46
S
7 8 7 11
DATA BYTE
8 8 11 1 1 11 1
ARd A
1
APEC
SLAVE ADDRESS COMMAND CODE SLAVE ADDRESSWr A A NA P
4675 F47
S
7 8 7 1
DATA BYTE LOW
8
DATA BYTE HIGH
811 1 1
Sr
1 1 11
A
1
Rd A
SLAVE ADDRESS COMMAND CODE SLAVE ADDRESSWr A A A PA
4675 F48
S
7 8 7 1
DATA BYTE LOW
8
DATA BYTE HIGH PEC
8 811 1 1 1 111
Sr
1
A
1
Rd A
SLAVE ADDRESS COMMAND CODE SLAVE ADDRESSWr A A SrS
7 8 7 11
BYTE COUNT = N
8 11 1 11 1
ARd A …
A PNA
4675 F49
DATA BYTE 1
8
DATA BYTE 2 DATA BYTE N
8 81 1 11
A …
SLAVE ADDRESS COMMAND CODE SLAVE ADDRESSWr A A SrS
7 8 7 11
BYTE COUNT = N
8 11 1 11 1
ARd A …
…
ADATA BYTE 1
8
DATA BYTE 2
81 1
A A PNA
4675 F50
DATA BYTE N PEC
8 81 11
Figure 43. Write Word Protocol
Figure 44. Write Word Protocol with PEC
Figure 45. Read Byte Protocol
Figure 46. Read Byte Protocol with PEC
Figure 47. Read Word Protocol
Figure 48. Read Word Protocol with PEC
Figure 49. Block Read Protocol
Figure 50. Block Read Protocol with PEC
LTM4675
81
Rev. C
For more information www.analog.com
APPENDIX B
SLAVE ADDRESS COMMAND CODE BYTE COUNT = MWr A AS
7 8 8 1
DATA BYTE 1
8 11 1 11
A A …
……
ADATA BYTE 2
8 1
ADATA BYTE M
8 1
SLAVE ADDRESS BYTE COUNT = NRd A ASr
7 8
DATA BYTE 1
8 11 1 11
A …
P
4675 F51
1
…
…ADATA BYTE 2
8
NADATA BYTE N
8 11
SLAVE ADDRESS COMMAND CODE BYTE COUNT = MWr A AS
7 8 8 1
DATA BYTE 1
8 11 1 11
A A …
…
ADATA BYTE 2
8 1
ADATA BYTE M
8 1
SLAVE ADDRESS BYTE COUNT = NRd A ASr
7 8
DATA BYTE 1
81 1 1 11
A …
…
…ADATA BYTE 2
8 1
ADATA BYTE N
8 1
P
4675 F52
1
NAPEC
8 1
ALERT RESPONSE
ADDRESS Rd A NA P
4675 F53
S
7 71 1 1 11
DEVICE ADDRESS
ALERT RESPONSE
ADDRESS Rd A AS
7 71 1 11
DEVICE ADDRESS NA P
4675 F54
8 1 1
PEC
Figure 51. Block Write – Block Read Process Call
Figure 52. Block Write – Block Read Process Call with PEC
Figure 53. Alert Response Address Protocol
Figure 54. Alert Response Address Protocol with PEC
LTM4675
82
Rev. C
For more information www.analog.com
APPENDIX C: PMBUS COMMAND DETAILS
ADDRESSING AND WRITE PROTECT
COMMAND NAME
CMD
CODE DESCRIPTION TYPE PAGED
DATA
FORMAT UNITS NVM
DEFAULT
VALUE
PAGE 0x00 Channel (page) presently selected for any
paged command.
R/W Byte N Reg 0x00
PAGE_PLUS_WRITE 0x05 Write a command directly to a specified page. W Block N
PAGE_PLUS_READ 0x06 Read a command directly from a specified
page.
Block R/W
Process
N
WRITE_PROTECT 0x10 Protect the device against unintended PMBus
modifications.
R/W Byte N Reg Y 0x00
MFR_ADDRESS 0xE6 Specify right-justified 7-bit device address. R/W Byte N Reg Y 0x4F
MFR_RAIL_ADDRESS 0xFA Specify unique right-justified 7-bit address
for channels comprising a PolyPhase output.
R/W Byte Y Reg Y 0x80
Related commands: MFR_COMMON.
PAGE
The PAGE command provides the ability to configure, control and monitor both PWM channels through only one
physical address, either the MFR_ADDRESS or GLOBAL device address. Each PAGE contains the operating memory
for one PWM channel.
Pages 0x00 and 0x01 correspond to channel 0 and channel 1, respectively, in this device.
Setting PAGE to 0xFF applies any following paged commands to both outputs. With PAGE set to 0xFF the LTM4675
will respond to read commands as if PAGE were set to 0x00 (channel 0 results).
This command has one data byte.
PAGE_PLUS_WRITE
The PAGE_PLUS_WRITE command provides a way to set the page within a device, send a command and then send
the data for the command, all in one communication packet. Commands allowed by the present write protection level
may be sent with PAGE_PLUS_WRITE.
The value stored in the PAGE command is not affected by PAGE_PLUS_WRITE. If PAGE_PLUS_WRITE is used to send
a non-paged command, the Page Number byte is ignored.
This command uses Write Block protocol. An example of the PAGE_PLUS_WRITE command with PEC sending a com-
mand that has two data bytes is shown in Figure 55.
SLAVE
ADDRESS
PAGE_PLUS
COMMAND CODE
BLOCK COUNT
(= 4)
W A AS
7 8 8 1
PAGE
NUMBER
8 11 1 11
A A …
COMMAND
CODE
8 1
A
UPPER DATA
BYTE A A P
4675 F55
A
8 81 1 11
PEC BYTE
LOWER DATA
BYTE
8
Figure 55. Example of PAGE_PLUS_WRITE
LTM4675
83
Rev. C
For more information www.analog.com
PAGE_PLUS_READ
The PAGE_PLUS_READ command provides the ability to set the page within a device, send a command and then read
the data returned by the command, all in one communication packet .
The value stored in the PAGE command is not affected by PAGE_PLUS_READ. If PAGE_PLUS_READ is used to access
data from a non-paged command, the Page Number byte is ignored.
This command uses Block Write – Block Read Process Call protocol. An example of the PAGE_PLUS_READ command
with PEC is shown in Figure 56.
NOTE: PAGE_PLUS commands cannot be nested. A PAGE_PLUS command cannot be used to read or write another
PAGE_PLUS command. If this is attempted, the LTM4675 will NACK the entire PAGE_PLUS packet and issue a CML
fault for Invalid/Unsupported Data.
WRITE_PROTECT
The WRITE_PROTECT command is used to control writing to the LTM4675 device. This command does not indicate
the status of the WP pin which is defined in the MFR_COMMON command. The WP pin takes precedence over the
value of this command unless the WRITE_PROTECT command is more stringent.
BYTE MEANING
0x80 Disable all writes except to the WRITE_PROTECT, PAGE, MFR_
EE_UNLOCK and STORE_USER_ALL command
0x40 Disable all writes except to the WRITE_PROTECT, PAGE,
MFR_EE_UNLOCK, MFR_CLEAR_PEAKS, STORE_USER_ALL,
OPERATION and CLEAR_FAULTS command. individual fault
bits can be cleared by writing a 1 to the respective bits in the
STATUS registers.
0x20 Disable all writes except to the WRITE_PROTECT, OPERATION,
MFR_EE_UNLOCK, MFR_CLEAR_PEAKS, CLEAR_FAULTS,
PAGE, ON_OFF_CONFIG, VOUT_COMMAND and STORE_USER_
ALL. Individual fault bits can be cleared by writing a 1 to the
respective bits in the STATUS registers.
0x10 Reserved, must be 0
0x08 Reserved, must be 0
0x04 Reserved, must be 0
0x02 Reserved, must be 0
0x01 Reserved, must be 0
Enable writes to all commands when WRITE_PROTECT is set to 0x00.
This command has one data byte.
APPENDIX C: PMBUS COMMAND DETAILS
Figure 56. Example of PAGE_PLUS_READ
P
1
SLAVE
ADDRESS
PAGE_PLUS
COMMAND CODE
BLOCK COUNT
(= 2)
W A AS
7 8 8 1
PAGE
NUMBER
8 11 1 11
A A …
COMMAND
CODE
8 1
A
SLAVE
ADDRESS
BLOCK COUNT
(= 2)
LOWER DATA
BYTE
R A ASr
7 8 8 1
UPPER DATA
BYTE
8 11 1 11
A A PEC BYTE
8 1
NA
4676A F56
LTM4675
84
Rev. C
For more information www.analog.com
If WP pin is high, PAGE, OPERATION, MFR_CLEAR_PEAKS, MFR_EE_UNLOCK and CLEAR_FAULTS commands are
supported. Individual fault bits can be cleared by writing a 1 to the respective bits in the STATUS registers.
MFR_ADDRESS
The MFR_ADDRESS command byte sets the 7 bits of the PMBus slave address for this device.
Setting this command to a value of 0x80 disables device addressing. The GLOBAL device address, 0x5A and 0x5B,
cannot be deactivated. If RCONFIG is set to ignore (MFR_CONFIG_ALL[6]=1b), the ASEL pin is still used to determine
the LSB of the channel address. If the ASEL pin is open, the LTM4675 will use the four LSBs of the MFR_ADDRESS
stored in EEPROM. Values of 0x5A, 0x5B, 0x0C, and 0x7C are not recommended.
This command has one data byte.
MFR_RAIL_ADDRESS
The MFR_RAIL_ADDRESS command enables direct device address access to the PAGE activated channel. The value
of this command should be common to all devices attached to a single power supply rail.
The user should only perform command writes to this address. If a read is performed from this address and the rail
devices do not respond with EXACTLY the same value, the LTM4675 will detect bus contention and set a CML com-
munications fault.
Setting this command to a value of 0x80 disables rail device addressing for the channel.
This command has one data byte.
GENERAL CONFIGURATION REGISTERS
COMMAND NAME CMD CODE DESCRIPTION TYPE PAGED
DATA
FORMAT UNITS NVM
DEFAULT
VALUE
MFR_CHAN_CONFIG 0xD0 Configuration bits that are channel specific. R/W Byte Y Reg Y 0x1F
MFR_CONFIG_ALL 0xD1 Configuration bits that are common to all
pages.
R/W Byte N Reg Y 0x09
MFR_CHAN_CONFIG
General purpose configuration command common to multiple ADI products.
BIT MEANING
7 Reserved
6 Reserved
5 Reserved
4 Disable RUN Low. When asserted the RUN pin is not pulsed low if commanded OFF
3 Short Cycle. When asserted the output will immediate off if commanded ON while waiting for TOFF_DELAY or TOFF_FALL. TOFF_MIN of 120ms
is honored then the part will command ON.
2 SHARE_CLOCK control, if SHARE_CLOCK is held low, the output is disabled
1 No GPIO ALERT, ALERT is not pulled low if GPIO is pulled low externally. Assert this bit if either POWER_GOOD or VOUT_UVUF are propagated
on GPIO
0Disables the VOUT decay value requirement for MFR_RETRY_TIME processing. When this bit is set to a 0, the output must decay to less than 12.5% of
the programmed value for any action that turns off the rail including a fault, an OFF/ON command, or a toggle of RUN from high to low to high.
This command has one data byte.
APPENDIX C: PMBUS COMMAND DETAILS
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APPENDIX C: PMBUS COMMAND DETAILS
MFR_CONFIG_ALL
General purpose configuration command common to multiple ADI products
BIT MEANING
7 Enable Fault Logging
6 Ignore Resistor Configuration Pins
5 Disable CML fault for Quick Command message
4 Disable SYNC out
3 Enable 255ms Time Out
2 A valid PEC required for PMBus writes to be accepted. If this bit is not set,
the part will accept commands with invalid PEC.
1 Enable the use of PMBus clock stretching
0 Enables a low to high transition on either RUN pin to issue a
CLEAR_FAULTS command
This command has one data byte.
ON/OFF/MARGIN
COMMAND NAME
CMD
CODE DESCRIPTION TYPE PAGED
DATA
FORMAT UNITS NVM
DEFAULT
VALUE
ON_OFF_CONFIG 0x02 RUN pin and PMBus bus on/off command configuration. R/W Byte Y Reg Y 0x1F
OPERATION 0x01 Operating mode control. On/off, margin high and margin
low.
R/W Byte Y Reg Y 0x80
MFR_RESET 0xFD Commanded reset without requiring a power-down.
Identical to RESTORE_USER_ALL.
Send Byte N NA
ON_OFF_CONFIG
The ON_OFF_CONFIG command configures the combination of RUNn pin input and serial bus commands needed to
turn the unit on and off. This includes how the unit responds when power is applied.
Programming an unsupported ON_OFF_CONFIG value will generate a CML fault and the command will be ignored.
This command has one data byte.
Table 22. Supported Values
VALUE MEANING
0x1F OPERATION value and RUNn pin must both command the device to start/run. Device executes immediate off when commanded off.
0x1E OPERATION value and RUNn pin must both command the device to start/run. Device uses TOFF_ command values when
commanded off.
0x17 RUNn pin control with immediate off when commanded off. OPERATION on/off control ignored.
0x16 RUNn pin control using TOFF_ command values when commanded off. OPERATION on/off control ignored.
Note: A high on the RUNn pin is always required to start power conversion. Power conversion will always stop with a low on RUNn.
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APPENDIX C: PMBUS COMMAND DETAILS
OPERATION
The OPERATION command is used to turn the unit on and off in conjunction with the input from the RUNn pins. It is
also used to cause the unit to set the output voltage to the upper or lower MARGIN VOLTAGEs. The unit stays in the
commanded operating mode until a subsequent OPERATION command or change in the state of the RUNn pin instructs
the device to change to another mode. If the part is stored in the MARGIN_LOW/HIGH state, the next MFR_RESET
or RESTORE_USER_ALL or SVIN power cycle will ramp to that state. If the OPERATION command is modified, for
example ON is changed to MARGIN_LOW, the output will move at a fixed slope set by the VOUT_TRANSITION_RATE.
The default operation command is sequence off.
Margin High (Ignore Faults) and Margin Low (Ignore Faults) operations are not supported by the LTM4675.
The part defaults to the Sequence Off state.
This command has one data byte.
Table 23. OPERATION Command Detail Register OPERATION Data Contents
When On_Off_Config_Use_PMBus Enables Operation_Control
SYMBOL ACTION VALUE
BITS
FUNCTION
Turn off immediately 0x00
Turn on 0x80
Margin Low 0x98
Margin High 0xA8
Sequence off 0x40
OPERATION Data Contents When On_Off_Config is Configured Such That
OPERATION Command Is Not Used to Command Channel On or Off
SYMBOL ACTION VALUE
BITS
FUNCTION
Output at Nominal 0x80
Margin Low 0x98
Margin High 0xA8
Note: Attempts to write a reserved value will cause a CML fault.
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APPENDIX C: PMBUS COMMAND DETAILS
MFR_RESET
This command provides a means by which the user can perform a reset of the LTM4675. Identical to RESTORE_USER_ALL.
This write-only command has no data bytes.
PWM CONFIG
COMMAND NAME CMD CODE DESCRIPTION TYPE PAGED
DATA
FORMAT UNITS NVM
DEFAULT
VALUE
MFR_PWM_MODE 0xD4 Configuration for the PWM engine of each channel. R/W Byte Y Reg Y 0xC1
MFR_PWM_CONFIG 0xF5 Set numerous parameters for the DC/DC controller
including phasing.
R/W Byte N Reg Y 0x10
FREQUENCY_SWITCH 0x33 Switching frequency of the controller. R/W Word N L11 kHz Y 500
0xFBE8
MFR_PWM_MODE
The MFR_PWM_MODE command allows the user to program the PWM controller to use, discontinuous (pulse-skipping
mode), or forced continuous conduction mode.
BIT MEANING
7 Range of ILIMIT
0 – Low Current Range
1 – High Current Range
6 Enable Servo Mode
5 Reserved
4 Page 0 Only: Use of TSNS1a-Sensed Temperature Telemetry
0 - Temperature sensed via TSNS1a is used to temperature-correct the current-sense information digitized by Channel 1.
1 - Temperature sensed via TSNS0 is used to temperature-correct the current-sense information digitized by Channel 1. Telemetry obtained
from the thermal sensor connected to TSNS1a can be external to the module, if desired.
3 Reserved
2 Reserved
1 Voltage Range
0 - Hi Voltage Range 5.5 volts max
1 - Lo Voltage Range 2.75 volts max
0PWM Mode
0 - Discontinuous Mode
1 - Continuous Mode
Whenever the channel is ramping on, the PWM mode will be discontinuous, regardless of the value of this
command.
Bit [7] of this command determines if the part is in high range or low range of the IOUT_OC_FAULT_LIMIT command.
Changing this bit value changes the PWM loop gain and compensation. Changing this bit value whenever an output is
active may have detrimental system results.
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APPENDIX C: PMBUS COMMAND DETAILS
Bit [6] The LTM4675 will not servo while the part is OFF, ramping on or ramping off. When set to a one, the output servo
is enabled. The output set point DAC will be slowly adjusted to minimize the difference between the READ_VOUT_ADC
and the VOUT_COMMAND (or the appropriate margined value).
Bit [1] of this command determines if the part is in high range or low voltage range. Changing this bit value changes
the PWM loop gain and compensation. This bit value cannot be changed when an output is active.
This command has one data byte.
MFR_PWM_CONFIG
The MFR_PWM_CONFIG command sets the switching frequency phase offset with respect to the falling edge of the
SYNC signal. The part must be in the OFF state to process this command. Either the RUN pins must be low or the part
must be commanded off. If the part is in the RUN state and this command is written, the command will be ignored and
a BUSY fault will be asserted. Bit 7 allows remote differential voltage sensing for PolyPhase rail applications.
BIT MEANING
7 EA Connection
0 – Independent EA and Channel Outputs
1 – EA1 uses EA0 input for PolyPhase operation
6 Reserved.
5 Reserved
4 Share Clock Enable : If this bit is 1, the
SHARE_CLK pin will not be released until
SVIN > VIN_ON. The SHARE_CLK pin will be
pulled low when SVIN < VIN_OFF. If this bit is 0, the SHARE_CLK
pin will not be pulled low when SVIN < VIN_OFF except for the
initial application of SVIN.
3 Reserved
BIT [2:0] CHANNEL 0 (DEGREES) CHANNEL 1 (DEGREES)
000b 0 180
001b 90 270
010b 0 240
011b 0 120
100b 120 240
101b 60 240
110b 120 300
Do not assert Bit [7] unless it is a PolyPhase application and both VOUT pins are tied together and both COMPna pins
are tied together.
This command has one data byte.
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APPENDIX C: PMBUS COMMAND DETAILS
FREQUENCY_SWITCH
The FREQUENCY_SWITCH command sets the switching frequency, in kHz, of a PMBus device. See Table 7 for recom-
mended values.
Supported Frequencies:
VALUE [15:0] RESULTING FREQUENCY (TYP)
0x0000 External Oscillator
0xF3E8 250kHz
0xFABC 350kHz
0xFB52 425kHz
0xFBE8 500kHz
0x023F 575kHz
0x028A 650kHz
0x02EE 750kHz
0x03E8 1000kHz
The part must be in the OFF state to process this command. Either the RUN pins must be low or the part must be
commanded off. If the part is in the RUN state and this command is written, the command will be ignored and a BUSY
fault will be asserted. When the part is commanded off and the frequency is changed, a PLL_UNLOCK status may be
detected as the PLL locks onto the new frequency.
This command has two data bytes and is formatted in Linear_5s_11s format.
VOLTAGE
Input Voltage (SVIN) and Limits
COMMAND NAME CMD CODE DESCRIPTION TYPE PAGED
DATA
FORMAT UNITS NVM
DEFAULT
VALUE
VIN_OV_FAULT_ LIMIT 0x55 Input supply (SVIN) overvoltage fault limit. R/W Word N L11 V Y 17.44
0xDA2E
VIN_UV_WARN_LIMIT 0x58 Input supply (SVIN) undervoltage warning limit. R/W Word N L11 V Y 5.297
0xCAA6
VIN_ON 0x35 Input voltage (SVIN) at which the unit should start
power conversion.
R/W Word N L11 V Y 5.500
0xCAC0
VIN_OFF 0x36 Input voltage (SVIN) at which the unit should stop
power conversion.
R/W Word N L11 V Y 5.250
0xCAA0
VIN_OV_FAULT_LIMIT
The VIN_OV_FAULT_LIMIT command sets the value of the measured (SVIN) input voltage, in volts, that causes an
input overvoltage fault. The fault is detected with the A/D converter resulting in latency up to 90ms, typical.
This command has two data bytes and is formatted in Linear_5s_11s format.
VIN_UV_WARN_LIMIT
The VIN_UV_WARN_LIMIT command sets the value of the SVIN input voltage that causes an SVIN input undervoltage
warning. The warning is detected with the A/D converter resulting in latency up to 90ms, typical.
This command has two data bytes and is formatted in Linear_5s_11s format.
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APPENDIX C: PMBUS COMMAND DETAILS
VIN_ON
The VIN_ON command sets the SVIN input voltage, in volts, at which the unit should start power conversion.
This command has two data bytes and is formatted in Linear_5s_11s format.
VIN_OFF
The VIN_OFF command sets the SVIN input voltage, in volts, at which the unit should stop power conversion.
This command has two data bytes and is formatted in Linear_5s_11s format.
Output Voltage and Limits
COMMAND NAME CMD CODE DESCRIPTION TYPE PAGED
DATA
FORMAT UNITS NVM
DEFAULT
VALUE
VOUT_MODE 0x20 Output voltage format and exponent (2–12). R Byte Y Reg 2–12
0x14
VOUT_MAX 0x24 Upper limit on the commanded output voltage
including VOUT_MARGIN_HIGH.
R/W Word Y L16 V Y 5.6
0x599A
VOUT_OV_FAULT_ LIMIT 0x40 Output overvoltage fault limit. R/W Word Y L16 V Y 1.1
0x119A
VOUT_OV_WARN_ LIMIT 0x42 Output overvoltage warning limit. R/W Word Y L16 V Y 1.075
0x1133
VOUT_MARGIN_HIGH 0x25 Margin high output voltage set point. Must be
greater than VOUT_COMMAND.
R/W Word Y L16 V Y 1.05
0x10CD
VOUT_COMMAND 0x21 Nominal output voltage set point. R/W Word Y L16 V Y 1.0
0x1000
VOUT_MARGIN_LOW 0x26 Margin low output voltage set point. Must be
less than VOUT_COMMAND.
R/W Word Y L16 V Y 0.95
0x0F33
VOUT_UV_WARN_ LIMIT 0x43 Output undervoltage warning limit. R/W Word Y L16 V Y 0.925
0x0ECD
VOUT_UV_FAULT_ LIMIT 0x44 Output undervoltage fault limit. R/W Word Y L16 V Y 0.9
0x0E66
MFR_VOUT_MAX 0xA5 Maximum allowed output voltage including
VOUT_OV_FAULT_LIMIT.
R Word Y L16 V 5.7
0x5B34
VOUT_MODE
The data byte for VOUT_MODE command, used for commanding and reading output voltage, consists of a 3-bit mode
(only linear format is supported) and a 5-bit parameter representing the exponent used in output voltage Read/Write
commands.
This read-only command has one data byte.
VOUT_MAX
The VOUT_MAX command sets an upper limit on any voltage, including VOUT_MARGIN_HIGH, the unit can command
regardless of any other commands or combinations. The maximum allowed value of this command is 5.7 volts. The
maximum output voltage the LTM4675 can produce is 5.5 volts including VOUT_MARGIN_HIGH. However, the
VOUT_OV_FAULT_LIMIT can be commanded as high as 5.7 volts.
This command has two data bytes and is formatted in Linear_16u format.
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APPENDIX C: PMBUS COMMAND DETAILS
VOUT_OV_FAULT_LIMIT
The VOUT_OV_FAULT_LIMIT command sets the value of the output voltage measured at the sense pins, in volts, which
causes an output overvoltage fault.
If the VOUT_OV_FAULT_LIMIT is modified and the switcher is active, allow 10ms after the command is modified to
assure the new value is being honored. The part indicates if it is busy making a calculation. Monitor bits 5 and 6 of
MFR_COMMON. Either bit is low if the part is busy. If this wait time is not met, and the VOUT_COMMAND is modified
above the old overvoltage limit, an OV condition might temporarily be detected resulting in undesirable behavior and
possible damage to the switcher.
If VOUT_OV_FAULT_RESPONSE is set to OV_PULLDOWN, the GPIO pin will not assert if VOUT_OV_FAULT is propa-
gated. The LTM4675 will pull the TG low and assert the BG bit as soon as the overvoltage condition is detected.
This command has two data bytes and is formatted in Linear_16u format.
VOUT_OV_WARN_LIMIT
The VOUT_OV_WARN_LIMIT command sets the value of the output voltage measured at the sense pins, in volts, which
causes an output voltage high warning. The READ_VOUT value will be used to determine if this limit has been exceeded.
In response to the VOUT_OV_WARN_LIMIT being exceeded, the device:
• Sets the NONE_OF_THE_ABOVE bit in the STATUS_BYTE
• Sets the VOUT bit in the STATUS_WORD
• Sets the VOUT Overvoltage Warning bit in the STATUS_VOUT command
• Notifies the host by asserting ALERT pin, unless masked.
This condition is detected by the ADC so the response time may be up to 90ms, typical.
This command has two data bytes and is formatted in Linear_16u format.
VOUT_MARGIN_HIGH
The VOUT_MARGIN_HIGH command loads the unit with the voltage to which the output is to be changed, in volts, when
the OPERATION command is set to “Margin High”. The value must be greater than VOUT_COMMAND. The maximum
guaranteed value on VOUT_MARGIN_HIGH is 5.5 volts.
This command will not be acted on during TON_RISE and TOFF_FALL output sequencing. The VOUT_TRANSITION_RATE
will be used if this command is modified while the output is active and in a steady-state condition.
This command has two data bytes and is formatted in Linear_16u format.
VOUT_COMMAND
The VOUT_COMMAND consists of two bytes and is used to set the output voltage, in volts. The maximum guaranteed
value on VOUT is 5.5 volts.
This command will not be acted on during TON_RISE and TOFF_FALL output sequencing. The VOUT_TRANSITION_RATE
will be used if this command is modified while the output is active and in a steady-state condition.
This command has two data bytes and is formatted in Linear_16u format.
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APPENDIX C: PMBUS COMMAND DETAILS
VOUT_MARGIN_LOW
The VOUT_MARGIN_LOW command loads the unit with the voltage to which the output is to be changed, in volts,
when the OPERATION command is set to “Margin Low”. The value must be less than VOUT_COMMAND.
This command will not be acted on during TON_RISE and TOFF_FALL output sequencing. The VOUT_TRANSITION_RATE
will be used if this command is modified while the output is active and in a steady-state condition.
This command has two data bytes and is formatted in Linear_16u format.
VOUT_UV_WARN_LIMIT
The VOUT_UV_ WARN_LIMIT command reads the value of the output voltage measured at the sense pins, in volts,
which causes an output voltage low warning.
In response to the VOUT_UV_WARN_LIMIT being exceeded, the device:
• Sets the NONE_OF_THE_ABOVE bit in the STATUS_BYTE
• Sets the VOUT bit in the STATUS_WORD
• Sets the VOUT Undervoltage Warning bit in the STATUS_VOUT command
• Notifies the host by asserting ALERT pin, unless masked.
This condition is detected by the ADC so the response time may be up to 90ms, typical.
This command has two data bytes and is formatted in Linear_16u format.
VOUT_UV_FAULT_LIMIT
The VOUT_UV_FAULT_LIMIT command reads the value of the output voltage measured at the sense pins, in volts,
which causes an output undervoltage fault.
This command has two data bytes and is formatted in Linear_16u format.
MFR_VOUT_MAX
The MFR_VOUT_MAX command is the maximum output voltage in volts for each channel including VOUT_OV_FAULT_
LIMIT. If the output voltages are set to high range (Bit 1 of MFR_PWM_MODE set to a 0) MFR_VOUT_MAX for channel
0 and 1 is 5.7V. If the output voltages are set to low range (Bit 1 of MFR_PWM_MODE set to a 1) the MFR_VOUT_MAX
for both channels is 2.75V. Entering VOUT_COMMAND values greater than this will result in a CML fault and the output
voltage setting will be clamped to the maximum level.
This read-only command has 2 data bytes and is formatted in Linear_16u format.
CURRENT
Input Current Calibration
COMMAND NAME CMD CODE DESCRIPTION TYPE PAGED
DATA
FORMAT UNITS NVM
DEFAULT
VALUE
MFR_IIN_OFFSET 0xE9 Coefficient used to add to the input current to
account for the IQ of the part.
R/W
Word
Y L11 A Y 0.02956
0x8BC9
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APPENDIX C: PMBUS COMMAND DETAILS
MFR_IIN_OFFSET
The MFR_IIN_OFFSET command allows the user to set an input current representing the quiescent current of each
channel. For accurate results at low output current, the part should be in continuous conduction mode. (MFR_PWM_
MODE[0]=1b). See Table 8 for recommended values.
This command has 2 data bytes and is formatted in Linear_5s_11s format.
Output Current Calibration
COMMAND NAME
CMD
CODE DESCRIPTION TYPE PAGED
DATA
FORMAT UNITS NVM
DEFAULT
VALUE
IOUT_CAL_GAIN 0x38 The ratio of the voltage at the current
sense pins to the sensed current.
R/W Word Y L11 mΩ Factory-
Only NVM
Trimmed,
4.46mΩ typical
MFR_IOUT_CAL_GAIN_TC 0xF6 Temperature coefficient of the current
sensing element.
R/W Word Y CF Y 3860
0x0F14
IOUT_CAL_GAIN
The IOUT_CAL_GAIN command is nominally used to set the resistance value of the current sense element, in milliohms.
(see also MFR_IOUT_CAL_GAIN_TC). Writes to this register result in a NACK and do not impact output current read-
back telemetry.
This command has two data bytes and is formatted in Linear_5s_11s format.
MFR_IOUT_CAL_GAIN_TC
The MFR_IOUT_CAL_GAIN_TC command allows the user to program the temperature coefficient of the IOUT_CAL_GAIN
inductor DCR in ppm/°C.
This command has two data bytes and is formatted in 16-bit 2’s complement integer ppm. N = –32768 to 32767 •
10–6. Nominal temperature is 27°C. The IOUT_CAL_GAIN is multiplied by:
[1.0 + MFR_IOUT_CAL_GAIN_TC • (READ_TEMPERATURE_1-27)]. DCR sensing will have a typical value of 3900.
The IOUT_CAL_GAIN and MFR_IOUT_CAL_GAIN_TC impact all current parameters including: READ_IOUT, READ_IIN,
IOUT_OC_FAULT_LIMIT and IOUT_OC_WARN_LIMIT. Writes to this register are not recommended; use the factory-
default value.
Input Current
COMMAND NAME CMD CODE DESCRIPTION TYPE PAGED
DATA
FORMAT UNITS NVM
DEFAULT
VALUE
IIN_OC_WARN_LIMIT 0x5D Input overcurrent warning limit. R/W Word N L11 A Y 8.5
0xD220
IIN_OC_WARN_LIMIT
The IIN_OC_WARN_LIMIT command sets the value of the input current, in amperes, that causes a warning indicating
the input current is high. The READ_IIN value will be used to determine if this limit has been exceeded.
In response to the IIN_OC_WARN_LIMIT being exceeded, the device:
• Sets the OTHER bit in the STATUS_BYTE
• Sets the INPUT bit in the upper byte of the STATUS_WORD
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APPENDIX C: PMBUS COMMAND DETAILS
• Sets the IIN Overcurrent Warning bit in the STATUS_INPUT command, and
• Notifies the host by asserting ALERT pin, unless masked
This condition is detected by the ADC so the response time may be up to 90ms, typical.
This command has two data bytes and is formatted in Linear_5s_11s format.
Output Current
COMMAND NAME CMD CODE DESCRIPTION TYPE PAGED
DATA
FORMAT UNITS NVM
DEFAULT
VALUE
IOUT_OC_FAULT_LIMIT 0x46 Output overcurrent fault limit. R/W Word Y L11 A Y 15.80
0xD3F3
IOUT_OC_WARN_LIMIT 0x4A Output overcurrent warning limit. R/W Word Y L11 A Y 10.80
0xD2B3
IOUT_OC_FAULT_LIMIT
The IOUT_OC_FAULT_LIMIT command sets the value of the peak output current limit, in amperes. When the controller
is in current limit, the overcurrent detector will indicate an overcurrent fault condition. The programmed overcurrent
fault limit value is rounded up to the nearest one of the following set of discrete values:
25mV/IOUT_CAL_GAIN Low Range (1.5x Nominal Loop Gain)
MFR_PWM_MODE [7]=0
28.6mV/IOUT_CAL_GAIN
32.1mV/IOUT_CAL_GAIN
35.7mV/IOUT_CAL_GAIN
39.3mV/IOUT_CAL_GAIN
42.9mV/IOUT_CAL_GAIN
46.4mV/IOUT_CAL_GAIN
50mV/IOUT_CAL_GAIN
37.5mV/IOUT_CAL_GAIN High Range (Nominal Loop Gain)
MFR_PWM_MODE [7]=1
42.9mV/IOUT_CAL_GAIN
48.2mV/IOUT_CAL_GAIN
53.6mV/IOUT_CAL_GAIN
58.9mV/IOUT_CAL_GAIN
64.3mV/IOUT_CAL_GAIN
69.6mV/IOUT_CAL_GAIN
75mV/IOUT_CAL_GAIN
Note: This is the peak of the current waveform. The READ_IOUT command returns the average current. The peak output
current limits are adjusted with temperature based on the MFR_IOUT_CAL_GAIN_TC using the equation:
IOUT_OC_FAULT_LIMIT = IOUT_CAL_GAIN • (1 + MFR_IOUT_CAL_GAIN_TC • (READ_TEMPERTURE_1-27.0)).
The LTpowerPlay GUI automatically convert the voltages to currents.
The IOUT range is set with bit 7 of the MFR_PWM_MODE command.
The IOUT_OC_FAULT_LIMIT is ignored during TON_RISE and TOFF_FALL.
This command has two data bytes and is formatted in Linear_5s_11s format.
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APPENDIX C: PMBUS COMMAND DETAILS
IOUT_OC_WARN_LIMIT
This command sets the value of the output current that causes an output overcurrent warning in amperes. The
READ_IOUT value will be used to determine if this limit has been exceeded.
In response to the IOUT_OC_WARN_LIMIT being exceeded, the device:
• Sets the NONE_OF_THE_ABOVE bit in the STATUS_BYTE
• Sets the IOUT bit in the STATUS_WORD
• Sets the IOUT Overcurrent Warning bit in the STATUS_IOUT command, and
• Notifies the host by asserting ALERT pin, unless masked.
This condition is detected by the ADC so the response time may be up to 90ms, typical.
The IOUT_OC_FAULT_LIMIT is ignored during TON_RISE and TOFF_FALL.
This command has two data bytes and is formatted in Linear_5s_11s format
TEMPERATURE
Power Stage DCR Temperature Calibration
COMMAND NAME CMD CODE DESCRIPTION TYPE PAGED
DATA
FORMAT UNITS NVM
DEFAULT
VALUE
MFR_TEMP_1_GAIN 0xF8 Sets the slope of the power stage temperature
sensor.
R/W Word Y CF Y 0.995
0x3FAE
MFR_TEMP_1_OFFSET 0xF9 Sets the offset of the power stage temperature
sensor with respect to –273.1°C.
R/W Word Y L11 C Y 0
0x8000
MFR_TEMP_1_GAIN
The MFR_TEMP_1_GAIN command will modify the slope of the power stage temperature sensor to account for non-
idealities in the element and errors associated with the remote sensing of the temperature in the inductor.
This command has two data bytes and is formatted in 16-bit 2’s complement integer. N = 8192 to 32767. The effective
adjustment is N • 2–14. The nominal value is 1.
MFR_TEMP_1_OFFSET
The MFR_TEMP_1_OFFSET command will modify the offset of the power stage temperature sensor to account for
non-idealities in the element and errors associated with the remote sensing of the temperature in the inductor.
This command has two data bytes and is formatted in Linear_5s_11s format. The part starts the calculation with a
value of –273.15 so the default adjustment value is zero.
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APPENDIX C: PMBUS COMMAND DETAILS
Power Stage Temperature Limits
COMMAND NAME CMD CODE DESCRIPTION TYPE PAGED
DATA
FORMAT UNITS NVM
DEFAULT
VALUE
OT_FAULT_LIMIT 0x4F Power stage overtemperature fault limit. R/W Word Y L11 C Y 128
0xF200
OT_WARN_LIMIT 0x51 Power stage overtemperature warning limit. R/W Word Y L11 C Y 125
0xEBE8
UT_FAULT_LIMIT 0x53 Power stage undertemperature fault limit. R/W Word Y L11 C Y –45
0xE530
OT_FAULT_LIMIT
The OT_FAULT_LIMIT command sets the value of the power stage temperature, in degrees Celsius, which causes an
overtemperature fault. The READ_TEMPERATURE_1 value will be used to determine if this limit has been exceeded.
This condition is detected by the ADC so the response time may be up to 90ms, typical.
This command has two data bytes and is formatted in Linear_5s_11s format.
OT_WARN_LIMIT
The OT_WARN_LIMIT command sets the value of the power stage temperature, in degrees Celsius, which causes an
overtemperature warning. The READ_TEMPERATURE_1 value will be used to determine if this limit has been exceeded.
In response to the OT_WARN_LIMIT being exceeded, the device:
• Sets the TEMPERATURE bit in the STATUS_BYTE
• Sets the Overtemperature Warning bit in the STATUS_TEMPERATURE command, and
• Notifies the host by asserting ALERT pin, unless masked.
This condition is detected by the ADC so the response time may be up to 90ms, typical.
This command has two data bytes and is formatted in Linear_5s_11s format.
UT_FAULT_LIMIT
The UT_FAULT_LIMIT command sets the value of the power stage temperature, in degrees Celsius, which causes
an undertemperature fault. The READ_TEMPERATURE_1 value will be used to determine if this limit has been
exceeded.
This condition is detected by the ADC so the response time may be up to 90ms, typical.
This command has two data bytes and is formatted in Linear_5s_11s format.
LTM4675
97
Rev. C
For more information www.analog.com
APPENDIX C: PMBUS COMMAND DETAILS
TIMING
Timing—On Sequence/Ramp
COMMAND NAME CMD CODE DESCRIPTION
TYPE PAGED
DATA
FORMAT UNITS NVM
DEFAULT
VALUE
TON_DELAY 0x60 Time from RUN and/or Operation on to output
rail turn-on.
R/W Word Y L11 ms Y 0.0
0x8000
TON_RISE 0x61 Time from when the output starts to rise
until the output voltage reaches the VOUT
commanded value.
R/W Word Y L11 ms Y 3.0
0xC300
TON_MAX_FAULT_LIMIT 0x62 Maximum time from the start of TON_RISE for
VOUT to cross the VOUT_UV_FAULT_LIMIT.
R/W Word Y L11 ms Y 5.0
0xCA80
VOUT_TRANSITION_RATE 0x27 Rate the output changes when VOUT
commanded to a new value.
R/W Word Y L11 V/ms Y 0.001
0x8042
TON_DELAY
The TON_DELAY command sets the time, in milliseconds, from when a start condition is received until the output
voltage starts to rise. Values from 0ms to 83 seconds are valid.
This command has two data bytes and is formatted in Linear_5s_11s format.
TON_RISE
The TON_RISE command sets the time, in milliseconds, from the time the output starts to rise to the time the output
enters the regulation band. Values from 0 to 1.3 seconds are valid. The part will be in discontinuous mode during
TON_RISE events. If TON_RISE is less than 0.25ms, the LTM4675 digital slope will be bypassed. The output voltage
transition will be controlled by the analog performance of the PWM switcher. The maximum allowed slope is 4V/ms.
This command has two data bytes and is formatted in Linear_5s_11s format.
TON_MAX_FAULT_LIMIT
The TON_MAX_FAULT_LIMIT command sets the value, in milliseconds, on how long the unit can attempt to power
up the output without reaching the output undervoltage fault limit.
A data value of 0ms means that there is no limit and that the unit can attempt to bring up the output voltage indefinitely.
The maximum limit is 83 seconds.
This command has two data bytes and is formatted in Linear_5s_11s format.
VOUT_TRANSITION_RATE
When a PMBus device receives either a VOUT_COMMAND or OPERATION (Margin High, Margin Low) that causes the
output voltage to change this command set the rate in V/ms at which the output voltage changes. This commanded
rate of change does not apply when the unit is commanded on or off.
This command has two data bytes and is formatted in Linear_5s_11s format.
LTM4675
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Rev. C
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APPENDIX C: PMBUS COMMAND DETAILS
Timing—Off Sequence/Ramp
COMMAND NAME CMD CODE DESCRIPTION TYPE PAGED
DATA
FORMAT UNITS NVM
DEFAULT
VALUE
TOFF_DELAY 0x64 Time from RUN and/or Operation off to the start
of TOFF_FALL ramp.
R/W Word Y L11 ms Y 0.0
0x8000
TOFF_FALL 0x65 Time from when the output starts to fall until the
output reaches zero volts.
R/W Word Y L11 ms Y 3.0
0xC300
TOFF_MAX_WARN_LIMIT 0x66 Maximum allowed time, after TOFF_FALL
completed, for the unit to decay below 12.5%.
R/W Word Y L11 ms Y 0.0
0x8000
TOFF_DELAY
The TOFF_DELAY command sets the time, in milliseconds, from when a stop condition is received until the output
voltage starts to fall. Values from 0 to 83 seconds are valid.
This command is excluded from fault events.
This command has two data bytes and is formatted in Linear_5s_11s format.
TOFF_FALL
The TOFF_FALL command sets the time, in milliseconds, from the end of the turn-off delay time until the output volt-
age is commanded to zero. It is the ramp time of the VOUT DAC. When the VOUT DAC is zero, the part will three-state.
The part will maintain the mode of operation programmed. For defined TOFF_FALL times, the user should set the part
to continuous conduction mode. Loading the max value indicates the part will ramp down at the slowest possible rate.
The minimum supported fall time is 0.25ms. A value less than 0.25ms will result in a 0.25ms ramp. The maximum fall
time is 1.3 seconds. The maximum allowed slope is 4V/ms.
In discontinuous conduction mode, the controller will not draw current from the load and the fall time will be set by
the output capacitance and load current.
This command has two data bytes and is formatted in Linear_5s_11s format.
TOFF_MAX_WARN_LIMIT
The TOFF_MAX_WARN_LIMIT command sets the value, in milliseconds, on how long the unit can attempt to turn off
the output until a warning is asserted. The output is considered off when the VOUT voltage is less than 12.5% of the
programmed VOUT_COMMAND value. The calculation begins after TOFF_FALL is complete. TOFF_MAX_WARN is not
enabled in VOUT_DECAY is disabled.
A data value of 0ms means that there is no limit and that the unit can attempt to turn off the output voltage indefinitely.
Other than 0, values from 120ms to 524 seconds are valid.
This command has two data bytes and is formatted in Linear_5s_11s format.
Precondition for Restart
COMMAND NAME CMD CODE DESCRIPTION TYPE PAGED
DATA
FORMAT UNITS NVM
DEFAULT
VALUE
MFR_RESTART_ DELAY 0xDC Delay from actual RUN active edge to virtual
RUN active edge.
R/W Word Y L11 ms Y 300
0xFA58
LTM4675
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Rev. C
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APPENDIX C: PMBUS COMMAND DETAILS
MFR_RESTART_DELAY
This command specifies the minimum RUN off time in milliseconds. This device will pull the RUN pin low for this length
of time once a falling edge of RUN has been detected. The minimum recommended value is 136ms.
Note: The restart delay is different than the retry delay. The restart delay pulls run low for the specified time, after which
a standard start-up sequence is initiated. The minimum restart delay should be equal to TOFF_DELAY + TOFF_FALL
+ 136ms. Valid values are from 136ms to 65.52 seconds in 16ms increments. To assure a minimum off time, set
the MFR_RESTART_DELAY 16ms longer than the desired time. The output rail can be off longer than the MFR_
RESTART_DELAY after the RUN pin is pulled high if the output decay bit 1 is enabled in MFR_CHAN_CONFIG and the
output takes a long time to decay below 12.5% of the programmed value.
This command has two data bytes and is formatted in Linear_5s_11s format.
FAULT RESPONSE
Fault Responses All Faults
COMMAND NAME CMD CODE DESCRIPTION TYPE PAGED
DATA
FORMAT UNITS NVM
DEFAULT
VALUE
MFR_RETRY_ DELAY 0xDB Retry interval during FAULT retry mode. R/W Word Y L11 ms Y 250
0xF3E8
MFR_RETRY_DELAY
This command sets the time in milliseconds between restarts if the fault response is to retry the controller at specified
intervals. This command value is used for all fault responses that require retry. The retry time starts once the fault has
been detected by the offending channel. Valid values are from 120ms to 83.88 seconds in 1ms increments.
Note: The retry delay time is determined by the longer of the MFR_RETRY_DELAY command or the time required
for the regulated output to decay below 12.5% of the programmed value. If the natural decay time of the output is
too long, it is possible to remove the voltage requirement of the MFR_RETRY_DELAY command by asserting bit 0 of
MFR_CHAN_CONFIG.
This command has two data bytes and is formatted in Linear_5s_11s format.
Fault Responses Input Voltage (SVIN)
COMMAND NAME CMD CODE DESCRIPTION TYPE PAGED
DATA
FORMAT UNITS NVM
DEFAULT
VALUE
VIN_OV_FAULT_RESPONSE 0x56 Action to be taken by the device when an SVIN
input supply overvoltage fault is detected.
R/W Byte Y Reg Y 0xB8
VIN_OV_FAULT_RESPONSE
The VIN_OV_FAULT_RESPONSE command instructs the device on what action to take in response to an (SVIN) input
overvoltage fault. The data byte is in the format given in Table 28.
The device also:
• Sets the NONE_OF_THE_ABOVE bit in the STATUS_BYTE
• Set the INPUT bit in the upper byte of the STATUS_WORD
LTM4675
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Rev. C
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APPENDIX C: PMBUS COMMAND DETAILS
• Sets the SVIN Overvoltage Fault bit in the STATUS_INPUT command, and
• Notifies the host by asserting ALERT pin, unless masked.
This command has one data byte.
Fault Responses Output Voltage
COMMAND NAME CMD CODE DESCRIPTION TYPE PAGED
DATA
FORMAT UNITS NVM
DEFAULT
VALUE
VOUT_OV_FAULT_RESPONSE 0x41 Action to be taken by the device when an
output overvoltage fault is detected.
R/W Byte Y Reg Y 0x7A
VOUT_UV_FAULT_RESPONSE 0x45 Action to be taken by the device when an
output undervoltage fault is detected.
R/W Byte Y Reg Y 0xB8
TON_MAX_FAULT_
RESPONSE
0x63 Action to be taken by the device when a
TON_MAX_FAULT event is detected.
R/W Byte Y Reg Y 0xB8
VOUT_OV_FAULT_RESPONSE
The VOUT_OV_FAULT_RESPONSE command instructs the device on what action to take in response to an output
overvoltage fault. The data byte is in the format given in Table 24.
The device also:
• Sets the VOUT_OV bit in the STATUS_BYTE
• Sets the VOUT bit in the STATUS_WORD
• Sets the VOUT Overvoltage Fault bit in the STATUS_VOUT command
• Notifies the host by asserting ALERT pin, unless masked.
The only value recognized for this command are:
0x80–The device shuts down (disables the output) and the unit does not attempt to retry. The output remains disabled
until the fault is cleared (PMBus, Part II, Section 10.7).
0xB8–The device shuts down (disables the output) and device attempts retry continuously, without limitation, until
it is commanded OFF (by the RUN pin or OPERATION command or both), bias power is removed, or another fault
condition causes the unit to shut down.
0x4n The device shuts down and the unit does not attempt to retry. The output remains disabled until the part is
commanded OFF then ON or the RUN pin is asserted low then high or MFR_RESET or RESTORE_USER_ALL through the
command or removal of SVIN. The OV fault must remain active for a period of n • 10µs, where n is a value from 0 to 7.
0x78+n The device shuts down and the unit attempts to retry continuously until either the fault condition is cleared or
the part is commanded OFF then ON or the RUN pin is asserted low then high or MFR_RESET or RESTORE_USER_ALL
through the command or removal of SVIN. The OV fault must remain active for a period of n • 10µs, where n is a value
from 0 to 7.
Any other value will result in a CML fault and the write will be ignored.
This command has one data byte.
LTM4675
101
Rev. C
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APPENDIX C: PMBUS COMMAND DETAILS
VOUT_UV_FAULT_RESPONSE
The VOUT_UV_FAULT_RESPONSE command instructs the device on what action to take in response to an output
undervoltage fault. The data byte is in the format given in Table 25.
The device also:
• Sets the VOUT bit in the STATUS_WORD
• Sets the VOUT undervoltage fault bit in the STATUS_VOUT command
• Notifies the host by asserting ALERT pin, unless masked.
The UV fault and warn are masked until the following criteria are achieved:
1) The TON_MAX_FAULT_LIMIT has been reached
2) The TON_DELAY sequence has completed
3) The TON_RISE sequence has completed
4) The VOUT_UV_FAULT_LIMIT threshold has been reached
5) The IOUT_OC_FAULT_LIMIT is not present
The UV fault and warn are masked whenever the channel is not active.
The UV fault and warn are masked during TON_RISE and TOFF_FALL sequencing.
This command has one data byte.
Table 24. VOUT_OV_FAULT_RESPONSE Data Byte Contents
BITS DESCRIPTION VALUE MEANING
7:6 Response
For all values of bits [7:6], the LTM4675:
• Sets the corresponding fault bit in the status commands and
• Notifies the host by asserting ALERT pin, unless masked.
The fault bit, once set, is cleared only when one or more of the
following events occurs:
• The device receives a CLEAR_FAULTS command.
• The output is commanded through the RUNn pin, the OPERATION
command, or the combined action of the RUNn pin and
OPERATION command, to turn off and then to turn back on, or
• Bias power is removed and reapplied to the LTM4675.
00 Part performs OV pull down only (i.e., turns off the top
MOSFET and turns on lower MOSFET while VOUT is >
VOUT_OV_FAULT)
01 The PMBus device continues operation for the delay time
specified by bits [2:0] and the delay time unit specified for that
particular fault. If the fault condition is still present at the end of
the delay time, the unit responds as programmed in the Retry
Setting (bits [5:3]).
10 The device shuts down immediately (disables the output) and
responds according to the retry setting in bits [5:3].
11 Not supported. Writing this value will generate a CML fault.
5:3 Retry Setting 000-110 The unit does not attempt to restart. The output remains
disabled until the fault is cleared until the device is commanded
OFF bias power is removed.
111 The PMBus device attempts to restart continuously, without
limitation, until it is commanded OFF (by the RUNn pin or
OPERATION command or both), bias power is removed, or
another fault condition causes the unit to shut down without
retry. Note: The retry interval is set by the MFR_RETRY_DELAY
command.
2:0 Delay Time XXX The delay time in 10µs increments. This delay time determines
how long the controller continues operating after a fault is
detected. Only valid for deglitched off state
LTM4675
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Rev. C
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APPENDIX C: PMBUS COMMAND DETAILS
TON_MAX_FAULT_RESPONSE
The TON_MAX_FAULT_RESPONSE command instructs the device on what action to take in response to a TON_MAX
fault. The data byte is in the format given in Table 28.
The device also:
• Sets the NONE_OF_THE_ABOVE bit in the STATUS_BYTE
• Sets the VOUT bit in the STATUS_WORD
• Sets the TON_MAX_FAULT bit in the STATUS_VOUT command, and
• Notifies the host by asserting ALERT pin, unless masked.
• A value of 0 disables the TON_MAX_FAULT_RESPONSE. It is not recommended to use 0.
This command has one data byte.
Table 25. VOUT_UV_FAULT_RESPONSE Data Byte Contents
BITS DESCRIPTION VALUE MEANING
7:6 Response
For all values of bits [7:6], the LTM4675:
• Sets the corresponding fault bit in the status commands and
• Notifies the host by asserting ALERT pin, unless masked.
The fault bit, once set, is cleared only when one or more of the
following events occurs:
• The device receives a CLEAR_FAULTS command
• The output is commanded through the RUNn pin, the OPERATION
command, or the combined action of the RUNn pin and
OPERATION command, to turn off and then to turn back on, or
• Bias power is removed and reapplied to the LTM4675
00 The PMBus device continues operation without interruption.
(Ignores the fault functionally)
01 The PMBus device continues operation for the delay time
specified by bits [2:0] and the delay time unit specified for
that particular fault. If the fault condition is still present at the
end of the delay time, the unit responds as programmed in the
Retry Setting (bits [5:3]).
10 The device shuts down (disables the output) and responds
according to the retry setting in bits [5:3].
11 Not supported. Writing this value will generate a CML fault.
5:3 Retry Setting 000-110 The unit does not attempt to restart. The output remains
disabled until the fault is cleared until the device is commanded
OFF bias power is removed.
111 The PMBus device attempts to restart continuously, without
limitation, until it is commanded OFF (by the RUNn pin or
OPERATION command or both), bias power is removed, or
another fault condition causes the unit to shut down without
retry. Note: The retry interval is set by the MFR_RETRY_DELAY
command.
2:0 Delay Time XXX The delay time in 10µs increments. This delay time determines
how long the controller continues operating after a fault is
detected. Only valid for deglitched off state.
LTM4675
103
Rev. C
For more information www.analog.com
APPENDIX C: PMBUS COMMAND DETAILS
Fault Responses Output Current
COMMAND NAME CMD CODE DESCRIPTION TYPE PAGED
DATA
FORMAT UNITS NVM
DEFAULT
VALUE
IOUT_OC_FAULT_RESPONSE 0x47 Action to be taken by the device when an
output overcurrent fault is detected.
R/W Byte Y Reg Y 0x00
IOUT_OC_FAULT_RESPONSE
The IOUT_OC_FAULT_RESPONSE command instructs the device on what action to take in response to an output
overcurrent fault. The data byte is in the format given in Table 26.
The device also:
• Sets the IOUT_OC bit in the STATUS_BYTE
• Sets the IOUT bit in the STATUS_WORD
• Sets the IOUT Overcurrent Fault bit in the STATUS_IOUT command, and
• Notifies the host by asserting ALERT pin, unless masked.
This command has one data byte.
Table 26. IOUT_OC_FAULT_RESPONSE Data Byte Contents
BITS DESCRIPTION VALUE MEANING
7:6 Response
For all values of bits [7:6], the LTM4675:
• Sets the corresponding fault bit in the status commands and
• Notifies the host by asserting ALERT pin, unless masked.
The fault bit, once set, is cleared only when one or more of the
following events occurs:
• The device receives a CLEAR_FAULTS command
• The output is commanded through the RUNn pin, the OPERATION
command, or the combined action of the RUNn pin and
OPERATION command, to turn off and then to turn back on, or
• Bias power is removed and reapplied to the LTM4675.
00 The LTM4675 continues to operate indefinitely while
maintaining the output current at the value set by IOUT_OC_
FAULT_LIMIT without regard to the output voltage (known as
constant-current or brick-wall limiting).
01 Not supported.
10 The LTM4675 continues to operate, maintaining the output
current at the value set by IOUT_OC_FAULT_LIMIT without
regard to the output voltage, for the delay time set by bits [2:0].
If the device is still operating in current limit at the end of the
delay time, the device responds as programmed by the Retry
Setting in bits [5:3].
11 The LTM4675 shuts down immediately and responds as
programmed by the Retry Setting in bits [5:3].
5:3 Retry Setting 000-110 The unit does not attempt to restart. The output remains
disabled until the fault is cleared by cycling the RUNn pin or
removing bias power.
111 The device attempts to restart continuously, without limitation,
until it is commanded OFF (by the RUNn pin or OPERATION
command or both), bias power is removed, or another fault
condition causes the unit to shut down. Note: The retry interval
is set by the MFR_RETRY_DELAY command.
2:0 Delay Time XXX The number of delay time units in 16ms increments. This
delay time is used to determine the amount of time a unit is
to continue operating after a fault is detected before shutting
down. Only valid for deglitched off state.
LTM4675
104
Rev. C
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APPENDIX C: PMBUS COMMAND DETAILS
Fault Responses IC Temperature
COMMAND NAME CMD CODE DESCRIPTION TYPE PAGED
DATA
FORMAT UNITS NVM
DEFAULT
VALUE
MFR_OT_FAULT_
RESPONSE
0xD6 Action to be taken by the device when an
internal overtemperature fault is detected.
R Byte N Reg 0xC0
MFR_OT_FAULT_RESPONSE
The MFR_OT_FAULT_RESPONSE command byte instructs the device on what action to take in response to an internal
overtemperature fault. The data byte is in the format given in Table 27.
The LTM4675 also:
• Sets the MFR bit in the STATUS_WORD, and
• Sets the Overtemperature Fault bit in the STATUS_MFR_SPECIFIC command
• Notifies the host by asserting ALERT pin, unless masked.
This command has one data byte.
Table 27. Data Byte Contents MFR_OT_FAULT_RESPONSE
BITS DESCRIPTION VALUE MEANING
7:6 Response
For all values of bits [7:6], the LTM4675:
• Sets the corresponding fault bit in the status commands and
• Notifies the host by asserting ALERT pin, unless masked.
The fault bit, once set, is cleared only when one or more of the
following events occurs:
• The device receives a CLEAR_FAULTS command
• The output is commanded through the RUNn pin, the OPERATION
command, or the combined action of the RUNn pin and
OPERATION command, to turn off and then to turn back on, or
• Bias power is removed and reapplied to the LTM4675
00 Not supported. Writing this value will generate a CML fault.
01 Not supported. Writing this value will generate a CML fault
10 The device shuts down immediately (disables the output) and
responds according to the retry setting in bits [5:3].
11 The device’s output is disabled while the fault is present.
Operation resumes and the output is enabled when the fault
condition no longer exists.
5:3 Retry Setting 000 The unit does not attempt to restart. The output remains
disabled until the fault is cleared.
001-111 Not supported. Writing this value will generate CML fault.
2:0 Delay Time XXX Not supported. Value ignored
Fault Responses Power Stage Temperature
COMMAND NAME CMD CODE DESCRIPTION TYPE PAGED
DATA
FORMAT UNITS NVM
DEFAULT
VALUE
OT_FAULT_ RESPONSE 0x50 Action to be taken by the device when a power
stage overtemperature fault is detected,
R/W Byte Y Reg Y 0xB8
UT_FAULT_ RESPONSE 0x54 Action to be taken by the device when a power
stage undertemperature fault is detected.
R/W Byte Y Reg Y 0x00
LTM4675
105
Rev. C
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APPENDIX C: PMBUS COMMAND DETAILS
OT_FAULT_RESPONSE
The OT_FAULT_RESPONSE command instructs the device on what action to take in response to a power stage over-
temperature fault. The data byte is in the format given in Table 28.
The device also:
• Sets the TEMPERATURE bit in the STATUS_BYTE
• Sets the Overtemperature Fault bit in the STATUS_TEMPERATURE command, and
• Notifies the host by asserting ALERT pin, unless masked.
This condition is detected by the ADC so the response time may be up to 90ms, typical.
This command has one data byte.
UT_FAULT_RESPONSE
The UT_FAULT_RESPONSE command instructs the device on what action to take in response to a power stage under-
temperature fault. The data byte is in the format given in Table 28.
The device also:
• Sets the TEMPERATURE bit in the STATUS_BYTE
• Sets the Undertemperature Fault bit in the STATUS_TEMPERATURE command, and
• Notifies the host by asserting ALERT pin, unless masked.
This condition is detected by the ADC so the response time may be up to 90ms, typical.
This command has one data byte.
Table 28. Data Byte Contents: TON_MAX_FAULT_RESPONSE, VIN_OV_FAULT_RESPONSE,
OT_FAULT_RESPONSE, UT_FAULT_RESPONSE
BITS DESCRIPTION VALUE MEANING
7:6 Response
For all values of bits [7:6], the LTM4675:
• Sets the corresponding fault bit in the status commands, and
• Notifies the host by asserting ALERT pin, unless masked.
The fault bit, once set, is cleared only when one or more of the
following events occurs:
• The device receives a CLEAR_FAULTS command
• The output is commanded through the RUNn pin, the OPERATION
command, or the combined action of the RUNn pin and
OPERATION command, to turn off and then to turn back on, or
• Bias power is removed and reapplied to the LTM4675
00 The PMBus device continues operation without interruption.
01 Not supported. Writing this value will generate a CML fault.
10 The device shuts down immediately (disables the output) and
responds according to the retry setting in bits [5:3].
11 Not supported. Writing this value will generate a CML fault.
5:3 Retry Setting 000-110 The unit does not attempt to restart. The output remains disabled
until the fault is cleared until the device is commanded OFF bias
power is removed.
111 The PMBus device attempts to restart continuously, without
limitation, until it is commanded OFF (by the RUNn pin or
OPERATION command or both), bias power is removed, or another
fault condition causes the unit to shut down without retry. Note:
The retry interval is set by the MFR_RETRY_DELAY command.
2:0 Delay Time XXX Not supported. Values ignored
LTM4675
106
Rev. C
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APPENDIX C: PMBUS COMMAND DETAILS
FAULT SHARING
Fault Sharing Propagation
COMMAND NAME CMD CODE DESCRIPTION TYPE PAGED
DATA
FORMAT UNITS NVM
DEFAULT
VALUE
MFR_GPIO_ PROPAGATEn0xD2 Configuration that determines which faults are
propagated to the GPIO pins.
R/W Word Y Reg Y 0x6893
MFR_GPIO_PROPAGATE
The MFR_GPIO_PROPAGATE command enables the faults that can cause the GPIOn pin to assert low. The command is
formatted as shown in Table 29. Faults can only be propagated to the GPIO if they are programmed to respond to faults.
This command has two data bytes.
Table 29. GPIOn Propagate Fault Configuration. The GPIO0 and GPIO1 pins are designed to provide electrical notification of selected events to
the user. Some of these events are common to both output channels. Others are specific to an output channel. They can also be used to share faults
between channels.
BIT(S) SYMBOL OPERATION
B[15] VOUT disabled while not decayed. This is used in a PolyPhase configuration when bit 0 of the MFR_CHAN_CONFIG is a zero. If the
channel is turned off, by toggling the RUN pin or commanding the part OFF, and then the RUN
is reasserted or the part is commanded back on before the output has decayed, VOUT will not
restart until the 12.5% decay is honored. The GPIO pin is asserted during this condition if bit 15
is asserted.
B[14] Mfr_gpio_propagate_short_CMD_cycle 0: No action
1: Asserts low if commanded off then on before the output has sequenced off. Re-asserts high
120ms after sequence off.
b[13] Mfr_gpio_propagate_ton_max_fault 0: No action if a TON_MAX_FAULT fault is asserted
1: Associated output will be asserted low if a TON_MAX_FAULT fault is asserted
GPIO0 is associated with page 0 TON_MAX_FAULT faults
GPIO1 is associated with page 1 TON_MAX_FAULT faults
b[12] Mfr_gpio0_propagate_vout_uvuf,
Mfr_gpio1_propagate_vout_uvuf
Unfiltered VOUT_UV_FAULT_LIMIT comparator output
GPIO0 is associated with channel 0
GPIO1 is associated with channel 1
b[11] Mfr_gpio0_propagate_int_ot,
Mfr_gpio1_propagate_int_ot
0: No action if the MFR_OT_FAULT_LIMIT fault is asserted
1: Associated output will be asserted low if the MFR_OT_FAULT_LIMIT fault is asserted
b[10] Mfr_pwrgd1_en* 0: No action if channel 1 POWER_GOOD is not true
1: Associated output will be asserted low if channel 1 POWER_GOOD is not true
If this bit is asserted, the GPIO_FAULT_RESPONSE must be ignore. If the GPIO_FAULT_
RESPONSE is not set to ignore, the part will latch off and never be able to start.
b[9] Mfr_pwrgd0_en* 0: No action if channel 0 POWER_GOOD is not true
1: Associated output will be asserted low if channel 0 POWER_GOOD is not true
If this bit is asserted, the GPIO_FAULT_RESPONSE must be ignore. If the GPIO_FAULT_
RESPONSE is not set to ignore, the part will latch off and never be able to start.
b[8] Mfr_gpio0_propagate_ut,
Mfr_gpio1_propagate_ut
0: No action if the UT_FAULT_LIMIT fault is asserted
1: Associated output will be asserted low if the UT_FAULT_LIMIT fault is asserted
GPIO0 is associated with page 0 UT faults
GPIO1 is associated with page 1 UT faults
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107
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APPENDIX C: PMBUS COMMAND DETAILS
Fault Sharing Response
COMMAND NAME CMD CODE DESCRIPTION TYPE PAGED
DATA
FORMAT UNITS NVM
DEFAULT
VALUE
MFR_GPIO_RESPONSE 0xD5 Action to be taken by the device when the GPIO pin
is asserted low.
R/W Byte Y Reg Y 0xC0
MFR_GPIO_RESPONSE
This command determines the controller’s response to the GPIOn pin being pulled low by an external source.
VALUE MEANING
0xC0 GPIO_INHIBIT The LTM4675 will three-state the output in response to the GPIO pin pulled low.
0x00 GPIO_IGNORE The LTM4675 continues operation without interruption.
The device also:
• Sets the NONE_OF_THE_ABOVE bit in the STATUS_BYTE
• Sets the MFR bit in the STATUS_WORD
• Sets the GPIOB bit in the STATUS_MFR_SPECIFIC command, and
• Notifies the host by asserting ALERT pin, unless masked. The ALERT pin pulled low can be disabled by setting bit[1]
of MFR_CHAN_CFG.
This command has one data byte.
Table 29. GPIOn Propagate Fault Configuration. The GPIO0 and GPIO1 pins are designed to provide electrical notification of selected events to
the user. Some of these events are common to both output channels. Others are specific to an output channel. They can also be used to share faults
between channels.
BIT(S) SYMBOL OPERATION
b[7] Mfr_gpio0_propagate_ot,
Mfr_gpio1_propagate_ot
0: No action if the OT_FAULT_LIMIT fault is asserted
1: Associated output will be asserted low if the OT_FAULT_LIMIT fault is asserted
GPIO0 is associated with page 0 OT faults
GPIO1 is associated with page 1 OT faults
b[6] Reserved
b[5] Reserved
b[4] Mfr_gpio0_propagate_input_ov,
Mfr_gpio1_propagate_input_ov
0: No action if the VIN_OV_FAULT_LIMIT fault is asserted
1: Associated output will be asserted low if the VIN_OV_FAULT_LIMIT fault is asserted
b[3] Reserved
b[2] Mfr_gpio0_propagate_iout_oc,
Mfr_gpio1_propagate_iout_oc
0: No action if the IOUT_OC_FAULT_LIMIT fault is asserted
1: Associated output will be asserted low if the IOUT_OC_FAULT_LIMIT fault is asserted
GPIO0 is associated with page 0 OC faults
GPIO1 is associated with page 1 OC faults
b[1] Mfr_gpio0_propagate_vout_uv,
Mfr_gpio1_propagate_vout_uv
0: No action if the VOUT_UV_FAULT_LIMIT fault is asserted
1: Associated output will be asserted low if the VOUT_UV_FAULT_LIMIT fault is asserted
GPIO0 is associated with page 0 UV faults
GPIO1 is associated with page 1 UV faults
b[0] Mfr_gpio0_propagate_vout_ov,
Mfr_gpio1_propagate_vout_ov
0: No action if the VOUT_OV_FAULT_LIMIT fault is asserted
1: Associated output will be asserted low if the VOUT_OV_FAULT_LIMIT fault is asserted
GPIO0 is associated with page 0 OV faults
GPIO1 is associated with page 1 OV faults
*The PWRGD status is designed as an indicator and not to be used for power supply sequencing.
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APPENDIX C: PMBUS COMMAND DETAILS
SCRATCHPAD
COMMAND NAME CMD CODE DESCRIPTION TYPE PAGED
DATA
FORMAT UNITS NVM
DEFAULT
VALUE
USER_DATA_00 0xB0 OEM reserved. Typically used for part serialization. R/W Word N Reg Y NA
USER_DATA_01 0xB1 Manufacturer reserved for LTpowerPlay. R/W Word Y Reg Y NA
USER_DATA_02 0xB2 OEM reserved. Typically used for part serialization. R/W Word N Reg Y NA
USER_DATA_03 0xB3 A NVM word available for the user. R/W Word Y Reg Y 0x0000
USER_DATA_04 0xB4 A NVM word available for the user. R/W Word N Reg Y 0x0000
USER_DATA_00 through USER_DATA_04
These commands are non-volatile memory locations for customer storage. The customer has the option to write any
value to the USER_DATA_nn at any time. However, the LTpowerPlay software and contract manufacturers use some
of these commands for inventory control. Modifying the reserved USER_DATA_nn commands may lead to undesirable
inventory control and incompatibility with these products.
These commands have 2 data bytes and are in register format.
IDENTIFICATION
COMMAND NAME CMD CODE DESCRIPTION TYPE PAGED
DATA
FORMAT UNITS NVM
DEFAULT
VALUE
PMBUS_REVISION 0x98 PMBus revision supported by this device. Current
revision is 1.2.
R Byte N Reg 0x22
CAPABILITY 0x19 Summary of PMBus optional communication protocols
supported by this device.
R Byte N Reg 0xB0
MFR_ID 0x99 The manufacturer ID of the LTM4675 in ASCII. R String N ASC LT C
MFR_MODEL 0x9A Manufacturer part number in ASCII. R String N ASC LTM4675*
MFR_SERIAL 0x9E Serial number of this specific unit in ASCII. R Block N CF NA
MFR_SPECIAL_ID 0xE7 Manufacturer code representing the LTM4675. R Word N Reg 0x47AX
* The MFR_MODEL value is "LTM4675 ". The value consists of 8 ASCII characters and the last character is a blank space punctuation character (" "), i.e.,
ASCII code 0x20 or 32d.
PMBus_REVISION
The PMBUS_REVISION command indicates the revision of the PMBus to which the device is compliant. The LTM4675
is PMBus Version 1.2 compliant in both Part I and Part II.
This read-only command has one data byte.
CAPABILITY
This command provides a way for a host system to determine some key capabilities of a PMBus device.
The LTM4675 supports packet error checking, 400kHz bus speeds, and ALERT pin.
This read-only command has one data byte.
MFR_ID
The MFR_ID command indicates the manufacturer ID of the LTM4675 using ASCII characters.
This read-only command is in block format.
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APPENDIX C: PMBUS COMMAND DETAILS
MFR_MODEL
The MFR_MODEL command indicates the manufacturer’s part number of the LTM4675 using ASCII characters. The
MFR_MODEL value is “LTM4675 ”. The value consists of 8 ASCII characters and the last character is a blank space
punctuation character (“ ”), i.e., ASCII code 0x20 or 32d.
This read-only command is in block format.
MFR_SERIAL
The MFR_SERIAL command contains up to 9 bytes of custom formatted data used to uniquely identify the LTM4675
configuration.
This read-only command is in block format.
MFR_SPECIAL_ID
The 16-bit word representing the part name. The 0x47A prefix denotes the part is an LTM4675, X is adjustable by the
manufacturer.
This read-only command has 2 data bytes.
FAULT WARNING AND STATUS
COMMAND NAME CMD CODE DESCRIPTION TYPE PAGED FORMAT UNITS NVM
DEFAULT
VALUE
CLEAR_FAULTS 0x03 Clear any fault bits that have been set. Send Byte N NA
SMBALERT_MASK 0x1B Mask ALERT Activity. Block R/W Y Reg Y See CMD
Details
MFR_CLEAR_PEAKS 0xE3 Clears all peaks values. Send Byte N NA
STATUS_BYTE 0x78 One byte summary of the unit’s fault
condition.
R/W Byte Y Reg NA
STATUS_WORD 0x79 Tw o byte summary of the unit’s fault condition. R/W Word Y Reg NA
STATUS_VOUT 0x7A Output voltage fault and warning status. R/W Byte Y Reg NA
STATUS_IOUT 0x7B Output current fault and warning status. R/W Byte Y Reg NA
STATUS_INPUT 0x7C Input supply (SVIN) fault and warning status. R/W Byte N Reg NA
STATUS_ TEMPERATURE 0x7D TSNSna-sensed fault and warning status for
READ_TEMERATURE_1.
R/W Byte Y Reg NA
STATUS_CML 0x7E Communication and memory fault and
warning status.
R/W Byte N Reg NA
STATUS_MFR_ SPECIFIC 0x80 Manufacturer specific fault and state
information.
R/W Byte Y Reg NA
MFR_PADS 0xE5 Digital status of the I/O pads. R Word N Reg NA
MFR_COMMON 0xEF Manufacturer status bits that are common
across multiple ADI ICs/modules.
R Byte N Reg NA
MFR_INFO 0xB6 Manufacturing Specific Information R Word N Reg NA
CLEAR_FAULTS
The CLEAR_FAULTS command is used to clear any fault bits that have been set. This command clears all bits in all
status commands simultaneously. At the same time, the device negates (clears, releases) its ALERT pin signal output
if the device is asserting the ALERT pin signal. If the fault is still present when the bit is cleared, the fault bit will remain
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APPENDIX C: PMBUS COMMAND DETAILS
set and the host notified by asserting the ALERT pin low. CLEAR_FAULTS can take up to 10µs to process. If a fault
occurs within that time frame it may be cleared before the status register is set.
This write-only command has no data bytes.
The CLEAR_FAULTS does not cause a unit that has latched off for a fault condition to restart. Units that have shut down
for a fault condition are restarted when:
• The output is commanded through the RUN pin, the OPERATION command, or the combined action of the RUN pin
and OPERATION command, to turn off and then to turn back on, or
• MFR_RESET or RESTORE_USER_ALL command is issued.
• Bias power is removed and reapplied to the integrated circuit
MFR_CLEAR_PEAKS
The MFR_CLEAR_PEAKS command clears the MFR_*_PEAK data values. A MFR_RESET or RESTORE_USER_ALL
will initiate this command.
This write-only command has no data bytes.
SMBALERT_MASK
The SMBALERT_MASK command can be used to prevent a particular status bit or bits from asserting ALERT as they
are asserted.
Figure 57 shows an example of the Write Word format used to set an ALERT mask, in this case without PEC. The bits
in the mask byte align with bits in the specified status register. For example, if the STATUS_TEMPERATURE command
code is sent in the first data byte, and the mask byte contains 0x40, then a subsequent External Overtemperature Warning
would still set bit 6 of STATUS_TEMPERATURE but not assert ALERT. All other supported STATUS_TEMPERATURE
bits would continue to assert ALERT if set.
Figure 58 shows an example of the Block Write – Block Read Process Call protocol used to read back the present state
of any supported status register, again without PEC.
SMBALERT_MASK cannot be applied to STATUS_BYTE, STATUS_WORD, MFR_COMMON or MFR_PADS. Factory default
masking for applicable status registers is shown below. Providing an unsupported command code to SMBALERT_MASK
will generate a CML for Invalid/Unsupported Data.
Figure 57. Example of Setting SMBALERT_MASK
Figure 58. Example of Reading SMBALERT_MASK
P
1
SLAVE
ADDRESS
SMBALERT_MASK
COMMAND CODE
STATUS_x
COMMAND CODE
W A AS
7 8 8 1 8 11 1 11
A AMASK BYTE
4675 F57
SLAVE
ADDRESS
SMBALERT_MASK
COMMAND CODE
BLOCK COUNT
(= 1)
W A AS
7 8 8 1
STATUS_x
COMMAND CODE
8 11 1 11
A A …
Sr
1
BLOCK COUNT
(= 1) A NA P
4675 F58
A
8 81 1 11
MASK BYTE
SLAVE
ADDRESS
7
R
1
LTM4675
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APPENDIX C: PMBUS COMMAND DETAILS
SMBALERT_MASK Default Setting: (Refer Also to Summary of the Status Registers, Figure 59)
STATUS RESISTER ALERT Mask Value MASKED BITS
STATUS_VOUTn0x00 None
STATUS_IOUTn0x00 None
STATUS_TEMPERATUREn0x00 None
STATUS_CML 0x00 None
STATUS_INPUT 0x00 None
STATUS_MFR_SPECIFICn0x11 Bit 4 (internal PLL unlocked), bit 0 (GPIOn pulled low by external device)
STATUS_BYTE
The STATUS_BYTE command returns a one-byte summary of the most critical faults.
STATUS_BYTE Message Contents:
BIT STATUS BIT NAME MEANING
7 BUSY A fault was declared because the LTM4675 was unable to respond.
6 OFF This bit is set if the channel is not providing power to its output, regardless of the reason, including simply not
being enabled.
5 VOUT_OV An output overvoltage fault has occurred.
4 IOUT_OC An output overcurrent fault has occurred.
3 VIN_UV Not supported (LTM4675 returns 0).
2 TEMPERATURE A temperature fault or warning has occurred.
1 CML A communications, memory or logic fault has occurred.
0 NONE OF THE ABOVE A fault Not listed in bits[7:1] has occurred.
This command has one data byte
Any supported fault bit in this command will initiate an ALERT event.
STATUS_WORD
The STATUS_WORD command returns a two-byte summary of the channel’s fault condition. The low byte of the
STATUS_WORD is the same as the STATUS_BYTE command.
STATUS_WORD High Byte Message Contents:
BIT STATUS BIT NAME MEANING
15 VOUT An output voltage fault or warning has occurred.
14 IOUT An output current fault or warning has occurred.
13 INPUT An SVIN input voltage fault or warning has occurred.
12 MFR_SPECIFIC A fault or warning specific to the LTM4675 has occurred.
11 POWER_GOOD# The POWER_GOOD state is false if this bit is set.
10 FANS Not supported (LTM4675 returns 0).
9 OTHER Not supported (LTM4675 returns 0).
8 UNKNOWN Not supported (LTM4675 returns 0).
Any supported fault bit in this command will initiate an ALERT event.
This command has two data bytes.
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APPENDIX C: PMBUS COMMAND DETAILS
STATUS_VOUT
The STATUS_VOUT command returns one byte of VOUT status information.
STATUS_VOUT Message Contents:
BIT MEANING
7 VOUT overvoltage fault.
6 VOUT overvoltage warning.
5 VOUT undervoltage warning.
4 VOUT undervoltage fault.
3 VOUT_MAX warning.
2 TON_MAX fault.
1 TOFF_MAX warning.
0 Not supported by the LTM4675 (returns 0).
ALERT can be asserted if any of bits[7:1] are set. These may be cleared by writing a 1 to their bit position in STATUS_VOUT, in lieu of a CLEAR_FAULTS
command.
This command has one data byte.
STATUS_IOUT
The STATUS_IOUT command returns one byte of IOUT status information.
STATUS_IOUT Message Contents:
BIT MEANING
7 IOUT overcurrent fault.
6 Not supported (LTM4675 returns 0).
5 IOUT overcurrent warning.
4:0 Not supported (LTM4675 returns 0).
ALERT can be asserted if any supported bits are set. Any supported bit may be cleared by writing a 1 to that bit position in STATUS_IOUT, in lieu of a
CLEAR_FAULTS command.
This command has one data byte.
STATUS_INPUT
The STATUS_INPUT command returns one byte of VIN (SVIN) status information.
STATUS_INPUT Message Contents:
BIT MEANING
7 SVIN overvoltage fault.
6 Not supported (LTM4675 returns 0).
5 SVIN undervoltage warning.
4 Not supported (LTM4675 returns 0).
3 Unit off for insufficient SVIN voltage.
2 Not supported (LTM4675 returns 0).
1 Input over current warning.
0 Not supported (LTM4675 returns 0)
ALERT can be asserted if bit 7 is set. Bit 7 may be cleared by writing it to a 1, in lieu of a CLEAR_FAULTS command.
This command has one data byte.
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APPENDIX C: PMBUS COMMAND DETAILS
STATUS_TEMPERATURE
The STATUS_TEMPERATURE command returns one byte of sensed power stage temperature status information.
STATUS_TEMPERATURE Message Contents:
BIT MEANING
7 External overtemperature fault.
6 External overtemperature warning.
5 Not supported (LTM4675 returns 0).
4 External undertemperature fault.
3:0 Not supported (LTM4675 returns 0).
ALERT can be asserted if any supported bits are set. Any supported bit may be cleared by writing a 1 to that bit position in STATUS_TEMPERATURE, in
lieu of a CLEAR_FAULTS command.
This command has one data byte.
STATUS_CML
The STATUS_CML command returns one byte of status information on received commands, internal memory and logic.
STATUS_CML Message Contents:
BIT MEANING
7 Invalid or unsupported command received.
6 Invalid or unsupported data received.
5 Packet error check failed.
4 Memory fault detected.
3 Processor fault detected.
2 Reserved (LTM4675 returns 0).
1 Other communication fault.
0 Other memory or logic fault.
ALERT can be asserted if any supported bits are set. Any supported bit may be cleared by writing a 1 to that bit position in STATUS_CML, in lieu of a
CLEAR_FAULTS command.
This command has one data byte.
STATUS_MFR_SPECIFIC
The STATUS_MFR_SPECIFIC commands returns one byte with the manufacturer specific status information.
Each channel has a copy of the same information. Only bit 0 is page specific.
The format for this byte is:
BIT MEANING
7 Internal Temperature Fault Limit Exceeded.
6 Internal Temperature Warn Limit Exceeded.
5 NVM CRC Fault.
4 PLL is Unlocked
3 Fault Log Present
2 VDD33 UV or OV Fault
0GPIO Pin Asserted Low by External Device (paged)
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APPENDIX C: PMBUS COMMAND DETAILS
If any of these bits are set, the MFR bit in the STATUS_WORD will be set.
The user is permitted to write a 1 to any bit in this command to clear a specific fault. This permits the user to clear
status by means other than using the CLEAR_FAULTS command. Exception: The fault log present bit can only be
cleared by issuing the MFR_FAULT_LOG_CLEAR command.
Any supported fault bit in this command will initiate an ALERT event.
This command has one data byte.
MFR_PADS
This command provides the user a means of directly reading the digital status of the I/O pins of the device. The bit
assignments of this command are as follows:
BIT ASSIGNED DIGITAL PIN
15 VDD33 OV Fault
14 VDD33 UV Fault
13 Reserved
12 Reserved
11 ADC Values Invalid, Occurs During Start-Up
10 SYNC Output Disabled Due to External Clock
9 PowerGood1
8 PowerGood0
7 Device Driving RUN1 Low
6 Device Driving RUN0 Low
5 RUN1
4 RUN0
3 Device Driving GPIO1 Low
2 Device Driving GPIO0 Low
1GPIO1
0GPIO0
A 1 indicates the condition is true.
This read-only command has two data bytes.
MFR_COMMON
The MFR_COMMON command contains bits that are common to all ADI digital power and telemetry products.
BIT MEANING
7 MODULE NOT DRIVING ALERT LOW
6 MODULE NOT BUSY
5 CALCULATIONS NOT PENDING
4 OUTPUT NOT IN TRANSITION
3 NVM Initialized
2 Reserved
1 SHARE_CLK Timeout
0 WP Pin Status
This read-only command has one data byte.
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APPENDIX C: PMBUS COMMAND DETAILS
(PAGED)
MFR_PADS
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
VDD33 0V
VDD33 UV
(reads 0)
(reads 0)
Invalid ADC Result(s)
SYNC Output Disabled Externally
Channel 1 is POWER_GOOD
Channel 0 is POWER_GOOD
LTM4675 Forcing RUN1 Low
LTM4675 Forcing RUN0 Low
RUN1 Pin State
RUN0 Pin State
LTM4675 Forcing GPIO1 Low
LTM4675 Forcing GPIO0 Low
GPIO1 Pin State
GPIO0 Pin State
STATUS_MFR_SPECIFIC
7
6
5
4
3
2
1
0
(PAGED)
4675 F59
STATUS_INPUT
7
6
5
4
3
2
1
0
STATUS_WORD
STATUS_BYTE
7
6
5
4
3
2
1
0
(PAGED)
MFR_COMMON
7
6
5
4
3
2
1
0
Module Not Driving ALERT Low
Module Not Busy
Internal Calculations Not Pending
Output Not In Transition
EEPROM Initialized
(reads 0)
SHARE_CLK_LOW
WP Pin High
MFR_INFO
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
EEPROM ECC Status
Reserved
Reserved
Reserved
Reserved
STATUS_TEMPERATURE
7
6
5
4
3
2
1
0
STATUS_CML
7
6
5
4
3
2
1
0
STATUS_VOUT*
7
6
5
4
3
2
1
0
(PAGED)
STATUS_IOUT
7
6
5
4
3
2
1
0
(PAGED)
MASKABLEDESCRIPTION
General Fault or Warning Event
Dynamic
Status Derived from Other Bits
Yes
No
No
GENERATES ALERT
Yes
No
Not Directly
BIT CLEARABLE
Yes
No
No
VOUT_OV Fault
VOUT_OV Warning
VOUT_UV Warning
VOUT_UV Fault
VOUT_MAX Warning
TON_MAX Fault
TOFF_MAX Warning
(reads 0)
IOUT_OC Fault
(reads 0)
IOUT_OC Warning
(reads 0)
(reads 0)
(reads 0)
(reads 0)
(reads 0)
OT Fault
OT Warning
(reads 0)
UT Fault
(reads 0)
(reads 0)
(reads 0)
(reads 0)
Invalid/Unsupported Command
Invalid/Unsupported Data
Packet Error Check Failed
Memory Fault Detected
Processor Fault Detected
(reads 0)
Other Communication Fault
Other Memory or Logic Fault
Internal Temperature Fault
Internal Temperature Warning
EEPROM CRC Error
Internal PLL Unlocked
Fault Log Present
(reads 0)
VOUT Short Cycled
GPIO Pulled Low By External Device
VIN_OV Fault SVIN
(reads 0)
VIN_UV Warning SVIN
(reads 0)
Unit Off for Insuffcient SVIN Voltage
(reads 0)
IIN_OC Warning
(reads 0)
15
14
13
12
11
10
9
8
VOUT
IOUT
INPUT
MFR_SPECIFIC
POWER_GOOD#
(reads 0)
(reads 0)
(reads 0)
BUSY
OFF
VOUT_OV
IOUT_OC
(reads 0)
TEMPERATURE
CML
NONE OF THE ABOVE
Figure 59. Summary of the Status Registers
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APPENDIX C: PMBUS COMMAND DETAILS
MFR_INFO
The MFR_INFO command contains additional status bits that are LTM4675-specific and may be common to multiple
ADI PSM products.
MFR_INFO Data Contents:
BIT MEANING
15:6 Reserved.
5 EEPROM ECC status.
0: Corrections have been made in the EEPROM user space.
1: No corrections have been made in the EEPROM user space.
4:0 Reserved
EEPROM ECC status is updated after each RESTORE_USER_ALL or RESET command, a power-on reset or an EEPROM
bulk read operation. This read-only command has two data bytes.
TELEMETRY
COMMAND NAME
CMD
CODE DESCRIPTION TYPE PAGED FORMAT UNITS NVM
DEFAULT
VALUE
READ_VIN 0x88 Measured input supply (SVIN) voltage. R Word N L11 V NA
READ_VOUT 0x8B Measured output voltage. R Word Y L16 V NA
READ_IIN 0x89 Calculated input supply current. R Word N L11 A NA
MFR_READ_IIN 0xED Calculated input current per channel. R Word Y L11 A NA
READ_IOUT 0x8C Measured output current. R Word Y L11 A NA
READ_TEMPERATURE_1 0x8D Power stage temperature sensor. This is the value
used for all temperature related processing, including
IOUT_CAL_GAIN.
R Word Y L11 C NA
READ_TEMPERATURE_2 0x8E Control IC die temperature. Does not affect any other
registers.
R Word N L11 C NA
READ_DUTY_CYCLE 0x94 Duty cycle of the top gate control signal. R Word Y L11 % NA
READ_POUT 0x96 Calculated output power. R Word Y L11 W NA
MFR_VOUT_PEAK 0xDD Maximum measured value of READ_VOUT since last
MFR_CLEAR_PEAKS.
R Word Y L16 V NA
MFR_VIN_PEAK 0xDE Maximum measured value of READ_VIN since last
MFR_CLEAR_PEAKS.
R Word N L11 V NA
MFR_TEMPERATURE_1_PEAK 0xDF Maximum measured value of power stage
temperature (READ_TEMPERATURE_1) since last
MFR_CLEAR_PEAKS.
R Word Y L11 C NA
MFR_TEMPERATURE_2_PEAK 0xF4 Maximum measured value of control IC die
temperature (READ_TEMPERATURE_2) since last
MFR_CLEAR_PEAKS.
R Word N L11 C NA
MFR_IOUT_PEAK 0xD7 Report the maximum measured value of READ_IOUT
since last MFR_CLEAR_PEAKS.
R Word Y L11 A NA
MFR_ADC_CONTROL 0xD8 ADC telemetry parameter selected for repeated fast
ADC read back.
R/W
Byte
N Reg 0x00
MFR_ADC_TELEMETRY_
STATUS
0xDA ADC telemetry status indicating which parameter is
most recently converted when the short round robin
ADC loop is enabled
R/W
Byte
N Reg NA
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APPENDIX C: PMBUS COMMAND DETAILS
READ_VIN
The READ_VIN command returns the measured SVIN input voltage, in volts.
This read-only command has two data bytes and is formatted in Linear_5s_11s format.
READ_VOUT
The READ_VOUT command returns the measured output voltage in the same format as set by the VOUT_MODE
command.
This read-only command has two data bytes and is formatted in Linear_16u format.
READ_IIN
The READ_IIN command returns the input current in Amperes. Note: Input current is calculated from READ_IOUT
current and the READ_DUTY_CYCLE value from both outputs plus the MFR_IIN_OFFSET. For accurate values at low
currents the part must be in continuous conduction mode. The greatest source of error if DCR sensing is used, is the
accuracy of the inductor parasitic DC resistance (DCR) at room temperature IOUT_CAL_GAIN.
READ_IIN = MFR_READ_IIN_PAGE0 + MFR_READ_IIN_PAGE1
This read-only command has two data bytes and is formatted in Linear_5s_11s format.
MFR_READ_IIN
The MFR_READ_IIN command is a paged reading of the input current that applies the paged MFR_IIN_OFFSET
parameter. This calculation is similar to READ_IIN except the paged values are used.
MFR_READ_IIN = MFR_IIN_OFFSET + (IOUT • DUTY_CYCLE)
This command has 2 data bytes and is formatted in Linear_5s_11s format.
READ_IOUT
The READ_IOUT command returns the average output current in amperes. The IOUT value is a function of:
a) the differential voltage derived from the power inductor ∆ISNSn
b) the IOUT_CAL_GAIN value
c) the MFR_IOUT_CAL_GAIN_TC value, and
d) READ_TEMPERATURE_1 value
e) The MFR_TEMP_1_GAIN and the MFR_TEMP_1_OFFSET
This read-only command has two data bytes and is formatted in Linear_5s_11s format.
READ_TEMPERATURE_1
The READ_TEMPERATURE_1 command returns the temperature, in degrees Celsius, of the external sense element.
This read-only command has two data bytes and is formatted in Linear_5s_11s format.
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118
Rev. C
For more information www.analog.com
APPENDIX C: PMBUS COMMAND DETAILS
READ_TEMPERATURE_2
The READ_TEMPERATURE_2 command returns the temperature, in degrees Celsius, of the internal sense element.
This read-only command has two data bytes and is formatted in Linear_5s_11s format.
READ_DUTY_CYCLE
The READ_DUTY_CYCLE command returns the duty cycle of controller, in percent.
This read-only command has two data bytes and is formatted in Linear_5s_11s format.
READ_POUT
The READ_POUT command is a paged reading of the DC/DC converter output power in Watts. The POUT is calculated
based on the most recent correlated output voltage and current readings.
This command has 2 data bytes and is formatted in Linear_5s_11s format.
MFR_VOUT_PEAK
The MFR_VOUT_PEAK command reports the highest voltage, in volts, reported by the READ_VOUT measurement.
This command is cleared using the MFR_CLEAR_PEAKS command.
This read-only command has two data bytes and is formatted in Linear_16u format.
MFR_VIN_PEAK
The MFR_VIN_PEAK command reports the highest voltage, in volts, reported by the READ_VIN measurement.
This command is cleared using the MFR_CLEAR_PEAKS command.
This read-only command has two data bytes and is formatted in Linear_5s_11s format.
MFR_TEMPERATURE_1_PEAK
The MFR_TEMPERATURE_1_PEAK command reports the highest temperature, in degrees Celsius, reported by the
READ_TEMPERATURE_1 measurement.
This command is cleared using the MFR_CLEAR_PEAKS command.
This read-only command has two data bytes and is formatted in Linear_5s_11s format.
MFR_TEMPERATURE_2_PEAK
The MFR_TEMPERATURE_2_PEAK command reports the highest temperature, in degrees Celsius, reported by the
READ_TEMPERATURE_2 measurement.
This command is cleared using the MFR_CLEAR_PEAKS command.
This read-only command has two data bytes and is formatted in Linear_5s_11s format.
LTM4675
119
Rev. C
For more information www.analog.com
APPENDIX C: PMBUS COMMAND DETAILS
MFR_IOUT_PEAK
The MFR_IOUT_PEAK command reports the highest current, in amperes, reported by the READ_IOUT measurement.
This command is cleared using the MFR_CLEAR_PEAKS command.
This read-only command has two data bytes and is formatted in Linear_5s_11s format.
MFR_ADC_CONTROL
The MFR_ADC_CONTROL command determines the ADC read back selection. A default value of 0 in the command runs
the standard telemetry loop with all parameters updated in a round robin fashion with a typical latency of 90ms. The
user can command a non-zero value to monitored a single parameter with an approximate update rate of 8ms. This
command has a latency of up to two ADC conversions or approximately 16ms (power stage temperature conversions
may have a latency of up to three ADC conversion or approximately 24ms). Selecting a value of 0x0D will enable a
short round robin loop. This commanded value runs a short telemetry loop only selecting VOUT0, IOUT0, VOUT1 and
IOUT1 in a round robin manner. The round robin typical latency is 27ms. It is recommended the part remain in standard
telemetry mode except for special cases where fast ADC updates of a single parameter is required. The part should be
commanded to monitor the desired parameter for a limited period of time (say, less than a second) then set the com-
mand back to standard round robin mode. If this command is set to any value except standard round robin telemetry
(0) all warnings and faults associated with telemetry other than the selected parameter are effectively disabled and
voltage servoing is disabled. When round robin is reasserted, all warnings and faults and servo mode are re-enabled.
COMMANDED VALUE TELEMETRY SELECTED
0x00 Standard ADC Round Robin Telemetry
0x01 SVIN
0x02 Reserved
0x03 Reserved
0x04 Internal IC Temperature
0x05 Channel 0 VOUT
0x06 Channel 0 IOUT
0x07 Reserved
0x08 Channel 0 Power Stage-Sensed Temperature
0x09 Channel 1 VOUT
0x0A Channel 1 IOUT
0x0B Reserved
0x0C Channel 1 Power Stage or TSNS1a-Sensed Temperature
0x0D ADC Short Round Robin
0x0E-0xFF Reserved
If a reserved command value is entered, the part will default to Internal IC Temperature and issue a CML[6] fault.
CML[6] faults will continue to be issued by the LTM4675 until a valid command value is entered.
This read/write command has 1 data byte and is formatted in register format.
LTM4675
120
Rev. C
For more information www.analog.com
APPENDIX C: PMBUS COMMAND DETAILS
MFR_ADC_TELEMETRY_STATUS
The MFR_ADC_TELEMETRY_STATUS command provides the user the means to determine the most recent ADC
conversion when the MFR_ADC_CONTROL short round robin loop is enabled using command 0xD8 value 0x0D. The
bit assignments of this command are as follows:
BIT TELEMETRY DATA AVAILABLE
7 Reserved returns 0
6 Reserved returns 0
5 Reserved returns 0
4 Reserved returns 0
3 Channel 1 IOUT readback (IOUT1)
2 Channel 1 VOUT readback (VOUT1)
1 Channel 0 IOUT readback (IOUT0)
0 Channel 0 VOUT readback (VOUT0)
Write to MFR_ADC_TELEMETRY_STATUS with data bits set to 1 clear the respective bits.
This read/write command has 1 data byte and is formatted in register format.
NVM (EEPROM) MEMORY COMMANDS
Store/Restore
COMMAND NAME
CMD
CODE DESCRIPTION TYPE PAGED FORMAT UNITS NVM
DEFAULT
VALUE
STORE_USER_ALL 0x15 Store user operating memory to EEPROM. Send Byte N NA
RESTORE_USER_ALL 0x16 Restore user operating memory from EEPROM.
Identical to MFR_RESET.
Send Byte N NA
MFR_COMPARE_USER_ALL 0xF0 Compares current command contents with NVM. Send Byte N NA
STORE_USER_ALL
The STORE_USER_ALL command instructs the PMBus device to copy the non-volatile user contents of the Operating
Memory to the matching locations in the non-volatile User NVM memory (EEPROM).
The 10 year data retention can only be guaranteed when STORE_USER_ALL is executed at 0°C ≤ TJ ≤ 85°C. Executing
this command at junction temperatures above 85°C or below 0°C is not recommended because data retention cannot
be guaranteed for that condition. If the die temperature exceeds 130°C, the STORE_USER_ALL command is disabled.
The command is re-enabled when the IC temperature drops below 125°C.
Communication with the LTM4675 and programming of the EEPROM can be initiated when VDD33 is available and
SVIN is not applied. To enable the part in this state, using global address 0x5B write 0x2B followed by 0xC4. The part
can now be communicated with, and the project file updated. To write the updated project file to the EEPROM issue a
STORE_USER_ALL command. When SVIN is applied, a MFR_RESET or RESTORE_USER_ALL must be issued to allow
the PWM to be enabled and valid ADCs to be read.
This write-only command has no data bytes.
LTM4675
121
Rev. C
For more information www.analog.com
APPENDIX C: PMBUS COMMAND DETAILS
RESTORE_USER_ALL
The RESTORE_USER_ALL command provides an alternate means by which the user can perform a MFR_RESET of
the LTM4675.
This write-only command has no data bytes.
MFR_COMPARE_USER_ALL
The MFR_COMPARE_USER_ALL command instructs the PMBus device to compare current command contents with
what is stored in non-volatile memory. If the compare operation detects differences, a CML bit 0 fault will be generated.
MFR_COMPARE_USER_ALL commands are disabled if the die exceeds 130°C and are not re-enabled until the die
temperature drops below 125°C.
This write-only command has no data bytes.
Fault Log Operation
A conceptual diagram of the fault log is shown in Figure 60. The fault log provides telemetry recording capability to
the LTM4675. During normal operation the contents of the status registers, the output voltage readings, temperature
readings as well as peak values of these quantities are stored in a continuously updated buffer in RAM. The operation
is similar to a strip chart recorder. When a fault occurs, the contents are written into EEPROM for nonvolatile storage.
The EEPROM fault log is then locked. The part can be powered down with the fault log available for reading at a later
time. As a consequence of adding ECC, the area in the EEPROM available for fault log is reduced. When reading the
fault log from RAM all 6 events of cyclical data remain. However, when the fault log is read from EEPROM (after a
reset), the last 2 events are lost. The read length of 147 bytes remains the same, but the fifth and sixth events are a
repeat of the fourth event.
4675 F60
TIME OF FAULT
TRANSFER TO
EEPROM AND
LOCK
AFTER FAULT
READ FROM
EEPROM AND
LOCK BUFFER
ADC READINGS
CONTINUOUSLY
FILL BUFFER
RAM BYTES EEPROM BYTES
8
•
•
•
•
•
•
Figure 60. Fault Log Conceptual Diagram
LTM4675
122
Rev. C
For more information www.analog.com
APPENDIX C: PMBUS COMMAND DETAILS
Table 30. Fault Logging. This table outlines the format of the block data from a read block data of the MFR_FAULT_LOG command.
Data Format Definitions LIN 11 = PMBus = Rev 1.2, Part 2, section 7.1
LIN 16 = PMBus Rev 1.2, Part 2, section 8. Mantissa portion only
BYTE = 8 bits interpreted per definition of this command
DATA BITS
DATA
FORMAT BYTE NUM BLOCK READ COMMAND
Block Length BYTE 147 The MFR_FAULT_LOG command is a fixed length of 147 bytes
The block length will be zero if a data log event has not been captured
HEADER INFORMATION
Fault Log Preface [7:0] ASC 0 Returns LTxx beginning at byte 0 if a partial or complete fault log exists.
Word xx is a factory identifier that may vary part to part.
[7:0] 1
[15:8] Reg 2
[7:0] 3
Fault Source [7:0] Reg 4 Refer to Table 31.
MFR_REAL_TIME [7:0] Reg 5 48 bit share-clock counter value when fault occurred (200µs resolution).
[15:8] 6
[23:16] 7
[31:24] 8
[39:32] 9
[47:40] 10
MFR_VOUT_PEAK (PAGE 0) [15:8] L16 11 Peak READ_VOUT on Channel 0 since last power-on or CLEAR_PEAKS
command.
[7:0] 12
MFR_VOUT_PEAK (PAGE 1) [15:8] L16 13 Peak READ_VOUT on Channel 1 since last power-on or CLEAR_PEAKS
command.
[7:0] 14
MFR_IOUT_PEAK (PAGE 0) [15:8] L11 15 Peak READ_IOUT on Channel 0 since last power-on or CLEAR_PEAKS
command.
[7:0] 16
MFR_IOUT_PEAK (PAGE 1) [15:8] L11 17 Peak READ_IOUT on Channel 1 since last power-on or CLEAR_PEAKS
command.
[7:0] 18
MFR_VIN_PEAK [15:8] L11 19 Peak READ_VIN since last power-on or CLEAR_PEAKS command.
[7:0] 20
READ_TEMPERATURE1 (PAGE 0) [15:8] L11 21 Channel 0 power stage during last event.
[7:0] 22
READ_TEMPERATURE1 (PAGE 1) [15:8] L11 23 Channel 1 power stage or TSNS1a-sensed temperature 1 during last
event.
[7:0] 24
READ_TEMPERATURE2 [15:8] L11 25 Internal temperature sensor during last event.
[7:0] 26
CYCLICAL DATA
EVENT n
(Data at Which Fault Occurred; Most Recent Data)
Event “n” represents one complete cycle of ADC reads through the MUX
at time of fault. Example: If the fault occurs when the ADC is processing
step 15, it will continue to take readings through step 25 and then store
the header and all 6 event pages to EEPROM
LTM4675
123
Rev. C
For more information www.analog.com
APPENDIX C: PMBUS COMMAND DETAILS
Table 30. Fault Logging. This table outlines the format of the block data from a read block data of the MFR_FAULT_LOG command.
READ_VOUT (PAGE 0) [15:8] LIN 16 27
[7:0] LIN 16 28
READ_VOUT (PAGE 1) [15:8] LIN 16 29
[7:0] LIN 16 30
READ_IOUT (PAGE 0) [15:8] LIN 11 31
[7:0] LIN 11 32
READ_IOUT (PAGE 1) [15:8] LIN 11 33
[7:0] LIN 11 34
READ_VIN [15:8] LIN 11 35
[7:0] LIN 11 36
READ_IIN [15:8] LIN 11 37
[7:0] LIN 11 38
STATUS_VOUT (PAGE 0) BYTE 39
STATUS_VOUT (PAGE 1) BYTE 40
STATUS_WORD (PAGE 0) [15:8] WORD 41
[7:0] WORD 42
STATUS_WORD (PAGE 1) [15:8] WORD 43
[7:0] WORD 44
STATUS_MFR_SPECIFIC (PAGE 0) BYTE 45
STATUS_MFR_SPECIFIC (PAGE 1) BYTE 46
EVENT n-1
(data measured before fault was detected)
READ_VOUT (PAGE 0) [15:8] LIN 16 47
[7:0] LIN 16 48
READ_VOUT (PAGE 1) [15:8] LIN 16 49
[7:0] LIN 16 50
READ_IOUT (PAGE 0) [15:8] LIN 11 51
[7:0] LIN 11 52
READ_IOUT (PAGE 1) [15:8] LIN 11 53
[7:0] LIN 11 54
READ_VIN [15:8] LIN 11 55
[7:0] LIN 11 56
READ_IIN [15:8] LIN 11 57
[7:0] LIN 11 58
STATUS_VOUT (PAGE 0) BYTE 59
STATUS_VOUT (PAGE 1) BYTE 60
STATUS_WORD (PAGE 0) [15:8] WORD 61
[7:0] WORD 62
STATUS_WORD (PAGE 1) [15:8] WORD 63
[7:0] WORD 64
STATUS_MFR_SPECIFIC (PAGE 0) BYTE 65
STATUS_MFR_SPECIFIC (PAGE 1) BYTE 66
LTM4675
124
Rev. C
For more information www.analog.com
APPENDIX C: PMBUS COMMAND DETAILS
Table 30. Fault Logging. This table outlines the format of the block data from a read block data of the MFR_FAULT_LOG command.
*
*
*
EVENT n-5
(Oldest Recorded Data)
READ_VOUT (PAGE 0) [15:8] LIN 16 127
[7:0] LIN 16 128
READ_VOUT (PAGE 1) [15:8] LIN 16 129
[7:0] LIN 16 130
READ_IOUT (PAGE 0) [15:8] LIN 11 131
[7:0] LIN 11 132
READ_IOUT (PAGE 1) [15:8] LIN 11 133
[7:0] LIN 11 134
READ_VIN [15:8] LIN 11 135
[7:0] LIN 11 136
READ_IIN [15:8] LIN 11 137
[7:0] LIN 11 138
STATUS_VOUT (PAGE 0) BYTE 139
STATUS_VOUT (PAGE 1) BYTE 140
STATUS_WORD (PAGE 0) [15:8] WORD 141
[7:0] WORD 142
STATUS_WORD (PAGE 1) [15:8] WORD 143
[7:0] WORD 144
STATUS_MFR_SPECIFIC (PAGE 0) BYTE 145
STATUS_MFR_SPECIFIC (PAGE 1) BYTE 146
LTM4675
125
Rev. C
For more information www.analog.com
Table 31. Explanation of Position_Fault Values
POSITION_FAULT VALUE SOURCE OF FAULT LOG
0xFF MFR_FAULT_LOG_STORE
0x00 TON_MAX_FAULT Channel 0
0x01 VOUT_OV_FAULT Channel 0
0x02 VOUT_UV_FAULT Channel 0
0x03 IOUT_OC_FAULT Channel 0
0x05 OT_FAULT Channel 0
0x06 UT_FAULT Channel 0
0x07 VIN_OV_FAULT Channel 0
0x0A MFR_OT_FAULT Channel 0
0x10 TON_MAX_FAULT Channel 1
0x11 VOUT_OV_FAULT Channel 1
0x12 VOUT_UV_FAULT Channel 1
0x13 IOUT_OC_FAULT Channel 1
0x15 OT_FAULT Channel 1
0x16 UT_FAULT Channel 1
0x17 VIN_OV_FAULT Channel 1
0x1A MFR_OT_FAULT Channel 1
APPENDIX C: PMBUS COMMAND DETAILS
Fault Logging
COMMAND NAME
CMD
CODE DESCRIPTION TYPE PAGED
DATA
FORMAT UNITS NVM
DEFAULT
VALUE
MFR_FAULT_LOG 0xEE Fault log data bytes. This sequentially retrieved data is
used to assemble a complete fault log.
R Block N CF Y NA
MFR_FAULT_LOG_ STORE 0xEA Command a transfer of the fault log from RAM to
EEPROM.
Send Byte N NA
MFR_FAULT_LOG_CLEAR 0xEC Initialize the EEPROM block reserved for fault logging. Send Byte N NA
MFR_FAULT_LOG
The MFR_FAULT_LOG command allows the user to read the contents of the FAULT_LOG after the first fault occurrence
since the last MFR_FAULT_LOG_CLEAR command was last written. The contents of this command are stored in non-volatile
memory, and are cleared by the MFR_FAULT_LOG_CLEAR command. The length and content of this command are listed
in Table 30. If the user accesses the MFR_FAULT_LOG command and no fault log is present, the command will return a
data length of 0. If a fault log is present, the MFR_FAULT_LOG will always return a block of data 147 bytes long. If a fault
occurs within the first second of applying power, some of the earlier pages in the fault log may not contain valid data.
NOTE: The approximate transfer time for this command is 3.4ms using a 400kHz clock.
This read-only command is in block format.
LTM4675
126
Rev. C
For more information www.analog.com
APPENDIX C: PMBUS COMMAND DETAILS
MFR_FAULT_LOG_STORE
The MFR_FAULT_LOG_STORE command forces the fault log operation to be written to EEPROM just as if a fault
event occurred. This command will generate a MFR_SPECIFIC fault if the “Enable Fault Logging” bit is set in the MFR_
CONFIG_ALL command.
If the die temperature exceeds 130°C, the MFR_FAULT_LOG_STORE command is disabled until the IC temperature
drops below 125°C.
Up-Time Counter is in the Fault Log header. The counter is the time since the last module reset (MFR_RESET,
RESTORE_USER_ALL, or SVIN - power cycle) in 200µs increments. This is a 48-bit binary counter.
This write-only command has no data bytes.
MFR_FAULT_LOG_CLEAR
The MFR_FAULT_LOG_CLEAR command will erase the fault log file stored values. It will also clear bit 3 in the
STATUS_MFR_SPECIFIC command. After a clear is issued, the status can take up to 8ms to clear.
This write-only command is send bytes.
Block Memory Write/Read
COMMAND NAME CMD CODE DESCRIPTION TYPE PAGED
DATA
FORMAT UNITS NVM
DEFAULT
VALUE
MFR_EE_UNLOCK 0xBD Unlock user EEPROM for access by MFR_EE_ERASE and
MFR_EE_DATA commands.
R/W Byte N Reg NA
MFR_EE_ERASE 0xBE Initialize user EEPROM for bulk programming by MFR_EE_
DATA.
R/W Byte N Reg NA
MFR_EE_DATA 0xBF Data transferred to and from EEPROM using sequential
PMBus word reads or writes. Supports bulk programming.
R/W
Word
N Reg NA
All the (EEPROM) commands are disabled if the die temperature exceeds 130°C. (EEPROM) commands are re-enabled
when the die temperature drops below 125°C.
MFR_EE_xxxx
MFR_EE_XXXX commands are used to facilitate bulk programming of the internal EEPROM. Contact the factory for
more details.
LTM4675
127
Rev. C
For more information www.analog.com
PACKAGE DESCRIPTION
PACKAGE ROW AND COLUMN LABELING MAY VARY
AMONG µModule PRODUCTS. REVIEW EACH PACKAGE
LAYOUT CAREFULLY.
Table 32. LTM4675 BGA Pinout
PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION
A1 VOUT0 B1 VOUT0 C1 VOUT0 D1 VOUT0 E1 GND F1 GND
A2 GND B2 GND C2 GND D2 GND E2 GPIO0F2 GPIO1
A3 GND B3 GND C3 TSNS0D3 TSNS0E3 ALERT F3 RUN0
A4 GND B4 GND C4 GND D4 SDA E4 SCL F4 RUN1
A5 GND B5 GND C5 GND D5 GND E5 SYNC F5 SGND
A6 GND B6 GND C6 GND D6 COMP0b E6 COMP0a F6 SGND
A7 GND B7 GND C7 GND D7 VOSNS0+ E7 VOSNS0- F7 INTVCC
A8 GND B8 SW0C8 GND D8 VORB0+ E8 VORB0- F8 GND
A9 VIN0 B9 VIN0 C9 VIN0 D9 VIN0 E9 GND F9 SVIN
PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION
G1 GND H1 GND J1 VOUT1 K1 VOUT1 L1 VOUT1 M1 VOUT1
G2 ASEL H2 FSWPHCFG J2 GND K2 GND L2 GND M2 GND
G3 VOUT0CFG H3 VTRIM0CFG J3 TSNS1a K3 TSNS1b L3 GND M3 GND
G4 VOUT1CFG H4 VTRIM1CFG J4 VDD25 K4 WP L4 GND M4 GND
G5 SGND H5 SHARE_CLK J5 VDD33 K5 GND L5 GND M5 GND
G6 SGND H6 COMP1a J6 COMP1b K6 GND L6 GND M6 GND
G7 INTVCC H7 VOSNS1 J7 VORB1 K7 GND L7 GND M7 GND
G8 GND H8 GND J8 GND K8 GND L8 SW1M8 GND
G9 GND H9 GND J9 VIN1 K9 VIN1 L9 VIN1 M9 VIN1
LTM4675
128
Rev. C
For more information www.analog.com
PACKAGE DESCRIPTION
1234567
TOP VIEW
8 9
M
L
K
J
H
G
F
E
D
C
B
A
VOUT0
VOUT0
FSWPHCFG
GPIO0
GPIO1
VIN0
VIN0
GND
GND
GND
SW0
GND
TSNS0
TSNS0
RUN0
ALERT
GND COMP0b VOSNS0+
VORB0–
SVIN
VORB0+
VOSNS0–
COMP0a
SYNC
SDA
SCL
RUN1
SGND INTVCC
GND GND
GND ASEL VOUT0CFG
VTRIM0CFG VTRIM1CFG SHARE_CLK COMP1a VOSNS1
VOUT1CFG
GNDGND
GND
VOUT1
TSNS1a
TSNS1b WP
SW1
VDD25 VDD33 COMP1b VORB1
VOUT1 VIN1
VIN1
LTM4675
130
Rev. C
For more information www.analog.com
PACKAGE DESCRIPTION
BGA Package
108-Lead (16mm × 11.9mm × 3.51mm)
(Reference LTC DWG # 05-08-1931 Rev B)
PACKAGE TOP VIEW
4
PIN “A1”
CORNER
X
Y
aaa Z
aaa Z
PACKAGE BOTTOM VIEW
3
SEE NOTES
D
E
b
e
e
b
F
G
DETAIL A
PIN 1
987654321
A
B
C
D
E
F
G
H
K
J
L
M
SUGGESTED PCB LAYOUT
TOP VIEW
0.000
0.0000
0.630 ±0.025 Ø 108x
0.6350
0.6350
1.9050
1.9050
3.1750
3.1750
4.4450
4.4450
5.7150
5.7150
6.9850
5.080
5.080
3.810
3.810
2.540
2.540
1.270
1.270
6.9850
DETAIL A
Øb (108 PLACES)
A
DETAIL B
PACKAGE SIDE VIEW
MX YZddd
MZeee
A2
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994
2. ALL DIMENSIONS ARE IN MILLIMETERS
BALL DESIGNATION PER JESD MS-028 AND JEP95
4
3
DETAILS OF PIN #1 IDENTIFIER ARE OPTIONAL,
BUT MUST BE LOCATED WITHIN THE ZONE INDICATED.
THE PIN #1 IDENTIFIER MAY BE EITHER A MOLD OR
MARKED FEATURE
BGA 108 0517 REV B
TRAY PIN 1
BEVEL PACKAGE IN TRAY LOADING ORIENTATION
COMPONENT
PIN “A1”
LTMXXXXXX
µModule
6
SEE NOTES
SYMBOL
A
A1
A2
b
b1
D
E
e
F
G
H1
H2
aaa
bbb
ccc
ddd
eee
MIN
3.31
0.50
2.81
0.60
0.60
0.36
2.45
NOM
3.51
0.60
2.91
0.75
0.63
16.00
11.90
1.27
13.97
10.16
0.41
2.50
MAX
3.71
0.70
3.01
0.90
0.66
0.46
2.55
0.15
0.10
0.20
0.30
0.15
TOTAL NUMBER OF BALLS: 108
DIMENSIONS
NOTES
BALL HT
BALL DIMENSION
PAD DIMENSION
SUBSTRATE THK
MOLD CAP HT
Z
DETAIL B
SUBSTRATE
A1
ccc Z
Z
// bbb Z
H2
H1
b1
MOLD
CAP
5. PRIMARY DATUM -Z- IS SEATING PLANE
6 PACKAGE ROW AND COLUMN LABELING MAY VARY
AMONG µModule PRODUCTS. REVIEW EACH PACKAGE
LAYOUT CAREFULLY
!
LTM4675
131
Rev. C
For more information www.analog.com
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog
Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications
subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
REVISION HISTORY
REV DATE DESCRIPTION PAGE NUMBER
A 10/16 Added LTM4677 to Features.
Added explicit guidance in Pin Descriptions on RCONFIGs for parallel-VOUT applications.
Removed erroneous mention of ISENSE Pins.
Called out ASEL Pin.
Table 4: Switching Frequency: from External to Sync Slave.
Table 5: Included term "MFR_ADDRESS" In table title.
Table 8: Frequency Command from 0x0000 to N/A.
Table 18: Corrected typo in heat sink manufacturer part number.
Corrected typo in MFR_SPECIAL_ID prefix, 0x47A.
1
15
30 and 117
33
46
47
51
65
109
B 06/17 Added "with ECC”.
Faster turn-on time from 70ms to 40ms tSTART.
Changed update rate from 100ms to 90ms.
1
1, 4
7, 8
C 03/20 Added Application Information
Changed RVSENSO+ to RVOSNSO+
Changed VVSENSO+ to VVOSNSO+
Changed VVSENSO– to VVOSNSO–
Changed VVSENS1 to VVOSNS1
Changed MFR_PWM_MODEn[1:0]=10b to MFR_PWM_MODEn[0]=1b
Corrected User-Editable bits [7:4] to [6:4]
Changed RCFG to RASEL
Changed MFR_RETRY_DELAY 10µs increments to 1mS
2
5
6
7
22
47
99
LTM4675
132
Rev. C
For more information www.analog.com
ANALOG DEVICES, INC. 2015-2020
03/20
www.analog.com
RELATED PARTS
TYPICAL APPLICATION
VOUT1, 1.8V
ADJUSTABLE
UP TO 9A
CINH
22µF
×3
CINL
220µF
10k
×9
VIN
5.75V TO 17V
PWM CLOCK SYNCH.
TIME BASE SYNCH.
• SLAVE ADDRESS = 1001111_R/W (0X4F)
• SWITCHING FREQUENCY: 500kHz
• NO GUI CONFIGURATION AND
NO PART SPECIFIC PROGRAMMING REQUIRED
IN MULTI-MODULE SYSTEMS, CONFIGURING
RAIL_ADDRESS IS RECOMMENDED
COUT0
100µF
×4
COUT1
100µF
×4
VOUT0, 1.0V
ADJUSTABLE
UP TO 9A
VIN0
VIN1
SVIN
VDD33
LOAD0
SCL
SDA
ALERT
RUN0
RUN1
GPIO0
GPIO1
SYNC
SHARE_CLK
ASEL
FSWPHCFG
VOUT0CFG
VTRIM0CFG
VOUT1CFG
VTRIM1CFG
INTVCC
VDD25
SW0
SW1
COMP0a
COMP0b
COMP1a
COMP1b
GND
WP
6.34k
1%
±50ppm/°C
LTM4675
4676A F61
+
SMBus INTERFACE WITH
PMBus COMMAND SET
ON/OFF CONTROL, FAULT
MANAGEMENT, POWER
SEQUENCING
LOAD1
VOUT0
TSNS0
VORB0+
VOSNS0+
VOSNS0–
VORB0–
VORB1
VOUT1
TSNS1a
TSNS1b
VOSNS1
SGND
PART NUMBER DESCRIPTION COMMENTS
LTM4650 Dual 25A or Single 50A Step-Down µModule Regulator 4.5V ≤ VIN ≤ 15V, 0.6V ≤ VOUT ≤ 1.8V, 16mm × 16mm × 5.01mm BGA
LTM4677 Dual 18A or Single 36A Step-Down µModule Regulator
with Digital Power System Management
4.5V ≤ VIN ≤ 16V, 0.6V ≤ VOUT ≤ 1.8V, 16mm × 16mm × 5.01mm BGA
LTM4676A Dual 13A or Single 26A Step-Down µModule Regulator
with Digital Power System Management
4.5V ≤ VIN ≤ 17V, 0.5V ≤ VOUT ≤ 5.5V, 16mm × 16mm × 5.01mm BGA
LTC3887/LTC3883 Dual and Single Output DC/DC Controllers with Power
System Management
0.5% TUE 16-Bit ADC, Voltage/Current/Temperature Monitoring and
Supervision
LTC2977/LTC2974 8- and 4-Channel PMBus Power System Managers 0.25% TUE 16-Bit ADC, Voltage/Temperature Monitoring and Supervision
Licensed under U.S. Patent 7000125 and other related patents worldwide. TUE is total unadjusted error.
Figure 61. 9A, 1V and 9A, 1.8V Output DC/DC µModule Regulator with Serial Interface
DESIGN RESOURCES
SUBJECT DESCRIPTION
µModule Design and Manufacturing Resources Design:
• Selector Guides
• Demo Boards and Gerber Files
• Free Simulation Tools
Manufacturing:
• Quick Start Guide
• PCB Design, Assembly and Manufacturing Guidelines
• Package and Board Level Reliability
µModule Regulator Products Search 1. Sort table of products by parameters and download the result as a spread sheet.
2. Search using the Quick Power Search parametric table.
Digital Power System Management Analog Devices’ family of digital power supply management ICs are highly integrated solutions that
offer essential functions, including power supply monitoring, supervision, margining and sequencing,
and feature EEPROM for storing user configurations and fault logging.
