CY7C10612DV33
16-Mbit (1 M × 16) Static RAM
Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600
Document Number: 001-49315 Rev. *C Revised October 18, 2011
16-Mbit (1 M × 16) Static RAM
Features
■High speed
❐tAA = 10 ns
■Low active power
❐ICC = 175 mA at 100 MHz
■Low CMOS standby power
❐ISB2 = 25 mA
■Operating voltages of 3.3 ± 0.3 V
■2.0 V data retention
■Automatic Power-down when deselected
■TTL compatible inputs and outputs
■Easy memory expansion with CE and OE features
■Available in Pb-free 54-pin TSOP II package
Functional Description
The CY7C10612DV33 is a high performance CMOS Static RAM
organized as 1,048,576 words by 16 bits.
To write to the device, take Chip Enables (CE) and Write Enable
(WE) input LOW. If Byte Low Enable (BLE) is LOW, then data
from I/O pins (I/O0 through I/O7), is written into the location
specified on the address pins (A0 through A19). If Byte High
Enable (BHE) is LOW, then data from I/O pins (I/O8 through
I/O15) is written into the location specified on the address pins
(A0 through A19).
To read from the device, take Chip Enables (CE) and Output
Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If
Byte Low Enable (BLE) is LOW, then data from the memory
location specified by the address pins appears on I/O0 to I/O7. If
Byte High Enable (BHE) is LOW, then data from memory
appears on I/O8 to I/O15. See Truth Table on page 10 for a
complete description of Read and Write modes.
The input or output pins (I/O0 through I/O15) are placed in a high
impedance state when the device is deselected (CE HIGH), the
outputs are disabled (OE HIGH), the BHE and BLE are disabled
(BHE, BLE HIGH), or during a write operation (CE LOW and WE
LOW).
The CY7C10612DV33 is available in a 54-pin TSOP II package
with center power and ground (revolutionary) pinout.
15
16
A1
A2
A3
A4
A5
A6
A7
A8
COLUMN
DECODER
ROW DECODER
SENSE AMPS
INPUT BUFFER
1M x 16
ARRAY
A0
A12
A14
A13
A
A
A17
A18
A10
A11
I/O0 – I/O7
OE
I/O8 – I/O15
CE
WE
BLE
BHE
A9
A19
Logic Block Diagram
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CY7C10612DV33
Document Number: 001-49315 Rev. *C Page 2 of 14
Contents
Selection Guide ................................................................3
Pin Configuration .............................................................3
Maximum Ratings .............................................................4
Operating Range ............................................................... 4
DC Electrical Characteristics ..........................................4
Capacitance ......................................................................4
Thermal Resistance ..........................................................4
AC Test Loads and Waveforms .......................................5
Data Retention Characteristics ....................................... 5
Data Retention Waveform ................................................ 5
AC Switching Characteristics .........................................6
Switching Waveforms ...................................................... 7
Truth Table ...................................................................... 10
Ordering Information ...................................................... 10
Ordering Code Definitions ......................................... 10
Package Diagrams .......................................................... 11
Acronyms ........................................................................ 12
Document Conventions ................................................. 12
Units of Measure ....................................................... 12
Document History Page ................................................. 13
Sales, Solutions, and Legal Information ...................... 14
Worldwide Sales and Design Support ....................... 14
Products .................................................................... 14
PSoC Solutions ......................................................... 14
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Document Number: 001-49315 Rev. *C Page 3 of 14
Selection Guide
Description -10 Unit
Maximum Access Time 10 ns
Maximum Operating Current 175 mA
Maximum CMOS Standby Current 25 mA
Pin Configuration
Figure 1. 54-pin TSOP II (Top View) [1]
1
2
3
4
5
6
7
8
9
11
14
31
32
36
35
34
33
37
40
39
38
12
13
41
44
43
42
16
15
29
30
I/O
11
18
17
20
19
23
28
25
24
22
21
27
26
V
SS
I/O
10
I/O
12
V
CC
I/O
13
I/O
14
V
SS
A
16
A
17
A
11
A
12
A
13
A
14
I/O
0
A
15
I/O
7
I/O
9
V
CC
I/O
8
I/O
15
A
19
A
4
A
3
A
2
A
1
CE
V
CC
WE
NC BLE
NC
V
SS
OE
A
8
A
7
A
6
A
5
A
0
NC
A
9
BHE
A
10
10
A
18
46
45
47
50
49
48
51
54
53
52
I/O
2
I/O
1
I/O
3
V
SS
V
CC
V
SS
I/O
6
I/O
5
V
CC
I/O
4
Note
1. NC pins are not connected on the die.
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Document Number: 001-49315 Rev. *C Page 4 of 14
Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the
device. User guidelines are not tested.
Storage Temperature ............................... –65 C to +150 C
Ambient Temperature with
Power Applied ......................................... –55 C to +125 C
Supply Voltage on
VCC Relative to GND [2] ...............................–0.5 V to +4.6 V
DC Voltage Applied to Outputs
in High Z State [2] ................................ –0.5 V to VCC + 0.5 V
DC Input Voltage [2] ............................ –0.5 V to VCC + 0.5 V
Current into Outputs (LOW) ........................................ 20 mA
Static Discharge Voltage
(MIL-STD-883, Method 3015) ..... ............................> 2001 V
Latch Up Current ................................................... > 200 mA
Operating Range
Range Ambient Temperature VCC
Industrial –40 C to +85 C 3.3 V 0.3 V
DC Electrical Characteristics
Over the Operating Range
Parameter Description Test Conditions
-10
Unit
Min Max
VOH Output HIGH voltage Min VCC, IOH = –4.0 mA 2.4 – V
VOL Output LOW voltage Min VCC, IOL = 8.0 mA – 0.4 V
VIH Input HIGH voltage 2.0 VCC + 0.3 V
VIL Input LOW voltage [2] –0.3 0.8 V
IIX Input leakage current GND VIN VCC –1 +1 A
IOZ Output leakage current GND VOUT VCC, Output disabled –1 +1 A
ICC VCC operating supply current VCC = Max, f = fMAX = 1/tRC, IOUT = 0 mA,
CMOS levels
–175mA
ISB1 Automatic CE power-down
current – TTL inputs
Max VCC, CE VIH,
VIN VIH or VIN VIL, f = fMAX
–30mA
ISB2 Automatic CE power-down
current – CMOS Inputs
Max VCC, CE VCC – 0.3 V,
VIN VCC – 0.3 V, or VIN 0.3 V, f = 0
–25mA
Capacitance
Parameter [3] Description Test Conditions 54-pin TSOP II Unit
CIN Input capacitance TA = 25 C, f = 1 MHz, VCC = 3.3 V 6 pF
COUT I/O capacitance 8pF
Thermal Resistance
Parameter [3] Description Test Conditions 54-pin TSOP II Unit
JA Thermal resistance
(junction to ambient)
Still air, soldered on a 3 × 4.5 inch, four layer printed circuit
board
24.18 C/W
JC Thermal resistance
(junction to case)
5.40 C/W
Note
2. VIL(min) = –2.0 V and VIH(max) = VCC + 2 V for pulse durations of less than 20 ns.
3. Tested initially and after any design or process changes that may affect these parameters.
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Document Number: 001-49315 Rev. *C Page 5 of 14
AC Test Loads and Waveforms
Figure 2. AC Test Loads and Waveforms [4]
90%
10%
3.0 V
GND
90%
10%
ALL INPUT PULSES
3.3 V
OUTPUT
5 pF*
INCLUDING
JIG AND
SCOPE (b)
R1 317
R2
351
RISE TIME: FALL TIME:
> 1 V/ns
(c)
OUTPUT
50
Z
0
= 50
V
TH
= 1.5 V
30 pF*
* CAPACITIVE LOAD CONSISTS
OF ALL COMPONENTS OF THE
TEST ENVIRONMENT
HIGH Z CHARACTERISTICS:
(a)
> 1 V/ns
Data Retention Characteristics
Over the Operating Range
Parameter Description Conditions Min Typ [5] Max Unit
VDR VCC for data retention 2 – – V
ICCDR Data retention current VCC = 2 V, CE VCC – 0.2 V,
VIN VCC – 0.2 V or VIN 0.2 V
––25mA
tCDR [6] Chip deselect to data retention time 0 – – ns
tR [7] Operation recovery time tRC ––ns
Data Retention Waveform
Figure 3. Data Retention Waveform
3.0 V3.0 V
tCDR
VDR > 2 V
DATA RETENTION MODE
tR
CE
VCC
Notes
4. Valid SRAM operation does not occur until the power supplies have reached the minimum operating VDD (3.0 V). 100 s (tpower) after reaching the minimum operating
VDD, normal SRAM operation begins including reduction in VDD to the data retention (VCCDR, 2.0 V) voltage.
5. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C.
6. Tested initially and after any design or process changes that may affect these parameters.
7. Full device operation requires linear VCC ramp from VDR to VCC(min.) 50 s or stable at VCC(min.) 50 s.
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Document Number: 001-49315 Rev. *C Page 6 of 14
AC Switching Characteristics
Over the Operating Range
Parameter [4] Description -10 Unit
Min Max
Read Cycle
tpower VCC(typical) to the first access [5] 100 – s
tRC Read cycle time 10 – ns
tAA Address to data valid – 10 ns
tOHA Data hold from address change 3 – ns
tACE CE LOW to data valid – 10 ns
tDOE OE LOW to data valid – 5 ns
tLZOE OE LOW to low Z 1 – ns
tHZOE OE HIGH to high Z [6] –5ns
tLZCE CE LOW to low Z [6] 3–ns
tHZCE CE HIGH to high Z [6] –5ns
tPU CE LOW to power-up [7] 0–ns
tPD CE HIGH to power-down [7] –10ns
tDBE Byte enable to data valid – 5 ns
tLZBE Byte enable to low Z 1 – ns
tHZBE Byte disable to high Z – 5 ns
Write Cycle [8, 9]
tWC Write cycle time 10 – ns
tSCE CE LOW to write end 7 – ns
tAW Address setup to write end 7 – ns
tHA Address hold from write end 0 – ns
tSA Address setup to write start 0 – ns
tPWE WE pulse width 7–ns
tSD Data setup to write end 5.5 – ns
tHD Data hold from write end 0 – ns
tLZWE WE HIGH to low Z [6] 3–ns
tHZWE WE LOW to high Z [6] –5ns
tBW Byte enable to end of write 7 – ns
Notes
4. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5 V, and input pulse levels of 0 to 3.0 V. Test conditions for the read cycle use
output loading shown in part a) of Figure 2 on page 5, unless specified otherwise.
5. tPOWER gives the minimum amount of time that the power supply is at typical VCC values until the first memory access is performed.
6. tHZOE, tHZCE, tHZWE, tHZBE , tLZOE, tLZCE, tLZWE, and tLZBE are specified with a load capacitance of 5 pF as in (b) of Figure 2 on page 5. Transition is measured 200 mV from steady
state voltage.
7. These parameters are guaranteed by design and are not tested.
8. The internal write time of the memory is defined by the overlap of WE, CE = VIL. Chip enable must be active and WE and byte enables must be LOW to initiate a write,
and the transition of any of these signals can terminate. The input data setup and hold timing should be referenced to the edge of the signal that terminates the write.
9. The minimum write cycle time for Write Cycle No. 2 (WE controlled, OE LOW) is the sum of tHZWE and tSD.
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Switching Waveforms
Figure 4. Read Cycle No. 1 (Address Transition Controlled) [10, 11]
Figure 5. Read Cycle No. 2 (OE Controlled) [11, 12]
PREVIOUS DATA VALID DATA OUT VALID
RC
tAA
tOHA
tRC
ADDRESS
DATA I/O
50%
50%
DATA OUT VALID
tRC
tACE
tDOE
tLZOE
tLZCE
tPU
HIGH IMPEDANCE
tHZOE
tHZBE
tPD
HIGH
OE
CE
ICC
ISB
IMPEDANCE
ADDRESS
DATA I/O
VCC
SUPPLY
tDBE
tLZBE
tHZCE
BHE,BLE
CURRENT
ICC
ISB
Notes
10. The device is continuously selected. OE, CE = VIL, BHE, BLE or both = VIL.
11. WE is HIGH for read cycle.
12. Address valid before or similar to CE transition LOW.
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Document Number: 001-49315 Rev. *C Page 8 of 14
Figure 6. Write Cycle No. 1 (CE Controlled) [13, 14]
Figure 7. Write Cycle No. 2 (WE Controlled, OE LOW) [13, 14]
Switching Waveforms (continued)
tHD
tSD
tSCE
tSA
tHA
tAW
tPWE
tWC
BW
t
DATA I/O
ADDRESS
CE
WE
BHE, BLE
DATA IN VALID
tHD
tSD
tSCE
tHA
tAW
tPWE
tWC
tBW
tSA
tLZWE
tHZWE
DATA I/O
ADDRESS
CE
WE
BHE,BLE
DATA IN VALID
Notes
13. Data I/O is high impedance if OE, BHE, and/or BLE = VIH.
14. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high impedance state.
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Document Number: 001-49315 Rev. *C Page 10 of 14
Ordering Code Definitions
Truth Table
CE OE WE BLE BHE I/O0–I/O7I/O8–I/O15 Mode Power
H X X X X High Z High Z Power-down Standby (ISB)
L L H L L Data Out Data Out Read all bits Active (ICC)
L L H L H Data Out High Z Read lower bits only Active (ICC)
L L H H L High Z Data Out Read upper bits only Active (ICC)
L X L L L Data In Data In Write all bits Active (ICC)
L X L L H Data In High Z Write lower bits only Active (ICC)
L X L H L High Z Data In Write upper bits only Active (ICC)
L H H X X High Z High Z Selected, outputs disabled Active (ICC)
Ordering Information
Speed
(ns) Ordering Code Package
Diagram Package Type Operating
Range
10 CY7C10612DV33-10ZSXI 51-85160 54-pin TSOP II (Pb-free) Industrial
Temperature Grade:
I = Industrial
Pb-free
Package Type:
ZS = 54-pin TSOP II
Speed Grade: 10 ns
Voltage range: 3 V to 3.6 V
Process Technology: C9, 90 nm
Single chip enable
Bus width = × 16
Density = 16-Mbit
Fast asynchronous SRAM family
Technology Code: C = CMOS
Marketing Code: 7 = SRAM
Company ID: CY = Cypress
CY 10 ZS
7C106 X
1I
-
V332 D
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Document Number: 001-49315 Rev. *C Page 12 of 14
Acronyms Document Conventions
Units of Measure
Table 1. Acronyms Used in this Document
Acronym Description
BHE byte high enable
BLE byte low enable
CE chip enable
CMOS complementary metal oxide semiconductor
I/O input/output
OE output enable
SRAM static random access memory
TSOP thin small outline package
TTL transistor-transistor logic
WE write enable
Table 2. Units of Measure
Symbol Unit of Measure
°C degree Celsius
MHz megahertz
µA microampere
smicrosecond
mA milliampere
mm millimeter
mV millivolt
ns nanosecond
ohm
% percent
pF picofarad
Vvolt
Wwatt
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Document Number: 001-49315 Rev. *C Page 13 of 14
Document History Page
Document Title: CY7C10612DV33, 16-Mbit (1 M × 16) Static RAM
Document Number: 001-49315
Rev. ECN No. Orig. of
Change
Submission
Date Description of Change
** 2589743 VKN /
PYRS
10/15/08 New datasheet
*A 2718906 VKN 06/15/09 Post to external web
*B 3128718 PRAS 01/05/11 Template updates.
Style changes.
IO changed to I/O through out the document.
Under Data Retention Characteristics on Page 6, “Typ” is associated with a
new footnote # 10.
Included ordering code definitions, Acronyms and units of measure tables.
Updated package diagram from ** to *A.
*C 3412972 TAVA 10/18/2011 Updated Features.
Updated DC Electrical Characteristics.
Updated Switching Waveforms.
Updated Package Diagrams.
Updated in new template.
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Document Number: 001-49315 Rev. *C Revised October 18, 2011 Page 14 of 14
All products and company names mentioned in this document may be the trademarks of their respective holders.
CY7C10612DV33
© Cypress Semiconductor Corporation, 2008-2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
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