CY7C1345
Document #: 38-05164 Rev. ** Page 4 of 17
Functional Overview
All syn chrono us in puts p ass through input regist ers co ntrolle d
by the rising edge of the clock. Maximum access delay from
the clock rise (tCDV) is 7.5 ns (117-MHz device).
The CY7C1345 supports secondary cache in systems utilizing
either a linear or interleaved burst sequence. The interleaved
burst o rder supp orts Pentium an d i 48 6 p roc es so rs. The linear
burst sequence is suited for processors that utilize a linear
burst s equ enc e. The bu rst order is user se lec tab le, and is d e-
termined by sampling the MODE input. Accesses can be initi-
ated with either the Processor Address Strobe (ADSP) or the
Controller Address Strobe (ADSC). Address advancement
through the burst sequence is controlled by the ADV input. A
two-bit on-chip wraparound burst counter captu res the first ad-
dress in a burst sequence and automatically increments the
address for the rest of the burst access.
Byte write operations are qualified with the Byte Write Enable
(BWE) and Byt e Write S elect (BW[3:0]) inputs. A Global Write
Enable (G W) overri des all byte write inp uts and wri tes data to
all four bytes. All writes are simplified with on-chip synchro-
nous self- t imed w rite ci rcu itry.
Three synchronous Chip Selects (CE1, CE2, CE3) and an
asynch ro nous Ou tp ut En able ( O E) provide for easy bank se-
lection and output three-state control. ADSP is ignored if CE1
is HIGH.
Single Read Acce sse s
A single re ad acc ess is ini tiated when the fol lowi ng condit ion s
are satisfied at clock rise: (1) CE1, CE2, and CE3 are all as-
serted active, and (2) ADSP or ADSC is asserted LOW (if the
access is initiated by ADSC, the write inputs must be deassert-
ed during this first cycle). The address presented to the ad-
dress inputs is latched into the address register and the burst
counter/ control logi c and presen ted to the m emory co re. If th e
OE input is asserted LOW , the requested data will be avail able
at the data outputs a maximum to tCDV after clock rise. ADSP
is ignored if CE1 is HIGH.
Single Wr ite Accesses Initia ted by ADSP
This access is initiated when the following conditions are sat-
isfied at clock rise: (1) CE1, CE2, and CE3 are all asserted
active, and (2) ADSP is asserted LOW. The addresses pre-
sented are loaded into the address register and the burst
counter/ control lo gic and d elivered to the RA M core. Th e write
inputs (GW, BWE, and BW[3:0]) are ignored during this first
clock cycle. If the write inputs are asserted active (see Write
Cycle Descriptions table for appropriate states that indicate a
write) on the next clock rise, the appropriate data will be
latched and written into the device. Byte writes are allowed.
During byte writes, BW0 controls DQ[7:0], BW1 controls
DQ[15:8], BW2 controls DQ[23:16], and BW3 contr o ls DQ [31:24].
All I/Os are three-stated during a byte write. Since this is a
common I/O device, the asynchronous OE input signal must
be deasserted and the I/Os must be three-stated prior to the
presentation of data to DQ[31:0]. As a safety precaution, the
data lines are three-stated once a write cycle is detected, re-
gardless of the state of OE.
Single Write Accesses Initiated by ADSC
This w rite acce ss is i nitiated whe n the f ollowin g condition s are
satis fie d at clo ck ris e : (1) CE1, CE2, and CE3 are al l as se rt ed
active, (2) ADSC is asserted LOW, (3) ADSP is deasserted
HIGH, and (4) the writ e input si gnals (GW, BWE, and BW[3:0])
indicate a write access. ADSC is ignored if ADSP is active LOW .
The addre sses pre sented are loa ded into th e address register
and the burst counter/control logic and delivered to the RAM
core. The i nfor mation pres ented to DQ[31:0] will be wr itten in to
the speci fied address location. Byte writes are allowed. During
byte wr ites, BW0 contro ls DQ[7:0], BW1 controls DQ[15:8], BW2
controls DQ[23:16], and BWS3 controls DQ[31:24]. All I/Os are
three- stated when a writ e is detected, even a byte write. Since
this is a common I/O device, the asynchronous OE input signal
must be dea sserted and the I/Os must be three-s tated prior to
the presentation of data to DQ[31:0]. As a safety precaution, the
data lines are three-stated once a write cycle is detected, re-
gardless of the state of OE.
Burst Sequences
The CY7C1345 provides an on-chip 2-bit wraparound burst
counter inside the SRAM. The burst counter is fed by A[1:0],
and can follow either a linear or interleaved burst order. The
burst order is determined by the state of the MODE input. A
LOW on MO DE will selec t a linear burst se quence. A HIGH on
MODE will select an interleaved burst order. Leaving MODE
unconnected will cause the device to default to a interleaved
burst sequence.
17, 40, 67,
90 VSS Ground Ground for the I/O circuitry of the device. Should be connected to ground of the
system.
5, 10, 14, 21,
26, 55, 60,
71, 76
VSSQ Ground Ground for the device. Should be connected to ground of the system.
4, 1 1, 20, 27,
54, 61, 70,
77
VDDQ I/O Power
Supply Power supply for the I/O circuitry. Should be connected to a 3.3V power supply.
1, 16, 30,
50–51, 66,
80
NC -No connects.
38, 39, 42,
43 DNU -Do not use pins. Should be left unconnected or tied LOW.
Pin Descriptions (continued)
Pin Number Name I/O Description