DATA SH EET
Product specification
File under Integrated Circuits, IC06 December 1990
INTEGRATED CIRCUITS
74HC/HCT238
3-to-8 line decoder/demultiplexer
For a complete data sheet, please also download:
•The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
•The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
•The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
December 1990 2
Philips Semiconductors Product specification
3-to-8 line decoder/demultiplexer 74HC/HCT238
FEATURES
•Demultiplexing capability
•Multiple input enable for easy expansion
•Ideal for memory chip select decoding
•Active HIGH mutually exclusive outputs
•Output capability: standard
•ICC category: MSI
GENERAL DESCRIPTION
The 74HC/HCT238 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT238 decoders accept three binary
weighted address inputs (A0, A1, A2) and when enabled,
provide 8 mutually exclusive active HIGH outputs
(Y0 to Y7).
The “238” features three enable inputs: two active LOW
(E1 and E2) and one active HIGH (E3). Every output will be
LOW unless E1 and E2 are LOW and E3 is HIGH.
This multiple enable function allows easy parallel
expansion of the “238” to a 1-of-32 (5 lines to 32 lines)
decoder with just four “238” ICs and one inverter.
The “238” can be used as an eight output demultiplexer by
using one of the active LOW enable inputs as the data
input and the remaining enable inputs as strobes. Unused
enable inputs must be permanently tied to their
appropriate active HIGH or LOW state.
The “238” is identical to the “138” but has non-inverting
outputs.
QUICK REFERENCE DATA
GND = 0 V; Tamb =25°C; tr=t
f= 6 ns
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW):
PD=C
PD × VCC2× fi+ ∑ (CL× VCC2 × fo) where:
fi= input frequency in MHz
fo= output frequency in MHz
∑ (CL× VCC2× fo) = sum of outputs
CL= output load capacitance in pF
VCC = supply voltage in V
2. For HC the condition is VI= GND to VCC
For HCT the condition is VI= GND to VCC − 1.5 V
ORDERING INFORMATION
See
“74HC/HCT/HCU/HCMOS Logic Package Information”
.
SYMBOL PARAMETER CONDITIONS TYPICAL UNIT
HC HCT
tPHL/ tPLH propagation delay CL= 15 pF; VCC =5 V
A
n
to Yn14 18 ns
E3 to Yn16 20 ns
En to Yn17 21 ns
CIinput capacitance 3.5 3.5 pF
CPD power dissipation capacitance per package notes 1 and 2 72 76 pF
December 1990 3
Philips Semiconductors Product specification
3-to-8 line decoder/demultiplexer 74HC/HCT238
PIN DESCRIPTION
PIN NO. SYMBOL NAME AND FUNCTION
1, 2, 3 A0 to A2address inputs
4, 5 E1, E2enable inputs (active LOW)
6E
3
enable input (active HIGH)
8 GND ground (0 V)
15, 14, 13, 12, 11, 10, 9, 7 Y0 to Y7outputs (active HIGH)
16 VCC positive supply voltage
Fig.1 Pin configuration. Fig.2 Logic symbol.
Fig.3 IEC logic symbol.
(a) (b)
December 1990 4
Philips Semiconductors Product specification
3-to-8 line decoder/demultiplexer 74HC/HCT238
Fig.4 Functional diagram. Fig.5 Logic diagram.
FUNCTION TABLE
Note
1. H = HIGH voltage level
L = LOW voltage level
X = don’t care
INPUTS OUTPUTS
E1E2E3A0A1A2Y0Y1Y2Y3Y4Y5Y6Y7
H
X
X
X
H
X
X
X
L
X
X
X
X
X
X
X
X
X
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
H
H
L
H
L
H
L
L
H
H
L
L
L
L
H
L
L
L
L
H
L
L
L
L
H
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
H
H
L
H
L
H
L
L
H
H
H
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
L
L
L
L
H
L
L
L
L
H
L
L
L
L
H
December 1990 5
Philips Semiconductors Product specification
3-to-8 line decoder/demultiplexer 74HC/HCT238
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see
“74HC/HCT/HCU/HCMOS Logic Family Specifications”
.
Output capability: standard
ICC category: MSI
AC CHARACTERISTICS FOR 74HC
GND = 0 V; tr=t
f= 6 ns; CL= 50 pF
SYMBOL PARAMETER
Tamb (°C)
UNIT
TEST CONDITIONS
74HC VCC
(V) WAVEFORMS
+25 −40 to +85 −40 to +125
min. typ. max. min. max. min. max.
tPHL/ tPLH propagation delay
An to Yn
47
17
14
150
30
26
190
38
33
225
45
38
ns 2.0
4.5
6.0
Fig.6
tPHL/ tPLH propagation delay
E3 to Yn
52
19
15
160
32
27
200
40
34
240
48
41
ns 2.0
4.5
6.0
Fig.6
tPHL/ tPLH propagation delay
En to Yn
50
18
14
155
31
26
195
39
33
235
47
40
ns 2.0
4.5
6.0
Fig.7
tTHL/ tTLH output transition time 19
7
6
75
15
13
95
19
16
110
22
19
ns 2.0
4.5
6.0
Figs 6 and 7
December 1990 6
Philips Semiconductors Product specification
3-to-8 line decoder/demultiplexer 74HC/HCT238
DC CHARACTERISTICS FOR 74HCT
For the DC characteristics see
“74HC/HCT/HCU/HCMOS Logic Family Specifications”
.
Output capability: standard
ICC category: MSI
Note to HCT types
The value of additional quiescent supply current (∆ICC) for a unit load of 1 is given in the family specifications.
To determine ∆ICC per input, multiply this value by the unit load coefficient shown in the table below.
AC CHARACTERISTICS FOR 74HCT
GND = 0 V; tr=t
f= 6 ns; CL= 50 pF
INPUT UNIT LOAD COEFFICIENT
An
En
E3
0.70
0.40
1.45
SYMBOL PARAMETER
Tamb (°C)
UNIT
TEST CONDITIONS
74HCT VCC
(V) WAVEFORMS
+25 −40 to +85 −40 to +125
min. typ. max. min. max. min. max.
tPHL propagation delay
An to Yn
21 35 44 53 ns 4.5 Fig.6
tPLH propagation delay
An to Yn
17 35 44 53 ns 4.5 Fig.6
tPHL propagation delay
E3 to Yn
22 37 46 56 ns 4.5 Fig.6
tPLH propagation delay
E3 to Yn
18 37 46 56 ns 4.5 Fig.6
tPHL propagation delay
En to Yn
21 35 44 53 ns 4.5 Fig.7
tPLH propagation delay
En to Yn
18 35 44 53 ns 4.5 Fig.7
tTHL/ tTLH output transition time 7 15 19 22 ns 4.5 Figs 6 and 7
December 1990 7
Philips Semiconductors Product specification
3-to-8 line decoder/demultiplexer 74HC/HCT238
AC WAVEFORMS
PACKAGE OUTLINES
See
“74HC/HCT/HCU/HCMOS Logic Package Outlines”
.
Fig.6 Waveforms showing the address input (An) and enable input (E3) to output (Yn) propagation delays and
the output transition times.
(1) HC : VM= 50%; VI= GND to VCC.
HCT: VM= 1.3 V; VI= GND to 3 V.
Fig.7 Waveforms showing the enable input (En) to output (Yn) propagation delays and the output transition
times.
(1) HC : VM= 50%; VI= GND to VCC.
HCT: VM= 1.3 V; VI= GND to 3 V.
