JULY 2004
DSC-6442/01
1
©2004 Integrated Device Technology, Inc.
Features
◆◆
◆◆
◆256K x 16 advanced high-speed CMOS Static RAM
◆◆
◆◆
◆JEDEC Center Power / GND pinout for reduced noise.
◆◆
◆◆
◆Equal access and cycle times
– Commercial and Industrial: 10/12/15ns
◆◆
◆◆
◆One Chip Select plus one Output Enable pin
◆◆
◆◆
◆Bidirectional data inputs and outputs directly
LVTTL-compatible
◆◆
◆◆
◆Low power consumption via chip deselect
◆◆
◆◆
◆Upper and Lower Byte Enable Pins
◆◆
◆◆
◆Single 3.3V power supply
◆◆
◆◆
◆Available in 44-pin, 400 mil plastic SOJ package and a 44-
pin, 400 mil TSOP Type II package and a 48 ball grid array,
9mm x 9mm package.
Description
The IDT71V416 is a 4,194,304-bit high-speed Static RAM organized
as 256K x 16. It is fabricated using IDT’s high-perfomance, high-reliability
CMOS technology. This state-of-the-art technology, combined with inno-
vative circuit design techniques, provides a cost-effective solution for high-
speed memory needs.
The IDT71V416 has an output enable pin which operates as fast as
5ns, with address access times as fast as 10ns. All bidirectional inputs and
outputs of the IDT71V416 are LVTTL-compatible and operation is from a
single 3.3V supply. Fully static asynchronous circuitry is used, requiring
no clocks or refresh for operation.
The IDT71V416 is packaged in a 44-pin, 400 mil Plastic SOJ and a
44-pin, 400 mil TSOP Type II package and a 48 ball grid array, 9mm x
9mm package.
Functional Block Diagram
Output
Enable
Buffer
Address
Buffers
Chip
Select
Buffer
Write
Enable
Buffer
Byte
Enable
Buffers
OE
A
0-A17 Row / Column
Decoders
CS
WE
BHE
BLE
4,194,304-bit
Memory
Array
Sense
Amps
and
Write
Drivers
16
High
Byte
Output
Buffer
High
Byte
Write
Buffer
Low
Byte
Write
Buffer
Low
Byte
Output
Buffer
8
8
8
8
8
8
8
8
I/O
15
I/O
8
I/O
7
I/O
0
6442 drw 01
3.3V CMOS Static RAM
4 Meg (256K x 16-Bit) IDT71V416YS
IDT71V416YL
6.422
IDT71V416YS, IDT71V416YL 3.3V CMOS Static RAM
4 Meg (256K x 16-Bit) Commercial and Industrial Temperature Ranges
*Pin 28 can either be a NC or connected to Vss
Top View
Pin Configurations - SOJ/TSOP
Pin Descriptions
SOJ Capacitance
(TA = +25°C, f = 1.0MHz)
NOTE:
1. This parameter is guaranteed by device characterization, but not production
tested.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
I
/O 7
A
9
A
8
A
7
A
6
A
5
W
E
I
/O 6
I
/O 5
I
/O 4
V
SS
V
DD
I
/O 3
I
/O 2
I
/O 1
I
/O 0
C
S
A
4
A
3
A
2
A
1
A
044
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A16
A15
OE
BHE
BLE
I/O 1
5
I/O 1
4
I/O 1
3
I/O 1
2
V
SS
V
DD
I/O 1
1
I/O 1
0
I/O 9
I/O 8
A14
A13
A12
A11
A10
A17
NC*
SO44-1
SO44-2
6442 drw 02
A
0
- A
17
Address Inputs Input
CS Chip Select Input
WE Write Enable Input
OE Outp ut E nab le Inp ut
BHE Hig h B yte E nab le Inp ut
BLE Low Byte Enable Inp ut
I/O
0
- I/O
15
Data Inp ut/ Outp ut I/ O
V
DD
3.3V Po we r Pwr
V
SS
Ground Gnd
6442 tbl 01
Symbol Parameter
(1)
Conditions Max. Unit
C
IN
Input Capacitance V
IN
= 3dV 7 pF
C
I/O
I/O Cap aci tanc e V
OUT
= 3dV 8 pF
6442 t bl 02
123456
ABLE OE A
0
A
1
A
2
NC
BI/O
0
BHE A
3
A
4
CS I/O
8
CI/O
1
I/O
2
A
5
A
6
I/O
10
I/O
9
DV
SS
I/O
3
A
17
A
7
I/O
11
V
DD
EV
DD
I/O
4
NC A
16
I/O
12
V
SS
FI/O
6
I/O
5
A
14
A
15
I/O
13
I/O
14
GI/O
7
NC A
12
A
13
WE I/O
15
HNC A
8
A
9
A
10
A
11
NC
6442 tbl 1
1
Pin Configurations - 48 BGA
48 BGA Capacitance
(TA = +25°C, f = 1.0MHz)
Symbol Parameter
(1)
Conditions Max. Unit
C
IN
Inp ut Cap ac i tanc e V
IN
= 3dV 6 pF
C
I/O
I/O Capacitance V
OUT
= 3dV 7 pF
6442 tb l 02b
6.42
IDT71V416YS, IDT71V416YL 3.3V CMOS Static RAM
4 Meg (256K x 16-Bit) Commercial and Industrial Temperature Ranges
3
Absolute Maximum Ratings(1) Recommended Operating
Temperature and Supply
Voltage
Recommended DC Operating
Conditions
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated
in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
NOTES:
1. VIH (max.) = VDD+2V for pulse width less than 5ns, once per cycle.
2. VIL (min.) = –2V for pulse width less than 5ns, once per cycle.
Truth Table(1)
NOTE:
1 . H = VIH, L = VIL, X = Don't care.
Symbol Rating Value Unit
V
DD
Supply Voltage Relativ e to
V
SS
-0.5 to +4.6 V
V
IN,
V
OUT
Te rminal Vo ltage Relativ e to
V
SS
-0.5 to V
DD
+0.5 V
T
BIAS
Temp erature Und er Bias -55 to +125
o
C
T
STG
Sto rag e Temp erature -55 to +125
o
C
P
T
Power Dissipation 1 W
I
OUT
DC Output Current 50 mA
6442 tbl 04
Grade Temperature V
SS
V
DD
Commercial 0
O
C to +70
O
C 0V See Below
Industrial –40
O
C to + 85
O
C 0V See Below
6442 tbl 05
Symbol Parameter Min. Typ. Max. Unit
V
DD
Sup ply Vo ltag e 3.0 3.3 3.6 V
V
SS
Ground 0 0 0 V
V
IH
In p ut H igh Vo l ta g e 2. 0
____
V
DD
+0.3
(1)
V
V
IL
In p ut L o w Vo l tag e -0.3
(2)
____
0.8 V
6442 tbl 06
CS OE WE BLE BHE I/O0-I/O7I/O8-I/O15 Function
H X X X X High-Z High-Z Deselected - Standby
LLHLHDATA
OUT Hi g h-Z Lo w B y te Read
LLHHL High-Z DATA
OUT Hi gh B yte Re ad
LLHLLDATA
OUT DATAOUT Word Read
LXLLL DATA
IN DATAIN Word Write
LXLLH DATA
IN Hig h-Z Lo w By te Wri te
LXLHL High-Z DATA
IN Hig h B yte Write
L H H X X Hig h-Z Hig h-Z Outp uts Dis ab le d
L X X H H Hig h-Z Hig h-Z Outp uts Dis ab le d
6442 tbl 03
6.424
IDT71V416YS, IDT71V416YL 3.3V CMOS Static RAM
4 Meg (256K x 16-Bit) Commercial and Industrial Temperature Ranges
AC Test Conditions
AC Test Loads
Figure 3. Output Capacitive Derating
Figure 1. AC Test Load
Figure 2. AC Test Load
(for tCLZ, tOLZ, tCHZ, tOHZ, tOW, and tWHZ)
*Including jig and scope capacitance.
Inp ut P uls e Le v e ls
Inp ut Ris e /Fal l Ti me s
Inp ut Timing Re fe renc e Le v e ls
Outp ut Re fe re nc e Le v els
AC Test Load
GND to 3.0V
1.5ns
1.5V
1.5V
Figures 1,2 and 3
6442 tbl 09
+1.5V
50Ω
I
/O Z
0
=50Ω
6442 drw 0
3
30pF
6442 drw 0
4
320Ω
350Ω5pF*
D
ATA
OUT
3.3V
IDT71V416S/71V416L
1
2
3
4
5
6
7
20 40 60 80 100 120 140 160 180 200
∆t
AA,
t
ACS
(Typical, ns)
CAPACITANCE (pF)
8
6442drw 0
5
•
•
•
•
•
•
•
DC Electrical Characteristics
(VDD = Min. to Max., Commercial and Industrial Temperature Ranges)
DC Electrical Characteristics(1, 2, 3)
(VDD = Min. to Max., VLC = 0.2V, VHC = VDD – 0.2V)
NOTES:
1. All values are maximum guaranteed values.
2. All inputs switch between 0.2V (Low) and VDD -0.2V (High).
3. Power specifications are preliminary.
4. fMAX = 1/tRC (all address inputs are cycling at fMAX); f = 0 means no address input lines are changing.
5. Standard power 10ns (S10) speed grade only.
Symbol Parameter
71V416S/L10 71V416S/L12 71V416S/L15
Unit
Com'l. Ind.
(5)
Com'l. Ind. Com'l. Ind.
I
CC
Dynamic Ope rating Current
CS < V
LC
, Outputs Open, V
DD
= Max., f = f
MAX(4)
S 200 200 180 180 170 170 mA
L 180 — 170 170 160 160
I
SB
Dynamic Standby Power Supply Current
CS > V
HC
, Outputs Open, V
DD
= Max ., f = f
MAX(4)
S707060605050mA
L 50 — 45 45 40 40
I
SB1
Full Standby Power Supply Current (static)
CS > V
HC
, Outputs Open, V
DD
= Max ., f = 0
(4)
S202020202020mA
L 10 — 10 10 10 10
6442 tbl 08
Symbol Parameter Test Conditions
IDT71V416
UnitMin. Max.
|I
LI
| Inp ut Leakage Current V
CC
= Max., V
IN
=
V
SS
to V
DD
___
5µA
|I
LO
| Output Leakage Current V
DD
= Max., CS = V
IH
, V
OUT
= V
SS
to V
DD
___
5µA
V
OL
Outp ut Lo w Vo ltag e I
OL
= 8mA, V
DD
= Min.
___
0.4 V
V
OH
Outp ut High Vo ltag e I
OH
= -4mA, V
DD
= Min. 2. 4
___
V
6442 tbl 07
6.42
IDT71V416YS, IDT71V416YL 3.3V CMOS Static RAM
4 Meg (256K x 16-Bit) Commercial and Industrial Temperature Ranges
5
71V416S/L10
(2)
71V416S/L12 71V416S/L15
Symbol Parameter Min.Max.Min.Max.Min.Max.Unit
READ CYCLE
t
RC
Re ad Cy cl e Time 10
____
12
____
15
____
ns
t
AA
Address Access Time
____
10
____
12
____
15 ns
t
ACS
Chip Select Access Time
____
10
____
12
____
15 ns
t
CLZ
(1)
Chip Se lec t Low to Output in Lo w-Z 4
____
4
____
4
____
ns
t
CHZ
(1)
Chi p Se le c t Hig h to Outp ut i n Hi g h-Z
____
5
____
6
____
7ns
t
OE
Ou tp ut Enab le Lo w to Outp ut Valid
____
5
____
6
____
7ns
t
OLZ
(1)
Outp ut Enab le Lo w to Outp ut in Lo w-Z 0
____
0
____
0
____
ns
t
OHZ
(1)
Outp ut Enab le Hig h to Outp ut in High-Z
____
5
____
6
____
7ns
t
OH
Output Hold from Address Change 4
____
4
____
4
____
ns
t
BE
B yte Enable Lo w to Output Valid
____
5
____
6
____
7ns
t
BLZ
(1)
By te Enable Lo w to Output in Lo w-Z 0
____
0
____
0
____
ns
t
BHZ
(1)
By te Enab le Hig h to Outp ut in Hig h-Z
____
5
____
6
____
7ns
WRI TE CYCLE
t
WC
Write Cycle Time 10
____
12
____
15
____
ns
t
AW
Address Valid to End of Write 8
____
8
____
10
____
ns
t
CW
Chip Select Low to End of Write 8
____
8
____
10
____
ns
t
BW
Byte Enable Low to End o f Write 8
____
8
____
10
____
ns
t
AS
Address Set-up Time 0
____
0
____
0
____
ns
t
WR
Address Hold from End of Write 0
____
0
____
0
____
ns
t
WP
Write Pulse Width 8
____
8
____
10
____
ns
t
DW
Data Valid to End of Write 5
____
6
____
7
____
ns
t
DH
Data H ol d Time 0
____
0
____
0
____
ns
t
OW
(1)
Write Enable High to Output in Low-Z 3
____
3
____
3
____
ns
t
WHZ
(1)
Write Enable Low to Output in Hig h-Z
____
6
____
7
____
7ns
6442 tbl 10
Timing Waveform of Read Cycle No. 1(1,2,3)
AC Electrical Characteristics
(VDD = Min. to Max., Commercial and Industrial Temperature Ranges)
NOTE:
1. This parameter is guaranteed with the AC Load (Figure 2) by device characterization, but is not production tested.
2. Low power 10ns (L10) speed 0ºC to +70ºC temperature range only.
DATA
OUT
ADDRESS
6442d06
t
RC
t
AA
t
OH
DATA
OUT
VALID
PREVIOUS DATA
OUT
VALID
t
OH
NOTES:
1. WE is HIGH for Read Cycle.
2. Device is continuously selected, CS is LOW.
3. OE, BHE, and BLE are LOW.
6.426
IDT71V416YS, IDT71V416YL 3.3V CMOS Static RAM
4 Meg (256K x 16-Bit) Commercial and Industrial Temperature Ranges
ADDRESS
OE
CS
DATA
OUT
6442 drw 07
(3)
DATA VALID
t
AA
t
RC
t
OE
t
OLZ
BHE, BLE
(3)
t
ACS
(3)
t
BLZ
t
CLZ
(2)
t
BE
(2)
t
OH
t
OHZ (3)
t
CHZ (3)
t
BHZ (3)
OUT
Timing Waveform of Read Cycle No. 2(1)
NOTES:
1. A write occurs during the overlap of a LOW CS, LOW BHE or BLE, and a LOW WE.
2. OE is continuously HIGH. If during a WE controlled write cycle OE is LOW, tWP must be greater than or equal to tWHZ + tDW to allow the I/O drivers to turn off and data
to be placed on the bus for the required tDW. If OE is HIGH during a WE controlled write cycle, this requirement does not apply and the minimum write pulse is as
short as the specified tWP.
3. During this period, I/O pins are in the output state, and input signals must not be applied.
4. If the CS LOW or BHE and BLE LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high-impedance state.
5. Transition is measured ±200mV from steady state.
Timing Waveform of Write Cycle No. 1 (WE Controlled Timing)(1,2,4)
NOTES:
1. WE is HIGH for Read Cycle.
2. Address must be valid prior to or coincident with the later of CS, BHE, or BLE transition LOW; otherwise tAA is the limiting parameter.
3. Transition is measured ±200mV from steady state.
ADDRESS
CS
DATA
IN
6442 drw
0
(5) (5)
(5)
DATA
IN
VALID
t
WC
t
AS
t
WHZ
(2)
t
CW
t
CHZ
t
OW
t
WR
WE
t
AW
DATA
OUT
t
DW
t
DH
PREVIOUS DATA VALID DATA VALID
BHE
,
BLE t
BW
t
WP
(5)
t
BHZ
(3)
6.42
IDT71V416YS, IDT71V416YL 3.3V CMOS Static RAM
4 Meg (256K x 16-Bit) Commercial and Industrial Temperature Ranges
7
Timing Waveform of Write Cycle No. 2 (CS Controlled Timing)(1,3)
NOTES:
1. A write occurs during the overlap of a LOW CS, LOW BHE or BLE, and a LOW WE.
2. During this period, I/O pins are in the output state, and input signals must not be applied.
3. If the CS LOW or BHE and BLE LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high-impedance state.
Timing Waveform of Write Cycle No. 3
(BHE, BLE Controlled Timing)(1,3)
ADDRESS
CS
DATA
IN
6442 drw
09
DATA
IN
VALID
t
WC
t
AS (2)
t
CW
t
WR
WE
t
AW
DATA
OUT
t
DW
t
DH
BHE, BLE t
BW
t
WP
ADDRESS
CS
DATA
IN
6442 drw
DATA
IN
VALID
t
WC
t
AS
(2)
t
CW
t
WR
WE
t
AW
DATA
OUT
t
DW
t
DH
BHE, BLE
t
BW
t
WP
6.428
IDT71V416YS, IDT71V416YL 3.3V CMOS Static RAM
4 Meg (256K x 16-Bit) Commercial and Industrial Temperature Ranges
X
Power
XX
Speed
XXX
Package
X
Process/
Temperature
Range
Blank
ICommercial (0°C to +70°C)
Industrial (-40°C to +85°C)
Y
PH
BE
44-pin, 400-mil SOJ (SO44-1)
44-pin TSOP Type II (SO44-2)
48 Ball Grid Array
10*
12
15
71V416
Device
Type
I
DT
Speed in nanoseconds
6442 drw 11a
* Commercial only for low power 10ns (L10) speed grade.
X
Y die stepping
Y
S
LStandard Power
Low Power
X
GRestricted hazardous
substance device
Ordering Information
6.42
IDT71V416YS, IDT71V416YL 3.3V CMOS Static RAM
4 Meg (256K x 16-Bit) Commercial and Industrial Temperature Ranges
9
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
Datasheet Document History
10/13/03 Released datasheet
07/30/04 p.8 Added "Restricted hazardous substance device " to ordering information.
CORPORATE HEADQUARTERS for SALES: for Tech Support:
6024 Silver Creek Valley Road 800-345-7015 or ipchelp@idt.com
San Jose, CA 95138 408-284-8200 800-345-7015
fax: 408-284-2775
www.idt.com