MAX1932 Digitally Controlled, 0.5% Accurate,
Safest APD Bias Supply
EVALUATION KIT AVAILABLE
General Description
The MAX1932 generates a low-noise, high-voltage output
to bias avalanche photodiodes (APDs) in optical
receivers. Very low output ripple and noise is achieved by
a constant-frequency, pulse-width modulated (PWM)
boost topology combined with a unique architecture that
maintains regulation with an optional RC or LC post filter
inside its feedback loop. A precision reference and error
amplifier maintain 0.5% output voltage accuracy.
The MAX1932 protects expensive APDs against adverse
operating conditions while providing optimal bias.
Traditional boost converters measure switch current for
protection, whereas the MAX1932 integrates accurate
high-side current limiting to protect APDs under
avalanche conditions. A current-limit flag allows easy cali-
bration of the APD operating point by indicating the pre-
cise point of avalanche breakdown. The MAX1932 control
scheme prevents output overshoot and undershoot to
provide safe APD operation without data loss.
The output voltage can be accurately set with either
external resistors, an internal 8-bit DAC, an external
DAC, or other voltage source. Output span and offset
are independently settable with external resistors. This
optimizes the utilization of DAC resolution for applica-
tions that may require limited output voltage range, such
as 4.5V to 15V, 4.5V to 45V, 20V to 60V, or 40V to 90V.
Applications
Optical Receivers and Modules
Fiber Optic Network Equipment
Telecom Equipment
Laser Range Finders
PIN Diode Bias Supply
Benefits and Features
•Unique Architecture Delivers Excellent Accuracy for
Improved System Performance
•0.5% Accurate Output
•Low Ripple Output (< 1mV)
•Protection Features Guarantee Safe Operation
•Accurate High-Side Current Limit
•Avalanche Indicator Flag
•Output-Voltage Flexibility Facilitates Multiple
Applications and Design Approaches
•4.5V to 90V Output
•Set Output Voltage via 8-Bit SPI-Compatible
Internal DAC, External DAC, or External Resistors
•Small Circuit Footprint Reduces Equipment Size
•12-Pin, 4mm x 4mm Thin QFN Package
•Circuit Height < 2mm
•Commonly Available 2.7V to 5.5V Input Voltage
Range
Ordering Information
PART TEMP RANGE PIN-PACKAGE
MAX1932ETC -40°C to +85°C 12 Thin QFN
MAX1932
INPUT
2.7V TO 5.5V
APD BIAS OUTPUT
4.5V TO 90V
DAC INPUTS
AVALANCHE
INDICATOR
FLAG
VIN
COMP
SCLK
GND FB
CS-
CS+
GATE
DACOUT
DIN
CS
CL
Typical Application Circuit
MAX1932
12
1
2
3
9
8
7
11 10
4 5 6
SCLK GND
COMP
FB
CS+
CS-
DACOUT GATE
VIN
DIN
CL
CS
Pin Configuration
19-2555; Rev 2; 5/15
MAX1932 Digitally Controlled, 0.5% Accurate,
Safest APD Bias Supply
Maxim Integrated | 2www.maximintegrated.com
Absolute Maximum Ratings
Electrical Characteristics
(VIN = 3.3V, CS = SCLK = DIN = 3.3V, CS+ = CS- = 45V, Circuit of Figure 2, TA= 0°C to +85°C, unless otherwise noted.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VIN to GND...............................................................-0.3V to +6V
DIN, SCLK, CS, FB to GND ......................................-0.3V to +6V
COMP, DACOUT, GATE, CL to GND ...........-0.3V to (VIN +0.3V)
CS+, CS- to GND .................................................-0.3V to +110V
Continuous Power Dissipation (TA= +70°C)
12-Pin Thin QFN (derate 16.9mW/°C above +70°C) .1349mW
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering 10s) ..................................+300°C
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
GENERAL
Input Supply Range VIN 2.7 5.5 V
VIN Undervoltage Lockout UVLO Both rise/fall, hysteresis = 100mV 2.1 2.6 V
Operating Supply Current IIN 0.5 1 mA
VIN Shutdown Supply Current ISHDN 00 hex loaded to DAC 25 65 µA
Input Resistance for CS+/CS- Resistance from either pin to ground 0.5 1 2.0 MΩ
Current-Limit Threshold
for CS+/CS- 1.80 2.00 2.20 V
Common-Mode Rejection
of Current Threshold CS+ = 3V to 100V ±0.005 %/V
Gate-Driver Resistance Gate high or low, IGATE = ±50mA 5 10 Ω
FB Input Bias Current -25 +25 nA
TA = +25°C 1.24375 1.2500 1.25625
FB Voltage VFB TA = 0°C to +85°C 1.24250 1.2500 1.25750 V
FB Voltage
Temperature Coefficient TCVFB 0.0007 %/°C
FB to COMP Transconductance COMP = 1.5V 50 110 200 µS
COMP Pulldown Resistance
in Shutdown DAC code = 00 hex 100 Ω
D AC OU T to FB V ol tag e D i ffer ence DAC code = FF hex -3 +3 mV
D AC OU T Differential Nonlinearity
(Note 1)
DAC Code = 01 to FF hex,
DAC guaranteed monotonic -1 +1 LSB
D AC OU T Voltage Temperature
Coefficient TCVDACOUT 0.0007 %/°C
DACOUT Load Regulation DAC code = 0F to FF hex, source or sink
50µA -1 +1 mV
Switching Frequency fOSC 250 300 340 kHz
GATE Maximum On-Time tON 3µs
MAX1932 Digitally Controlled, 0.5% Accurate,
Safest APD Bias Supply
Maxim Integrated | 3www.maximintegrated.com
Electrical Characteristics (continued)
(VIN = 3.3V, CS = SCLK = DIN = 3.3V, CS+ = CS- = 45V, Circuit of Figure 2, TA= 0°C to +85°C, unless otherwise noted.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
DIGITAL INPUTS (DIN, SCLK, CS)
Input Low Voltage 0.6 V
Input High Voltage 1.4 V
Input Hysteresis 200 mV
TA = +25°C -1 +1 µA
Input Leakage Current TA = 0°C to +85°C 10 nA
Input Capacitance 5pF
DIGITAL OUTPUT (CL)
Output Low Voltage ISINK = 1mA 0.1 V
Output High Voltage ISOURCE = 0.5mA VIN - 0.5 V
SPI TIMING (FIGURE 5)
SCLK Clock Frequency fSCLK 2 MHz
SCLK Low Period tCL 125 ns
SCLK High Period tCH 125 ns
Data Hold Time tDH 0ns
Data Setup Time tDS 125 ns
CS Assertion to SCLK
Rising Edge Setup Time tCSS0 200 ns
CS Deassertion to SCLK
Rising Edge Setup Time tCSS1 200 ns
SCLK Rising Edge
to CS Deassertion tCSH1 200 ns
SCLK Rising Edge
to CS Assertion tCSH0 200 ns
CS High Period tCSW 300 ns
Electrical Characteristics
(VIN = 3.3V, CS = SCLK = DIN = 3.3V, CS+ = CS- = 45V, Circuit of Figure 2, TA= -40°C to +85°C, unless otherwise noted.) (Note 2)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
GENERAL
Input Supply Range VIN 2.7 5.5 V
VIN Undervoltage Lockout UVLO Both rise/fall, hysteresis = 100mV 2.1 2.6 V
Operating Supply Current IIN 1mA
VIN Shutdown Supply Current ISHDN 00 hex loaded to DAC 65 µA
Input Resistance for CS+/CS- Resistance from either pin to ground 0.5 2 MΩ
Current-Limit Threshold
for CS+/CS- 1.80 2.20 V
Gate-Driver Resistance Gate high or low, IGATE = ±50mA 10 Ω
FB Input Bias Current -30 +30 nA
MAX1932 Digitally Controlled, 0.5% Accurate,
Safest APD Bias Supply
Maxim Integrated | 4www.maximintegrated.com
Note 1: DACOUT = DAC code x (1.25V/256) + 1.25V/256.
Note 2: Specifications to -40°C are guaranteed by design and not production tested.
Electrical Characteristics (continued)
(VIN = 3.3V, CS = SCLK = DIN = 3.3V, CS+ = CS- = 45V, Circuit of Figure 2, TA= -40°C to +85°C, unless otherwise noted.) (Note 2)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
FB Voltage VFB 1.23875 1.26125 V
FB to COMP Transconductance COMP = 1.5V 50 200 µS
COMP Pulldown Resistance
in Shutdown DAC code = 00 hex 100 Ω
D AC OU T to FB V ol tag e D i ffer ence DAC code = FF hex -4 +4 mV
D AC OU T Differential Nonlinearity
(Note 1)
DAC Code = 01 to FF hex, DAC
guaranteed monotonic -1 +1 LSB
D AC OU T Load Regulation DAC code = 0F to FF hex, source or sink
50µA -1 +1 mV
Switching Frequency fOSC 240 360 kHz
DIGITAL INPUTS (DIN, SCLK, CS)
Input Low Voltage 0.6 V
Input High Voltage 1.4 V
DIGITAL OUTPUT (CL)
Output Low Voltage ISINK = 1mA 0.1 V
Output High Voltage ISOURCE = 0.5mA VIN - 0.5 V
SPI TIMING (FIGURE 5)
SCLK Clock Frequency fSCLK 2 MHz
SCLK Low Period tCL 125 ns
SCLK High Period tCH 125 ns
Data Hold Time tDH 0ns
Data Setup Time tDS 125 ns
CS Assertion to SCLK
Rising Edge Setup Time tCSS0 200 ns
CS Deassertion to SCLK
Rising Edge Setup Time tCSS1 200 ns
SCLK Rising Edge
to CS Deassertion tCSH1 200 ns
SCLK Rising Edge
to CS Assertion tCSH0 200 ns
CS High Period tCSW 300 ns
MAX1932 Digitally Controlled, 0.5% Accurate,
Safest APD Bias Supply
Maxim Integrated | 5www.maximintegrated.com
SWITCHING WAVEFORMS
MAX1932 toc01
1μs/div
0.05A/div
50V/div
0.002V/div
VLX
IL
VOUT RIPPLE (AC-COUPLED)
VOUT = 90V
SWITCHING WAVEFORM WITH LC FILTER
MAX1932 toc02
1μs/div
0.05A/div
50V/div
0.002V/div
VLX
IL
VOUT RIPPLE (AC-COUPLED)
VOUT = 90V, L = 300μH, C = 1μF, FIGURE 7
STARTUP AND SHUTDOWN WAVEFORMS
MAX1932 toc03
20ms/div
50mA/div
50V/div
INPUT
CURRENT
OUTPUT
VOLTAGE
OUTPUT VOLTAGE vs. INPUT VOLTAGE
MAX1932 toc04
INPUT VOLTAGE (V)
4.5
3.52.5 5.5
VFB vs. TEMPERATURE
MAX1932 toc05
TEMPERATURE (°C)
80
60-40 -20 020 4060 100
OUTPUT VOLTAGE vs. LOAD CURRENT
MAX1932 toc06
LOAD CURRENT (mA)
OUTPUT VOLTAGE (V)
2.52.01.51.00.5
55
60
65
70
75
80
85
90
95
50
03.0
CURRENT LIMIT
ACTIVATED
VCC = 5V, INDUCTOR = 100μH,
R1 = 806Ω
FEEDBACK DIVIDER CURRENT AND CS-
CURRENT INCLUDED
OUTPUT VOLTAGE STEP-DOWN
DUE TO DAC CHANGE
MAX1932 toc07
10ms/div
1V/div
OFFSET = 62.962V = 88 hex
STEP DOWN FROM 80 hex TO 88 hex
OUTPUT VOLTAGE STEP-UP
DUE TO DAC CHANGE
MAX1932 toc08
10ms/div
1V/div
OFFSET = 62.962V = 88 hex
STEP VALUE = 64.233 = 80 hex
OUTPUT VOLTAGE STEP
DUE TO DACOUT CHANGE
MAX1932 toc09
20ms/div
20V/div
0.5V/div
DACOUT EXTERNAL SOURCE
Typical Operating Characteristics
(VIN = 5V, Circuit of Figure 2, TA=+25°C, unless otherwise noted)
MAX1932 Digitally Controlled, 0.5% Accurate,
Safest APD Bias Supply
Maxim Integrated | 6www.maximintegrated.com
Detailed Description
Fixed Frequency PWM
The MAX1932 uses a constant frequency, PWM, con-
troller architecture. This controller sets the switch on-
time and drives an external N-channel MOSFET (see
Figure 1). As the load varies, the error amplifier sets the
inductor peak current necessary to supply the load and
regulate the output voltage.
Output Current Limit
The MAX1932 uses an external resistor at CS+ and CS-
to sense the output current (see Figure 2). The typical
current-limit threshold is 2V. CL is designed to help find
the optimum APD bias point by going low to indicate
when the APD reaches avalanche and that current limit
has been activated. To minimize noise, CL only
changes state on an internal oscillator edge.
Output Control DAC
An internal digital-to-analog converter can be used to
control the output voltage of the DC-DC converter
(Figure 2). The DAC output is changed through an SPI™
serial interface using an 8-bit control byte. On power-up,
the DAC defaults to FF hex (1.25V), which corresponds
to a minimum boost converter output voltage.
Alternately, the output voltage can be set with external
resistors, an external DAC, or a voltage source. Output
span and offset are independently settable with exter-
nal resistors. See the
Applications Information
section
for output control equations.
SPI Interface/Shutdown
Use an SPI-compatible 3-wire serial interface with the
MAX1932 to control the DAC output voltage and to shut
down the MAX1932. Figures 4 and 5 show timing diagrams
for the SPI protocol. The MAX1932 is a write-only device
and uses CS along with SCLK and DIN to communicate.
The serial port is always operational when the device is
powered. To shut down the DC-DC converter portion only,
update the DAC registers to 00 hex.
Applications Information
Voltage Feedback Sense Point
Feedback can be taken from in front of, or after, the cur-
rent-limit sense resistor. The current-limit sense resistor
forms a lowpass filter with the output capacitor. Taking
feedback after the current-limit sense resistor (see Figure
2), optimizes the output voltage accuracy, but requires
overcompensation, which slows down the control loop
response. For faster response, the feedback can be
taken from in front of the current-sense resistor (see
Figure 3). This configuration however, makes the output
voltage more sensitive to load variation and degrades
output accuracy by an amount equal to the load current
times the current-sense resistor value.
Pin Description
PIN NAME FUNCTION
1 SCLK DAC Serial Clock Input
2 DIN DAC Serial Data Input
3CL Current-Limit Indicator Flag. CL = 0 indicates that the part is in current limit. Logic high level = VIN.
4 CS+ Current-Limit Plus Sense Input. Connect a resistor from CS+ to CS- in series with the output. The differential
threshold is 2V. CS+ has typically 1MΩ resistance to ground.
5 CS- Current-Limit Minus Sense Input. CS- has typically 1MΩ resistance to ground.
6 DACOUT Internal DAC Output. Generates a control voltage for adjustable output operation. DACOUT can source or
sink 50µA.
7FB
Feedback input. Connect to a resistive voltage-divider between the output voltage (VOUT) and FB to set the
output voltage. The feedback set point is 1.25V.
8 COMP Compensation Pin. Compensates the DC-DC converter control loop with a series RC to GND. COMP is
actively discharged to ground during shutdown or undervoltage conditions.
9 GND Ground
10 GATE Gate-Driver Output for External N-FET
11 VIN IC Supply Voltage (2.7V to 5.5V). Bypass VIN with a 1µF or greater ceramic capacitor.
12 CS DAC Chip-Select Input
SPI is a trademark of Motorola, Inc.
MAX1932 Digitally Controlled, 0.5% Accurate,
Safest APD Bias Supply
Maxim Integrated | 7www.maximintegrated.com
Output and DAC Adjustments Range
Many biasing applications require an adjustable output
voltage, which is easily obtained using the MAX1932’s
DAC output (Figure 2).
The DAC output voltage is given by the following equation:
On power-up, DACOUT defaults to FF hex or 1.25V,
which corresponds to the minimum VOUT output voltage.
The voltage generated at DACOUT is coupled to FB
through R6. DACOUT can sink only 50µA so:
Select the minimum output voltage (VOUTFF), and the
maximum output voltage (VOUT01) for the desired
adjustment range. R5 sets the adjustment span using
the following equation:
R5 = (VOUTFF - VOUT01) (R6/1.25V)
R8 sets the minimum output of the adjustment range
with the following equation:
R8 = (1.25V ✕R5)/(VOUTFF)
Setting the Output Voltage without
the DAC
Adjust the output voltage by connecting a voltage-
divider from the output (VOUT) to FB (Figure 2 with R6
omitted). Select R8 between 10kΩto 50kΩ. Calculate
R5 with the following equation:
Inductor Selection
Optimum inductor selection depends on input voltage,
output voltage, maximum output current, switching fre-
quency, and inductor size. Inductors are typically spec-
ified by their inductance (L), peak current (IPK), and
resistance (LR).
The inductance value is given by:
where VIN is the input voltage, IOUT(MAX) is the maxi-
mum output current delivered, VOUT is the output volt-
age, and T is the switching period (3.3µs), ηis the
estimated power conversion efficiency, and D is the
maximum duty cycle:
D < (VOUT - VIN)/VOUT up to a maximum of 0.9
Since the L equation factors in efficiency, for inductor cal-
culation purposes, an ηof 0.5 to 0.75 is usually suitable.
For example, with a maximum DC load current of 2.5mA,
a 90V output, VIN = 5V, D = 0.9, T = 3.3µs, and ηesti-
mated at 0.75, the above equation yields an L of 111µH,
so 100µH would be a suitable value.
The peak inductor current is given by:
These are typical calculations. For worst case, refer to
the article titled “Choosing the MAX1932 External
Indicator, Diode, Current Sense Resistor, and Output
Filter Capacitor for Worst Case Conditions” located on
the Maxim website in the Application Notes section (visit
www.maxim-ic.com/an1805).
External Power-Transistor Selection
An N-FET power switch is required for the MAX1932. The
N-FET switch should be selected to have adequate on-
resistance with the MOSFET VGS = VIN(MIN). The break-
down voltage of the N-FET must be greater than VOUT.
For higher-current output applications (such as 5mA at
90V), SOT23 high-voltage low-gate-threshold N-FETs
may not have adequate current capability. For example,
with a 5V input, a 90V, 5mA output requires an inductor
peak of 240mA. For such cases it may be necessary to
simply parallel two N-FETs to achieve the required cur-
rent rating. With SOT23 devices this often results in
smaller and lower cost than using a larger N-FET device.
Diode Selection
The output diode should be rated to handle the output
voltage and the peak switch current. Make sure that the
diode’s peak current rating is at least IPK and that its
breakdown voltage exceeds VOUT. Fast reverse recov-
ery time (trr < 10ns) and low junction capacitance
IVDT
L
PK IN
=××
LVDT
IV
IN
OUT MAX OUT
=
()
×××
×
22
2
η
()
RRVOUT
V
58
125 1=−
⎛
⎝
⎜⎞
⎠
⎟
.
RV
A
6125
50
≥μ
.
V CODE VV
DACOUT =×
⎛
⎝
⎜⎞
⎠
⎟+⎛
⎝
⎜⎞
⎠
⎟
125
256
125
256
..
MAX1932 Digitally Controlled, 0.5% Accurate,
Safest APD Bias Supply
Maxim Integrated | 8www.maximintegrated.com
(<10pF) are recommended to minimize losses. A small-
signal silicon switching diode is suitable if efficiency is
not critical.
Output Filter Capacitor Selection
The output capacitors of the MAX1932 must have high
enough voltage rating to operate with the VOUT
required. Output capacitor effective series resistance
(ESR) determines the amplitude of the high-frequency
ripple seen on the output voltage. In the typical appli-
cation circuit, a second RC formed by R1 and C3 fur-
ther reduces ripple.
Input Bypass Capacitor Selection
The input bypass capacitor reduces the peak currents
drawn from the voltage source and reduces noise
caused by the MAX1932’s switching action. The input
source impedance determines the size of the capacitor
required at the input (VIN). A low ESR capacitor is rec-
ommended. A 1µF ceramic capacitor is adequate for
most applications. Place the bypass capacitor as close
as possible to the VIN and GND pins.
Current-Sense Resistor Selection
Current limit is used to set the maximum delivered out-
put current. In the typical application circuit, MAX1932
is designed to current limit at:
Note that ILIMIT must include current drawn by the
feedback divider (if sensing feedback after R1) and the
input current of CS-.
Stability and Compensation
Component Selection
Compensation components, R7 and C4, introduce a
pole and a zero necessary to stabilize the MAX1932
(see Figure 6). The dominant pole, POLE1, is formed by
the output impedance of the error amplifier (REA) and
C4. The R7/C4 zero, ZERO1, is selected to cancel the
pole formed by the output filter cap C3 and output load
RLD, POLE2. The additional pole of R1/C3, POLE3,
should be at least a decade past the crossover fre-
quency to not affect stability:
POLE1 (dominant pole) = 1 / (2π✕REA ✕C4)
ZERO1 (integrator zero) = 1 / (2π✕R7 ✕C4)
POLE2 (output load pole) = K1 / (2π✕RLD ✕(C2 + C3))
POLE3 (output filter pole) = 1 / (2π✕R1 ✕C3)
The DC open-loop gain is given by:
AOL = K2 ✕Gm ✕REA
where REA = 310MΩ,
gM= 110µS,
RLD is the parallel combination of feedback network
and the load resistance.
A properly compensated MAX1932 results in a gain vs.
frequency plot that crosses 0dB with a single pole
slope (20dB per decade). See Figure 6.
Table 1 lists suggested component values for several
typical applications.
Further Noise Reduction
The current-limit sense resistor is typically used as part
of an output lowpass filter to reduce noise and ripple.
For further reduction of noise, an LC filter can be added
as shown in Figure 7. Output ripple and noise with and
without the LC filter are shown in the
Typical Operating
Characteristics
. If a post LC filter is used, it is best to
use a coil with fairly large resistance (or a series resis-
tor) so that ringing at the response peak of the LC filter
is damped. For a 330µH and 1µF filter, 22Ωaccom-
plishes this, but a resistor is not needed if the coil resis-
tance is greater than 15Ω.
Output Accuracy and Feedback
Resistor Selection
The MAX1932 features 0.5% feedback accuracy. The
total voltage accuracy of a complete APD bias circuit is
the sum of the FB set-point accuracy, plus resistor ratio
error and temperature coefficient. If absolute accuracy
is critical, the best resistor choice is an integrated net-
work with specified ratio tolerance and temperature
coefficient. If using discrete resistors in high-accuracy
applications, pay close attention to resistor tolerance
and temperature coefficients.
Temperature Compensation
APDs exhibit a change in gain as a function of temper-
ature. This gain change can be compensated with an
appropriate adjustment in bias voltage. For this reason
it may be desirable to vary the MAX1932 output voltage
as a function of temperature. This can be done in soft-
KV Volts
Volts
V
VV
V
VV
R T ond
L Henries
FB IN
OUT IN
OUT
OUT IN
LD
2075
2
2
2
=×
×
××
⎛
⎝
⎜
⎞
⎠
⎟×
×
⎛
⎝
⎜
⎜
⎞
⎠
⎟
⎟
()
.( )
()
()
-
-
sec
KVV
VV
OUT IN
OUT IN
12
=×-
-
RV
ILIMIT
12
=
MAX1932 Digitally Controlled, 0.5% Accurate,
Safest APD Bias Supply
Maxim Integrated | 9www.maximintegrated.com
ware by the system through the on-chip DAC, but can
also be accomplished in hardware using an external
thermistor or IC temperature sensor. Figure 8 shows
how an NTC thermistor can be connected to make the
bias voltage increase with temperature.
PC Board Layout and Grounding
Careful PC board layout is important for minimizing
ground bounce and noise. In addition, keep all connec-
tions to FB as a short as possible. In particular, locate
feedback resistors (R5, R6, and R8) as close to FB as
possible. Use wide, short traces to interconnect large
current paths for N1, D1, L1, C1, C2. Do not share
these connections with other signal paths. Refer to the
MAX1932 EV kit for a PC board layout example.
VIN, VOUT, IOUT(MAX) INDUCTOR L1
(µH)
CSNS
C2 (µF)
RSNS
R1 (Ω)
COUT
C3 (µF)
RCOMP
R7 (kΩ)
CCOMP
C4 (µF)
5VIN, 40-90VOUT at 2.5mA 100 0.047 806 0.1 20 0.22
5VIN, 20-60VOUT at 2.5mA 150 0.10 806 0.047 15 0.22
5VIN, 20-60VOUT at 5mA 82 0.22 392 0.10 10 0.47
3VIN, 40-90VOUT at 2.5mA 33 0.047 806 0.1 20 0.22
3VIN, 4.5-15VOUT at 2.5mA 220 0.47 806 0.01 7.5 0.47
Table 1. Compensation Components for Typical Circuits (Figure 2)
MAX1932 Digitally Controlled, 0.5% Accurate,
Safest APD Bias Supply
Maxim Integrated | 10www.maximintegrated.com
987kΩ
987kΩ
13kΩ
COMP
ERROR
COMPARATOR
CS+
CS-
PWM CONTROL
AND GATE DRIVER GATE
SPI
SERIAL
INTERFACE
SCLK
REF
1.25V
UVLO
FB
ERROR
AMPLIFIER
8-BIT DAC
DIN
8
REF
DACOUT
CLIM
BUFFER
VIN
GND
CL
13kΩ
CS
RAMP
OSC
Figure 1. Functional Diagram
MAX1932 Digitally Controlled, 0.5% Accurate,
Safest APD Bias Supply
Maxim Integrated | 11www.maximintegrated.com
MAX1932
INPUT
2.7V TO 5.5V
VOUT
40V TO 90V
VIN
COMP
SCLK
GND FB
CS-
CS+
GATE
DACOUT
DIN
CS
CL
R7
20kΩ
C4
0.22μF
C1 1μF
R1
806Ω
N1
BSS123
L1
100μH
D1
100V
C2
0.047 C3
0.1μF
R5
1MΩ
R8
32.4kΩ
R6
24.9kΩ
Figure 2. Typical Operating Circuit
DIN
SCLK
18
D7 D6 D5 D4 D3 D2 D1 DO
CS
INSTRUCTION
EXECUTED
Figure 4. Serial Interface Timing Diagram
MAX1932
VOUT
FB
CS-
CS+
GATE
Figure 3. Taking Feedback Ahead of Output Filter
MAX1932 Digitally Controlled, 0.5% Accurate,
Safest APD Bias Supply
Maxim Integrated | 12www.maximintegrated.com
CS
SCLK
DIN
tDS
tDH
tCL
tCH
tCSS0
tCSH0 tCSW
tCSH1
tCSS1
Figure 5. Detailed Serial Interface Timing Diagram
MAX1932 Digitally Controlled, 0.5% Accurate,
Safest APD Bias Supply
Maxim Integrated | 13www.maximintegrated.com
20
FREQUENCY (Hz)
0.01 0.1 1.0
36Hz
100 1k 10k
40
60
80
100
120
POLE1
ZERO1
POLE2
POLE3
AOL
0.0023Hz
36Hz
36Hz
4.2kHz
102dB
0.0023Hz
36Hz
91Hz
4.2kHz
98dB
90V,
1mA
90V,
2.5mA
MAGNITUDE (dB)
91Hz
4.2k
10
Figure 6. Loop Response
MAX1932 Digitally Controlled, 0.5% Accurate,
Safest APD Bias Supply
Maxim Integrated | 14www.maximintegrated.com
MAX1932
VOUT
330μH
0.1μF1μF
FB
CS-
CS+
GATE
VIN
Figure 7. Adding a Post LC Filter
MAX1932
VIN
VOUT
TO CS+ TO CS-
FB
GATE
R1
R5
R8
R9
R10
NTC
THERMISTOR
Figure 8. Adding an NTC Thermistor for Hardware Temperature Compensation; Output Voltage Increases with Temperature Rise
MAX1932 Digitally Controlled, 0.5% Accurate,
Safest APD Bias Supply
Maxim Integrated | 15www.maximintegrated.com
Package Information
For the latest package outline information and land patterns (foot-
prints), go to www.maximintegrated.com/packages. Note that a
“+”, “#”, or “-” in the package code indicates RoHS status only.
Package drawings may show a different suffix character, but the
drawing pertains to the package regardless of RoHS status.
PACKAGE
TYPE
PACKAGE
CODE OUTLINE NO. LAND
PATTERN NO.
12 TQFN T1244-4 21-0139 90-0068
Chip Information
TRANSISTOR COUNT: 1592
PROCESS: BICMOS
MAX1932 Digitally Controlled, 0.5% Accurate,
Safest APD Bias Supply
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent
licenses are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and
max limits) shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc. © 2015 Maxim Integrated Products, Inc. | 16
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim Integrated’s website at www.maximintegrated.com.
Revision History
REVISION
NUMBER
REVISION
DATE
DESCRIPTION
PAGES
CHANGED
2 5/15 Updated Benefits and Features section 1
