– 1 – E01Z20-PS
Sony reserves the right to change products and specifications without pr ior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
CXG1122EN
16 pin VSON (Plastic)
SP5T GSM Triple-Band/GPRS Antenna Switch
Description
The CXG1122EN is one of a range of low inser tion
loss, high power MMIC antenna switches for GSM/
GPRS triple-band, dual-band (CXG1121TN) and
applications. The low insertion loss on transmit
means increased talk time as the Tx power amplifier
can be operated at a lower output level. On-chip logic
reduces the component count and simplifies the PCB
layout by allowing the direct connection of the switch
to digital baseband control lines with the CMOS logic
levels.
This switch is an SP5T, one antenna can be routed
to either of the 2 Tx or 3 Rx ports. It requires 3 CMOS
control lines (CTL1, CTL2 and Tx ON).
The Sony's GaAs JFET process is used for low
insertion loss. An evaluation PCB is available.
Features
•Inser tion loss: (Tx) 0.5dB typ. at 34dBm (GSM900)
•3 CMOS compatible control lines
•Low second harmonic: –40dBm typ. at 34dBm (GSM900)
•Small package size: 16-pin VSON (2.7mm × 3.5mm × 0.9mm)
Applications
Triple-band handsets using the combinations of followings:
•GSM900/DCS1800/PCS1900
•GPRS
•DECT
Structure
GaAs J-FET MMIC
Absolute Maximum Ratings (Ta = 25°C)
•Bias voltage VDD 7V
•Control voltage VCTL 5V
•Operating temperature Topr –20 to +80 °C
GaAs MMICs are ESD sensitive devices. Special handling precautions are required.
– 2 –
CXG1122EN
Pin Configuration
ANT
GND
Tx1
GND
Tx2
GND
V
DD
Tx ON
Rx1
GND
Rx2
GND
Rx3
GND
CTL1
CTL2 1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
T ruth T able
CTL1
H
L
H
L
L
On Pass
ANT – Tx1 GSM900
ANT – Tx2 DCS1800 & PCS1900
ANT – Rx1 GSM900/DCS1800/PCS1900
ANT – Rx2 GSM900/DCS1800/PCS1900
ANT – Rx3 GSM900/DCS1800/PCS1900
CTL2
Don't care
Don't care
L
L
H
Tx ON
H
H
L
L
L
– 3 –
CXG1122EN
Electrical characteristics (Ta = 25°C)
Unit
dB
dB
dB
dB
dB
dB
dB
dB
dB
dBm
dBm
dBm
µA
mA
Max.
0.7
1.2
0.85
1.4
1.4
–36
–30
120
1
Typ.
0.5
1.0
0.65
1.2
1.2
20
16
25
20
1.2
–40
–34
36
80
0.3
Min.
18
14
23
18
Condition
∗1
∗2
∗3
∗4
∗5
∗3
∗4, ∗5
∗1
∗2
∗1, ∗2
∗1, ∗2
VCTL = 3.0V
VDD = 3.3V
Path
Tx1, Tx2 – ANT
Tx1, Tx2 – ANT
Rx1 – ANT
Rx2 – ANT
Rx3 – ANT
ANT – Tx1, Tx2
Tx – Rx1, Rx2, Rx3
Tx – Rx1, Rx2, Rx3
Tx1, Tx2 – ANT
Tx1, Tx2 – ANT
Symbol
IL
ISO
VSWR
2fo
3fo
P1dB
ICTL
ITX/IRX
Item
Insertion loss
Isolation
VSWR
Harmonics∗
P1dB compression
input power
Control current
Supply current for
Tx and Rx modes
Electrical character istics are measured with all the RF ports terminated in 50Ω.
∗Har monics measured with Tx inputs har monically matched. I t is recommended t h a t t h e ha rmonic matching is
used to ensure the optimum performance.
∗1Power incident on GSM Tx, Pin = 34dBm, 880 to 915MHz, VDD = 3.3V, GSM Tx enabled
∗2Power incident on DCS/PCS Tx, Pin = 32dBm, 1710 to 1910MHz, VDD = 3.3V, DCS/PCS Tx enabled
∗3Power incident on ANT, Pin = 10dBm, 925 to 960MHz, VDD = 3.3V, GSM Rx enabled
∗4Power incident on ANT, Pin = 10dBm, 1805 to 1880MHz, VDD = 3.3V, DCS Rx enabled
∗5Power incident on ANT, Pin = 10dBm, 1930 to 1990MHz, VDD = 3.3V, PCS Rx enabled
Supply V oltage V alue (VDD)
Mode
GSM/DCS Tx
GSM/DCS/PCS Rx
Min.
3.0
2.7
Typ.
3.3
3.0
Max.
3.5
3.5
Unit
V
V
Logic
High
Low
Min.
2.4
0
Typ.
2.8 Max.
3.2
0.4
Unit
V
V
CMOS Logic Value
– 4 –
CXG1122EN
DC Block Capacitors and Decoupling Capacitors
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
47pF
100pF
100pF
47pF
22pF
100pF
100pF
22pF
22pF
47pF ANT
GND
Tx1
GND
Tx2
GND
V
DD
Tx ON
Rx1
GND
Rx2
GND
Rx3
GND
CTL1
CTL2
Note) Capacitors are required on all the RF ports for DC blocking (22pF – 47pF). Decoupling capacitors are
required on VDD and on control lines.
– 5 –
CXG1122EN
Application Note
Impedance Matching for Harmonic Minimization
This note outlines the method used to find the source impedance to present to a transmit por t at the second
harmonic frequency (2fo) to reduce the second harmonic level at the antenna.
This should be carried out for a set of devices that represent the process variants. This way a compromise can
be found that suits all the variants.
The necessar y equipment is shown immediately below.
The device should be mounted on a PCB with 50Ω tracks running from all the RF pins to SMA connectors on
the PCB edge (DUT). All the ports should be e xternally DC b loc ked and the unused ports should be terminated in
50Ω. All the measurements should be performed at the incident powers for which the harmonic levels are
specified in this document.
The 2nd harmonic level at the antenna por t is measured using the spectrum analyzer and the vertical and
horizontal position of the load pull stub adjusted such that this level is minimized.
The device should then be removed from the board and an SMA connector mounted such that the source
impedance seen by the transmit por t at 2fo can be measured using a VNA.
Measurements should be de-embedded to the end of the SMA center pin.
A network should then be designed to match the impedance of the low pass filter (LPF), which usually comes
in front of the device, to the 2fo source impedance that gives sufficiently reduced 2fo levels for all the devices
measured.
The network should be designed to maintain a good match and inser tion loss at the fundamental frequency.
Signal
Generator B.P.F. 10dB
Coupler
Power Meter
Diplexer
DC Block
D.U.T.
DC Block
Spectrum
Analyzer
Load Pull
Tuner
Fundamental, fo Second Harmonic, 2fo
– 6 –
CXG1122EN
Package Outline Unit: mm
Sony Corporation
0.05
SONY CODE
EIAJ CODE
JEDEC CODE
PACKAGE MATERIAL
LEAD TREATMENT
LEAD MATERIAL
PACKAGE MASS
EPOXY RESIN
SOLDER PLATING
COPPER ALLOY
PACKAGE STRUCTURE
16PIN VSON (PLASTIC)
VSON-16P-01
0.02 g
A
3.5
2.7
2.5
0.4 B
0.05 MSA-B
S
S
0.6
0.5 ± 0.2
1.4 0.35 ± 0.1
0.35 ± 0.1
TERMINAL SECTION
0.2 ± 0.01
Solder Plating
0.14 – 0.03
0.13 ± 0.025
+ 0.09
(Stand Off)
0.03 ± 0.03
ranges of 0.1mm and 0.25mm from the end of a terminal.
NOTE: 1) The dimensions of the terminal section apply to the
0.15 SB
0.15 SB
A
x2
x4
0.8 – 0.05
+ 0.1
0.23 ± 0.02
LEAD PLATING SPECIFICATIONS
ITEM
LEAD MATERIAL COPPER ALLOY
SOLDER COMPOSITION Sn-Bi Bi:1-4wt%
PLATING THICKNESS 5-18µm
SPEC.
