APPLICATION CIRCUIT
_
+
VDD
VO+
VO-
GND
6
5
8
7
To Battery
Cs
Bias
Circuitry
IN-
IN+
4
3
2
+
-
In From
DAC
SHUTDOWN
RI
RI
1
C(BYPASS)(1)
DGN PACKAGE
(TOP VIEW)
1
2
3
4
8
7
6
5
SHUTDOWN
BYPASS
IN+
IN-
VO-
GND
VDD
VO+
100 kΩ
40 kΩ
40 kΩ
8
SHUTDOWN
BYPASS
IN+
IN-
VO-
GND
VDD
VO+
8-PIN QFN (DRB) PACKAGE
(TOP VIEW)
7
6
5
1
2
3
4
(1) C(BYPASS) is optional.
TPA6211A1
www.ti.com
SLOS367D –AUGUST 2003–REVISED JUNE 2011
3.1-W MONO FULLY DIFFERENTIAL AUDIO POWER AMPLIFIER
Check for Samples: TPA6211A1
1FEATURES APPLICATIONS
2•Designed for Wireless or Cellular Handsets •Ideal for Wireless Handsets, PDAs, and
and PDAs Notebook Computers
•3.1 W Into 3ΩFrom a 5-V Supply at DESCRIPTION
THD = 10% (Typ) The TPA6211A1 is a 3.1-W mono fully-differential
•Low Supply Current: 4 mA Typ at 5 V amplifier designed to drive a speaker with at least
•Shutdown Current: 0.01 μA Typ 3-Ωimpedance while consuming only 20 mm2total
•Fast Startup With Minimal Pop printed-circuit board (PCB) area in most applications.
•Only Three External Components The device operates from 2.5 V to 5.5 V, drawing
–Improved PSRR (-80 dB) and Wide Supply only 4 mA of quiescent supply current. The
Voltage (2.5 V to 5.5 V) for Direct Battery TPA6211A1 is available in the space-saving
Operation 3-mm ×3-mm QFN (DRB) and the 8-pin MSOP
(DGN) PowerPAD™packages.
–Fully Differential Design Reduces RF
Rectification Features like –80 dB supply voltage rejection from
–-63 dB CMRR Eliminates Two Input 20 Hz to 2 kHz, improved RF rectification immunity,
Coupling Capacitors small PCB area, and a fast startup with minimal pop
makes the TPA6211A1 ideal for PDA/smart phone
applications.
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2PowerPAD is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date. Copyright ©2003–2011, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
TPA6211A1
SLOS367D –AUGUST 2003–REVISED JUNE 2011
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION
PACKAGED DEVICES(1)
TAEVALUATION MODULES
SMALL OUTLINE MSOP PowerPAD™
(DRB) (DGN)
–40°C to 85°C TPA6211A1DRB TPA6211A1DGN TPA6211A1EVM
(1) The DGN and DRB are available taped and reeled. To order taped and reeled parts, add the suffix R
to the part number (TPA6211A1DGNR or TPA6211A1DRBR).
Terminal Functions
TERMINAL I/O DESCRIPTION
NAME DRB, DGN
IN- 4 I Negative differential input
IN+ 3 I Positive differential input
VDD 6 I Power supply
VO+ 5 O Positive BTL output
GND 7 I High-current ground
VO- 8 O Negative BTL output
SHUTDOWN 1 I Shutdown terminal (active low logic)
BYPASS 2 Mid-supply voltage, adding a bypass capacitor improves PSRR
Connect to ground. Thermal pad must be soldered down in all applications to properly secure
Thermal Pad - - device on the PCB.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted(1)
UNIT
VDD Supply voltage –0.3 V to 6 V
VIInput voltage –0.3 V to VDD + 0.3 V
Continuous total power dissipation See Dissipation Rating Table
TAOperating free-air temperature –40°C to 85°C
TJJunction temperature –40°C to 150°C
Tstg Storage temperature –65°C to 150°C
(1) Stresses beyond those listed under "absolute maximum ratings"may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions"is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
PACKAGE DISSIPATION RATINGS
TA≤25°C DERATING TA= 70°C TA= 85°C
PACKAGE POWER RATING FACTOR(1) POWER RATING POWER RATING
DGN 2.13 W 17.1 mW/°C 1.36 W 1.11 W
DRB 2.7 W 21.8 mW/°C 1.7 W 1.4 W
(1) Derating factor based on high-k board layout.
2Copyright ©2003–2011, Texas Instruments Incorporated
38 kW
RI
40 kW
RI
42 kW
RI
TPA6211A1
www.ti.com
SLOS367D –AUGUST 2003–REVISED JUNE 2011
RECOMMENDED OPERATION CONDITIONS MIN TYP MAX UNIT
VDD Supply voltage 2.5 5.5 V
VIH High-level input voltage SHUTDOWN 1.55 V
VIL Low-level input voltage SHUTDOWN 0.5 V
TAOperating free-air temperature –40 85 °C
ELECTRICAL CHARACTERISTICS
TA= 25°CPARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Output offset voltage (measured
VOS VI= 0 V differential, Gain = 1 V/V, VDD = 5.5 V -9 0.3 9 mV
differentially)
PSRR Power supply rejection ratio VDD = 2.5 V to 5.5 V –85 –60 dB
VIC Common mode input range VDD = 2.5 V to 5.5 V 0.5 VDD-0.8 V
VDD = 5.5 V, VIC = 0.5 V to 4.7 V -63 –40
CMRR Common mode rejection ratio dB
VDD = 2.5 V, VIC = 0.5 V to 1.7 V -63 –40
VDD = 5.5 V 0.45
RL= 4 Ω, Gain = 1 V/V,
Low-output swing VIN+ = VDD, VIN- = 0 V or VDD = 3.6 V 0.37 V
VIN+ = 0 V, VIN- = VDD VDD = 2.5 V 0.26 0.4
VDD = 5.5 V 4.95
RL= 4 Ω, Gain = 1 V/V,
High-output swing VIN+ = VDD, VIN- = 0 V or VDD = 3.6 V 3.18 V
VIN- = VDD VIN+ = 0 V VDD = 2.5 V 2 2.13
| IIH | High-level input current, shutdown VDD = 5.5 V, VI= 5.8 V 58 100 μA
| IIL | Low-level input current, shutdown VDD = 5.5 V, VI=–0.3 V 3 100 μA
IQQuiescent current VDD = 2.5 V to 5.5 V, no load 4 5 mA
V(SHUTDOWN) ≤0.5 V, VDD = 2.5 V to 5.5 V,
I(SD) Supply current 0.01 1 μA
RL= 4Ω
Gain RL= 4ΩV/V
Resistance from shutdown to GND 100 kΩ
Copyright ©2003–2011, Texas Instruments Incorporated 3
TPA6211A1
SLOS367D –AUGUST 2003–REVISED JUNE 2011
www.ti.com
OPERATING CHARACTERISTICS
TA= 25°C, Gain = 1 V/V
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VDD = 5 V 2.45
THD + N= 1%, f = 1 kHz, RL= 3 ΩVDD = 3.6 V 1.22
VDD = 2.5 V 0.49
VDD = 5 V 2.22
POOutput power THD + N= 1%, f = 1 kHz, RL= 4 ΩVDD = 3.6 V 1.1 W
VDD = 2.5 V 0.47
VDD = 5 V 1.36
THD + N= 1%, f = 1 kHz, RL= 8 ΩVDD = 3.6 V 0.72
VDD = 2.5 V 0.33
PO= 2 W VDD = 5 V 0.045%
f = 1 kHz, RL= 3 ΩPO= 1 W VDD = 3.6 V 0.05%
PO= 300 mW VDD = 2.5 V 0.06%
PO= 1.8 W VDD = 5 V 0.03%
Total harmonic distortion plus
THD+N f = 1 kHz, RL= 4 ΩPO= 0.7 W VDD = 3.6 V 0.03%
noise PO= 300 mW VDD = 2.5 V 0.04%
PO= 1 W VDD = 5 V 0.02%
f = 1 kHz, RL= 8 ΩPO= 0.5 W VDD = 3.6 V 0.02%
PO= 200 mW VDD = 2.5 V 0.03%
f = 217 Hz -80
VDD = 3.6 V, Inputs ac-grounded with
kSVR Supply ripple rejection ratio dB
Ci= 2 μF, V(RIPPLE) = 200 mVpp f = 20 Hz to 20 kHz -70
SNR Signal-to-noise ratio VDD = 5 V, PO= 2 W, RL= 4 Ω105 dB
No weighting 15
VDD = 3.6 V, f = 20 Hz to 20 kHz,
VnOutput voltage noise μVRMS
Inputs ac-grounded with Ci= 2 μFA weighting 12
CMRR Common mode rejection ratio VDD = 3.6 V, VIC = 1 Vpp f = 217 Hz -65 dB
ZIInput impedance 38 40 44 kΩ
VDD = 3.6 V, No CBYPASS 4μs
Start-up time from shutdown VDD = 3.6 V, CBYPASS = 0.1 μF 27 ms
4Copyright ©2003–2011, Texas Instruments Incorporated
0
0.5
1
1.5
2
2.5
3
3.5
2.5 3 3.5 4 4.5 5
VDD - Supply V oltage - V
- Output Power - WP
O
f = 1 kHz
Gain = 1 V/V PO = 3 Ω, THD 10%
PO = 4 Ω, THD 10%
PO = 3 Ω, THD 1%
PO = 4 Ω, THD 1%
PO = 8 Ω, THD 1%
PO = 8 Ω, THD 10%
RL - Load Resistance - Ω
- Output Power - WP
O
0
0.5
1
1.5
2
2.5
3
3.5
3 8 13 18 23 28
VDD = 5 V, THD 1%
VDD = 2.5 V, THD 10%
VDD = 2.5 V, THD 1%
VDD = 5 V, THD 10%
VDD = 3.6 V, THD 10%
VDD = 3.6 V, THD 1%
f = 1 kHz
Gain = 1 V/V
TPA6211A1
www.ti.com
SLOS367D –AUGUST 2003–REVISED JUNE 2011
TYPICAL CHARACTERISTICS
Table of Graphs
FIGURE
vs Supply voltage 1
POOutput power vs Load resistance 2
PDPower dissipation vs Output power 3, 4
vs Output power 5, 6, 7
THD+N Total harmonic distortion + noise vs Frequency 8-12
vs Common-mode input voltage 13
KSVR Supply voltage rejection ratio vs Frequency 14, 15, 16, 17
KSVR Supply voltage rejection ratio vs Common-mode input voltage 18
GSM Power supply rejection vs Time 19
GSM Power supply rejection vs Frequency 20
vs Frequency 21
CMRR Common-mode rejection ratio vs Common-mode input voltage 22
Closed loop gain/phase vs Frequency 23
Open loop gain/phase vs Frequency 24
vs Supply voltage 25
IDD Supply current vs Shutdown voltage 26
Start-up time vs Bypass capacitor 27
OUTPUT POWER OUTPUT POWER
vs vs
SUPPLY VOLTAGE LOAD RESISTANCE
Figure 1. Figure 2.
Copyright ©2003–2011, Texas Instruments Incorporated 5
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0 0.3 0.6 0.9 1.2 1.5 1.8
VDD = 3.6 V
4 Ω
8 Ω
PO - Output Power - W
- Power Dissiaption - WP
D
0
0.2
0.4
0.6
0.8
1
1.2
1.4
0 0.3 0.6 0.9 1.2 1.5 1.8
VDD = 5 V 4 Ω
8 Ω
PO - Output Power - W
- Power Dissiaption - WP
D
0.01
10
0.02
0.05
0.1
0.2
0.5
1
2
5
20m 350m 100m 200m 500m 1 2
PO - Output Power - W
THD+N - Total Harmonic Distortion + Noise - %
RL = 3 Ω,
C(BYPASS) = 0 to 1 µF,
Gain = 1 V/V
2.5 V 3.6 V 5 V
0.01
20
0.02
0.05
0.1
0.2
0.5
1
2
5
10
10m 320m 50m 100m 200m 500m 1 2
PO - Output Power - W
THD+N - Total Harmonic Distortion + Noise - %
2.5 V 3.6 V
5 V
RL = 4 Ω,
C(BYPASS) = 0 to 1 µF,
Gain = 1 V/V
TPA6211A1
SLOS367D –AUGUST 2003–REVISED JUNE 2011
www.ti.com
POWER DISSIPATION POWER DISSIPATION
vs vs
OUTPUT POWER OUTPUT POWER
Figure 3. Figure 4.
TOTAL HARMONIC DISTORTION + NOISE TOTAL HARMONIC DISTORTION + NOISE
vs vs
OUTPUT POWER OUTPUT POWER
Figure 5. Figure 6.
6Copyright ©2003–2011, Texas Instruments Incorporated
0.005
10
0.01
0.02
0.05
0.1
0.2
0.5
1
2
5
20 20k50 100 200 500 1k 2k 5k 10k
f - Frequency - Hz
THD+N - Total Harmonic Distortion + Noise - %
1 W
2 W
VDD = 5 V,
RL = 3 Ω,,
C(BYPASS) = 0 to 1 µF,
Gain = 1 V/V,
CI = 2 µF
0.01
20
0.02
0.05
0.1
0.2
0.5
1
2
5
10
10m 320m 50m 100m 200m 500m 1 2
PO - Output Power - W
THD+N - Total Harmonic Distortion + Noise - %
2.5 V
3.6 V
5 V
RL = 8 Ω,
C(BYPASS) = 0 to 1 µF,
Gain = 1 V/V
0.001
10
0.002
0.005
0.01
0.02
0.05
0.1
0.2
0.5
1
2
5
20 20k50 100 200 500 1k 2k 5k 10k
0.5 W
0.1 W
1 W
f - Frequency - Hz
THD+N - Total Harmonic Distortion + Noise - %
VDD = 3.6 V,
RL = 4 Ω,,
C(BYPASS) = 0 to 1 µF,
Gain = 1 V/V,
CI = 2 µF
0.005
10
0.01
0.02
0.05
0.1
0.2
0.5
1
2
5
20 20k
50 100 200 500 1k 2k 5k 10k
f - Frequency - Hz
THD+N - Total Harmonic Distortion + Noise - %
2 W
1.8 W
1 W
VDD = 5 V,
RL = 4 Ω,,
C(BYPASS) = 0 to 1 µF,
Gain = 1 V/V,
CI = 2 µF
TPA6211A1
www.ti.com
SLOS367D –AUGUST 2003–REVISED JUNE 2011
TOTAL HARMONIC DISTORTION + NOISE TOTAL HARMONIC DISTORTION + NOISE
vs vs
OUTPUT POWER FREQUENCY
Figure 7. Figure 8.
TOTAL HARMONIC DISTORTION + NOISE TOTAL HARMONIC DISTORTION + NOISE
vs vs
FREQUENCY FREQUENCY
Figure 9. Figure 10.
Copyright ©2003–2011, Texas Instruments Incorporated 7
0.001
10
0.002
0.005
0.01
0.02
0.05
0.1
0.2
0.5
1
2
5
20 20k50 100 200 500 1k 2k 5k 10k
0.4 W
0.28 W
f - Frequency - Hz
THD+N - Total Harmonic Distortion + Noise - %
VDD = 2.5 V,
RL = 4 Ω,,
C(BYPASS) = 0 to 1 µF,
Gain = 1 V/V,
CI = 2 µF
0.001
10
0.002
0.005
0.01
0.02
0.05
0.1
0.2
0.5
1
2
5
20 20k50 100 200 500 1k 2k 5k 10k
f - Frequency - Hz
THD+N - Total Harmonic Distortion + Noise - %
0.1 W
0.6 W 0.25 W
VDD = 3.6 V,
RL = 8 Ω,,
C(BYPASS) = 0 to 1 µF,
Gain = 1 V/V,
CI = 2 µF
f - Frequency - Hz
+0
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
20 20k50 100 200 500 1k 2k 5k 10k
kSVR - Supply Voltage Rejection Ratio - dB
VDD = 3.6 V
VDD = 2.5 V
VDD = 5 V
RL = 4 Ω,,
C(BYPASS) = 0.47 µF,
Gain = 1 V/V,
CI = 2 µF,
Inputs ac Grounded
0.04
0.042
0.044
0.046
0.048
0.05
0.052
0.054
0.056
0.058
0.06
0 1 2 3 4 5
f = 1 kHz
PO = 200 mW,
RL = 1 kHz
VIC - Common Mode Input Voltage - V
THD+N - Total Harmonic Distortion + Noise - %
VDD = 3.6 V
VDD = 5 V
VDD = 2.5 V
TPA6211A1
SLOS367D –AUGUST 2003–REVISED JUNE 2011
www.ti.com
TOTAL HARMONIC DISTORTION + NOISE TOTAL HARMONIC DISTORTION + NOISE
vs vs
FREQUENCY FREQUENCY
Figure 11. Figure 12.
TOTAL HARMONIC DISTORTION + NOISE SUPPLY VOLTAGE REJECTION RATIO
vs vs
COMMON MODE INPUT VOLTAGE FREQUENCY
Figure 13. Figure 14.
8Copyright ©2003–2011, Texas Instruments Incorporated
f - Frequency - Hz
+0
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
20 20k50 100 200 500 1k 2k 5k 10k
kSVR - Supply Voltage Rejection Ratio - dB
VDD = 3.6 V
VDD = 2.5 V
RL = 4 Ω,,
C(BYPASS) = 0.47 µF,
Gain = 5 V/V,
CI = 2 µF,
Inputs ac Grounded
VDD = 5 V
f - Frequency - Hz
+0
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
20 20k50 100 200 500 1k 2k 5k 10k
kSVR - Supply Voltage Rejection Ratio - dB
RL = 4 Ω,,
C(BYPASS) = 0.47 µF,
CI = 2 µF,
VDD = 2.5 V to 5 V
Inputs Floating
kSVR − Supply Voltage Rejection Ratio − dB
f − Frequency − Hz
+0
−100
−90
−80
−70
−60
−50
−40
−30
−20
−10
20 20k50 100 200 500 1k 2k 5k 10k
RL = 4 Ω,,
CI = 2 µF,
Gain = 1 V/V,
VDD = 3.6 V
C(BYPASS) = 0.47 µF
C(BYPASS) = 1 µF
C(BYPASS) = 0.1 µF
No C(BYPASS)
−100
−90
−80
−70
−60
−50
−40
−30
−20
−10
0
0 1 2 3 4 5 6
VDD = 5 V
VDD = 3.6 V
VDD = 2.5 V
DC Common Mode Input − V
kSVR − Supply Voltage Rejection Ratio − dB
RL = 4 Ω,,
CI = 2 µF,
Gain = 1 V/V,
C(BYPASS) = 0.47 µF
VDD = 3.6 V,
f = 217 Hz,
Inputs ac Grounded
TPA6211A1
www.ti.com
SLOS367D –AUGUST 2003–REVISED JUNE 2011
SUPPLY VOLTAGE REJECTION RATIO SUPPLY RIPPLE REJECTION RATIO
vs vs
FREQUENCY FREQUENCY
Figure 15. Figure 16.
SUPPLY VOLTAGE REJECTION RATIO SUPPLY VOLTAGE REJECTION RATIO
vs vs
FREQUENCY DC COMMON MODE INPUT
Figure 17. Figure 18.
Copyright ©2003–2011, Texas Instruments Incorporated 9
C1
Frequency
217 Hz
C1 − Duty
20%
C1 Pk−Pk
500 mV
Ch1 100 mV/div
Ch4 10 mV/div 2 ms/div
VDD
VOUT
Voltage − V
t − Time − ms
RL = 8 Ω
CI = 2.2 µF
C(BYPASS) = 0.47 µF
−180
−160
−140
−120
−100
0 400 800 1200 1600 2000
−150
−100
−50
0
f − Frequency − Hz
− Supply Voltage − dBVVDD
VDD Shown in Figure 19,
RL = 8 Ω,
CI = 2.2 µF,
Inputs Grounded
− Output Voltage − dBV
VO
C(BYPASS) = 0.47 µF
TPA6211A1
SLOS367D –AUGUST 2003–REVISED JUNE 2011
www.ti.com
GSM POWER SUPPLY REJECTION
vs
TIME
Figure 19.
GSM POWER SUPPLY REJECTION
vs
FREQUENCY
Figure 20.
10 Copyright ©2003–2011, Texas Instruments Incorporated
f - Frequency - Hz
+0
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
20 20k50 100 200 500 1k 2k 5k 10k
CMRR - Common-Mode Rejection Ratio - dB
VDD = 2.5 V
RL = 4 Ω,,
VIC = 200 mV Vp-p,
Gain = 1 V/V,
VDD = 5 V
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
VDD = 5 V
VDD = 2.5 V
VDD = 3.5 V
VIC - Common Mode Input Voltage - V
CMRR - Common Mode Rejection Ratio - dB
RL = 4 Ω,,
Gain = 1 V/V,
dc Change in VIC
−40
−30
−20
−10
0
10
20
30
40
50
60
70
80
90
100
−180
−150
−120
−90
−60
−30
0
30
60
90
120
150
180
VDD = 5 V,
RL = 8 Ω
Gain
Phase
100 1 k 10 k 100 k 1 M
f − Frequency − Hz
Phase − Degrees
Gain − dB
-80
-70
-60
-50
-40
-30
-20
-10
0
10
20
30
40
-180
-150
-120
-90
-60
-30
0
30
60
90
120
150
180
1 100 10 k 100 k 1 M 10 M1 k
f - Frequency - Hz
Gain - dB
Phase - Degrees
Gain
Phase
VDD = 5 V
RL = 8 Ω
AV = 1
10
TPA6211A1
www.ti.com
SLOS367D –AUGUST 2003–REVISED JUNE 2011
COMMON MODE REJECTION RATIO COMMON-MODE REJECTION RATIO
vs vs
FREQUENCY COMMON-MODE INPUT VOLTAGE
Figure 21. Figure 22.
CLOSED LOOP GAIN/PHASE OPEN LOOP GAIN/PHASE
vs vs
FREQUENCY FREQUENCY
Figure 23. Figure 24.
Copyright ©2003–2011, Texas Instruments Incorporated 11
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5
TA = 25°C
TA = -40°C
TA = 125°C
VDD = 5 V
VDD - Supply V oltage - V
IDD - Supply Current - mA
0.00001
0.0001
0.001
0.01
0.1
1
10
012 3 4 5
VDD = 3.6 V
VDD = 5 V
VDD = 2.5 V
Voltage on SHUTDOWN Terminal - V
IDD - Supply Current - mA
0
50
100
150
200
250
300
0 0.2 0.4 0.6 0.8 1
C(Bypass) - Bypass Capacitor - µF
Start-Up Time - ms
TPA6211A1
SLOS367D –AUGUST 2003–REVISED JUNE 2011
www.ti.com
SUPPLY CURRENT SUPPLY CURRENT
vs vs
SUPPLY VOLTAGE SHUTDOWN VOLTAGE
Figure 25. Figure 26.
START-UP TIME
vs
BYPASS CAPACITOR
Figure 27.
12 Copyright ©2003–2011, Texas Instruments Incorporated
_
+
VDD
VO+
VO−
GND
6
5
8
7
To Battery
Cs
IN−
IN+
4
3
+
−
In From
DAC
RI
RI
40 kΩ
40 kΩ
(1) C(BYPASS) is optional
Bias
Circuitry
2
SHUTDOWN 1
C(BYPASS)(1) 100 kΩ
TPA6211A1
www.ti.com
SLOS367D –AUGUST 2003–REVISED JUNE 2011
APPLICATION INFORMATION
mid-supply voltage affects both positive and
negative channels equally, thus canceling at the
FULLY DIFFERENTIAL AMPLIFIER differential output. Removing the bypass capacitor
The TPA6211A1 is a fully differential amplifier with slightly worsens power supply rejection ratio
differential inputs and outputs. The fully differential (kSVR), but a slight decrease of kSVR may be
amplifier consists of a differential amplifier and a acceptable when an additional component can be
common- mode amplifier. The differential amplifier eliminated (See Figure 17).
ensures that the amplifier outputs a differential •Better RF-immunity: GSM handsets save power
voltage that is equal to the differential input times the by turning on and shutting off the RF transmitter at
gain. The common-mode feedback ensures that the a rate of 217 Hz. The transmitted signal is
common-mode voltage at the output is biased around picked-up on input and output traces. The fully
VDD/2 regardless of the common- mode voltage at the differential amplifier cancels the signal much
input. better than the typical audio amplifier.
Advantages of Fully Differential Amplifiers APPLICATION SCHEMATICS
•Input coupling capacitors not required: A fully
differential amplifier with good CMRR, like the Figure 28 through Figure 31 show application
TPA6211A1, allows the inputs to be biased at schematics for differential and single-ended inputs.
voltage other than mid-supply. For example, if a Typical values are shown in Table 1.
DAC has a lower mid-supply voltage than that of
the TPA6211A1, the common-mode feedback Table 1. Typical Component Values
circuit compensates, and the outputs are still COMPONENT VALUE
biased at the mid-supply point of the TPA6211A1. RI40 kΩ
The inputs of the TPA6211A1 can be biased from C(BYPASS) (1) 0.22 μF
0.5 V to VDD - 0.8 V. If the inputs are biased
outside of that range, input coupling capacitors CS1μF
are required. CI0.22 μF
•Mid-supply bypass capacitor, C(BYPASS), not
required: The fully differential amplifier does not
require a bypass capacitor. Any shift in the (1) C(BYPASS) is optional.
Figure 28. Typical Differential Input Application Schematic
Copyright ©2003–2011, Texas Instruments Incorporated 13
_
+
VDD
VO+
VO−
GND
6
5
8
7
To Battery
Cs
IN−
IN+
4
3
RI
RI
40 kΩ
40 kΩ
+
−CI
CI
(1) C(BYPASS) is optional
Bias
Circuitry
2
SHUTDOWN 1
C(BYPASS)(1) 100 kΩ
IN
CI
CI
_
+
VDD
VO+
VO−
GND
6
5
8
7
To Battery
Cs
IN−
IN+
4
3
RI
RI
40 kΩ
40 kΩ
(1) C(BYPASS) is optional
Bias
Circuitry
2
SHUTDOWN 1
C(BYPASS)(1) 100 kΩ
TPA6211A1
SLOS367D –AUGUST 2003–REVISED JUNE 2011
www.ti.com
Figure 29. Differential Input Application Schematic Optimized With Input Capacitors
Figure 30. Single-Ended Input Application Schematic
14 Copyright ©2003–2011, Texas Instruments Incorporated
_
+
VDD
VO+
VO−
GND
6
5
8
7
To Battery
Cs
IN−
IN+
4
3
RI
RI
40 kΩ
40 kΩ
+
−CI
CI
CF
CF
Ca
Ca
Ra
Ra
(1) C(BYPASS) is optional
Bias
Circuitry
2
SHUTDOWN 1
C(BYPASS)(1) 100 kΩ
Gain = RF/RI
fc+1
2pRICI
-3 dB
fc
TPA6211A1
www.ti.com
SLOS367D –AUGUST 2003–REVISED JUNE 2011
Figure 31. Differential Input Application Schematic With Input Bandpass Filter
Input Capacitor (CI)
Selecting Components The TPA6211A1 does not require input coupling
Resistors (RI)capacitors when driven by a differential input source
biased from 0.5 V to VDD - 0.8 V. Use 1% tolerance
The input resistor (RI) can be selected to set the gain or better gain-setting resistors if not using input
of the amplifier according to equation 1. coupling capacitors.
(1) In the single-ended input application, an input
The internal feedback resistors (RF) are trimmed to capacitor, CI, is required to allow the amplifier to bias
40 kΩ.the input signal to the proper dc level. In this case, CI
and RIform a high-pass filter with the corner
Resistor matching is very important in fully differential frequency defined in Equation 2.
amplifiers. The balance of the output on the reference
voltage depends on matched ratios of the resistors.
CMRR, PSRR, and the cancellation of the second (2)
harmonic distortion diminishes if resistor mismatch
occurs. Therefore, 1%-tolerance resistors or better
are recommended to optimize performance.
Bypass Capacitor (CBYPASS) and Start-Up Time
The internal voltage divider at the BYPASS pin of this
device sets a mid-supply voltage for internal
references and sets the output common mode
voltage to VDD/2. Adding a capacitor filters any noise
into this pin, increasing kSVR. C(BYPASS)also
determines the rise time of VO+ and VO- when the
device exits shutdown. The larger the capacitor, the
slower the rise time. The value of CIis an important consideration. It
Copyright ©2003–2011, Texas Instruments Incorporated 15
fc(HPF) +1
2p10 kWCI
CI+1
2p10 kWfc(HPF)
CI+1
2pRIfc
fc(LPF) +1
2pRaCa
Ca+1
2p1kΩfc(LPF)
fc(LPF) +1
2pRFCF
where RFis the internal 40 kWresistor
fc(LPF) +1
2p40 kWCF
CF+1
2p40 kWfc(LPF)
9 dB
fc(HPF) = 100 Hz
12 dB
AV
+20 dB/dec
−40 dB/dec
−20 dB/dec
f
fc(LPF) = 10 kHz
fc(HPF) +1
2pRICI
where RIis the input resistor
TPA6211A1
SLOS367D –AUGUST 2003–REVISED JUNE 2011
www.ti.com
directly affects the bass (low frequency) performance
of the circuit. Consider the example where RIis 10 (8)
kΩand the specification calls for a flat bass response
down to 100 Hz. Equation 2 is reconfigured as Therefore,
Equation 3.
(9)
(3) Substituting 100 Hz for fc(HPF) and solving for CI:
In this example, CIis 0.16 μF, so the likely choice CI= 0.16 μF
ranges from 0.22 μF to 0.47 μF. Ceramic capacitors
are preferred because they are the best choice in At this point, a first-order band-pass filter has been
preventing leakage current. When polarized created with the low-frequency cutoff set to 100 Hz
capacitors are used, the positive side of the capacitor and the high-frequency cutoff set to 10 kHz.
faces the amplifier input in most applications. The The process can be taken a step further by creating a
input dc level is held at VDD/2, typically higher than second-order high-pass filter. This is accomplished by
the source dc level. It is important to confirm the placing a resistor (Ra) and capacitor (Ca) in the input
capacitor polarity in the application. path. It is important to note that Ramust be at least
10 times smaller than RI; otherwise its value has a
Band-Pass Filter (Ra, Ca, and Ca)noticeable effect on the gain, as Raand RIare in
It may be desirable to have signal filtering beyond the series.
one-pole high-pass filter formed by the combination of
CIand RI. A low-pass filter may be added by placing Step 3: Additional Low-Pass Filter
a capacitor (CF) between the inputs and outputs, Ramust be at least 10x smaller than RI,
forming a band-pass filter. Set Ra=1kΩ
An example of when this technique might be used
would be in an application where the desirable (10)
pass-band range is between 100 Hz and 10 kHz, with
a gain of 4 V/V. The following equations illustrate how Therefore,
the proper values of CFand CIcan be determined.
Step 1: Low-Pass Filter (11)
Substituting 10 kHz for fc(LPF) and solving for Ca:
Ca= 160 pF
(4) Figure 32 is a bode plot for the band-pass filter in the
previous example. Figure 31 shows how to configure
the TPA6211A1 as a band-pass filter.
(5)
Therefore,
(6)
Substituting 10 kHz for fc(LPF) and solving for CF:
CF= 398 pF
Step 2: High-Pass Filter
Figure 32. Bode Plot
(7) Decoupling Capacitor (CS)
Since the application in this case requires a gain of The TPA6211A1 is a high-performance CMOS audio
4 V/V, RImust be set to 10 kΩ.amplifier that requires adequate power supply
Substituting RIinto equation 6. decoupling to ensure the output total harmonic
distortion (THD) is as low as possible. Power-supply
decoupling also prevents oscillations for long lead
16 Copyright ©2003–2011, Texas Instruments Incorporated
RL2x VO(PP)
VO(PP)
-VO(PP)
VDD
VDD
fc+1
2pRLCC
V(rms) +
VO(PP)
2 2
Ǹ
Power +
V(rms)2
RL
TPA6211A1
www.ti.com
SLOS367D –AUGUST 2003–REVISED JUNE 2011
lengths between the amplifier and the speaker. For
higher frequency transients, spikes, or digital hash on
the line, a good low equivalent-series-resistance
(ESR) ceramic capacitor, typically 0.1 μF to 1 μF,
placed as close as possible to the device VDD lead
works best. For filtering lower frequency noise
signals, a 10-μF or greater capacitor placed near the
audio power amplifier also helps, but is not required
in most applications because of the high PSRR of this
device.
USING LOW-ESR CAPACITORS
Low-ESR capacitors are recommended throughout
this applications section. A real (as opposed to ideal)
capacitor can be modeled simply as a resistor in Figure 33. Differential Output Configuration
series with an ideal capacitor. The voltage drop
across this resistor minimizes the beneficial effects of
the capacitor in the circuit. The lower the equivalent In a typical wireless handset operating at 3.6 V,
value of this resistance the more the real capacitor bridging raises the power into an 8-Ωspeaker from a
behaves like an ideal capacitor. singled-ended (SE, ground reference) limit of 200
mW to 800 mW. This is a 6-dB improvement in sound
DIFFERENTIAL OUTPUT VERSUS power—loudness that can be heard. In addition to
SINGLE-ENDED OUTPUT increased power, there are frequency-response
concerns. Consider the single-supply SE
Figure 33 shows a Class-AB audio power amplifier configuration shown in Figure 34. A coupling
(APA) in a fully differential configuration. The capacitor (CC) is required to block the dc-offset
TPA6211A1 amplifier has differential outputs driving voltage from the load. This capacitor can be quite
both ends of the load. One of several potential large (approximately 33 μF to 1000 μF) so it tends to
benefits to this configuration is power to the load. The be expensive, heavy, occupy valuable PCB area, and
differential drive to the speaker means that as one have the additional drawback of limiting
side is slewing up, the other side is slewing down, low-frequency performance. This frequency-limiting
and vice versa. This in effect doubles the voltage effect is due to the high-pass filter network created
swing on the load as compared to a with the speaker impedance and the coupling
ground-referenced load. Plugging 2 ×VO(PP) into the capacitance. This is calculated with Equation 13.
power equation, where voltage is squared, yields 4×
the output power from the same supply rail and load
impedance Equation 12.(13)
(12)
Copyright ©2003–2011, Texas Instruments Incorporated 17
RL
CCVO(PP)
VO(PP)
VDD
-3 dB
fc
V(LRMS)
VO
IDD
IDD(avg)
TPA6211A1
SLOS367D –AUGUST 2003–REVISED JUNE 2011
www.ti.com
For example, a 68-μF capacitor with an 8-Ωspeaker subtracting the RMS value of the output voltage from
would attenuate low frequencies below 293 Hz. The VDD. The internal voltage drop multiplied by the
BTL configuration cancels the dc offsets, which average value of the supply current, IDD(avg),
eliminates the need for the blocking capacitors. determines the internal power dissipation of the
Low-frequency performance is then limited only by amplifier.
the input network and speaker response. Cost and An easy-to-use equation to calculate efficiency starts
PCB space are also minimized by eliminating the out as being equal to the ratio of power from the
bulky coupling capacitor. power supply to the power delivered to the load. To
accurately calculate the RMS and average values of
power in the load and in the amplifier, the current and
voltage waveform shapes must first be understood
(see Figure 35).
Figure 34. Single-Ended Output and Frequency Figure 35. Voltage and Current Waveforms for
Response BTL Amplifiers
Increasing power to the load does carry a penalty of Although the voltages and currents for SE and BTL
increased internal power dissipation. The increased are sinusoidal in the load, currents from the supply
dissipation is understandable considering that the are different between SE and BTL configurations. In
BTL configuration produces 4×the output power of an SE application the current waveform is a
the SE configuration. half-wave rectified shape, whereas in BTL it is a
full-wave rectified waveform. This means RMS
conversion factors are different. Keep in mind that for
FULLY DIFFERENTIAL AMPLIFIER most of the waveform both the push and pull
EFFICIENCY AND THERMAL INFORMATION transistors are not on at the same time, which
Class-AB amplifiers are inefficient, primarily because supports the fact that each amplifier in the BTL
of voltage drop across the output-stage transistors. device only draws current from the supply for half the
The two components of this internal voltage drop are waveform. The following equations are the basis for
the headroom or dc voltage drop that varies inversely calculating amplifier efficiency.
to output power, and the sinewave nature of the
output. The total voltage drop can be calculated by
18 Copyright ©2003–2011, Texas Instruments Incorporated
Efficiency of a BTL amplifier +PL
PSUP
Where:
PL+VLrms2
RL, andVLRMS +VP
2
Ǹ, therefore, PL+VP2
2RL
PL = Power delivered to load
PSUP = Power drawn from power supply
VLRMS = RMS voltage on BTL load
RL = Load resistance
VP = Peak voltage on BTL load
IDDavg = Average current drawn from the power supply
VDD = Power supply voltage
ηBTL = Efficiency of a BTL amplifier
and PSUP +VDD IDDavg and IDDavg +1
pŕp
0
VP
RLsin(t) dt + * 1
p VP
RL[cos(t)]p
0+2VP
pRL
Therefore,
PSUP +2 VDD VP
pRL
substituting PL and PSUP into equation 6,
Efficiency of a BTL amplifier +
VP2
2 RL
2 VDD VP
pRL
+
pVP
4 VDD
VP+2 PLRL
Ǹ
Where:
hBTL +
p2 PLRL
Ǹ
4 VDD
Therefore,
TPA6211A1
www.ti.com
SLOS367D –AUGUST 2003–REVISED JUNE 2011
(14)
(15)
Table 2. Efficiency and Maximum Ambient Temperature vs Output Power
Output Power Efficiency Internal Dissipation Power From Supply Max Ambient Temperature (1)
(W) (%) (W) (W) (°C)
5-V, 3-ΩSystems
0.5 27.2 1.34 1.84 85(2)
1 38.4 1.60 2.60 76
2.45 60.2 1.62 4.07 75
3.1 67.7 1.48 4.58 82
5-V, 4-ΩBTL Systems
0.5 31.4 1.09 1.59 85(2)
1 44.4 1.25 2.25 85(2)
2 62.8 1.18 3.18 85(2)
2.8 74.3 0.97 3.77 85(2)
5-V, 8-ΩSystems
0.5 44.4 0.625 1.13 85(2)
1 62.8 0.592 1.60 85(2)
1.36 73.3 0.496 1.86 85(2)
1.7 81.9 0.375 2.08 85(2)
(1) DRB package
(2) Package limited to 85°C ambient
Copyright ©2003–2011, Texas Instruments Incorporated 19
θJA +1
Derating Factor +1
0.0218 +45.9°CńW
TAMax +TJMax *θJA PDmax
+150 *45.9(1.27)+91.7°C
PDmax +2V2
DD
p2RL
TPA6211A1
SLOS367D –AUGUST 2003–REVISED JUNE 2011
www.ti.com
Table 2 employs Equation 15 to calculate efficiencies The maximum ambient temperature depends on the
for four different output power levels. Note that the heat sinking ability of the PCB system. The derating
efficiency of the amplifier is quite low for lower power factor for the 3 mm ×3 mm DRB package is shown in
levels and rises sharply as power to the load is the dissipation rating table. Converting this to θJA:
increased resulting in a nearly flat internal power
dissipation over the normal operating range. Note that (17)
the internal dissipation at full output power is less
than in the half power range. Calculating the Given θJA, the maximum allowable junction
efficiency for a specific system is the key to proper temperature, and the maximum internal dissipation,
power supply design. For a 2.8-W audio system with the maximum ambient temperature can be calculated
4-Ωloads and a 5-V supply, the maximum draw on with Equation 18. The maximum recommended
the power supply is almost 3.8 W. junction temperature for the TPA6211A1 is 150°C.
A final point to remember about Class-AB amplifiers
is how to manipulate the terms in the efficiency (18)
equation to the utmost advantage when possible.
Note that in Equation 15, VDD is in the denominator. Equation 18 shows that the maximum ambient
This indicates that as VDD goes down, efficiency goes temperature is 91.7°C (package limited to 85°C
up. ambient) at maximum power dissipation with a 5-V
supply.
A simple formula for calculating the maximum power
dissipated, PDmax, may be used for a differential Table 2 shows that for most applications no airflow is
output application: required to keep junction temperatures in the
specified range. The TPA6211A1 is designed with
thermal protection that turns the device off when the
junction temperature surpasses 150°C to prevent
(16) damage to the IC. In addition, using speakers with an
PDmax for a 5-V, 4-Ωsystem is 1.27 W. impedance higher than 4-Ωdramatically increases
the thermal performance by reducing the output
current.
20 Copyright ©2003–2011, Texas Instruments Incorporated
0,65 mm
0,38 mm
Solder Mask: 1,4 mm x 1,85 mm centered in package
0,7 mm
1,4 mm
Make solder paste a hatch pattern to fill 50%
3,3 mm
1,95 mm
0,33 mm plugged vias (5 places)
TPA6211A1
www.ti.com
SLOS367D –AUGUST 2003–REVISED JUNE 2011
PCB LAYOUT
Use the following land pattern for board layout with the 8-pin QFN (DRB) package. Note that the solder paste
should use a hatch pattern to fill solder paste at 50% to ensure that there is not too much solder paste under the
package.
Figure 36. TPA6211A1 8-Pin QFN (DRB) Board Layout (Top View)
Copyright ©2003–2011, Texas Instruments Incorporated 21
PACKAGE OPTION ADDENDUM
www.ti.com 18-Jun-2011
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
TPA6211A1DGN ACTIVE MSOP-
PowerPAD DGN 8 80 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPA6211A1DGNG4 ACTIVE MSOP-
PowerPAD DGN 8 80 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPA6211A1DGNR ACTIVE MSOP-
PowerPAD DGN 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPA6211A1DGNRG4 ACTIVE MSOP-
PowerPAD DGN 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPA6211A1DRB ACTIVE SON DRB 8 121 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPA6211A1DRBG4 ACTIVE SON DRB 8 121 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPA6211A1DRBR ACTIVE SON DRB 8 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPA6211A1DRBRG4 ACTIVE SON DRB 8 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
PACKAGE OPTION ADDENDUM
www.ti.com 18-Jun-2011
Addendum-Page 2
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TPA6211A1 :
•Automotive: TPA6211A1-Q1
NOTE: Qualified Version Definitions:
•Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TPA6211A1DGNR MSOP-
Power
PAD
DGN 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
TPA6211A1DGNR MSOP-
Power
PAD
DGN 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
TPA6211A1DRBR SON DRB 8 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
TPA6211A1DRBR SON DRB 8 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPA6211A1DGNR MSOP-PowerPAD DGN 8 2500 358.0 335.0 35.0
TPA6211A1DGNR MSOP-PowerPAD DGN 8 2500 364.0 364.0 27.0
TPA6211A1DRBR SON DRB 8 3000 367.0 367.0 35.0
TPA6211A1DRBR SON DRB 8 3000 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
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