May 1998
NDT3055
N-Channel Enhancement Mode Field Effect Transistor
General Description Features
Absolute Maximum Ratings TA = 25oC unless otherwise noted
Symbol Parameter NDT3055 Units
VDSS Drain-Source Voltage 60 V
VGSS Gate-Source Voltage - Continuous ±20 V
IDMaximum Drain Current - Continuous (Note 1a) 4A
- Pulsed 25
PDMaximum Power Dissipation (Note 1a)3W
(Note 1b) 1.3
(Note 1c)1.1
TJ,TSTG Operating and Storage Temperature Range -65 to 150 °C
THERMAL CHARACTERISTICS
RθJA Thermal Resistance, Junction-to-Ambient (Note 1a) 42 °C/W
RθJC Thermal Resistance, Junction-to-Case (Note 1) 12 °C/W
* Order option J23Z for cropped center drain lead.
NDT3055 Rev.B
4 A, 60 V. RDS(ON) = 0.100 @ VGS = 10 V.
High density cell design for extremely low RDS(ON).
High power and current handling capability in a widely used
surface mount package.
SOIC-16
SuperSOTTM-3 SuperSOTTM-8 SO-8 SOT-223
SuperSOTTM-6
These N-Channel enhancement mode power field effect
transistors are produced using Fairchild's proprietary,
high cell density, DMOS technology. This very high
density process is especially tailored to minimize
on-state resistance and provide superior switching
performance. These devices are particularly suited for
low voltage applications such as DC motor control and
DC/DC conversion where fast switching, low in-line
power loss, and resistance to transients are needed.
G
D
S
D
SOT-223
D
DS
GG
D
S
SOT-223*
(J23Z)
D
S
G
© 1998 Fairchild Semiconductor Corporation
Electrical Characteristics (TA = 25 OC unless otherwise noted )
Symbol Parameter Conditions Min Typ Max Units
OFF CHARACTERISTICS
BVDSS Drain-Source Breakdown Voltage VGS = 0 V, ID = 250 µA 60 V
BVDSS/TJBreakdown Voltage Temp. Coefficient ID = 250 µA, Referenced to 25 o C63 mV/o C
IDSS Zero Gate Voltage Drain Current VDS = 48 V, VGS = 0 V 10 µA
TJ =125°C 100 µA
IGSSF Gate - Body Leakage, Forward VGS = 20 V, VDS = 0 V 100 nA
IGSSR Gate - Body Leakage, Reverse VGS = -20 V, VDS = 0 V -100 nA
ON CHARACTERISTICS (Note 2)
VGS(th) Gate Threshold Voltage VDS = VGS, ID = 250 µA 2 3 4 V
TJ =125°C 1.5 2.4 3
RDS(ON) Static Drain-Source On-Resistance VGS = 10 V, ID = 4 A0.084 0.1
TJ =125°C 0.14 0.18
ID(ON) On-State Drain Current VGS = 10 V, VDS = 10 V 15 A
gFS Forward Transconductance VDS = 15 V, ID = 4 A 6S
DYNAMIC CHARACTERISTICS
Ciss Input Capacitance VDS = 30 V, VGS = 0 V,
f = 1.0 MHz 250 pF
Coss Output Capacitance 100 pF
Crss Reverse Transfer Capacitance 30 pF
SWITCHING CHARACTERISTICS (Note 2)
tD(on)Turn - On Delay Time VDD = 25 V, ID = 1.2 A,
VGS = 10 V, RGEN = 50 10 25 ns
trTurn - On Rise Time 18 50 ns
tD(off) Turn - Off Delay Time 37 65 ns
tfTurn - Off Fall Time 30 60 ns
QgTotal Gate Charge VDS = 40 V, ID = 4 A,
VGS = 10 V 9 15 nC
Qgs Gate-Source Charge 2.3 nC
Qgd Gate-Drain Charge 2.6 nC
DRAIN-SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS
ISMaximum Continuous Drain-Source Diode Forward Current 2.5 A
VSD Drain-Source Diode Forward Voltage VGS = 0 V, IS = 2.5 A (Note 2)0.85 1.2 V
Notes:
1. RθJA is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. RθJC is
guaranteed by design while RθCA is determined by the user's board design.
Typical RθJA using the board layouts shown below on FR-4 PCB in a still air environment:
Scale 1 : 1 on letter size paper
2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%
NDT3055 Rev.B
a. 42oC/W when mounted on a 1 in2 pad of
2oz Cu. b. 95oC/W when mounted on a 0.066 in2
pad of 2oz Cu. c. 110oC/W when mounted on a 0.00123
in2 pad of 2oz Cu.
NDT3055 Rev.B
Typical Electrical Characteristics
Figure 1. On-Region Characteristics.Figure 2. On-Resistance Variation with
Drain Current and Gate Voltage.
Figure 3. On-Resistance Variation
with Temperature.
Figure 5. Transfer Characteristics.
Figure 4. On-Resistance Variation with
Gate-to- Source Voltage.
-50 -25 0 25 50 75 100 125 150
0.4
0.8
1.2
1.6
2
T , JUNCTION TEMPERATURE (°C)
DRAIN-SOURCE ON-RESISTANCE
J
V =10V
GS
I = 4A
D
R , NORMALIZED
DS(ON)
012345
0
3
6
9
12
15
V , DRAIN-SOURCE VOLTAGE (V)
I , DRAIN-SOURCE CURRENT (A)
DS
D
V =10V
GS
6.0V
4.5V
5.0V
7.0V
5.5V
8.0V
04812 16 20
0.5
1
1.5
2
2.5
3
I , DRAIN CURRENT (A)
DRAIN-SOURCE ON-RESISTANCE
V = 5.5V
GS
D
R , NORMALIZED
DS(ON)
6.0V
10V
8.0V
7.0V
6.5V
2468
0
2
4
6
8
10
V , GATE TO SOURCE VOLTAGE (V)
I , DRAIN CURRENT (A)
25°C
125°C
V = 10V
DS
GS
D
T = -55°C
J
00.2 0.4 0.6 0.8 11.2
0.0001
0.001
0.01
0.1
1
10
V , BODY DIODE FORWARD VOLTAGE (V)
I , REVERSE DRAIN CURRENT (A)
T = 125°C
A
25°C
-55°C
V = 0V
GS
SD
S
Figure 6. Body Diode Forward Voltage
Variation with Current and
Temperature.
4 6 8 10
0
0.1
0.2
0.3
0.4
V , GATE TO SOURCE VOLTAGE (V)
R , ON-RESISTANCE (OHM)
DS(ON)
GS
T = 25°C
A
T = 125°C
A
I = 2A
D
NDT3055 Rev.B
Figure 10. Single Pulse Maximum Power
Dissipation.
Figure 8. Capacitance Characteristics.
Figure 7. Gate Charge Characteristics.
Figure 9. Maximum Safe Operating Area.
Typical Electrical Characteristics (continued)
0.0001 0.001 0.01 0.1 110 100 300
0.001
0.002
0.005
0.01
0.02
0.05
0.1
0.2
0.5
1
t , TIME (sec)
TRANSIENT THERMAL RESISTANCE
r(t), NORMALIZED EFFECTIVE
1
Single Pulse
D = 0.5
0.1
0.05
0.02
0.01
0.2
Duty Cycle, D = t / t
1 2
R (t) = r(t) * R
R = 110 °C/W
T - T = P * R (t)
A
J
P(pk)
t
1 t
2
θJA
θJA
θJA
θJA
Figure 11. Transient Thermal Response Curve.
Thermal characterization performed using the conditions described in note 1c.
Transient thermal response will change depending on the circuit board design.
0.1 0.3 1 4 10 30 60
10
20
50
100
200
500
1000
V , DRAIN TO SOURCE VOLTAGE (V)
CAPACITANCE (pF)
DS
C
iss
f = 1 MHz
V = 0V
GS
C
oss
C
rss
036912 15
0
3
6
9
12
15
Q , GATE CHARGE (nC)
V , GATE-SOURCE VOLTAGE (V)
g
GS
I = 4A
DV = 10V
DS
40V
20V
0.1 0.2 0.5 1 2 5 10 30 60 100
0.01
0.03
0.1
0.3
1
3
10
50
V , DRAIN-SOURCE VOLTAGE (V)
I , DRAIN CURRENT (A)
DS
D
1s
100ms
10s
10ms
RDS(ON) LIMIT
1ms
DC
V = 10V
SINGLE PULSE
R = 110 C/W
T = 25°C
GS
A
θJA o
100us
0.001 0.01 0.1 110 100 300
0
20
40
60
80
SINGLE PULSE TIME (SEC)
POWER (W)
SINGLE PULSE
R =110°C/W
T = 25°C
θJA
A
TRADEMARKS
ACEx™
CoolFET™
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E2CMOSTM
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Obsolete
This datasheet contains the design specifications for
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any manner without notice.
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supplementary data will be published at a later date.
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changes at any time without notice in order to improve
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