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_______________General Description
The MAX793/MAX794/MAX795 microprocessor (µP)
supervisory circuits monitor and control the activities of
+3.0V/+3.3V µPs by providing backup-battery switchover,
among other features such as low-line indication, µP
reset, write protection for CMOS RAM, and a watchdog
(see the
Selector Guide
below). The backup-battery volt-
age can exceed VCC, permitting the use of 3.6V lithium
batteries in systems using 3.0V to 3.3V for VCC.
The MAX793/MAX795 offer a choice of reset threshold
voltage range (denoted by suffix letter): 3.00V to 3.15V
(T), 2.85V to 3.00V (S), and 2.55V to 2.70V (R). The
MAX794’s reset threshold is set externally with a resistor
divider. The MAX793/MAX794 are available in 16-pin
DIP and narrow SO packages, and the MAX795 comes
in 8-pin DIP and SO packages. For similar devices
designed for 5V systems, see the
µP Supervisory
Circuits
table at the back of this data sheet.
________________________Applications
Battery-Powered Computers and Controllers
Embedded Controllers
Intelligent Controllers
Critical µP Power Monitoring
Portable Equipment
____________________________Features
MAX793/MAX794/MAX795
♦Precision Supply-Voltage Monitor:
Fixed Reset Trip Voltage (MAX793/MAX795)
Adjustable Reset Trip Voltage (MAX794)
♦Guaranteed Reset Assertion to VCC = 1V
♦Backup-Battery Power Switching—Battery
Voltage Can Exceed VCC
♦On-Board Gating of Chip-Enable Signals—7ns
Max Propagation Delay
MAX793/MAX794 Only
♦Battery Freshness Seal
♦Battery OK Output (MAX793)
♦Uncommitted Voltage Monitor for Power-Fail or
Low-Battery Warning
♦Independent Watchdog Timer (1.6sec timeout)
♦Manual Reset Input
______________Ordering Information
Ordering Information continued on last page.
* The MAX793/MAX795 offer a choice of reset threshold voltage.
Select the letter corresponding to the desired reset threshold
voltage range (T = 3.00V to 3.15V, S = 2.85V to 3.00V, R = 2.55V
to 2.70V) and insert it into the blank to complete the part number.
The MAX794’s reset threshold is adjustable.
MAX793/MAX794/MAX795
3.0V/3.3V Adjustable Microprocessor
Supervisory Circuits
________________________________________________________________
Maxim Integrated Products
1
MAX793
RESET
LOWLINE
WDI
CE IN
CE OUT
3.0V OR 3.3V
+5V
BATT
A0-A15
MR
+5V SUPPLY
FAILURE
BATT ON
PFI
WDO
OUT CMOS
RAM
ADDRESS
DECODER
0.1µF
PMOS
0.1µF
VCC
PFO
GND
I/O
µP
NMI
RESET
VCC
VCC
0.1µF
3.6V
BATT OK
(OPTIONAL)
Si9433DY
SILICONIX
19-0366; Rev 1; 1/96
PART*
MAX793_CPE
MAX793_CSE
MAX793_EPE -40°C to +85°C
0°C to +70°C
0°C to +70°C
TEMP. RANGE PIN-PACKAGE
16 Plastic DIP
16 Narrow SO
16 Plastic DIP
MAX793_ESE -40°C to +85°C 16 Narrow SO
FEATURE
Active-Low Reset
Active-High Reset
Programmable Reset
Threshold
Low-Line Early Warning
Output
MAX793
✔
✔
✔
MAX794
✔
✔
✔
✔
MAX795
✔
Backup-Battery
Switchover
External Switch Driver
Power-Fail Comparator
✔
✔
✔
✔
✔
✔
Battery OK Output ✔
✔
✔
_____________________Selector Guide
__________Typical Operating Circuit
Watchdog Input
Battery Freshness Seal ✔
✔
✔
✔
Manual Reset Input ✔
✔
✔
Chip-Enable Gating ✔ ✔
Pins-Package 16-DIP/SO 16-DIP/SO 8-DIP/SO
Pin Configurations appear at end of data sheet.
µA
MAX793/MAX794/MAX795
3.0V/3.3V Adjustable Microprocessor
Supervisory Circuits
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
(VCC = 3.17V to 5.5V for the MAX793T/MAX795T, VCC = 3.02V to 5.5V for the MAX793S/MAX795S, VCC = 2.72V to 5.5V for the
MAX793R/MAX794/MAX795R, VBATT = 3.6V, TA= TMIN to TMAX, unless otherwise noted. Typical values are at TA= +25°C.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
Terminal Voltage (with respect to GND)
VCC ........................................................................-0.3V to 6.0V
VBATT .....................................................................-0.3V to 6.0V
All Other Inputs ..................-0.3V to the higher of VCC or VBATT
Continuous Input Current
VCC .................................................................................200mA
VBATT ................................................................................50mA
GND..................................................................................20mA
Output Current
VOUT................................................................................200mA
All Other Outputs ..............................................................20mA
Continuous Power Dissipation (TA= +70°C)
8-Pin Plastic DIP (derate 9.09mW/°C above +70°C) .....727mW
8-Pin SO (derate 5.88mW/°C above +70°C)..................471mW
16-Pin Plastic DIP (derate 10.53mW/°C above +70°C) .842mW
16-Pin Narrow SO (derate 9.52mW/°C above +70°C)...696mW
Operating Temperature Ranges
MAX793_C_ _/MAX794C_ _/MAX795_C_ _......... 0°C to +70°C
MAX793_E_ _/MAX794E_ _/MAX795_E_ _........-40°C to +85°C
Storage Temperature Range.............................-65°C to +160°C
Lead Temperature (soldering, 10sec).............................+300°C
MAX79_E
MAX79_C
VBATT > VCC
(Note 6)
IOUT = 250µA (Note 4)
IOUT = 30mA (Note 4)
VSW > VCC > 1.75V (Note 5)
IOUT = 75mA
VBATT = 2.3V
CONDITIONS
Battery Switch Threshold
(VCC falling) V
2.30 2.41 2.52
VSW 2.55 2.68 2.80
2.69 2.82 2.95
mV20 65
VCC -
VBATT
V
VBATT - 0.14
VOUT
OUT Output Voltage in
Battery-Backup Mode VBATT - 0.1 VBATT - 0.034
V
1.1 5.5
1.0 5.5
Operating Voltage Range,
VCC, VBATT (Note 1)
V
VCC - 0.001 VCC - 0.5mV
VOUT
OUT Output Voltage in
Normal Mode VCC - 0.12 VCC - 0.050
VCC - 0.3 VCC - 0.125
µA0.5
Battery Leakage Current
(Note 3)
µA1
BATT Supply Current
(excluding IOUT) (Note 2)
UNITSMIN TYP MAXSYMBOLPARAMETER
VCC = 0V, VOUT = 0V µA1
BATT Leakage Current,
Freshness Seal Enabled
IOUT = 250µA
IOUT = 1mA
MAX793T/MAX795T
MAX793S/MAX795S
This value is identical to the reset threshold,
VCC rising for VBATT > VRST
VCC -
VBATT
MAX793R/MAX795R/
MAX794
VBATT < VRST mV25 65
Battery Switch Threshold
(VCC rising) (Note 7)
MAX793/MAX794,
MR = VCC µA
62 80
ISUPPLY
46 60
VCC Supply Current
(excluding IOUT, ICE OUT)
VCC = 2.1V,
VBATT = 2.3V µA
32 45
ISUPPLY
VCC Supply Current in
Battery-Backup Mode
(excluding IOUT)
VCC < 3.6V
VCC < 5.5V
MAX793/MAX794
MAX795 24 35
MAX795 49 70
35 50VCC < 3.6V
VCC < 5.5V
MAX793/MAX794/MAX795
3.0V/3.3V Adjustable Microprocessor
Supervisory Circuits
_______________________________________________________________________________________ 3
ELECTRICAL CHARACTERISTICS (continued)
(VCC = 3.17V to 5.5V for the MAX793T/MAX795T, VCC = 3.02V to 5.5V for the MAX793S/MAX795S, VCC = 2.72V to 5.5V for the
MAX793R/MAX794/MAX795R, VBATT = 3.6V, TA= TMIN to TMAX, unless otherwise noted. Typical values are at TA= +25°C.)
CONDITIONS
2.85 2.925 3.00
3.00 3.075 3.15 UNITSMIN TYP MAXSYMBOLPARAMETER
VCC Falling
3.00 3.085 3.17
2.55 2.625 2.70
VRST V
VRST IN V
VCC Falling
VCC Rising
RESET IN Threshold
(MAX794 only) 1.212 1.240 1.262
Reset Threshold (Note 8)
2.55 2.635 2.72
2.85 2.935 3.02
VLR mV
MAX793
LOWLINE-to-Reset
Threshold, (V LOWLINE -
VRST), VCC Falling
VCC < 3.6V
51525
30 45 60
mV
MAX793S/MAX795S
MAX793T/MAX795T
MAX794
MAX793
3.08
Low-Line Comparator
Hysteresis 3.23
mV
10
10
mstRP 140 200 280Reset Timeout Period
V
MAX793R/MAX795R 2.78
nA
VPFI rising
VPFI falling
PFI Input Current
MAX794
V
-25 2 25
VTH 1.212 1.250 1.287
PFI Input Threshold 1.212 1.240 1.262
VLL
1.317
LOWLINE Threshold,
VCC Rising
VVBOK 2.00 2.25 2.50
BATT OK Threshold
(MAX793)
VOH VISOURCE = 300µA, VCC = VRST max
BATT OK, BATT ON, WDO,
LOWLINE Output Voltage
High
ISOURCE =300µA, VCC = VRST min
0.8VCC 0.86VCC
VVOH 0.8VCC 0.86VCC
RESET Output Voltage High
mV10 20PFI Hysteresis, PFI Rising
MAX793T/MAX795T
MAX793S/MAX795S
MAX793R/MAX795R
MAX793T/MAX795T
MAX793S/MAX795S
MAX793R/MAX795R
nA
RESET IN Leakage Current
(MAX794 only) -25 2 25
MAX794
VOH VISOURCE = 65µA, VCC = VRST maxPFO Output Voltage High 0.8VCC
VOH VISOURCE = 100µA, VCC = 2.3V, VBATT = 3V
BATT ON Output
Voltage High 0.8VBATT
ILEAK µAVCC = VRST max
RESET Output Leakage
Current (Note 9) -1 -1
ISC µAVCC = 3.3V, V PFO = 0V
PFO Output Short to GND
Current 180 500
VOL V
ISINK = 1.2mA; RESET, LOWLINE tested
with VCC = VRST min; RESET, BATTOK,
WDO tested with VCC = VRST max
PFO, RESET, RESET, WDO,
LOWLINE Output Voltage
Low 0.08 0.2VCC
INPUT AND OUTPUT LEVELS
VCC Rising 1.212 1.250 1.282
MAX793/MAX794/MAX795
3.0V/3.3V Adjustable Microprocessor
Supervisory Circuits
4 _______________________________________________________________________________________
CONDITIONS
VOL V
VOL VISINK = 3.2mA, VCC = VRST max
MAX79_E, VBATT = VCC = 1.2V, ISINK = 200µA
BATT ON Output
Voltage Low
MAX79_C, VBATT = VCC = 1.0V, I SINK = 40µA
0.2VCC
RESET Output Voltage Low
UNITSMIN TYP MAXSYMBOLPARAMETER
VIL V
tMR nsMAX793/MAX794 only
VRST max < VCC < 5.5V
MR Pulse Width 100 50
All Inputs Including PFO
(Note 10) 0.3VCC
VIH 0.7VCC
0.17 0.3
0.13 0.3
ELECTRICAL CHARACTERISTICS (continued)
(VCC = 3.17V to 5.5V for the MAX793T/MAX795T, VCC = 3.02V to 5.5V for the MAX793S/MAX795S, VCC = 2.72V to 5.5V for the
MAX793R/MAX794/MAX795R, VBATT = 3.6V, TA= TMIN to TMAX, unless otherwise noted. Typical values are at TA= +25°C.)
tMD ns
MAX793/MAX794 only, MR = 0V
MAX793/MAX794 only µA
MR-to-Reset Delay 25 70 250MR Pull-Up Current 75 250
Ω
nsVCC = VRST max, Figure 9
Enable mode, VCC = VRST max
CE IN-to-CE OUT
Propagation Delay
Disable mode
27
CE IN-to-CE OUT
Resistance
VOH
VOL
V
VCC = VRST max, IOUT = 1.6mA,
V CE IN = 0V
VCC = VRST max, IOUT = -1mA,
V CE IN = VCC
CE OUT Drive from CE IN 0.2VCC
0.8VCC
nA
46
ILEAK ±10CE IN Leakage Current
Note 1: VCC supply current, logic input leakage, watchdog functionality (MAX793/MAX794), MR functionality (MAX793/MAX794),
PFI functionality (MAX793/MAX794), state of RESET and RESET (MAX793/MAX794) tested at VBATT = 3.6V and VCC = 5.5V.
The state of RESET is tested at VCC = VCC min.
Note 2: Tested at VBATT = 3.6V, VCC = 3.5V and 0V. The battery current will rise to 10µA over a narrow transition window around
VCC = 1.9V.
Note 3: Leakage current into the battery is tested under the worst-case conditions at VCC = 5.5V, VBATT = 1.8V and VCC = 1.5V,
VBATT = 1.0V.
Note 4: Guaranteed by design.
Note 5: When VSW > VCC > VBATT, OUT remains connected to VCC until VCC drops below VBATT. The VCC-to-VBATT comparator
has a small 15mV typical hysteresis to prevent oscillation. For VCC < 1.75V (typical), OUT switches to BATT regardless of
VBATT.
Note 6: When VBATT > VCC > VSW, OUT remains connected to VCC until VCC drops below the battery switch threshold (VSW).
Note 7: OUT switches from BATT to VCC when VCC rises above the reset threshold, if VBATT > VRST. In this case, switchover back
to VCC occurs at the exact voltage that causes reset to be asserted, however switchover occurs 200ms prior to reset. If
VBATT < VRST, OUT switches from BATT to VCC when VCC exceeds VBATT.
Note 8: The reset threshold tolerance is wider for VCC rising than for VCC falling to accommodate the 10mV typical hysteresis,
which prevents internal oscillation.
Note 9: The leakage current into or out of the RESET pin is tested with RESET not asserted (RESET output high impedance).
Note 10: PFO is normally an output, but is used as an input when activating the battery freshness seal.
µs10Reset to CE OUT High Delay
tWD sec
0V < VCC < 5.5V
Watchdog Timeout Period
IOH = 500µA, VCC < 2.3V
µA
1.00 1.60 2.25
-1 0.01 1WDI Input Current
VVOH 0.8VBATT
CE OUT Output Voltage
High (reset active)
nsWDI Pulse Width 1.00
MANUAL RESET INPUT
CHIP-ENABLE GATING
WATCHDOG (MAX793/MAX794 only)
MAX793/MAX794/MAX795
3.0V/3.3V/Adjustable Microprocessor
Supervisory Circuits
_______________________________________________________________________________________
5
3.0
2.8
2.6
2.4
2.2
2.0
1.8
1.6
1.4
1.2
1.0 -40 100
VCC-TO-OUT ON-RESISTANCE
vs. TEMPERATURE
MAX793 TOC1
TEMPERATURE (°C)
VCC-TO-OUT ON-RESISTANCE (Ω)
20-20 0 8040 60
IOUT = 30mA
VCC = 3.0V
VCC = 3.3V
VCC = 5V
160
140
120
100
80
60
40 -40 100
BATT-TO-OUT ON-RESISTANCE
vs. TEMPERATURE
MAX793 TOC2
TEMPERATURE (°C)
BATT-TO-OUT ON-RESISTANCE (Ω)
20-20 0 8040 60
VBATT = 3.6V
VBATT = 3.0V
VBATT = 5V IOUT = 250µA
VCC = 0V
70
60
50
40
30
20
10
0-40 100
VCC SUPPLY CURRENT vs. TEMPERATURE
(NORMAL OPERATING MODE)
MAX793 TOC3
TEMPERATURE (°C)
VCC SUPPLY CURRENT (µA)
20-20 0 8040 60
MAX793/4, VCC = 3.3V
MAX795, VCC = 3.3V
MAX793/4, VCC = 5V
VBATT = VCC = VOUT
MAX795, VCC = 5V
0.10
0.08
0.06
0.04
0.02
0-40 100
BATTERY SUPPLY CURRENT vs.
TEMPERATURE (BATTERY-BACKUP MODE)
MAX793 TOC4
TEMPERATURE (°C)
SUPPLY CURRENT (µA)
20-20 0 8040 60
VCC = 0V
VBATT = 3.6V
100
90
80
70
60
50
40
30
20
10
0-40 100
MAX793
LOWLINE-TO-RESET THRESHOLD
vs. TEMPERATURE
MAX793 TOC7
TEMPERATURE (°C)
LOWLINE-TO-RESET THRESHOLD (mV)
20-20 0 8040 60
VCC FALLING
250
200
150
100
50
0-40 100
RESET TIMEOUT PERIOD
vs. TEMPERATURE
MAX793 TOC5
TEMPERATURE (°C)
RESET TIMEOUT PERIOD (ms)
20-20 0 8040 60
VCC RISING FROM
OV TO VRST MAX
30
25
20
15
10
5
0-40 100
RESET COMPARATOR PROPAGATION DELAY
vs. TEMPERATURE (VCC FALLING)
MAX793 TOC6
TEMPERATURE (°C)
PROPAGATION DELAY (µs)
20-20 0 8040 60
10
8
6
4
2
0-40 100
MAX793/MAX794
LOWLINE COMPARATOR PROPAGATION DELAY
vs. TEMPERATURE
MAX793 TOC8
TEMPERATURE (°C)
PROPAGATION DELAY (µs)
20-20 0 8040 60
40mV OVERDRIVE
VCC RISING
VCC FALLING
1.250
1.245
1.240
1.235
1.230-40 100
MAX793/MAX794
PFI THRESHOLD vs. TEMPERATURE
MAX793 TOC9
TEMPERATURE (°C)
PFI THRESHOLD (V)
20-20 0 8040 60
__________________________________________Typical Operating Characteristics
(TA = +25°C, unless otherwise noted.)
MAX793/MAX794/MAX795
3.0V/3.3V Adjustable Microprocessor
Supervisory Circuits
6 _______________________________________________________________________________________
____________________________Typical Operating Characteristics (continued)
(TA = +25°C, unless otherwise noted.)
1.242
1.241
1.240
1.239
1.238
1.237
1.236
30
25
20
15
10
5
0
-40 100
MAX794
RESET IN THRESHOLD AND LOWLINE-TO-RESET IN
THRESHOLD vs. TEMPERATURE
TEMPERATURE (°C)
RESET IN THRESHOLD (V)
LOWLINE-TO-RESET IN THRESHOLD (mV)
20-20 0 8040 60
VLOWLINE - VRST
VRESET IN
VCC FALLING
MAX793 TOC10
2.5
2.0
1.5
1.0
0.5
0-40 100
MAX793
BATT OK THRESHOLD vs. TEMPERATURE
MAX793 TOC11
TEMPERATURE (°C)
BATT OK THRESHOLD (V)
20-20 0 8040 60
VBATT FALLING
60
50
40
30
20
10
0-40 100
CE IN-TO-CE OUT ON-RESISTANCE
vs. TEMPERATURE
TEMPERATURE (°C)
CE IN-TO-CE OUT ON-RESISTANCE (Ω)
20-20 0 8040 60
VCC = VRST MAX
MAX793 TOC12
1.70
1.65
1.60
1.55
1.50-40 100
MAX793/MAX794
WATCHDOG TIMEOUT PERIOD
vs. TEMPERATURE
MAX793 TOC13
TEMPERATURE (°C)
WATCHDOG TIMEOUT PERIOD (sec)
20-20 0 8040 60
20
15
10
5
0-40 100
MAX793/MAX794
BATTERY FRESHNESS SEAL
LEAKAGE CURRENT vs. TEMPERATURE
MAX793 TOC14
TEMPERATURE (°C)
LEAKAGE CURRENT (nA)
20-20 0 8040 60
VBATT = 5.5V
VCC = 0V
VOUT = 0V
1.002
1.001
1.000
0.999
0.998
0.997
0.996-40 100
RESET THRESHOLD vs.
TEMPERATURE (NORMALIZED)
MAX793 TOC15
TEMPERATURE (°C)
VRST (NORMALIZED)
20-20 0 8040 60
VCC FALLING
10
8
6
4
2
0-40 100
MAX793/MAX794
PFI TO PFO PROPAGATION DELAY
vs. TEMPERATURE
MAX793 TOC16
TEMPERATURE (°C)
PROPAGATION DELAY (µs)
20-20 0 8040 60
VPFI FALLING
20mV OVERDRIVE
MAX793/MAX794/MAX795
3.0V/3.3V Adjustable Microprocessor
Supervisory Circuits
_______________________________________________________________________________________ 7
______________________________________________________________Pin Description
PIN
Supply Output for CMOS RAM. When VCC rises above the reset threshold or above
VBATT, OUT is connected to VCC through an internal P-channel MOSFET switch. When
VCC falls below VSW and VBATT, BATT connects to OUT.
OUT1 1
Reset Input. Connect to an external resistor divider to select the reset threshold. The
reset threshold can be programmed anywhere in the VSW to 5.5V range.
RESET IN
(MAX794)
3 —
Battery Status Output. High in normal operating mode when VBATT exceeds VBOK, other-
wise low. VBATT is checked continuously. Disabled and logic low while VCC is below VSW.
BATT OK
(MAX793)
Main Supply InputVCC
2 2
Power-Fail Comparator Output. When PFI is less than VPFT or when VCC falls below
VSW, PFO goes low; otherwise, PFO remains high. PFO is also used to enable the bat-
tery freshness seal (see B
attery Freshness Seal
, and
Power-Fail Comparator
sections).
PFO7 —
Active-High Reset Output. Sources and sinks current. RESET is the inverse of RESET.RESET13
Chip-Enable Output. CE OUT goes low only when CE IN is low and reset is not asserted.
If CE IN is low when reset is asserted, CE OUT will remain low for 10µs or until CE IN
goes high, whichever occurs first. CE OUT is pulled up to OUT.
CE OUT12
—
6
GroundGND6
Power-Fail Comparator Input. When PFI is less than VPFT or when VCC falls below VSW,
PFO goes low; otherwise, PFO remains high (see
Power-Fail Comparator
section).
Connect to VCC if unused.
PFI4
Chip-Enable Input. The input to the chip-enable gating circuit. Connect to GND if unusedCE IN11 5
4
—
Watchdog Output. WDO goes low if WDI remains either high or low for longer than the
watchdog timeout period. WDO returns high on the next transition of WDI. WDO is a
logic high for VSW < VCC < VRST, and low when VCC is below VSW.
WDO9 —
Manual Reset Input. A logic low on MR asserts reset. Reset remains asserted as long as
MR is low and for 200ms after MR returns high. The active-low input has an internal
70µA pull-up current. In can be driven from a TTL- or CMOS-logic line or shorted to
ground with a switch. Leave open if unused.
MR8 —
Watchdog Input. If WDI remains either high or low for longer than the watchdog timeout
period, the internal watchdog timer runs out and WDO goes low. WDO returns high on
the next transition of WDI. Connect WDO to MR to generate a reset due to a watchdog
fault.
WDI10 —
Early Power-Fail Warning Output. Low when VCC falls to VLR. This output can be used to
generate an NMI to provide early warning of imminent power-failure.
LOWLINE14 —
Open-Drain, Active-Low Reset Output. Pulses low for 200ms when triggered, and stays
low whenever VCC is below the reset threshold or when MR is a logic low. It remains low
for 200ms after either VCC rises above the reset threshold, the watchdog triggers a reset
(WDO connected to MR), or MR goes low to high.
RESET15 7
Backup-Battery Input. When VCC falls below VSW and VBATT, OUT switches from VCC to
BATT. When VCC rises above the reset threshold or above VBATT, OUT reconnects to
VCC. VBATT may exceed VCC. Connect VCC, OUT, and BATT together if no battery is
used.
BATT16 8
Logic Output/External Bypass Switch-Driver Output. High when OUT switches to BATT.
Low when OUT switches to VCC. Connect the base/gate of PNP/PMOS transistor to
BATT ON for IOUT requirements exceeding 75mA.
BATT ON5 3
MAX793/
MAX794
FUNCTIONNAME
MAX795
MAX793/MAX794/MAX795
3.0V/3.3V Adjustable Microprocessor
Supervisory Circuits
8 _______________________________________________________________________________________
_______________Detailed Description
General Timing Characteristics
The MAX793/MAX794/MAX795 are designed for 3.3V
and 3V systems, and provide a number of supervisory
functions (see the
Selector Guide
on the front page).
Figures 1 and 2 show the typical timing relationships of
the various outputs during power-up and power-down
with typical VCC rise and fall times.
Manual Reset Input (MAX793/MAX794)
Many microprocessor-based products require manual-
reset capability, allowing the operator, a test technician,
or external logic circuitry to initiate a reset. On the
MAX793/MAX794, a logic low on MRasserts reset. Reset
remains asserted while MR is low, and for tRP (200ms)
after it returns high. During the first half of the reset time-
out period (tRP), the state of MR is ignored if PFO is exter-
nally forced low, to facilitate enabling the battery fresh-
ness seal. MR has an internal 70µA pull-up current, so it
can be left open if it is not used. This input can be driven
with TTL- or CMOS-logic levels, or with open-drain/collec-
tor outputs. Connect a normally open momentary switch
from MR to GND to create a manual-reset function; exter-
nal debounce circuitry is not required. If MR is driven
from long cables or the device is used in a noisy environ-
ment, connect a 0.1µF capacitor from MR to ground to
provide additional noise immunity.
Reset Outputs
A microprocessor’s (µP’s) reset input starts the µP in a
known state. These MAX793/MAX794/MAX795 µP
supervisory circuits assert a reset to prevent code exe-
cution errors during power-up, power-down, and
VLOWLINE (MAX793/MAX794)
VRESET (PULLED UP TO VCC)
VRESET (MAX793/MAX794)
(PFO FOLLOWS PFI)
VCE OUT VBATT
VWDO
(MAX793/MAX794)
VBOK
(MAX793)
MAX794: VRESET IN = VCC (VRST IN / VRST)
PFO
(MAX793/MAX794)
BATT ON
SHOWN FOR VCC = 0V to 3.3V, VBATT = 3.6V, CE IN = GND.
TYPICAL PROPAGATION DELAYS REFLECT A 40mV OVERDRIVE.
5µs
VSW
VCC
VRST VLL
tRP
25µs
25µs
25µs
25µs
tRP
tRP/2
tRP/2
Figure 1. Timing Diagram, VCC Rising
brownout conditions. RESET is guaranteed to be a
logic low for 0V < VCC < VRST, provided VBATT is
greater than 1V. Without a backup battery (VBATT =
VCC = VOUT), RESET is guaranteed valid for VCC ≥1V.
Once VCC exceeds the reset threshold, an internal
timer keeps RESET low for the reset timeout period
(tRP); after this interval, RESET becomes high imped-
ance (Figure 2). RESET is an open-drain output, and
requires a pull-up resistor to VCC (Figure 3). Use a
4.7kΩto 1MΩpull-up resistor that will provide sufficient
current to assure the proper logic levels to the µP.
If a brownout condition occurs (VCC dips below the
reset threshold), RESET goes low. Each time RESET is
asserted, it stays low for the reset timeout period. Any
time VCC goes below the reset threshold, the internal
timer restarts.
The watchdog output (WDO) can also be used to initi-
ate a reset. See the
Watchdog Output
section.
The RESET output is the inverse of the RESET output,
and it can both source and sink current.
MAX793/MAX794/MAX795
3.0V/3.3V Adjustable Microprocessor
Supervisory Circuits
_______________________________________________________________________________________ 9
VCC
VLOWLINE
(MAX793/MAX794)
VRESET
(RESET PULLED UP TO VCC)
VRESET
(MAX793/MAX794)
VCE OUT
VWDO
(MAX793/MAX794)
VBOK
(MAX793)
VPFO
(MAX793/MAX794)
SHOWN FOR VCC = 3.3V to 0V, VBATT = 3.6V, CE IN = GND, PFI = VCC.
TYPICAL DELAY TIMES REFLECT A 40mV OVERDRIVE
VBATT ON
MAX794: VRESET IN = VCC (VRST IN / VRST)
VBATT
VBATT
4µs
VLL VRST
VSW
20µs
20µs
25µs
10µs
25µs
25µs
25µs
25µs
Figure 2. Timing Diagram, VCC Falling
MAX793/MAX794/MAX795
Reset Threshold
The MAX793T/MAX795T are intended for 3.3V systems
with a ±5% power-supply tolerance and a 10% systems
tolerance. Except when MR is asserted, reset will not
assert as long as the power supply remains above
3.15V (3.3V - 5%). Reset is guaranteed to assert
before the power supply falls below 3.0V (3.3V - 10%).
The MAX793S/MAX795S are designed for 3.3V ±10%
power supplies. Except when MR is asserted, they are
guaranteed not to assert reset as long as the supply
remains above 3.0V (3.0V is just above 3.3V - 10%).
Reset is guaranteed to assert before the power supply
falls below 2.85V (3.3V - 14%).
The MAX793R/MAX795R are optimized to monitor 3.0V
±10% power supplies. Reset will not occur until VCC
falls below 2.7V (3.0V - 10%), but is guaranteed to
occur before the supply falls below 2.55V (3.0V - 15%).
Program the MAX794’s reset threshold with an external
voltage divider to RESET IN. The reset-threshold toler-
ance will be a combination of the RESET IN tolerance
and the tolerance of the resistors used to make the
external voltage divider. Calculate the reset threshold
as follows:VRST = VRST IN (R1 / R2 + 1)
Using the standard application circuit (Figure 3), the
reset threshold may be programmed anywhere in the
range of VSW (the battery switch threshold) to 5.5V.
Reset is asserted when VCC falls below VSW.
Battery Freshness Seal
The MAX793/MAX794’s battery freshness seal discon-
nects the backup battery from internal circuitry until it is
needed. This allows an OEM to ensure that the backup
battery connected to BATT will be fresh when the final
product is put to use. To enable the freshness seal,
connect a battery to BATT, ground PFO, bring VCC
above the reset threshold and hold it there until reset is
deasserted following the reset timeout period, then
bring VCC back down again (Figure 4). Once the bat-
tery freshness seal is enabled (disconnecting the back-
up battery from the internal circuitry and anything
connected to OUT), it remains enabled until VCC is
brought above VRST. Note that connecting PFO to MR
will not interfere with battery freshness seal operation.
BATT OK Output (MAX793)
BATT OK indicates the status of the backup battery.
When reset is not asserted, the MAX793 checks the
battery voltage continuously. If VBATT is below VBOK
(2.0V min), BATT OK goes low; otherwise, it remains
pulled up to VCC. BATT OK also goes low when VCC
goes below VSW.
Watchdog Input (MAX793/MAX794)
In the MAX793/MAX794, the watchdog circuit monitors
the µP’s activity. If the µP does not toggle the watch-
dog input (WDI) within 1.6sec, WDO goes low. The
internal 1.6sec timer is cleared and WDO returns high
3.0V/3.3V Adjustable Microprocessor
Supervisory Circuits
10 ______________________________________________________________________________________
MAX794
RESET
LOWLINE
WDI
CE IN
CE OUT
3.3V
+5V
BATT
RESET IN
A0-A15
MR
+5V SUPPLY
FAILURE
BATT ON
PFI
4.7k
WDO
OUT CMOS
RAM
ADDRESS
DECODER
0.1µF
PMOS
0.1µF
VCC
PFO
VRST = VRST IN
(
R1 + 1
)
GND
I/O
NMI
RESET
VCC
VCC
0.1µF
3.6V
R1
DS
R2
(OPTIONAL)
Si9433DY
SILICONIX
R2
Figure 3. MAX794 Standard Application Circuit
VCC
VRST VRST
RESET
PFO
(EXTERNALLY HELD AT 0V)
RESET PULLED UP TO VCC
PFO STATE LATCHED,
FRESHNESS SEAL ENABLED.
tRP
Figure 4. Battery Freshness Seal Enable Timing
either when a reset occurs or when a transition (low-to-
high or high-to-low) takes place at WDI. As long as
reset is asserted, the timer remains cleared and does
not count. As soon as reset is released or WDI
changes state, the timer starts counting (Figure 5).
WDI can detect pulses as short as 100ns. Unlike the
5V MAX690 family, the watchdog function cannot be
disabled.
Watchdog Output (MAX793/MAX794)
In the MAX793/MAX794, WDO remains high (WDO is
pulled up to VCC) if there is a transition or pulse at WDI
during the watchdog timeout period. WDO goes low if
no transition occurs at WDI during the watchdog timeout
period. The watchdog function is disabled and WDO is
a logic high when reset is asserted if VCC is above VSW.
WDO is a logic low when VCC is below VSW.
If a system reset is desired on every watchdog fault,
simply diode-OR connect WDO to MR (Figure 6).
When a watchdog fault occurs in this mode, WDO goes
low, pulling MR low, which causes a reset pulse to be
issued. Ten microseconds after reset is asserted, the
watchdog timer clears and WDO returns high. This
delay results in a 10µs pulse at WDO, allowing external
circuitry to “capture” a watchdog fault indication. A
continuous high or low on WDI will cause 200ms reset
pulses to be issued every 1.6sec.
Chip-Enable Signal Gating
Internal gating of chip-enable (CE) signals prevents erro-
neous data from corrupting CMOS RAM in the event of an
undervoltage condition. The MAX793/MAX794/MAX795
use a series transmission gate from CE IN to CE OUT
(Figure 7). During normal operation (reset not asserted),
the CE transmission gate is enabled and passes all CE
transitions. When reset is asserted, this path becomes
disabled, preventing erroneous data from corrupting the
CMOS RAM. The short CE propagation delay from CEIN
to CE OUT enables these µP supervisors to be used with
most µPs. If CE IN is low when reset asserts, CE OUT
remains low for typically 10µs to permit completion of the
current write cycle.
Chip-Enable Input
The CE transmission gate is disabled and CE IN is high
impedance (disabled mode) while reset is asserted.
During a power-down sequence when VCC passes the
reset threshold, the CE transmission gate disables and
CE IN immediately becomes high impedance if the volt-
age at CE IN is high. If CE IN is low when reset
asserts, the CE transmission gate will disable at the
moment CE IN goes high, or 10µs after reset asserts,
whichever occurs first (Figure 8). This permits the cur-
rent write cycle to complete during power-down.
MAX793/MAX794/MAX795
3.0V/3.3V Adjustable Microprocessor
Supervisory Circuits
______________________________________________________________________________________ 11
VCC
VRST
RESET
tWD
WDO
WDI
WDO CONNECTED TO µP INTERRUPT
RESET PULLED UP TO VCC
tRP
Figure 5. Watchdog Timing Relationship
VCC
VCC
RESET
WDO
WDO
4.7k
TO µP
MR
RESET
WDI
tRP
tRP tWP
∼10µs
MAX793/MAX794
Figure 6. Generating a Reset on Each Watchdog Fault
MAX793/MAX794/MAX795
The CE transmission gate remains disabled and CE IN
remains high impedance (regardless of CE IN activity)
for the first half of the reset timeout period (tRP / 2), any
time a reset is generated. While disabled, CE IN is
high impedance. When the CE transmission gate is
enabled, the impedance of CE IN appears as a 46Ω
resistor in series with the load at CE OUT.
The propagation delay through the CE transmission
gate depends on VCC, the source impedance of the
drive connected to CE IN, and the loading on CE OUT
(see the Chip-Enable Propagation Delay vs. CE OUT
Load Capacitance graph in the
Typical Operating
Characteristics
). The CE propagation delay is produc-
tion tested from the 50% point on CE IN to the 50%
point on CE OUT using a 50Ωdriver and 50pF of load
capacitance (Figure 9). For minimum propagation
delay, minimize the capacitive load at CE OUT, and
use a low-output-impedance driver.
Chip-Enable Output
When the CE transmission gate is enabled, the imped-
ance of CE OUT is equivalent to a 46Ωresistor in series
with the source driving CE IN. In the disabled mode,
the transmission gate is off and an active pull-up con-
nects CE OUT to OUT (Figure 8). This pull-up turns off
when the transmission gate is enabled.
Early Power-Fail Warning
(MAX793/MAX794)
Critical systems often require an early warning indicat-
ing that power is failing. This warning provides time for
the µP to store vital data and take care of any additional
“housekeeping” functions, before the power supply
gets too far out of tolerance for the µP to operate reli-
ably. The MAX793/MAX794 offer two methods of
achieving this early warning. If access to the unregu-
lated supply is feasible, the power-fail comparator input
(PFI) can be connected to the unregulated supply
3.0V/3.3V Adjustable Microprocessor
Supervisory Circuits
12 ______________________________________________________________________________________
CHIP-ENABLE
OUTPUT
CONTROL
CE OUT
N
P
P
OUT
CE IN
MAX793
MAX794
MAX795
RESET
GENERATOR
Figure 7. Chip-Enable Transmission Gate
VBATT VCC
VRST VRST
VSW
VRST
VCC
CE OUT
RESET
(PULLED TO VCC)
CE IN
VBATT = 3.6V
RESET PULLED UP TO VCC
tRP
10µs
tRP/2
VBATT
VSW
VRST
Figure 8. Chip-Enable Timing
MAX793/MAX794/MAX795
3.0V/3.3V Adjustable Microprocessor
Supervisory Circuits
______________________________________________________________________________________ 13
through a voltage divider, with the power-fail compara-
tor output (PFO) providing the NMI to the µP (Figure
10). If there is no easy access to the unregulated sup-
ply, the LOWLINE output can be used to generate an
NMI to the µP (see
LOWLINE Output
section).
LOWLINE Output (MAX793/MAX794)
The low-line comparator monitors VCC with a threshold
voltage typically 45mV above the reset threshold (10mV
of hysteresis) for the MAX793, and 15mV above RESET
IN (4mV of hysteresis) for the MAX794. For normal
operation (VCC above the reset threshold), LOWLINE is
pulled to VCC. Use LOWLINE to provide an NMI to the
µP when power begins to fall.
In most battery-operated portable systems, reserve
energy in the battery provides ample time to complete
the shutdown routine once the low-line warning is
encountered and before reset asserts. If the system
must also contend with a more rapid VCC fall time, such
as when the main battery is disconnected or a high-
side switch is opened during normal operation, use
capacitance on the VCC line to provide time to execute
the shutdown routine (Figure 11).
First, calculate the worst-case time required for the sys-
tem to perform its shutdown routine. Then, with the worst-
case shutdown time, the worst-case load current, and the
minimum low-line to reset threshold (VLR min), calculate
the amount of capacitance required to allow the shut-
down routine to complete before reset is asserted:
CHOLD > ILOAD x tSHDN / VLR
where ILOAD is the current being drained from the
capacitor, VLR is the low-line to reset threshold differ-
ence (VLL - VRST), and tSHDN is the time required for
the system to complete an orderly shutdown routine.
Power-Fail Comparator (MAX793/MAX794)
The MAX793/MAX794’s PFI input is compared to an
internal reference. If PFI is less than the power-fail
threshold (VPFT), PFO goes low. The power-fail com-
parator is intended for use as an undervoltage detector
to signal a failing power supply (Figure 12). However,
the comparator does not need to be dedicated to this
function because it is completely separate from the rest
of the circuitry.
VCC
GND
VCC
50pF
CL*
CE IN
*CL INCLUDES LOAD CAPACITANCE AND SCOPE PROBE CAPACITANCE.
50Ω
3.6V
25Ω EQUIVALENT
SOURCE IMPEDANCE
50Ω
50Ω CABLE
BATT
CE OUT
MAX793
MAX794
MAX795
Figure 9. CE Propagation Delay Test Circuit
VCC
GND
PFI TO µP NMI
R1
UNREGULATED
SUPPLY 3.0V OR 3.3V
R2
PFO
MAX793
MAX794
REGULATOR
Figure 10. Using the Power-Fail Comparator to Generate
Power-Fail Warning
GND
VCC TO µP NMI
CHOLD
CHOLD > ILOAD x tSHDN
VLR
3.0V OR 3.3V LOWLINE
MAX793
MAX794
REGULATOR
Figure 11. Using LOWLINE to Provide Power-Fail Warning
to the µP
MAX793/MAX794/MAX795
3.0V/3.3V Adjustable Microprocessor
Supervisory Circuits
14 ______________________________________________________________________________________
The power-fail comparator turns off and PFO goes low
when VCC falls below VSW on power-down. During the
first half of the reset timeout period (tRP), PFO is forced
high, irrespective of VPFI. At the beginning of the sec-
ond half of tRP, the power-fail comparator is enabled
and PFO follows PFI. If the comparator is unused, con-
nect PFI to VCC and leave PFO unconnected. PFO may
be connected to MR so that a low voltage on PFI will
generate a reset (Figure 12b). In this configuration,
when the monitored voltage causes PFI to fall below
VPFT, PFO pulls MR low, causing a reset to be assert-
ed. Reset remains asserted as long as PFO holds MR
low, and for 200ms after PFO pulls MR high when the
monitored supply is above the programmed threshold.
Backup-Battery Switchover
In the event of a brownout or power failure, it may be
necessary to preserve the contents of RAM. With a
backup battery installed at BATT, the devices automati-
cally switch RAM to backup power when VCC falls. In
order to allow the backup battery (e.g., a 3.6V lithium
cell) to have a higher voltage than VCC, this family of µP
supervisors (designed for 3.3V and 3V systems) does
not always connect BATT to OUT when VBATT is
greater than VCC. BATT connects to OUT (through a
140Ωswitch) either when VCC falls below VSW and
VBATT is greater than VCC, or when VCC falls below
1.75V (typ) regardless of the BATT voltage.
Switchover at VSW ensures that battery-backup mode is
entered before VOUT gets too close to the 2.0V mini-
mum required to reliably retain data in most CMOS
RAM, (switchover at higher VCC voltages would
decrease backup-battery life). When VCC recovers,
switchover is deferred either until VCC crosses VBATT if
VBATT is below VRST, or when VCC rises above the
reset threshold (VRST) if VBATT is above VRST. This
power-up switchover technique prevents VCC from
charging the backup battery through OUT when using
an external transistor driven by BATT ON. OUT con-
nects to VCC through a 4Ω(max) PMOS power switch
when VCC crosses the reset threshold (Figure 13).
BATT ON (MAX793/MAX794)
BATT ON is high when OUT is connected to BATT.
Although BATT ON can be used as a logic output to
indicate the battery switchover status, it is most often
used as a gate or base drive for an external pass tran-
sistor for high-current applications (see
Driving an
External Switch with BATT ON
in the
Applications
Information
section). When VCC exceeds VRST on
power-up, BATT ON sinks 3.2mA at 0.4V. In battery-
backup mode, this terminal sources 100µA from BATT.
MAX793
MAX794
VCC
GND
PFI PFO
R1
R2
VIN
0V VIN
PFO
VTRIP
VL
VPFT = 1.237V
VPFH = 10mV
WHERE
3.0V OR 3.3V
VTRIP = R2 +
R1
1
)
(
R2
1–R1
VCC
(VPFT + VPFH)
VL = R2 +
R1
1
)
(
R2
1–R1
VCC
(VPFT)NOTE: VTRIP, VL ARE NEGATIVE
VCC
MAX793
MAX794
VCC
GND
PFI PFO
R1
R2
PFO
VTRIP VH
3.0V OR 3.3V
VIN
VTRIP =
)
(
R2
R1 + R2
VPFT
VH = (VPFT + VPFH)
VCC
VIN
MR
(b)(a)
)
(
R2
R1 + R2
Figure 12. Using the Power-Fail Comparator to Monitor an Additional Power Supply: (a) VIN Is Negative, (b) VIN Is Positive
__________Applications Information
These µP supervisory circuits are not short-circuit pro-
tected. Shorting VOUT to ground, excluding power-up
transients such as charging a decoupling capacitor,
destroys the device. Decouple both VCC and BATT
pins to ground by placing 0.1µF ceramic capacitors as
close to the device as possible.
Driving an External Switch with BATT ON
BATT ON can be directly connected to the base of a
PNP transistor or the gate of a PMOS transistor. The
PNP connection is straightforward: connect the emitter
to VCC, the collector to OUT, and the base to BATT ON
(Figure 14a). No current-limiting resistor is required,
but a resistor connecting the base of the PNP to BATT
ON can be used to limit the current drawn from VCC,
prolonging battery life in portable equipment.
If you are using a PMOS transistor, however, it must be
connected backwards from the traditional method.
Connect the gate to BATT ON, the drain to VCC, and
the source to OUT (Figure 14b). This method orients
the body diode from VCC to OUT and prevents the
backup battery from discharging through the FET when
its gate is high. Two PMOS transistors in the Siliconix
LITTLE FOOT™ series are specified with VGS down to
-2.7V. The Si9433DY has a maximum 100mΩdrain-
source on-resistance with 2.7V of gate drive and a 2A
drain-source current. The Si9434DY specifies a 60mΩ
drain-source on-resistance with 2.7V of gate drive and
a 5.1A drain-source current.
Using a SuperCap™ as a Backup
Power Source
SuperCaps™ are capacitors with extremely high
capacitance values (e.g., order of 0.47F) for their size.
Figure 15 shows two ways to use a SuperCap as a
backup power source. The SuperCap can be connect-
ed through a diode to the 3V input (Figure 15a); or, if a
5V supply is also available, the SuperCap can be
charged up to the 5V supply (Figure 15b), allowing a
longer backup period. Since VBATT can exceed VCC
while VCC is above the reset threshold, there are no
special precautions when using these µP supervisors
with a SuperCap.
Operation without a
Backup Power Source
These µP supervisors were designed for battery-
backed applications. If a backup battery is not used,
connect BATT, OUT, and VCC together, or use a differ-
ent µP supervisor. See the
µP Supervisory Circuits
table at the end of this data sheet.
Replacing the Backup Battery
The backup power source can be removed while VCC
remains valid, without danger of triggering a reset
pulse, provided that BATT is decoupled with a 0.1µF
capacitor to ground. As long as VCC stays above the
reset threshold, battery-backup mode cannot be
entered.
MAX793/MAX794/MAX795
3.0V/3.3V Adjustable Microprocessor
Supervisory Circuits
______________________________________________________________________________________ 15
CE IN High impedance
CE OUT Pulled to BATT
RESET Logic low
BATT Connected to OUT
LOWLINE Logic low
RESET Pulled up to VCC
WDO Logic low
WDI Disabled
BATT OK Logic low
PFO Logic low
MR Disabled, but still pulled up to VCC
PFI Disabled
VCC Disconnected from OUT
BATT ON Pulled up to BATT
OUT Connected to BATT through an internal
140Ωswitch
PIN NAME STATUS
Table 1. Input and Output Status in
Battery-Backup Mode
VCC
3.3V
3.6V 3.3V 3.6V
VOUT
VBATT = 3.6V
VRST
VSW
Figure 13. Battery Switchover Timing
™ LITTLE FOOT is a trademark of Siliconix Inc.
SuperCap is a trademark of Baknor Industries.
MAX793/MAX794/MAX795
____________________________Erratum
Initial versions of the MAX793 and MAX794 have a
logic design error that can cause the loss of output volt-
age (OUT) when V
CC
is absent even though a backup
battery is connected to the BATT input. Applications
that do not use the MR input (including all MAX795
applications) are unaffected by this phenomenon.
Also, applications that do not use PFO are unaffected if
PFI is tied to V
CC
.
The loss of output voltage is caused by the IC incor-
rectly entering the battery “freshness seal” mode.
Normally, freshness seal mode is activated by ground-
ing PFO during a power-up reset timeout period. Then,
the removal of V
CC
powers the IC down without con-
necting the backup battery to OUT.
The IC decides whether or not to enter freshness seal
mode during all reset timeout periods. During a power-
up reset timeout period (which occurs when V
CC
is
raised above the MAX793’s reset threshold or the volt-
age on the MAX794’s RESET IN pin is raised above the
RESET IN threshold), the IC momentarily disconnects
the PFO pin from the comparator output and lightly
pulls PFO up to V
CC
. The voltage level on the PFO pin
is then tested and, if it is low, freshness seal mode is
chosen. (PFO is reconnected to the comparator output
before the end of the reset timeout period.)
However, when a reset is initiated by MR, the PFO pin
incorrectly remains connected to the comparator output
during the entire timeout period and is not pulled up. If
the comparator is driving PFO low during an MR reset
3.0V/3.3V Adjustable Microprocessor
Supervisory Circuits
16 ______________________________________________________________________________________
MAX793
MAX794
MAX795
3.0V OR 3.3V TO CMOS RAM
BODY DIODE
GND
MAX793
MAX794
MAX795
BATT ONVCC OUT
S
D
G
PMOS FET
BATT ONVCC OUT
GND
(b)(a)
Figure 14. Driving an External Transistor with BATT ON
MAX793
MAX794
OUT TO STATIC
RAM
BATT
VCC
GND
1N4148
RESET TO µP
0.47F
3.0V OR 3.3V
MAX793
MAX794
OUT TO STATIC
RAM
BATT
VCC VCC
GND
1N4148
RESET TO µP
0.47F
3.0V OR
3.3V
+5V
(b)(a)
VCC
Figure 15. Using a SuperCap™ as a Backup Source
timeout period (because PFI is below the PFI thresh-
old), the IC will test the voltage level on PFO, find that it
is low, and incorrectly decide to enter freshness seal
mode. If V
CC
is later removed, the backup battery will
not be connected to OUT and any devices powered by
OUT will lose power.
Applications that do not use the PFO comparator need
not be affected by this problem. Simply connect PFI to
V
CC
and PFO will be driven high during all reset time-
out periods. Freshness seal mode can be entered only
when PFO is low.
The IC is under revision to correct this problem. The
revised IC will disable PFO during all reset timeout peri-
ods including MR-initiated ones. This revision will not
affect applications that either do not use MR or do not
use PFO, but could affect applications that require the
use of the PFO output during MR-initiated reset timeout
periods. The revised ICs are expected to be available
in late 1996. For technical assistance, please contact
Maxim Applications at 1-800-998-8800 or at
http:// www. maxim-ic.com.
MAX793/MAX794/MAX795
3.0V/3.3V Adjustable Microprocessor
Supervisory Circuits
______________________________________________________________________________________ 17
MAX793
MAX794
VCC
GND
0V
TO µP
VL = R1 VPFT
PFI
PFO
R1
R2 R3
*OPTIONAL
C1*
VIN
VTRIP
VIN
PFO0V VH
VL
R1 + R2
R2
VH = (VPFT + VPFH) (R1)
VTRIP = VPFT
+
R1
1+
R2
1R3
1–R3
VCC
VPFT = 1.237V
VPFH = 10mV
WHERE
VCC
GND
TO µP
PFI
PFO
R1
R2 R3
*OPTIONAL
C1*
VIN
R1 + R2
)
R2
VH = R1 (VPFT + VPFH)
VTRIP = VPFT
(
+
R1
1+
R2
1R3
1–R3
VD
VPFT = 1.237V
VPFH = 10mV
VD = DIODE FORWARD VOLTAGE DROP
VL = VTRIP
WHERE
MAX793
MAX794
0V
PFO0V VHVIN
VTRIP
(b)(a)
(
)
( )
( )
+
R1
1+
R2
1R3
1
( )
Figure 16. Adding Hysteresis to the Power-Fail Comparator: (a) Symmetrical Hysteresis, (b) Hysteresis Only on Rising VIN
MAX793
MAX794
MAX795
VCC
GND
VCC
N
RESET
GENERATOR
GND
VCC
RESET RESET
µP
Figure 17. Interfacing to µPs with Bidirectional Reset I/O
MAX793/MAX794/MAX795
Adding Hysteresis to the Power-Fail
Comparator (MAX793/MAX794)
The power-fail comparator has a typical input hystere-
sis of 10mV. This is sufficient for most applications
where a power-supply line is being monitored through
an external voltage divider (see the section
Monitoring
an Additional Power Supply
).
If additional noise margin is desired, connect a resistor
between PFO and PFI as shown in Figure 16a. Select
the ratio of R1 and R2 such that PFI sees VPFT when
VIN falls to its trip point (VTRIP). R3 adds the additional
hysteresis and should typically be more than 10 times
the value of R1 or R2. The hysteresis window extends
both above (VH) and below (VL) the original trip point
(VTRIP).
Connecting an ordinary signal diode in series with R3,
as shown in Figure 16b, causes the lower trip point (VL)
to coincide with the trip point without hysteresis (VTRIP),
so the entire hysteresis window occurs above VTRIP.
This method provides additional noise margin without
compromising the accuracy of the power-fail threshold
when the monitored voltage is falling. It is useful for
accurately detecting when a voltage falls past a thresh-
old. The current through R1 and R2 should be at least
1µA to ensure that the 25nA (max over temperature)
PFI input current does not shift the trip point. R3 should
be larger than 82kΩso it does not load down the PFO
pin. Capacitor C1 is optional, and adds noise rejection.
Monitoring an Additional Power Supply
These µP supervisors can monitor either positive or
negative supplies using a resistor voltage divider to
PFI. PFO can be used to generate an interrupt to the
µP or to cause reset to assert (Figure 12).
Interfacing to µPs with
Bidirectional Reset Pins
Since the RESET output is open drain, the MAX793/
MAX794/MAX795 interface easily with µPs that have
bidirectional reset pins, such as the Motorola 68HC11.
Connecting the RESET output of the µP supervisor
directly to the RESET input of the microcontroller with a
single pull-up resistor allows either device to assert
reset (Figure 17).
Negative-Going V
CC
Transients
These supervisors are relatively immune to short-dura-
tion negative-going VCC transients (glitches) while issu-
ing resets to the µP during power-up, power-down, and
brownout conditions. Therefore, resetting the µP when
VCC experiences only small glitches is usually not rec-
ommended.
Figure 18 shows maximum transient duration vs. reset-
comparator overdrive, for which reset pulses are not
generated. The graph was produced using negative-
going VCC pulses, starting at 3.3V and ending below
the reset threshold by the magnitude indicated (reset
comparator overdrive). The graph shows the maximum
pulse width a negative-going VCC transient can typically
3.0V/3.3V Adjustable Microprocessor
Supervisory Circuits
18 ______________________________________________________________________________________
100
010 20 30 100
10
20
30
80
90
MAX793-FIG 18
RESET COMPARATOR OVERDRIVE, VRST - VCC (mV)
MAXIMUM PULSE DURATION (µs)
40 50 60 70 80 90
60
40
50
70
Figure 18. Maximum Transient Duration without Causing a
Reset Pulse vs. Reset Comparator Overdrive
START
SET WDI
HIGH
RETURN
PROGRAM
CODE
Subroutine or
Program Loop
SET WDI LOW
Figure 19. Watchdog Flow Diagram
MAX793/MAX794/MAX795
3.0V/3.3V Adjustable Microprocessor
Supervisory Circuits
______________________________________________________________________________________ 19
___________________Chip Information
_________________Pin Configurations
CE IN
CE OUT
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
BATT
RESET
LOWLINE
RESET
PFI
(RESET IN) BATT OK
VCC
OUT
TOP VIEW
MAX793
MAX794
CE OUT
CE IN
WDI
WDO
MR
PFO
GND
BATT ON
DIP / Narrow SO
1
2
3
4
8
7
6
5
BATT
GND
BATT ON
VCC
OUT
MAX795
DIP/SO
RESET
( ) ARE FOR MAX794
TRANSISTOR COUNT: 1271
have without causing a reset pulse to be issued. As
the amplitude of the transient increases (i.e., goes far-
ther below the reset threshold), the maximum allowable
pulse width decreases. Typically, a VCC transient that
goes 40mV below the reset threshold and lasts for
10µs or less will not cause a reset pulse to be issued.
A 0.1µF bypass capacitor mounted close to the VCC
pin provides additional transient immunity.
Watchdog Software Considerations
There is a way to help the watchdog timer monitor soft-
ware execution more closely, which involves setting
and resetting the watchdog input at different points in
the program rather than “pulsing” the watchdog input
high-low-high or low-high-low. This technique avoids a
“stuck” loop, in which the watchdog timer would con-
tinue to be reset within the loop, keeping the watchdog
from timing out. Figure 19 shows an example of a flow
diagram where the I/O driving the watchdog input is
set high at the beginning of the program, set low at the
beginning of every subroutine or loop, then set high
again when the program returns to the beginning. If
the program should “hang” in any subroutine, the prob-
lem would quickly be corrected, since the I/O is contin-
ually set low and the watchdog timer is allowed to time
out, causing a reset or interrupt to be issued.
_Ordering Information (continued)
* The MAX793/MAX795 offer a choice of reset threshold voltage.
Select the letter corresponding to the desired reset threshold volt-
age range (T = 3.00V to 3.15V, S = 2.85V to 3.00V, R = 2.55V
to 2.70V) and insert it into the blank to complete the part number.
The MAX794’s reset threshold is adjustable.
16 Narrow SO-40°C to +85°CMAX794ESE 16 Plastic DIP
16 Narrow SO
16 Plastic DIP
PIN-PACKAGETEMP. RANGE
0°C to +70°C
0°C to +70°C
-40°C to +85°CMAX794EPE
MAX794CSE
MAX794CPE
PART*
8 SO-40°C to +85°CMAX795_ESA 8 Plastic DIP
8 SO
8 Plastic DIP0°C to +70°C
0°C to +70°C
-40°C to +85°CMAX795_EPA
MAX795_CSA
MAX795_CPA
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
20
__________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 (408) 737-7600
© 1996 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.
MAX793/MAX794/MAX795
3.0V/3.3V Adjustable Microprocessor
Supervisory Circuits
DIM
A
A1
B
C
E
e
H
L
MIN
0.053
0.004
0.014
0.007
0.150
0.228
0.016
MAX
0.069
0.010
0.019
0.010
0.157
0.244
0.050
MIN
1.35
0.10
0.35
0.19
3.80
5.80
0.40
MAX
1.75
0.25
0.49
0.25
4.00
6.20
1.27
INCHES MILLIMETERS
21-0041A
Narrow SO
SMALL-OUTLINE
PACKAGE
(0.150 in.)
DIM
D
D
D
MIN
0.189
0.337
0.386
MAX
0.197
0.344
0.394
MIN
4.80
8.55
9.80
MAX
5.00
8.75
10.00
INCHES MILLIMETERS
PINS
8
14
16
1.270.050
L
0°-8°
HE
D
e
A
A1 C
0.101mm
0.004in.
B
DIM
A
A1
A2
A3
B
B1
C
D1
E
E1
e
eA
eB
L
MIN
–
0.015
0.125
0.055
0.016
0.045
0.008
0.005
0.300
0.240
0.100
0.300
–
0.115
MAX
0.200
–
0.175
0.080
0.022
0.065
0.012
0.080
0.325
0.310
–
–
0.400
0.150
MIN
–
0.38
3.18
1.40
0.41
1.14
0.20
0.13
7.62
6.10
2.54
7.62
–
2.92
MAX
5.08
–
4.45
2.03
0.56
1.65
0.30
2.03
8.26
7.87
–
–
10.16
3.81
INCHES MILLIMETERS
Plastic DIP
PLASTIC
DUAL-IN-LINE
PACKAGE
(0.300 in.)
DIM
D
D
D
D
D
D
PKG.
P
P
P
P
P
N
MIN
0.348
0.735
0.745
0.885
1.015
1.14
MAX
0.390
0.765
0.765
0.915
1.045
1.265
MIN
8.84
18.67
18.92
22.48
25.78
28.96
MAX
9.91
19.43
19.43
23.24
26.54
32.13
INCHES MILLIMETERS
PINS
8
14
16
18
20
24
C
AA2
E1
D
E
eA
eB
A3
B1
B
0° - 15°
A1
L
D1
e
21-0043A
________________________________________________________Package Information
