CS5351-DZZR - Cirrus Logic, Inc. - Datasheet.Directory

http://www.cirrus.com

108 dB, 192 kHz, Multi-bit Audio A/D Converter

Features

Advanced Multi-bit Delta-Sigma Architecture

24-bit Conversion

108 dB Dynamic Range

-98 dB THD+N

System Sampling Rates up to 192 kHz

135 mW Power Consumption

High-Pass Filter and DC Offset Calibration

Supports Logic Levels Between 5 and 2.5 V

Single-Ended Analog Inputs

Overflow Detection

Pin Compatible with the CS5361

General Description

The CS5351 is a complete analog-to-digital converter

for digital audio systems. It performs sampling, analog-

to-digital conversion, and anti-alias filtering. The device

generates 24-bit values for both left and right inputs in

serial form at sample rates up to 192 kHz per channel.

The CS5351 uses a 5th-order, multi-bit, delta-sigma

modulator followed by digital filtering and decimation,

which removes the need for an external anti-alias filter.

The ADC uses a differential architecture which provides

excellent noise rejection.

The CS5351 is ideal for audio systems requiring wide

dynamic range, negligible distortion, and low noise.

Such applications include A/V receivers, DVD-R, CD-R,

digital mixing consoles, and effects processors.

ORDERING INFORMATION

CS5351-KSZ, Lead Free -10° to 70°C 24-pin SOIC

CS5351-KZZ, Lead Free -10° to 70°C 24-pin TSSOP

CS5351-DZZ, Lead Free -40° to 85°C 24-pin TSSOP

CDB5351 Evaluation Board

Voltage Reference Serial Output Interface

Digital

Filter

High

Pass

Filter

High

Pass

Filter

Decimation

Digital

Filter

Decimation

DAC

S/H

DAC

S/H

AINR

SCLK SDOUT MCLK

RST

VQ3 LRCK

AINL

FILT+ I²S/LJ

M/S

HPF

MODE0

MODE1

REFGND V

MDIV

LP Filter

ΔΣ

OVFL

VQ1VQ2

MAY '07

DS565F2

CS5351

2DS565F2
CS5351
TABLE OF CONTENTS
1. CHARACTERISTICS AND SPECIFICATIONS ...................................................................................... 4
SPECIFIED OPERATING CONDITIONS  .............................................................................................. 4
ABSOLUTE MAXIMUM RATINGS  ........................................................................................................ 4
ANALOG CHARACTERISTICS (CS5351-KSZ/KZZ) ............................................................................. 5
ANALOG CHARACTERISTICS (CS5351-DZZ)  .................................................................................... 6
DIGITAL FILTER CHARACTERISTICS .................................................................................................7
DC ELECTRICAL CHARACTERISTICS .............................................................................................. 10
DIGITAL CHARACTERISTICS  ............................................................................................................ 10
THERMAL CHARACTERISTICS ......................................................................................................... 10
SWITCHING CHARACTERISTICS - SERIAL AUDIO PORT  .............................................................. 11
2. PIN DESCRIPTIONS  ............................................................................................................................ 14
3. TYPICAL CONNECTION DIAGRAM  ................................................................................................... 15
4. APPLICATIONS  ................................................................................................................................... 16
4.1 Operational Mode/Sample Rate Range Select  .............................................................................. 16
4.2 System Clocking  ............................................................................................................................ 16
4.2.1 Slave Mode  ........................................................................................................................... 16
4.2.2 Master Mode  ......................................................................................................................... 17
4.3 Power-Up Sequence ...................................................................................................................... 17
4.4 Analog Connections ....................................................................................................................... 18
4.5 High-Pass Filter and DC Offset Calibration  ................................................................................... 18
4.6 Overflow Detection ......................................................................................................................... 19
4.6.1 OVFL Output Timing  ............................................................................................................. 19
4.7 Grounding and Power Supply Decoupling  ..................................................................................... 19
4.8 Synchronization of Multiple Devices  .............................................................................................. 19
5. PARAMETER DEFINITIONS ................................................................................................................ 20
6. PACKAGE DIMENSIONS     ................................................................................................................. 21
7. REVISION HISTORY  ............................................................................................................................ 23

DS565F2 3
CS5351
LIST OF FIGURES
Figure 1. Single-Speed Mode Stopband Rejection  ..................................................................................... 8
Figure 2. Single-Speed Mode Transition Band  ........................................................................................... 8
Figure 3. Single-Speed Mode Transition Band (Detail) ............................................................................... 8
Figure 4. Single-Speed Mode Passband Ripple  ......................................................................................... 8
Figure 5. Double-Speed Mode Stopband Rejection .................................................................................... 8
Figure 6. Double-Speed Mode Transition Band .......................................................................................... 8
Figure 7. Double-Speed Mode Transition Band (Detail)  ............................................................................. 9
Figure 8. Double-Speed Mode Passband Ripple ........................................................................................ 9
Figure 9. Quad-Speed Mode Stopband Rejection  ...................................................................................... 9
Figure 10. Quad-Speed Mode Transition Band  .......................................................................................... 9
Figure 11. Quad-Speed Mode Transition Band (Detail) .............................................................................. 9
Figure 12. Quad-Speed Mode Passband Ripple  ........................................................................................ 9
Figure 13. Master Mode, Left-Justified SAI ............................................................................................... 12
Figure 14. Slave Mode, Left-Justified SAI ................................................................................................. 12
Figure 15. Master Mode, I²S SAI ............................................................................................................... 12
Figure 16. Slave Mode, I²S SAI ................................................................................................................. 12
Figure 17. OVFL Output Timing  ................................................................................................................ 12
Figure 18. Left-Justified Serial Audio Interface  ......................................................................................... 13
Figure 19. I²S Serial Audio Interface  ......................................................................................................... 13
Figure 20. OVFL Output Timing, I²S Format  ............................................................................................. 13
Figure 21. OVFL Output Timing, Left-Justified Format ............................................................................. 13
Figure 22. Typical Connection Diagram .................................................................................................... 15
Figure 23. CS5351 Master Mode Clocking  ............................................................................................... 17
Figure 24. CS5351 Recommended Analog Input Buffer ........................................................................... 18
LIST OF TABLES
Table 1. CS5351 Mode Control ................................................................................................................. 16
Table 2. CS5351 Slave Mode Clock Ratios  .............................................................................................. 16
Table 3. CS5351 Common Master Clock Frequencies ............................................................................. 17

4DS565F2

CS5351

1. CHARACTERISTICS AND SPECIFICATIONS

(All Min/Max characteristics and specifications are guaranteed over the Specified Operating Conditions. Typical

performance characteristics and specifications are derived from measurements taken at typical supply voltages

and TA = 25°C.)

SPECIFIED OPERATING CONDITIONS

(GND = 0 V, all voltages with respect to 0 V.)

ABSOLUTE MAXIMUM RATINGS

(GND = 0 V, All voltages with respect to ground.) (Note 1)

Notes: 1. Operation beyond these limits may result in permanent damage to the device.

Normal operation is not guaranteed at these extremes.

2. Any pin except supplies. Transient currents of up to ±100 mA on the analog input pins will not cause

SCR latch-up.

3. The maximum over/under voltage is limited by the input current.

Parameter Symbol Min Typ Max Unit

DC Power Supplies: Positive Analog

Positive Digital

Positive Logic

4.75

3.1

2.37

5.0

3.3

5.25

Ambient Operating Temperature Commercial (-KSZ/-KZZ)

Automotive (-DZZ)

TAC

TAI

-10

-40

°C

Parameter Symbol Min Max Units

DC Power Supplies: Analog

Logic

Digital

-0.3

+6.0

Input Current (Note 2) Iin -10 +10 mA

Analog Input Voltage (Note 3) VIN GND - 0.7 VA + 0.7 V

Digital Input Voltage (Note 3) VIND -0.7 VL + 0.7 V

Ambient Operating Temperature (Power Applied) TA-50 +95 °C

Storage Temperature Tstg -65 +150 °C

DS565F2 5

CS5351

ANALOG CHARACTERISTICS (CS5351-KSZ/KZZ)

(Test conditions (unless otherwise specified): Input test signal is a 1 kHz sine wave; measurement bandwidth is

10 Hz to 20 kHz.)

Notes: 4. Referred to the typical full-scale input voltage.

Parameter Symbol Min Typ Max Unit

Single-Speed Mode Fs = 48 kHz

Dynamic Range A-weighted

unweighted

102

108

105

Total Harmonic Distortion + Noise (Note 4)

-1 dB

-20 dB

-60 dB

THD+N

-98

-84

-44

-92

Double-Speed Mode Fs = 96 kHz

Dynamic Range A-weighted

unweighted

40 kHz bandwidth unweighted

102

108

105

102

Total Harmonic Distortion + Noise (Note 4)

-1 dB

-20 dB

-60 dB

40 kHz bandwidth -1 dB

THD+N

-98

-84

-44

-95

-92

Quad-Speed Mode Fs = 192 kHz

Dynamic Range A-weighted

unweighted

40 kHz bandwidth unweighted

102

108

105

102

Total Harmonic Distortion + Noise (Note 4)

-1 dB

-20 dB

-60 dB

40 kHz bandwidth -1 dB

THD+N

-98

-84

-44

-95

-92

Dynamic Performance for All Modes

Interchannel Isolation - 95 - dB

DC Accuracy

Interchannel Gain Mismatch - 0.1 - dB

Gain Error -2 - 2 %

Gain Drift -100 - 100 ppm/°C

Offset Error HPF enabled

HPF disabled

100

LSB

Analog Input Characteristics

Full-scale Input Voltage 0.55*VA 0.56*VA .57*VA Vpp

Input Impedance 7.5 - - kΩ

Common Mode Rejection Ratio CMRR - 82 - dB

6DS565F2

CS5351

ANALOG CHARACTERISTICS (CS5351-DZZ)

(Test conditions (unless otherwise specified): Input test signal is a 1 kHz sine wave; measurement bandwidth is

10 Hz to 20 kHz.)

Parameter Symbol Min Typ Max Unit

Single-Speed Mode Fs = 48 kHz

Dynamic Range A-weighted

unweighted

100

108

105

Total Harmonic Distortion + Noise (Note 4)

-1 dB

-20 dB

-60 dB

THD+N

-98

-84

-44

-90

Double-Speed Mode Fs = 96 kHz

Dynamic Range A-weighted

unweighted

40 kHz bandwidth unweighted

100

108

105

102

Total Harmonic Distortion + Noise (Note 4)

-1 dB

-20 dB

-60 dB

40 kHz bandwidth -1 dB

THD+N

-98

-84

-44

-95

-90

Quad-Speed Mode Fs = 192 kHz

Dynamic Range A-weighted

unweighted

40 kHz bandwidth unweighted

100

108

105

102

Total Harmonic Distortion + Noise (Note 4)

-1 dB

-20 dB

-60 dB

40 kHz bandwidth -1 dB

THD+N

-98

-84

-44

-95

-90

Dynamic Performance for All Modes

Interchannel Isolation - 95 - dB

DC Accuracy

Interchannel Gain Mismatch - 0.1 - dB

Gain Error -5 - 5 %

Gain Drift -100 - 100 ppm/°C

Offset Error HPF enabled

HPF disabled

100

LSB

Analog Input Characteristics

Full-scale Input Voltage 0.53*VA 0.56*VA 0.59*VA Vpp

Input Impedance 7.5 - - kΩ

Common Mode Rejection Ratio CMRR - 82 - dB

DS565F2 7
CS5351
DIGITAL FILTER CHARACTERISTICS
      
Notes: 5. The filter frequency response scales precisely with Fs.
6. Response shown is for Fs equal to 48 kHz. Filter characteristics scale with Fs.
Parameter Symbol Min Typ Max Unit
Single-Speed Mode (2 kHz to 51 kHz sample rates)
Passband (-0.1 dB)  (Note 5) 0-0.47Fs
Passband Ripple -0.1 - 0.035 dB
Stopband (Note 5) 0.58 - - Fs
Stopband Attenuation -95 - - dB
Total Group Delay (Fs = Output Sample Rate) tgd -12/Fs- s
Interchannel Phase Deviation - 0.0001 - Deg
Double-Speed Mode (50 kHz to 102 kHz sample rates)
Passband (-0.1 dB) (Note 5) 0-0.45Fs
Passband Ripple -0.1 - 0.035 dB
Stopband (Note 5) 0.68 - - Fs
Stopband Attenuation -92 - - dB
Total Group Delay (Fs = Output Sample Rate) tgd -9/Fs- s
Interchannel Phase Deviation - 0.0001 - Deg
Quad-Speed Mode (100 kHz to 204 kHz sample rates)
Passband (-0.1 dB) (Note 5) 0-0.24Fs
Passband Ripple -0.1 - 0.035 dB
Stopband (Note 5) 0.78 - - Fs
Stopband Attenuation -92 - - dB
Total Group Delay (Fs = Output Sample Rate) tgd -5/Fs- s
Interchannel Phase Deviation - 0.0001 - Deg
High Pass Filter Characteristics
Frequency Response -3.0 dB
-0.13 dB (Note 6)
-1
20
-
-
Hz
Hz
Phase Deviation @ 20 Hz (Note 6) -10-Deg
Passband Ripple --0dB
Filter Settling Time 105/Fs s

8DS565F2

CS5351

Figure 1. Single-Speed Mode Stopband Rejection Figure 2. Single-Speed Mode Transition Band

-140

-130

-120

-110

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

0.00.10.20.30.40.50.60.70.80.91.0

Frequency (normalized to Fs)

Amplitude (dB)

-140

-130

-120

-110

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

0.40 0.42 0.44 0.46 0.48 0.50 0.52 0.54 0.56 0.58 0.60

Frequency (normalized to Fs)

Amplitude (dB)

Figure 3. Single-Speed Mode Transition Band (Detail) Figure 4. Single-Speed Mode Passband Ripple

-10

-9

-8

-7

-6

-5

-4

-3

-2

-1

0.45 0.46 0.47 0.48 0.49 0.50 0.51 0.52 0.53 0.54 0.55

Frequency (normalized to Fs)

Amplitude (dB)

-0.10

-0.08

-0.05

-0.03

0.00

0.03

0.05

0.08

0.10

0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50

Frequency (normalized to Fs)

Amplitude (dB)

Figure 5. Double-Speed Mode Stopband Rejection Figure 6. Double-Speed Mode Transition Band

-140

-130

-120

-110

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0

Frequency (normalized to Fs)

Amplitude (dB)

-140

-130

-120

-110

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

0.40 0.43 0.45 0.48 0.50 0.53 0.55 0.58 0.60 0.63 0.65 0.68 0.70

Frequency (normalized to Fs)

Amplitude (dB)

DS565F2 9

CS5351

Figure 7. Double-Speed Mode Transition Band (Detail) Figure 8. Double-Speed Mode Passband Ripple

-10

-9

-8

-7

-6

-5

-4

-3

-2

-1

0.40 0.43 0.45 0.48 0.50 0.53 0.55

Frequency (normalized to Fs)

Amplitude (dB)

-0.10

-0.08

-0.05

-0.03

0.00

0.03

0.05

0.08

0.10

0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50

Frequency (normalized to Fs)

Amplitude (dB)

Figure 9. Quad-Speed Mode Stopband Rejection Figure 10. Quad-Speed Mode Transition Band

Amplitude (dB)

Frequency (normalized to Fs)

Amplitude (dB)

Frequency (normalized to Fs)

Figure 11. Quad-Speed Mode Transition Band (Detail) Figure 12. Quad-Speed Mode Passband Ripple

Amplitude (dB)

Frequency (norm alized to Fs)

Frequency (normalized to Fs)

Amplitude (dB)

10 DS565F2

CS5351

DC ELECTRICAL CHARACTERISTICS

(GND = 0 V, all voltages with respect to ground. MCLK=12.288 MHz; Master Mode)

Notes: 7. Power Down Mode is defined as RST = Low with all clocks and data lines held static.

8. Valid with the recommended capacitor values on FILT+ and VQ as shown in the Typical Connection

Diagram.

DIGITAL CHARACTERISTICS

THERMAL CHARACTERISTICS

Parameter Symbol Min Typ Max Unit

Power Supply Current VA = 5 V

(Normal Operation) VL,VD = 5 V

VL,VD = 3.3 V

17.5

14.5

21.5

27.5

Power Supply Current VA = 5 V

(Power-Down Mode) (Note 7) VL,VD = 5 V

100

μA

Power Consumption

(Normal Operation) VA, VD, VL = 5 V

VA = 5 V, VL, VD = 3.3 V

(Power-Down Mode)

198

135

243

161

Power Supply Rejection Ratio (1 kHz) (Note 8) PSRR - 65 - dB

VQ Nominal Voltage

Output Impedance

Maximum allowable DC current source/sink

2.5

0.01

kΩ

Filt+ Nominal Voltage

Output Impedance

Maximum allowable DC current source/sink

0.01

kΩ

Parameter Symbol Min Typ Max Units

High-Level Input Voltage (% of VL) VIH 70% - - V

Low-Level Input Voltage (% of VL) VIL --30%V

High-Level Output Voltage at Io = 100 μA(% of VL)V

OH 70% - - V

Low-Level Output Voltage at Io = 100 μA(% of VL)V

OL --15%V

OVFL Current Sink Iovfl --4.0mA

Input Leakage Current (all pins except SCLK and LRCK) Iin -10 - 10 μA

Input Leakage Current (SCLK and LRCK) Iin -25 - 25 μA

Parameter Symbol Min Typ Max Unit

Allowable Junction Temperature --135

°C

Junction to Ambient Thermal Impedance

(Multi-layer PCB) TSSOP

(Multi-layer PCB) SOIC

(Single-layer PCB) TSSOP

(Single-layer PCB) SOIC

θJA-TM

θJA-SM

θJA-TS

θJA-SS

105

°C/W

DS565F2 11

CS5351

SWITCHING CHARACTERISTICS - SERIAL AUDIO PORT

(Logic "0" = GND = 0 V; Logic "1" = VL, CL = 20 pF)

Parameter Symbol Min Typ Max Unit

Output Sample Rate Single-Speed Mode

Double-Speed Mode

Quad-Speed Mode

100

102

204

kHz

OVFL to LRCK edge setup time tsetup 16/fsclk --s

OVFL to LRCK edge hold time thold 1/fsclk --s

OVFL time-out on overrange condition

Fs = 44.1, 88.2, 176.4 kHz

Fs = 48, 96, 192 kHz

740

680

MCLK Specifications

MCLK Period tclkw 38 - 1953 ns

MCLK Pulse Duty Cycle 40 50 60 %

Master Mode

SCLK falling to LRCK tmslr -20 - 20 ns

SCLK falling to SDOUT valid tsdo 0 - 32 ns

SCLK Duty Cycle - 50 - %

Slave Mode

Single-Speed

Output Sample Rate Fs 2 - 51 kHz

LRCK Duty Cycle 405060%

SCLK Period tsclkw 153 - - ns

SCLK Duty Cycle 455055%

SCLK falling to SDOUT valid tdss - - 32 ns

SCLK falling to LRCK edge tslrd -20 - 20 ns

Double-Speed

Output Sample Rate Fs 50 - 102 kHz

LRCK Duty Cycle 405060%

SCLK Period tsclkw 153 - - ns

SCLK Duty Cycle 455055%

SCLK falling to SDOUT valid tdss - - 32 ns

SCLK falling to LRCK edge tslrd -20 - 20 ns

Quad-Speed

Output Sample Rate Fs 100 - 204 kHz

LRCK Duty Cycle 405060%

SCLK Period tsclkw 77 - - ns

SCLK Duty Cycle 455055%

SCLK falling to SDOUT valid tdss - - 32 ns

SCLK falling to LRCK edge tslrd -8 - 3 ns

12 DS565F2

CS5351

Figure 13. Master Mode, Left-Justified SAI Figure 14. Slave Mode, Left-Justified SAI

SCLK output

tmslr

SDOUT

tsdo

LRCK

output

MSB MSB-1

CLK input

LRCK input

dss

MSB MSB-1 MSB-2

tsclkw

SDOUT

srdl

Figure 15. Master Mode, I²S SAI Figure 16. Slave Mode, I²S SAI

SCLK input

LRCK input

MSB MSB-1

tsclkw

SDOUT

srdl

dss

SCLK input

LRCK input

MSB MSB-1

tsclkw

SDOUT

srdl

dss

OVFL

tsetup

LRCK

thold

Figure 17. OVFL Output Timing

DS565F2 13

CS5351

Figure 18. Left-Justified Serial Audio Interface

SDATA 23 22 7 623 22

SCLK

LRCK

23 2254321087654321089 9

Left Channel Right Channel

Figure 19. I²S Serial Audio Interface

SDATA 23 22 8 723 22

SCLK

LRCK

23 2265432108765432109 9

Left Channel Right Channel

Figure 20. OVFL Output Timing, I²S Format

LRCK

OVFL

SCLK

OVFL_R OVFL_L OVFL_R

Figure 21. OVFL Output Timing, Left-Justified Format

LRCK

OVFL

SCLK

OVFL_R OVFL_L OVFL_R

14 DS565F2

CS5351

2. PIN DESCRIPTIONS

Pin Name # Pin Description

RST 1Reset (Input) - The device enters a low power mode when low.

M/S 2Master/Slave Mode (Input) - Selects operation as either clock master or slave.

LRCK 3Left Right Clock (Input/Output) - Determines which channel, Left or Right, is currently active on the

serial audio data line.

SCLK 4 Serial Clock (Input/Output) - Serial clock for the serial audio interface.

MCLK 5 Master Clock (Input) - Clock source for the delta-sigma modulator and digital filters.

VD 6 Digital Power (Input) - Positive power supply for the digital section.

GND 7

18 Ground (Input) - Ground reference. Must be connected to analog ground.

VL 8 Logic Power (Input) - Positive power for the digital input/output.

SDOUT 9 Serial Audio Data Output (Output) - Output for two’s complement serial audio data.

MDIV 10 MCLK Divider (Input) - Enables a master clock divide by two function.

HPF 11 High Pass Filter Enable (Input) - Enables the Digital High-Pass Filter.

I²S/LJ 12 Serial Audio Interface Format Select (Input) -Selects either the Left-Justified or I²S format for the SAI.

14 Mode Selection (Input) - Determines the operational mode of the device.

OVFL 15 Overflow (Output, open drain) - Detects an overflow condition on both left and right channels.

AINL

AINR

Analog Inputs (Input) - The full-scale analog input level is specified in the Analog Characteristics speci-

fication table.

VQ1

VQ2

VQ3

Quiescent Voltage (Output) - Filter connection for the internal quiescent reference voltage.

VA 19 Analog Power (Input) - Positive power supply for the analog section.

REF_GND 23 Reference Ground (Input) - Ground reference for the internal sampling circuits.

FILT+ 24 Positive Voltage Reference (Output) - Positive reference voltage for the internal sampling circuits.

RST 124FILT+

M/S 223REFGND

LRCK 322VQ3

SCLK 421AINR

MCLK 520VQ2

VD 619VA

GND 718GND

VL 817VQ1

SDOUT 916AINL

MDIV 10 15 OVFL

HPF 11 14 M1

I²S/LJ 12 13 M0

DS565F2 15

CS5351

3. TYPICAL CONNECTION DIAGRAM

FILT+

AINL

0.01 μF

A/D CONVERTER

SCLK

CS5351

M/S

MCLK

AINR

47 μF+

RST

VA V L

+5V

1μF

+5V to 2.5V

5.1 Ω

1μF

SDOUT

GND

I2S/LJ

LRCK

GND

Power Down

and Mode

Settings

Audio Data

Processor

Timing Logic

and Clock

0.01 μF

HPF

REFGND

MDIV

+5 V to 3.3 V

1μF

Analog

Input

Buffer

(Figure 24)

OVFL

10 kΩ

* Resistor may only be used

if VD is derived from VA. If

used, do not drive any other

logic from VD

0.01 μF

0.01 μF0.01 μF

VQ1

VQ3

VQ2

Figure 22. Typical Connection Diagram

16 DS565F2

CS5351

4. APPLICATIONS

4.1 Operational Mode/Sample Rate Range Select

The output sample rate, Fs, can be adjusted from 2 kHz to 204 kHz. The CS5351 must be set to the proper

speed mode via the mode pins, M1 and M0. Refer to Table 1.

4.2 System Clocking

The device supports operation in either Master Mode, where the left/right and serial clocks are synchronous-

ly generated on-chip, or Slave Mode, which requires external generation of the left/right and serial clocks.

The device also includes a master clock divider in Master Mode where the master clock will be internally

divided prior to any other internal circuitry when MDIV is enabled, set to logic 1. In Slave Mode, the MDIV

pin needs to be disabled, set to logic 0.

4.2.1 Slave Mode

LRCK and SCLK operate as inputs in Slave Mode. The left/right clock must be synchronously derived

from the master clock and be equal to Fs. It is also recommended that the serial clock be synchronously

derived from the master clock and be equal to 64x Fs to maximize system performance. Refer to Table 2

for required clock ratios.

Table 2. CS5351 Slave Mode Clock Ratios

M1 (Pin 14) M0 (Pin 13) MODE Output Sample Rate (Fs)

Single-Speed Mode 2 kHz - 51 kHz

Double-Speed Mode 50 kHz - 102 kHz

Quad-Speed Mode 100 kHz - 204 kHz

Reserved

Table 1. CS5351 Mode Control

Single-Speed Mode

Fs = 2 kHz to 51 kHz

Double-Speed Mode

Fs = 50 kHz to 102 kHz

Quad-Speed Mode

Fs = 100 kHz to 204 kHz

MCLK/LRCK Ratio 256x, 512x 128x, 256x 128x

SCLK/LRCK Ratio 32x, 64x, 128x 32x, 64x 32x, 64x

DS565F2 17

CS5351

4.2.2 Master Mode

In Master Mode, LRCK and SCLK operate as outputs. The left/right and serial clocks are internally derived

from the master clock with the left/right clock equal to Fs and the serial clock equal to 64x Fs, as shown

in Figure 23. Refer to Table 3 for common master clock frequencies.

4.3 Power-Up Sequence

Reliable power-up can be accomplished by keeping the device in reset until the power supplies, clocks and

configuration pins are stable. It is also recommended that reset be enabled if the analog or digital supplies

drop below the minimum specified operating voltages to prevent power glitch related issues.

The internal reference voltage must be stable for the device to produce valid data. Therefore, there is a de-

lay between the release of reset and the generation of valid output due to the finite output impedance of

FILT+ and the presence of the external capacitance.

÷ 128

÷ 256

÷ 64

M0M1

LRCK Output

(Equal to Fs)

Single

Speed

Quad

Speed

Double

Speed

÷ 2

÷ 4

÷ 1

SCLK Output

Single

Speed

Quad

Speed

Double

Speed

÷ 2

÷ 1 0

MCLK

MDIV

Figure 23. CS5351 Master Mode Clocking

SAMPLE RATE (kHz)

MDIV = 0

MCLK (MHz)

MDIV = 1

MCLK (MHz)

32 8.192 16.384

44.1 11.2896 22.5792

48 12.288 24.576

64 8.192 16.384

88.2 11.2896 22.5792

96 12.288 24.576

176.4 11.2896 22.5792

192 12.288 24.576

Table 3. CS5351 Common Master Clock Frequencies

18 DS565F2

CS5351

4.4 Analog Connections

The analog modulator samples the input at 6.144 MHz. The digital filter will reject signals within the stop-

band of the filter. However, there is no rejection for input signals which are (n ×6.144 MHz) the digital pass-

band frequency, where n=0,1,2,...Refer to Figure 24 which shows the suggested filter that will attenuate any

noise energy at 6.144 MHz, in addition to providing the optimum source impedance for the modulators. The

use of capacitors which have a large voltage coefficient (such as general purpose ceramics) must be avoid-

ed since these can degrade signal linearity.

4.5 High-Pass Filter and DC Offset Calibration

The operational amplifiers in the input circuitry driving the CS5351 may generate a small DC offset into the

A/D converter. The CS5351 includes a high pass filter after the decimator to remove any DC offset which

could result in recording a DC level, possibly yielding "clicks" when switching between devices in a multi-

channel system.

The high pass filter continuously subtracts a measure of the DC offset from the output of the decimation

filter. If the HPF pin is taken high during normal operation, the current value of the DC offset register is frozen

and this DC offset will continue to be subtracted from the conversion result. This feature makes it possible

to perform a system DC offset calibration by:

Running the CS5351 with the high pass filter enabled until the filter settles. See the Digital Filter Character-

istics for filter settling time.

Disabling the high pass filter and freezing the stored DC offset.

A system calibration performed in this way will eliminate offsets anywhere in the signal path between the

calibration point and the CS5351.

Figure 24. CS5351 Recommended Analog Input Buffer

AINL

VQ1

VQ3

470 pF

C0G

CS5351

634 Ω

91 Ω

2700 pF

C0G

1μF

100 kΩ

1μF0.01 μF

AINR

2700 pF

C0G

470 pF

C0G

91 Ω

634 Ω

VQ2

100 kΩ

DS565F2 19

CS5351

4.6 Overflow Detection

The CS5351 includes overflow detection on both the left and right channels. This time multiplexed informa-

tion is presented as open drain, active low on pin 15, OVFL. The OVFL_L and OVFL_R data will go to a

logical low as soon as an overrange condition in either channel is detected. The data will remain low as

specified in the Switching Characteristics - Serial Audio Port section. This ensures sufficient time to detect

an overrange condition regardless of the speed mode. After the timeout, the OVFL_L and OVFL_R data will

return to a logical high if there has not been any other overrange condition detected. Please note that an

overrange condition on either channel will restart the timeout period for both channels.

4.6.1 OVFL Output Timing

In Left-Justified format, the OVFL pin is updated one SCLK period after an LRCK transition. In I²S format,

the OVFL pin is updated two SCLK periods after an LRCK transition. Refer to Figures 23 and 24. In both

cases the OVFL data can be easily demultiplexed by using the LRCK to latch the data. In left-justified for-

mat, the rising edge of LRCK would latch the right channel overflow status, and the falling edge of LRCK

would latch the left channel overflow status. In I²S format, the falling edge of LRCK would latch the right

channel overflow status and the rising edge of LRCK would latch the left channel overflow status.

4.7 Grounding and Power Supply Decoupling

As with any high-resolution converter, the CS5351 requires careful attention to power supply and grounding

arrangements if its potential performance is to be realized. Figure 22 shows the recommended power ar-

rangements, with VA and VL connected to clean supplies. VD, which powers the digital filter, may be run

from the system logic supply or may be powered from the analog supply via a resistor. In this case, no ad-

ditional devices should be powered from VD. Decoupling capacitors should be as near to the ADC as pos-

sible, with the low value ceramic capacitor being the nearest. All signals, especially clocks, should be kept

away from the FILT+ and VQ pins in order to avoid unwanted coupling into the modulators. The FILT+ and

VQ decoupling capacitors, particularly the 0.01 µF, must be positioned to minimize the electrical path from

FILT+ and REFGND. The CDB5351 evaluation board demonstrates the optimum layout and power supply

arrangements. To minimize digital noise, connect the ADC digital outputs only to CMOS inputs.

4.8 Synchronization of Multiple Devices

In systems where multiple ADCs are required, care must be taken to achieve simultaneous sampling. To

ensure synchronous sampling, the MCLK and LRCK must be the same for all of the CS5351’s in the system.

If only one master clock source is needed, one solution is to place one CS5351 in Master Mode, and slave

all of the other CS5351’s to the one master. If multiple master clock sources are needed, a possible solution

would be to supply all clocks from the same external source and time the CS5351 reset with the inactive

edge of MCLK. This will ensure that all converters begin sampling on the same clock edge.

20 DS565F2

CS5351

5. PARAMETER DEFINITIONS

Dynamic Range

The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified

bandwidth. Dynamic Range is a signal-to-noise ratio measurement over the specified bandwidth made

with a -60 dBFS signal. 60 dB is added to resulting measurement to refer the measurement to full-scale.

This technique ensures that the distortion components are below the noise level and do not affect the

measurement. This measurement technique has been accepted by the Audio Engineering Society,

AES17-1991, and the Electronic Industries Association of Japan, EIAJ CP-307. Expressed in decibels.

Total Harmonic Distortion + Noise

The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified

bandwidth (typically 10 Hz to 20 kHz), including distortion components. Expressed in decibels. Measured

at -1 and -20 dBFS as suggested in AES17-1991 Annex A.

Frequency Response

A measure of the amplitude response variation from 10 Hz to 20 kHz relative to the amplitude response

at 1 kHz. Units in decibels.

Interchannel Isolation

A measure of crosstalk between the left and right channels. Measured for each channel at the converter's

output with no signal to the input under test and a full-scale signal applied to the other channel. Units in

decibels.

Interchannel Gain Mismatch

The gain difference between left and right channels. Units in decibels.

Gain Error

The deviation from the nominal full-scale analog output for a full-scale digital input.

Gain Drift

The change in gain value with temperature. Units in ppm/°C.

Offset Error

The deviation of the mid-scale transition (111...111 to 000...000) from the ideal. Units in mV.

DS565F2 21

CS5351

6. PACKAGE DIMENSIONS

INCHES MILLIMETERS

DIM MIN MAX MIN MAX

A 0.093 0.104 2.35 2.65

A1 0.004 0.012 0.10 0.30

B 0.013 0.020 0.33 0.51

C 0.009 0.013 0.23 0.32

D 0.598 0.614 15.20 15.60

E 0.291 0.299 7.40 7.60

e 0.040 0.060 1.02 1.52

H 0.394 0.419 10.00 10.65

L 0.016 0.050 0.40 1.27

∝0° 8° 0° 8°

24L SOIC (300 MIL BODY) PACKAGE DRAWING

∝

SEATING

PLANE

22 DS565F2

CS5351

Notes:

1. “D” and “E1” are reference datums and do not included mold flash or protrusions, but do include mold

mismatch and are measured at the parting line, mold flash or protrusions shall not exceed 0.20 mm per

side.

2. Dimension “b” does not include dambar protrusion/intrusion. Allowable dambar protrusion shall be

0.13 mm total in excess of “b” dimension at maximum material condition. Dambar intrusion shall not re-

duce dimension “b” by more than 0.07 mm at least material condition.

3. These dimensions apply to the flat section of the lead between 0.10 and 0.25 mm from lead tips.

INCHES MILLIMETERS NOTE

DIM MIN NOM MAX MIN NOM MAX

A -- -- 0.043 -- -- 1.10

A1 0.002 0.004 0.006 0.05 -- 0.15

A2 0.03346 0.0354 0.037 0.85 0.90 0.95

b 0.00748 0.0096 0.012 0.19 0.245 0.30 2,3

D 0.303 0.307 0.311 7.70 7.80 7.90 1

E 0.248 0.2519 0.256 6.30 6.40 6.50

E1 0.169 0.1732 0.177 4.30 4.40 4.50 1

e -- 0.026 BSC -- -- 0.65 BSC --

L 0.020 0.024 0.028 0.50 0.60 0.70

µ0° 4° 8° 0° 4° 8°

JEDEC #: MO-153

Controlling Dimension is Millimeters.

24L TSSOP (4.4 mm BODY) PACKAGE DRAWING

123

eb2A1

A2 A

SEATING

PLANE

E11

SIDE VIEW

END VIEW

TOP VIEW

∝

DS565F2 23

CS5351

7. REVISION HISTORY

Release Changes

PP2 Preliminary datasheet.

F1 Improve Gain Error specification under Analog Characteristics.

Specify Full-scale Input Voltage in terms of VA under Analog Characteristics.

Update Differential Input Impedance under Analog Characteristics.

Increase maximum Power-Supply Current, IA, under DC Electrical Characteristics.

Reduce maximum Power Consumption under DC Electrical Characteristics.

Update FILT+ Output Impedance specification under DC Electrical Characteristics.

Extend maximum Fs in Single-Speed Mode to 51 kHz.

Extend maximum Fs in Double-Speed Mode to 102 kHz.

Extend maximum Fs in Quad-Speed Mode to 204 kHz.

Decrease maximum SCLK falling to LRCK edge specification in Quad-Speed Mode.

Replace minimum MCLK high/low timing specifications with duty cycle specification.

Replace minimum SCLK high/low timing specifications with duty cycle specification.

Replace recommended analog input buffer with new input buffer topology.

F2 Updated ordering information.

Contacting Cirrus Logic Support

For all product questions and inquiries, contact a Cirrus Logic Sales Representative.

To find the one nearest you, go to www.cirrus.com.

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