DOCUMENT NUMBER 9S12DP512DGV1/D MC9S12DP512 Device Guide V01.25 Covers also MC9S12DT512, MC9S12DJ512, MC9S12A512 Original Release Date: 27 Nov 2001 Revised: 05 Jul 2005 Freescale Semiconductor, Inc. 1 DOCUMENT NUMBER 9S12DP512DGV1/D Revision History Version Revision Effective Number Date Date V01.00 27 Nov 2001 Author Description of Changes 11 Feb 2002 - Initial version based on DP256 V2.09. V01.01 13 Mar 2002 13 Mar 2002 - Updated document formats. - Removed reference to SIM in overview. - Changed XCLKS to PE7 in signal description. - Removed "Oscillator start-up time from POR or STOP" from Oscillator Characterisitcs. - Changed VDD and VDDPLL to 2.35V. - Updated CINS. - Updated IOL/IOH values. - Updated input capacitance. - Updated NVM timing characteristics. V01.02 02 Apr 2002 02 Apr 2002 - Updated document reference (SPI, SCI). V01.03 15 Apr 2002 15 Apr 2002 - Corrected values in device memory map (RAM start, flash protected sector sizes). - Updated document reference (SCI). V01.04 06 Jun 2002 06 Jun 2002 - Changed all operating frequency references to 50MHz EXTAL and removed references to 80 pin LQFP. 05 Jul 2002 - Preface Table "Document References": Changed to full naming for each block. - Table "Interrupt Vector Locations", Column "Local Enable": Corrected several register and bit names. - Table "Signal Properties": Added column "Internal Pull Resistor". - Table "PLL Characteristics": Updated parameters K1 and f1 - Figure "Basic Pll functional diagram": Inserted XFC pin in diagram - Enhanced section "XFC Component Selection" - Added to Sections ATD, ECT and PWM: freeze mode = active BDM mode. V01.05 05 Jul 2002 Freescale reserves the right to make changes without further notice to any products herein to improve reliability, function or design.Freescale does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others.Freescale products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Freescale product could create a situation where personal injury or death may occur. Should Buyer purchase or use Freescale products for any such unintended or unauthorized application, Buyer shall indemnify and hold Freescale and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Freescale was negligent regarding the design or manufacture of the part. MC9S12DP512 Device Guide V01.25 Version Revision Effective Number Date Date V01.06 24 Jul 2002 24 Jul 2002 Author Description of Changes - Updated SPI electrical characteristics. - Updated Derivative Differences table. - Added ordering number example. - Added Detailed Register Map. - Changed Internal Pull Resistor column of signal table. - Added pull device description for MODC pin. - Corrected XCLKS figure titles. Moved table to section Modes of Operation. - Removed '1/2' from BDM in Figure Clock Connections. - Completely reworked section Modes of Operation. Added Chip Configuration Summary and Low Power Mode description. - Changed classification to C for internal pull currents inTable 5V I/O Characteristics. - Changed input leakage to 1uA for all pins. - Updated VREG section and layout recommendation. - Moved Power and Gound Connection Summary table to start of Power Supply Pins section. - Added ROMONE to pinout - Corrected mem map: 'MEBI map x of 3' - Corrected mem map: KEYEN bits in FSEC. - Added section Printed Circuit Board Layout Proposal. - Corrected addresses in Reserved, CAN and EEP buffer map. - Updated NVM electricals. V01.07 29 Jul 2002 05 Aug 2002 V01.08 21 Aug 2002 21 Aug 2002 - Updated table 'Document References' - Added section 'Oscillator (OSC) Block Description' V01.09 24 Sep 2002 24 Sep 2002 - Section HCS12 Core Block Desciption: mentioned alternalte clock of BDM to be equivalent to oscillator clock - Corrected tables 0-1 and 0-2 V01.10 18 Oct 2002 18 Oct 2002 - Added derivatives to cover sheet. - Added part ID for 1L00M maskset. - Corrected in footnote of Table "PLL Characteristics": fOSC = 4MHz. V01.11 29 Oct 2002 29 Oct 2002 - Renamed Preface section to Derivative Differences and Document references. - Added A512 derivative. - Updated module set of DJ512 in Table 0-1. - Added details for derivatives without CAN and/or BDLC modules. V01.12 03 Dec 2002 03 Dec 2002 - Corrected several entries in 'Detailed Memory Map'. - Removed footnote on input leakage current from table '5V I/O Characteristics'. V01.13 08 Jan 2003 08 Jan 2003 - Updated section 'Unsecuring the Microcontroller'. - Updated footnote 1 in table 'Operating Conditions'. V01.14 23 Jan 2003 23 Jan 2003 - Renamed ROMONE pin to ROMCTL. V01.15 28 Feb 2003 28 Feb 2003 - Corrected PE[1,0] pull specification in Signal Properties Summary Table. 3 MC9S12DP512 Device Guide V01.25 Version Revision Effective Number Date Date Author Description of Changes V01.16 31 Mar 2003 31 Mar 2003 - Corrections in App. A 'NVM, Flash and EEPROM': - Number of words per flash row = 64 - Replaced 'burst programming' with 'row programming' - Sector erase size = 1024 bytes - Corrected feature description ECT - Corrected min. bus freq. in table 'Operating Conditions' V01.17 30 May 2003 30 May 2003 - Replaced references to HCS12 Core Guide with the individual HCS12 Block guides throughout document - Table 'Absolute Maximum Ratings' corrected footnote on clamp of TEST pin V01.18 23 Jul 2003 23 Jul 2003 - Mentioned 'S12 LRAE' bootloader in Flash section - Document References: corrected S12 CPU document reference V01.19 24 Jul 2003 24 Jul 2003 - Added part ID for 2L00M maskset. V01.20 01 Sep 2003 01 Sep 2003 - Added part ID for 3L00M maskset. - Added cycle definition to 'CPU 12 Block Description'. - Diagram 'Clock Connections': Connected Bus Clock to HCS12 Core. - Corrected 'Background Debug Module' to 'HCS12 Breakpoint' at address $0028 - $002F in table 1-1. - Corrected 'Blank Check Time Flash' value in table 'NVM Timing Characteristics' - Added EXTAL pin VIH, VIL and EXTAL pin hysteresis value to 'Oscillator Characteristics'. Updated oscillator description and table note. V01.21 08 Mar 2004 08 Mar 2004 - Added part ID for 4L00M maskset. - Corrected pin name KWP5 in device pinout. V01.22 23 Aug 2004 23 Aug 2004 - Updated VIH,EXTAL and VIL,EXTAL in table 'Oscillator Characteristics' - Removed item 'Oscillator' from table 'Operating Conditions' as already covered in table 'Oscillator Characteristics' V01.23 09 Feb 2005 09 Feb 2005 - Corrected Flash Row Programming Time in NVM Timing Characteristics V01.24 01 Apr 2005 01 Apr 2005 - Changed TJavg and added footnote to data retention time in NVM Reliability Characteristics V01.25 05 Jul 2005 05 Jul 2005 - Updated NVM Reliability Characteristics MC9S12DP512 Device Guide V01.25 Table of Contents Section 1 Introduction 1.1 1.2 1.3 1.4 1.5 1.5.1 1.6 1.7 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 Device Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 Detailed Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 Part ID Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 Memory Size Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 Section 2 Signal Description 2.1 Device Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 2.2 Signal Properties Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 2.3 Detailed Signal Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 2.3.1 EXTAL, XTAL -- Oscillator Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 2.3.2 RESET -- External Reset Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 2.3.3 TEST -- Test Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 2.3.4 VREGEN -- Voltage Regulator Enable Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 2.3.5 XFC -- PLL Loop Filter Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 2.3.6 BKGD / TAGHI / MODC -- Background Debug, Tag High, and Mode Pin . . . . . . . .56 2.3.7 PAD15 / AN15 / ETRIG1 -- Port AD Input Pin of ATD1 . . . . . . . . . . . . . . . . . . . . . .56 2.3.8 PAD[14:08] / AN[14:08] -- Port AD Input Pins of ATD1 . . . . . . . . . . . . . . . . . . . . . .56 2.3.9 PAD7 / AN07 / ETRIG0 -- Port AD Input Pin of ATD0 . . . . . . . . . . . . . . . . . . . . . . .56 2.3.10 PAD[06:00] / AN[06:00] -- Port AD Input Pins of ATD0 . . . . . . . . . . . . . . . . . . . . . .56 2.3.11 PA[7:0] / ADDR[15:8] / DATA[15:8] -- Port A I/O Pins . . . . . . . . . . . . . . . . . . . . . . .57 2.3.12 PB[7:0] / ADDR[7:0] / DATA[7:0] -- Port B I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . .57 2.3.13 PE7 / NOACC / XCLKS -- Port E I/O Pin 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 2.3.14 PE6 / MODB / IPIPE1 -- Port E I/O Pin 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 2.3.15 PE5 / MODA / IPIPE0 -- Port E I/O Pin 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 2.3.16 PE4 / ECLK -- Port E I/O Pin 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 2.3.17 PE3 / LSTRB / TAGLO -- Port E I/O Pin 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 2.3.18 PE2 / R/W -- Port E I/O Pin 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 2.3.19 PE1 / IRQ -- Port E Input Pin 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 5 MC9S12DP512 Device Guide V01.25 2.3.20 2.3.21 2.3.22 2.3.23 2.3.24 2.3.25 2.3.26 2.3.27 2.3.28 2.3.29 2.3.30 2.3.31 2.3.32 2.3.33 2.3.34 2.3.35 2.3.36 2.3.37 2.3.38 2.3.39 2.3.40 2.3.41 2.3.42 2.3.43 2.3.44 2.3.45 2.3.46 2.3.47 2.3.48 2.3.49 2.3.50 2.3.51 2.3.52 2.3.53 2.3.54 2.3.55 PE0 / XIRQ -- Port E Input Pin 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 PH7 / KWH7 / SS2 -- Port H I/O Pin 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 PH6 / KWH6 / SCK2 -- Port H I/O Pin 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 PH5 / KWH5 / MOSI2 -- Port H I/O Pin 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 PH4 / KWH4 / MISO2 -- Port H I/O Pin 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 PH3 / KWH3 / SS1 -- Port H I/O Pin 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 PH2 / KWH2 / SCK1 -- Port H I/O Pin 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 PH1 / KWH1 / MOSI1 -- Port H I/O Pin 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 PH0 / KWH0 / MISO1 -- Port H I/O Pin 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 PJ7 / KWJ7 / TXCAN4 / SCL / TXCAN0 -- PORT J I/O Pin 7. . . . . . . . . . . . . . . . . .60 PJ6 / KWJ6 / RXCAN4 / SDA / RXCAN0 -- PORT J I/O Pin 6 . . . . . . . . . . . . . . . . .60 PJ[1:0] / KWJ[1:0] -- Port J I/O Pins [1:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 PK7 / ECS / ROMCTL -- Port K I/O Pin 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 PK[5:0] / XADDR[19:14] -- Port K I/O Pins [5:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 PM7 / TXCAN3 / TXCAN4 -- Port M I/O Pin 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 PM6 / RXCAN3 / RXCAN4 -- Port M I/O Pin 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 PM5 / TXCAN2 / TXCAN0 / TXCAN4 / SCK0 -- Port M I/O Pin 5. . . . . . . . . . . . . . .61 PM4 / RXCAN2 / RXCAN0 / RXCAN4/ MOSI0 -- Port M I/O Pin 4. . . . . . . . . . . . . .61 PM3 / TXCAN1 / TXCAN0 / SS0 -- Port M I/O Pin 3 . . . . . . . . . . . . . . . . . . . . . . . .61 PM2 / RXCAN1 / RXCAN0 / MISO0 -- Port M I/O Pin 2 . . . . . . . . . . . . . . . . . . . . . .61 PM1 / TXCAN0 / TXB -- Port M I/O Pin 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 PM0 / RXCAN0 / RXB -- Port M I/O Pin 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 PP7 / KWP7 / PWM7 / SCK2 -- Port P I/O Pin 7 . . . . . . . . . . . . . . . . . . . . . . . . . . .62 PP6 / KWP6 / PWM6 / SS2 -- Port P I/O Pin 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 PP5 / KWP5 / PWM5 / MOSI2 -- Port P I/O Pin 5. . . . . . . . . . . . . . . . . . . . . . . . . . .62 PP4 / KWP4 / PWM4 / MISO2 -- Port P I/O Pin 4. . . . . . . . . . . . . . . . . . . . . . . . . . .62 PP3 / KWP3 / PWM3 / SS1 -- Port P I/O Pin 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 PP2 / KWP2 / PWM2 / SCK1 -- Port P I/O Pin 2 . . . . . . . . . . . . . . . . . . . . . . . . . . .63 PP1 / KWP1 / PWM1 / MOSI1 -- Port P I/O Pin 1. . . . . . . . . . . . . . . . . . . . . . . . . . .63 PP0 / KWP0 / PWM0 / MISO1 -- Port P I/O Pin 0. . . . . . . . . . . . . . . . . . . . . . . . . . .63 PS7 / SS0 -- Port S I/O Pin 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 PS6 / SCK0 -- Port S I/O Pin 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 PS5 / MOSI0 -- Port S I/O Pin 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 PS4 / MISO0 -- Port S I/O Pin 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 PS3 / TXD1 -- Port S I/O Pin 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 PS2 / RXD1 -- Port S I/O Pin 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 MC9S12DP512 Device Guide V01.25 2.3.56 PS1 / TXD0 -- Port S I/O Pin 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 2.3.57 PS0 / RXD0 -- Port S I/O Pin 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 2.3.58 PT[7:0] / IOC[7:0] -- Port T I/O Pins [7:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 2.4 Power Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 2.4.1 VDDX,VSSX -- Power & Ground Pins for I/O Drivers . . . . . . . . . . . . . . . . . . . . . . . .65 2.4.2 VDDR, VSSR -- Power & Ground Pins for I/O Drivers & Internal Voltage Regulator65 2.4.3 VDD1, VDD2, VSS1, VSS2 -- Internal Logic Power Supply Pins . . . . . . . . . . . . . . .65 2.4.4 VDDA, VSSA -- Power Supply Pins for ATD and VREG . . . . . . . . . . . . . . . . . . . . .65 2.4.5 VRH, VRL -- ATD Reference Voltage Input Pins . . . . . . . . . . . . . . . . . . . . . . . . . . .65 2.4.6 VDDPLL, VSSPLL -- Power Supply Pins for PLL . . . . . . . . . . . . . . . . . . . . . . . . . . .65 2.4.7 VREGEN -- On Chip Voltage Regulator Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . .66 Section 3 System Clock Description 3.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 Section 4 Modes of Operation 4.1 4.2 4.3 4.3.1 4.3.2 4.3.3 4.4 4.4.1 4.4.2 4.4.3 4.4.4 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69 Chip Configuration Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69 Security. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70 Securing the Microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70 Operation of the Secured Microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70 Unsecuring the Microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71 Stop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71 Pseudo Stop. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71 Wait . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71 Run. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72 Section 5 Resets and Interrupts 5.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73 5.2 Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73 5.2.1 Vector Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73 5.3 Effects of Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74 5.3.1 I/O pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74 5.3.2 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75 Section 6 HCS12 Core Block Description 7 MC9S12DP512 Device Guide V01.25 6.1 6.1.1 6.2 6.2.1 6.3 6.3.1 6.4 6.5 6.5.1 6.6 CPU12 Block Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77 Device-specific information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77 HCS12 Module Mapping Control (MMC) Block Description . . . . . . . . . . . . . . . . . . . . . .77 Device-specific information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77 HCS12 Multiplexed External Bus Interface (MEBI) Block Description . . . . . . . . . . . . . .77 Device-specific information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77 HCS12 Interrupt (INT) Block Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77 HCS12 Background Debug (BDM) Block Description . . . . . . . . . . . . . . . . . . . . . . . . . .78 Device-specific information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78 HCS12 Breakpoint (BKP) Block Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78 Section 7 Clock and Reset Generator (CRG) Block Description 7.1 Device-specific information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78 Section 8 Oscillator (OSC) Block Description 8.1 Device-specific information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78 Section 9 Enhanced Capture Timer (ECT) Block Description Section 10 Analog to Digital Converter (ATD) Block Description Section 11 Inter-IC Bus (IIC) Block Description Section 12 Serial Communications Interface (SCI) Block Description Section 13 Serial Peripheral Interface (SPI) Block Description Section 14 J1850 (BDLC) Block Description Section 15 Pulse Width Modulator (PWM) Block Description Section 16 Flash EEPROM 512K Block Description Section 17 EEPROM 4K Block Description Section 18 RAM Block Description Section 19 MSCAN Block Description MC9S12DP512 Device Guide V01.25 Section 20 Port Integration Module (PIM) Block Description Section 21 Voltage Regulator (VREG) Block Description Section 22 Printed Circuit Board Layout Proposal Appendix A Electrical Characteristics A.1 General. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85 A.1.1 Parameter Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85 A.1.2 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85 A.1.3 Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86 A.1.4 Current Injection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87 A.1.5 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87 A.1.6 ESD Protection and Latch-up Immunity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88 A.1.7 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89 A.1.8 Power Dissipation and Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .89 A.1.9 I/O Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91 A.1.10 Supply Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92 A.2 ATD Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95 A.2.1 ATD Operating Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95 A.2.2 Factors influencing accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95 A.2.3 ATD accuracy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97 A.3 NVM, Flash and EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99 A.3.1 NVM timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99 A.3.2 NVM Reliability. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101 A.4 Voltage Regulator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103 A.5 Reset, Oscillator and PLL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105 A.5.1 Startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105 A.5.2 Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106 A.5.3 Phase Locked Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107 A.6 MSCAN. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111 A.7 SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113 A.7.1 Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113 A.7.2 Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115 A.8 External Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117 A.8.1 General Muxed Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117 9 MC9S12DP512 Device Guide V01.25 Appendix B Package Information B.1 B.2 General. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .121 112-pin LQFP package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .122 MC9S12DP512 Device Guide V01.25 List of Figures Figure 0-1 Figure 1-1 Figure 1-2 Figure 2-1 Figure 2-2 Figure 2-3 Figure 2-4 Figure 2-5 Figure 3-1 Figure 22-1 Figure 22-2 Figure A-1 Figure A-2 Figure A-3 Figure A-4 Figure A-5 Figure A-6 Figure A-7 Figure A-8 Figure A-9 Figure A-10 Figure B-1 Order Part Number Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 MC9S12DP512 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 MC9S12DP512 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 Pin Assignments in 112-pin LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 PLL Loop Filter Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 Colpitts Oscillator Connections (PE7=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 Pierce Oscillator Connections (PE7=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 External Clock Connections (PE7=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 Clock Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 Recommended PCB Layout for 112LQFP Colpitts Oscillator . . . . . . . . . . . . . . .82 Recommended PCB Layout for 112LQFP Pierce Oscillator . . . . . . . . . . . . . . . .83 ATD Accuracy Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Typical Endurance vs Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 Basic PLL functional diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 Jitter Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 Maximum bus clock jitter approximation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 SPI Master Timing (CPHA=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 SPI Master Timing (CPHA=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 SPI Slave Timing (CPHA=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 SPI Slave Timing (CPHA=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 General External Bus Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 112-pin LQFP mechanical dimensions (case no. 987) . . . . . . . . . . . . . . . . . . 122 11 MC9S12DP512 Device Guide V01.25 MC9S12DP512 Device Guide V01.25 List of Tables Table 0-1 Derivative Differences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Table 0-2 Document References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 Table 1-1 Device Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 $0000 - $000F MEBI map 1 of 3 (HCS12 Multiplexed External Bus Interface) . . . . . . . . . .27 $0010 - $0014 MMC map 1 of 4 (HCS12 Module Mapping Control) . . . . . . . . . . . . . . . . . .27 $0015 - $0016 INT map 1 of 2 (HCS12 Interrupt) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 $0017 - $0019 Reserved . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 $001A - $001B Device ID Register (Table 1-3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 $001C - $001D MMC map 3 of 4 (HCS12 Module Mapping Control, Table 1-4) . . . . . . . . .28 $001E - $001E MEBI map 2 of 3 (HCS12 Multiplexed External Bus Interface) . . . . . . . . . .28 $001F - $001F INT map 2 of 2 (HCS12 Interrupt) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 $0020 - $0027 Reserved . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 $0028 - $002F BKP (HCS12 Breakpoint) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 $0030 - $0031 MMC map 4 of 4 (HCS12 Module Mapping Control) . . . . . . . . . . . . . . . . . .29 $0032 - $0033 MEBI map 3 of 3 (HCS12 Multiplexed External Bus Interface) . . . . . . . . . .29 $0034 - $003F CRG (Clock and Reset Generator) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 $0040 - $007F ECT (Enhanced Capture Timer 16 Bit 8 Channels) . . . . . . . . . . . . . . . . . .30 $0080 - $009F ATD0 (Analog to Digital Converter 10 Bit 8 Channel) . . . . . . . . . . . . . . . . .33 $00A0 - $00C7 PWM (Pulse Width Modulator 8 Bit 8 Channel). . . . . . . . . . . . . . . . . . . . . .34 $00C8 - $00CF SCI0 (Asynchronous Serial Interface) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 $00D0 - $00D7 SCI1 (Asynchronous Serial Interface) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 $00D8 - $00DF SPI0 (Serial Peripheral Interface) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 $00E0 - $00E7 IIC (Inter IC Bus) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 $00E8 - $00EF BDLC (Bytelevel Data Link Controller J1850) . . . . . . . . . . . . . . . . . . . . . . .37 $00F0 - $00F7 SPI1 (Serial Peripheral Interface) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 $00F8 - $00FF SPI2 (Serial Peripheral Interface) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 $0100 - $010F Flash Control Register (fts512k4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 $0110 - $011B EEPROM Control Register (eets4k) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 $011C - $011F Reserved for RAM Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 $0120 - $013F ATD1 (Analog to Digital Converter 10 Bit 8 Channel) . . . . . . . . . . . . . . . . .40 $0140 - $017F CAN0 (Freescale Scalable CAN - FSCAN) . . . . . . . . . . . . . . . . . . . . . . . . .41 Table 1-2 Detailed MSCAN Foreground Receive and Transmit Buffer Layout. . . . . . . . . . .42 $0180 - $01BF CAN1 (Freescale Scalable CAN - FSCAN) . . . . . . . . . . . . . . . . . . . . . . . . .43 13 MC9S12DP512 Device Guide V01.25 $01C0 - $01FF CAN2 (Freescale Scalable CAN - FSCAN) . . . . . . . . . . . . . . . . . . . . . . . . .44 $0200 - $023F CAN3 (Freescale Scalable CAN - FSCAN) . . . . . . . . . . . . . . . . . . . . . . . . .45 $0240 - $027F PIM (Port Integration Module PIM_9DP256) . . . . . . . . . . . . . . . . . . . . . . . .46 $0280 - $02BF CAN4 (Freescale Scalable CAN - FSCAN) . . . . . . . . . . . . . . . . . . . . . . . . .48 $02C0 - $03FF Reserved . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 Table 1-3 Assigned Part ID Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 Table 1-4 Memory size registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 Table 2-1 Signal Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 Table 2-2 MC9S12DP512 Power and Ground Connection Summary . . . . . . . . . . . . . . . . . .64 Table 4-1 Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69 Table 4-2 Clock Selection Based on PE7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70 Table 4-3 Voltage Regulator VREGEN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70 Table 5-1 Interrupt Vector Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73 Table 22-1 Suggested External Component Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81 Table A-1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87 Table A-2 ESD and Latch-up Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88 Table A-3 ESD and Latch-up Protection Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .88 Table A-4 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89 Table A-5 Thermal Package Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91 Table A-6 5V I/O Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92 Table A-7 Supply Current Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93 Table A-8 ATD Operating Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95 Table A-9 ATD Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96 Table A-10 ATD Conversion Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97 Table A-11 NVM Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100 Table A-12 NVM Reliability Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101 Table A-13 Voltage Regulator Recommended Load Capacitances . . . . . . . . . . . . . . . . . . . .103 Table A-14 Startup Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105 Table A-15 Oscillator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106 Table A-16 PLL Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110 Table A-17 MSCAN Wake-up Pulse Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111 Table A-18 Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113 Table A-19 SPI Master Mode Timing Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114 Table A-20 SPI Slave Mode Timing Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116 Table A-21 Expanded Bus Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119 MC9S12DP512 Device Guide V01.25 Derivative Differences and Document References Derivative Differences Table 0-1 shows the availability of peripheral modules on the various derivatives. For details about the compatibility within the MC9S12D-Family refer also to engineering bulletin EB386. Table 0-1 Derivative Differences1 Modules MC9S12DP512 MC9S12DT512 MC9S12DJ512 MC9S12A512 # of CANs 5 3 2 0 CAN0 -- CAN1 -- -- CAN2 -- -- -- CAN3 -- -- -- CAN4 -- J1850/BDLC -- -- Package 112 LQFP 112 LQFP 112 LQFP 112 LQFP Package Code PV PV PV PV Mask set L00M L00M L00M L00M Temp Options M, V, C M, V, C M, V, C C Notes An errata exists contact Sales Office An errata exists contact Sales Office An errata exists contact Sales Office An errata exists contact Sales Office NOTES: 1. : Available for this device, --: Not available for this device The following figure provides an ordering number example for the MC9S12D-Family devices. MC9S12 DP512 C PV Package Option Temperature Option Device Title Controller Family Temperature Options C = -40C to 85C V = -40C to 105C M = -40C to 125C Package Options FU = 80 QFP PV = 112 LQFP Figure 0-1 Order Part Number Example 15 MC9S12DP512 Device Guide V01.25 The following items should be considered when using a derivative (Table 0-1): * * * Registers - Do not write or read CAN0 registers (after reset: address range $0140 - $017F), if using a derivative without CAN0. - Do not write or read CAN1registers (after reset: address range $0180 - $01BF), if using a derivative without CAN1. - Do not write or read CAN2 registers (after reset: address range $01C0 - $01FF), if using a derivative without CAN2. - Do not write or read CAN3 registers (after reset: address range $0200 - $023F), if using a derivative without CAN3. - Do not write or read CAN4 registers (after reset: address range $0280 - $02BF), if using a derivative without CAN4. - Do not write or read BDLC registers (after reset: address range $00E8 - $00EF), if using a derivative without BDLC. Interrupts - Fill the four CAN0 interrupt vectors ($FFB0 - $FFB7) according to your coding policies for unused interrupts, if using a derivative without CAN0. - Fill the four CAN1 interrupt vectors ($FFA8 - $FFAF) according to your coding policies for unused interrupts, if using a derivative without CAN1. - Fill the four CAN2 interrupt vectors ($FFA0 - $FFA7) according to your coding policies for unused interrupts, if using a derivative without CAN2. - Fill the four CAN3 interrupt vectors ($FF98 - $FF9F) according to your coding policies for unused interrupts, if using a derivative without CAN3. - Fill the four CAN4 interrupt vectors ($FF90 - $FF97) according to your coding policies for unused interrupts, if using a derivative without CAN4. - Fill the BDLC interrupt vector ($FFC2, $FFC3) according to your coding policies for unused interrupts, if using a derivative without BDLC. Ports - The CAN0 pin functionality (TXCAN0, RXCAN0) is not available on port PJ7, PJ6, PM5, PM4, PM3, PM2, PM1 and PM0, if using a derivative without CAN0. - The CAN1 pin functionality (TXCAN1, RXCAN1) is not available on port PM3 and PM2, if using a derivative without CAN1. - The CAN2 pin functionality (TXCAN2, RXCAN2) is not available on port PM5 and PM4, if using a derivative without CAN2. - The CAN3 pin functionality (TXCAN3, RXCAN3) is not available on port PM7 and PM6, if using a derivative without CAN3. MC9S12DP512 Device Guide V01.25 - The CAN4 pin functionality (TXCAN4, RXCAN4) is not available on port PJ7, PJ6, PM7, PM6, PM5 and PM4, if using a derivative without CAN0. - The BDLC pin functionality (TXB, RXB) is not available on port PM1 and PM0, if using a derivative without BDLC. - Do not write MODRR1 and MODRR0 bits of Module Routing Register (PIM_9DP256 Block Guide), if using a derivative without CAN0. - Do not write MODRR3 and MODRR2 bits of Module Routing Register (PIM_9DP256 Block Guide), if using a derivative without CAN4. Document References The Device Guide provides information about the MC9S12DP512 device made up of standard HCS12 blocks and the HCS12 processor core. This document is part of the customer documentation. A complete set of device manuals also includes the individual Block Guides of the implemented modules. In an effort to reduce redundancy, all module specific information is located only in the respective Block Guide. If applicable, special implementation details of the module are given in the block description sections of this document. See Table 0-2 for names and versions of the referenced documents throughout the Device Guide. Table 0-2 Document References Block Guide Version Document Order Number HCS12 CPU Reference Manual V02 S12CPUV2/D HCS12 Module Mapping Control (MMC) Block Guide V04 S12MMCV4/D HCS12 Multiplexed External Bus Interface (MEBI) Block Guide V03 S12MEBIV3/D HCS12 Interrupt (INT) Block Guide V01 S12INTV1/D HCS12 Background Debug (BDM) Block Guide V04 S12BDMV4/D HCS12 Breakpoint (BKP) Block Guide V01 S12BKPV1/D Clock and Reset Generator (CRG) Block Guide V04 S12CRGV4/D Enhanced Capture Timer 16 Bit 8 Channel (ECT_16B8C) Block Guide V01 S12ECT16B8V1/D Analog to Digital Converter 10 Bit 8 Channel (ATD_10B8C) Block Guide V02 S12ATD10B8CV2/D Inter IC Bus (IIC) Block Guide V02 S12IICV2/D Asynchronous Serial Interface (SCI) Block Guide V02 S12SCIV2/D Serial Peripheral Interface (SPI) Block Guide V03 S12SPIV3/D Pulse Width Modulator 8 Bit 8 Channel (PWM_8B8C) Block Guide V01 S12PWM8B8CV1/D 512K Byte Flash (FTS512K4) Block Guide V01 S12FTS512K4V1/D 4K Byte EEPROM (EETS4K) Block Guide V02 S12EETS4KV2/D Byte Level Data Link Controller -J1850 (BDLC) Block Guide V01 S12BDLCV1/D Freescale Scalable CAN (MSCAN) Block Guide V02 S12MSCANV2/D Voltage Regulator (VREG) Block Guide V01 S12VREGV1/D Port Integration Module (PIM_9DP256) Block Guide1 V03 S12DP256PIMV3/D Oscillator (OSC) Block Guide V02 S12OSCV2/D 17 MC9S12DP512 Device Guide V01.25 NOTES: 1. Reused due to functional equivalence. MC9S12DP512 Device Guide V01.25 Section 1 Introduction 1.1 Overview The MC9S12DP512 microcontroller unit (MCU) is a 16-bit device composed of standard on-chip peripherals including a 16-bit central processing unit (HCS12 CPU), 512K bytes of Flash EEPROM, 14K bytes of RAM, 4K bytes of EEPROM, two asynchronous serial communications interfaces (SCI), three serial peripheral interfaces (SPI), an 8-channel IC/OC enhanced capture timer, two 8-channel, 10-bit analog-to-digital converters (ADC), an 8-channel pulse-width modulator (PWM), a digital Byte Data Link Controller (BDLC), 29 discrete digital I/O channels (Port A, Port B, Port K and Port E), 20 discrete digital I/O lines with interrupt and wake up capability, five CAN 2.0 A, B software compatible modules (MSCAN12), and an Inter-IC Bus. The MC9S12DP512 has full 16-bit data paths throughout. However, the external bus can operate in an 8-bit narrow mode so single 8-bit wide memory can be interfaced for lower cost systems. The inclusion of a PLL circuit allows power consumption and performance to be adjusted to suit operational requirements. 1.2 Features * HCS12 Core - 16-bit HCS12 CPU i. Upward compatible with M68HC11 instruction set ii. Interrupt stacking and programmer's model identical to M68HC11 iii. Instruction queue iv. Enhanced indexed addressing * * - MEBI (Multiplexed External Bus Interface) - MMC (Module Mapping Control) - INT (Interrupt control) - BKP (Breakpoints) - BDM (Background Debug Mode) CRG (Clock and Reset Generation) - Low current Colpitts oscillator or - Pierce oscillator - PLL - COP watchdog - Real Time Interrupt - Clock Monitor 8-bit and 4-bit ports with interrupt functionality 19 MC9S12DP512 Device Guide V01.25 * * * * * * * - Digital filtering - Programmable rising or falling edge trigger Memory - 512K Flash EEPROM - 4K byte EEPROM - 14K byte RAM Two 8-channel Analog-to-Digital Converters - 10-bit resolution - External conversion trigger capability Five 1M bit per second, CAN 2.0 A, B software compatible modules - Five receive and three transmit buffers - Flexible identifier filter programmable as 2 x 32 bit, 4 x 16 bit or 8 x 8 bit - Four separate interrupt channels for Rx, Tx, error and wake-up - Low-pass filter wake-up function - Loop-back for self test operation Enhanced Capture Timer - 16-bit main counter with 7-bit prescaler - 8 programmable input capture or output compare channels - Four 8-bit or two 16-bit pulse accumulators 8 PWM channels - Programmable period and duty cycle - 8-bit 8-channel or 16-bit 4-channel - Separate control for each pulse width and duty cycle - Center-aligned or left-aligned outputs - Programmable clock select logic with a wide range of frequencies - Fast emergency shutdown input - Usable as interrupt inputs Serial interfaces - Two asynchronous Serial Communications Interfaces (SCI) - Three Synchronous Serial Peripheral Interface (SPI) Byte Data Link Controller (BDLC) - SAE J1850 Class B Data Communications Network Interface Compatible and ISO Compatible for Low-Speed (<125 Kbps) Serial Data Communications in Automotive Applications MC9S12DP512 Device Guide V01.25 * * Inter-IC Bus (IIC) - Compatible with I2C Bus standard - Multi-master operation - Software programmable for one of 256 different serial clock frequencies 112-Pin LQFP package - I/O lines with 5V input and drive capability - 5V A/D converter inputs - Operation at 50MHz equivalent to 25MHz Bus Speed over -40C <= TA <= 125C - Development support - Single-wire background debugTM mode (BDM) - On-chip hardware breakpoints 1.3 Modes of Operation User modes * * Normal and Emulation Operating Modes - Normal Single-Chip Mode - Normal Expanded Wide Mode - Normal Expanded Narrow Mode - Emulation Expanded Wide Mode - Emulation Expanded Narrow Mode Special Operating Modes - Special Single-Chip Mode with active Background Debug Mode - Special Test Mode (Freescale use only) - Special Peripheral Mode (Freescale use only) Low power modes * Stop Mode * Pseudo Stop Mode * Wait Mode 21 MC9S12DP512 Device Guide V01.25 1.4 Block Diagram Figure 1-1 shows a block diagram of the MC9S12DP512 device. MC9S12DP512 Device Guide V01.25 SPI0 DDRA DDRB PTA PTB BDLC (J1850) Multiplexed Narrow Bus Internal Logic 2.5V VDD1,2 VSS1,2 PLL 2.5V VDDPLL VSSPLL PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 ADDR7 ADDR6 ADDR5 ADDR4 ADDR3 ADDR2 ADDR1 ADDR0 CAN1 CAN2 DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0 CAN3 DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0 Multiplexed Wide Bus DATA15 ADDR15 PA7 DATA14 ADDR14 PA6 DATA13 ADDR13 PA5 DATA12 ADDR12 PA4 DATA11 ADDR11 PA3 DATA10 ADDR10 PA2 DATA9 ADDR9 PA1 DATA8 ADDR8 PA0 CAN0 CAN4 IIC I/O Driver 5V VDDX VSSX A/D Converter 5V & Voltage Regulator Reference PWM VDDA VSSA Voltage Regulator 5V & I/O VDDR VSSR SPI1 SPI2 RXB TXB RXCAN TXCAN RXCAN TXCAN RXCAN TXCAN RXCAN TXCAN RXCAN TXCAN SDA SCL KWJ0 KWJ1 KWJ6 KWJ7 PWM0 PWM1 PWM2 PWM3 PWM4 PWM5 PWM6 PWM7 KWP0 KWP1 KWP2 KWP3 KWP4 KWP5 KWP6 KWP7 MISO MOSI SCK SS MISO MOSI SCK SS KWH0 KWH1 KWH2 KWH3 KWH4 KWH5 KWH6 KWH7 AD1 PTT MISO MOSI SCK SS Multiplexed Address/Data Bus PTS SCI1 PS0 PS1 PS2 PS3 PS4 PS5 PS6 PS7 PTM RXD TXD RXD TXD SCI0 TEST PT0 PT1 PT2 PT3 PT4 PT5 PT6 PT7 PM0 PM1 PM2 PM3 PM4 PM5 PM6 PM7 PTJ Enhanced Capture Timer IOC0 IOC1 IOC2 IOC3 IOC4 IOC5 IOC6 IOC7 PJ0 PJ1 PJ6 PJ7 PTP XIRQ IRQ System R/W Integration LSTRB Module ECLK (SIM) MODA MODB NOACC/XCLKS DDRK Periodic Interrupt COP Watchdog Clock Monitor Breakpoints PK0 PK1 PK2 PK3 PK4 PK5 PK7 PP0 PP1 PP2 PP3 PP4 PP5 PP6 PP7 XADDR14 XADDR15 XADDR16 XADDR17 XADDR18 XADDR19 ECS PH0 PH1 PH2 PTH PTE PE0 PE1 PE2 PE3 PE4 PE5 PE6 PE7 Clock and Reset Generation Module PIX0 PIX1 PIX2 PIX3 PIX4 PIX5 ECS DDRT PLL PPAGE DDRS XFC VDDPLL VSSPLL EXTAL XTAL RESET CPU12 PAD08 PAD09 PAD10 PAD11 PAD12 PAD13 PAD14 PAD15 AN08 AN09 AN10 AN11 AN12 AN13 AN14 AN15 DDRM Single-wire Background Debug Module DDRE BKGD Voltage Regulator PAD00 PAD01 PAD02 PAD03 PAD04 PAD05 PAD06 PAD07 VRH VRL VDDA VSSA DDRJ VDDR VSSR VREGEN VDD1,2 VSS1,2 AN00 AN01 AN02 AN03 AN04 AN05 AN06 AN07 VRH VRL VDDA VSSA DDRP 4K Byte EEPROM ATD1 DDRH 14K Byte RAM VRH VRL VDDA VSSA Module to Port Routing ATD0 AD0 512K Byte Flash EEPROM PTK Figure 1-1 MC9S12DP512 Block Diagram PH3 PH4 PH5 PH6 PH7 23 MC9S12DP512 Device Guide V01.25 1.5 Device Memory Map Table 1-1 and Figure 1-2 show the device memory map of the MC9S12DP512 after reset. Note that after reset the bottom 1k of the EEPROM ($0000 - $03FF) are hidden by the register space Table 1-1 Device Memory Map Address Module $0000 - $000F HCS12 Multiplexed External Bus Interface $0010 - $0014 HCS12 Module Mapping Control Size (Bytes) 16 5 $0015 - $0016 HCS12 Interrupt 2 $0017 - $0019 Reserved 3 $001A - $001B Device ID register (PARTID) 2 $001C - $001D HCS12 Module Mapping Control 2 $001E HCS12 Multiplexed External Bus Interface 1 $001F HCS12 Interrupt 1 $0020 - $0027 Reserved 8 $0028 - $002F HCS12 Breakpoint 8 $0030 - $0031 HCS12 Module Mapping Control 2 $0032 - $0033 HCS12 Multiplexed External Bus Interface 2 $0034 - $003F Clock and Reset Generator (PLL, RTI, COP) 12 $0040 - $007F Enhanced Capture Timer 16-bit 8 channels 64 $0080 - $009F Analog to Digital Converter 10-bit 8 channels (ATD0) $00A0 - $00C7 Pulse Width Modulator 8-bit 8 channels (PWM) 32 40 $00C8 - $00CF Serial Communications Interface 0 (SCI0) 8 $00D0 - $00D7 Serial Communications Interface 0 (SCI1) 8 $00D8 - $00DF Serial Peripheral Interface (SPI0) 8 $00E0 - $00E7 Inter IC Bus 8 $00E8 - $00EF Byte Data Link Controller (BDLC) 8 $00F0 - $00F7 Serial Peripheral Interface (SPI1) 8 $00F8 - $00FF Serial Peripheral Interface (SPI2) $0100- $010F Flash Control Register 16 $0110 - $011B EEPROM Control Register 12 $011C - $011F Reserved 8 4 $0120 - $013F Analog to Digital Converter 10-bit 8 channels (ATD1) 32 $0140 - $017F Freescale Scalable Can (CAN 64 $0180 - $01BF Freescale Scalable Ca $01C0 - $01FF Freescale Scalable Can (CAN 64 64 $0200 - $023F Freescale Scalable Can (CAN3) 64 $0240 - $027F Port Integration Module (PIM) 64 $0280 - $02BF Freescale Scalable Can (CAN4) $02C0 - $03FF Reserved 64 320 $0000 - $0FFF EEPROM array $0800 - $3FFF RAM array 14336 4096 $4000 - $7FFF Fixed Flash EEPROM array incl. 1K, 2K, 4K or 8K Protected Sector at start 16384 MC9S12DP512 Device Guide V01.25 Table 1-1 Device Memory Map Module Size (Bytes) $8000 - $BFFF Flash EEPROM Page Window 16384 Fixed Flash EEPROM array $C000 - $FFFF incl. 2K, 4K, 8K or 16K Protected Sector at end and 256 bytes of Vector Space at $FF80 - $FFFF 16384 Address 25 MC9S12DP512 Device Guide V01.25 Figure 1-2 MC9S12DP512 Memory Map $0000 $0000 $0400 REGISTERS (Mappable to any 2k Block within the first 32K) $03FF $0800 $0000 4K Bytes EEPROM (Mappable to any 4K Block) $0FFF $0800 $4000 $3FFF $4000 14K Bytes RAM (Mappable to any 16K and alignable to top or bottom) 16K Fixed Flash Page $3E = 62 (This is dependant on the state of the ROMHM bit) $7FFF $8000 $8000 16K Page Window 32 x 16K Flash EEPROM pages EXTERN $BFFF $C000 $C000 16K Fixed Flash Page $3F = 63 $FFFF $FF00 BDM (if active) $FF00 VECTORS VECTORS VECTORS EXPANDED* NORMAL SINGLE CHIP SPECIAL SINGLE CHIP $FFFF $FFFF * Assuming that a `0' was driven onto port K bit 7 during MCU is reset into normal expanded wide or narrow mode. MC9S12DP512 Device Guide V01.25 1.5.1 Detailed Register Map $0000 - $000F Address Name $0000 PORTA $0001 PORTB $0002 DDRA $0003 DDRB $0004 $0007 Reserved $0008 PORTE $0009 DDRE $000A PEAR $000B MODE $000C PUCR $000D RDRIV $000E EBICTL $000F Reserved $0010 - $0014 Address Name $0010 INITRM $0011 INITRG $0012 INITEE $0013 MISC $0014 Reserved MEBI map 1 of 3 (HCS12 Multiplexed External Bus Interface) Bit 7 Read: Bit 7 Write: Read: Bit 7 Write: Read: Bit 7 Write: Read: Bit 7 Write: Read: 0 Write: Read: Bit 7 Write: Read: Bit 7 Write: Read: NOACCE Write: Read: MODC Write: Read: PUPKE Write: Read: RDPK Write: Read: 0 Write: Read: 0 Write: Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 6 5 4 3 2 1 Bit 0 6 5 4 3 2 1 Bit 0 6 5 4 3 2 1 Bit 0 6 5 4 3 2 1 Bit 0 0 0 0 0 0 0 0 6 5 4 3 2 Bit 1 Bit 0 6 5 4 3 Bit 2 0 0 PIPOE NECLK LSTRE RDWE 0 0 EMK EME PUPBE PUPAE RDPB RDPA 0 MODB MODA 0 0 0 0 0 0 0 0 0 IVIS 0 0 0 0 0 0 0 0 0 0 0 0 0 PUPEE RDPE ESTR 0 MMC map 1 of 4 (HCS12 Module Mapping Control) Bit 7 Read: RAM15 Write: Read: 0 Write: Read: EE15 Write: Read: 0 Write: Read: 0 Write: Bit 6 Bit 5 Bit 4 Bit 3 RAM14 RAM13 RAM12 RAM11 REG14 REG13 REG12 REG11 EE14 EE13 EE12 EE11 0 0 0 0 0 0 Bit 2 0 Bit 1 0 0 0 0 0 Bit 0 RAMHAL 0 EEON EXSTR1 EXSTR0 ROMHM ROMON 0 0 0 0 27 MC9S12DP512 Device Guide V01.25 $0015 - $0016 Address INT map 1 of 2 (HCS12 Interrupt) Name $0015 ITCR $0016 ITEST Read: Write: Read: Write: $0017 - $0019 Address $0017$0019 Read: Write: $001A - $001B Address PARTIDH $001B PARTIDL Read: Write: Read: Write: $001C - $001D Address Name $001C MEMSIZ0 $001D MEMSIZ1 $001E $001F Read: Write: Read: Write: $0020 - $0027 Address $0020 $0027 Bit 0 WRINT ADR3 ADR2 ADR1 ADR0 INTE INTC INTA INT8 INT6 INT4 INT2 INT0 Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 0 Bit 0 0 Bit 7 ID15 Bit 6 ID14 Bit 5 ID13 Bit 4 ID12 Bit 3 ID11 Bit 2 ID10 Bit 1 ID9 Bit 0 ID8 ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0 Bit 3 0 0 Bit 2 Bit 1 Bit 0 ram_sw2 ram_sw1 ram_sw0 0 pag_sw1 pag_sw0 Bit 7 Bit 6 IRQE IRQEN Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 0 Bit 0 0 Bit 0 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 PSEL7 PSEL6 PSEL5 PSEL4 PSEL3 PSEL2 PSEL1 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 0 Reserved Name Reserved Bit 1 INT map 2 of 2 (HCS12 Interrupt) Name HPRIO Bit 2 MEBI map 2 of 3 (HCS12 Multiplexed External Bus Interface) $001F - $001F Address Bit 3 Bit 7 Bit 6 Bit 5 Bit 4 Read: reg_sw0 0 eep_sw1 eep_sw0 Write: Read: rom_sw1 rom_sw0 0 0 Write: Name INTCR Bit 4 MMC map 3 of 4 (HCS12 Module Mapping Control, Table 1-4) $001E - $001E Address Bit 5 0 Device ID Register (Table 1-3) Name $001A Bit 6 0 Reserved Name Reserved Bit 7 0 Read: Write: Bit 7 0 Bit 6 0 Bit 0 0 MC9S12DP512 Device Guide V01.25 $0028 - $002F Address Name $0028 BKPCT0 $0029 BKPCT1 $002A BKP0X $002B BKP0H $002C BKP0L $002D BKP1X $002E BKP1H $002F BKP1L BKP (HCS12 Breakpoint) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Read: 0 0 0 0 BKEN BKFULL BKBDM BKTAG Write: Read: BK0MBH BK0MBL BK1MBH BK1MBL BK0RWE BK0RW BK1RWE BK1RW Write: Read: 0 0 BK0V5 BK0V4 BK0V3 BK0V2 BK0V1 BK0V0 Write: Read: Bit 15 14 13 12 11 10 9 Bit 8 Write: Read: Bit 7 6 5 4 3 2 1 Bit 0 Write: Read: 0 0 BK1V5 BK1V4 BK1V3 BK1V2 BK1V1 BK1V0 Write: Read: Bit 15 14 13 12 11 10 9 Bit 8 Write: Read: Bit 7 6 5 4 3 2 1 Bit 0 Write: $0030 - $0031 Address MMC map 4 of 4 (HCS12 Module Mapping Control) Name $0030 PPAGE $0031 Reserved Read: Write: Read: Write: $0032 - $0033 Address PORTK $0033 DDRK Read: Write: Read: Write: $0034 - $003F Address SYNR $0035 REFDV $0036 CTFLG Test Only $0037 CRGFLG $0038 CRGINT 0 0 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PIX5 PIX4 PIX3 PIX2 PIX1 PIX0 0 0 0 0 0 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 6 5 4 3 2 1 Bit 0 Bit 7 6 5 4 3 2 1 Bit 0 CRG (Clock and Reset Generator) Name $0034 Bit 6 0 MEBI map 3 of 3 (HCS12 Multiplexed External Bus Interface) Name $0032 Bit 7 0 Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Bit 7 0 Bit 6 0 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SYN5 SYN4 SYN3 SYN2 SYN1 SYN0 0 0 0 0 TOUT7 TOUT6 TOUT5 TOUT4 RTIF PROF RTIE 0 0 0 LOCKIF LOCKIE REFDV3 REFDV2 REFDV1 REFDV0 TOUT3 TOUT2 LOCK TRACK 0 0 TOUT1 SCMIF SCMIE TOUT0 SCM 0 29 MC9S12DP512 Device Guide V01.25 $0034 - $003F Address Name $0039 CLKSEL $003A PLLCTL $003B RTICTL $003C COPCTL $003D $003E $003F FORBYP Test Only CTCTL Test Only ARMCOP CRG (Clock and Reset Generator) Bit 7 Bit 6 Bit 5 Bit 4 Read: PLLSEL PSTP SYSWAI ROAWAI Write: Read: CME PLLON AUTO ACQ Write: Read: 0 RTR6 RTR5 RTR4 Write: Read: 0 0 WCOP RSBCK Write: Read: 0 RTIBYP COPBYP PLLBYP Write: Read: TCTL7 TCTL6 TCTL5 TCTL4 Write: Read: 0 0 0 0 Write: Bit 7 6 5 4 $0040 - $007F Address TIOS $0041 CFORC $0042 OC7M $0043 OC7D $0044 TCNT (hi) $0045 TCNT (lo) $0046 TSCR1 $0047 TTOV $0048 TCTL1 $0049 TCTL2 $004A TCTL3 $004B TCTL4 $004C TIE $004D TSCR2 $004E TFLG1 Bit 2 Bit 1 Bit 0 PLLWAI CWAI RTIWAI COPWAI PRE PCE SCME RTR2 RTR1 RTR0 CR2 CR1 CR0 0 RTR3 0 0 0 TCLT3 TCTL2 TCTL1 TCTL0 0 3 0 2 0 1 0 Bit 0 FCM 0 ECT (Enhanced Capture Timer 16 Bit 8 Channels) Name $0040 Bit 3 Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 IOS7 IOS6 IOS5 IOS4 IOS3 IOS2 IOS1 IOS0 0 FOC7 0 FOC6 0 FOC5 0 FOC4 0 FOC3 0 FOC2 0 FOC1 0 FOC0 OC7M7 OC7M6 OC7M5 OC7M4 OC7M3 OC7M2 OC7M1 OC7M0 OC7D7 OC7D6 OC7D5 OC7D4 OC7D3 OC7D2 OC7D1 OC7D0 Bit 15 14 13 12 11 10 9 Bit 8 Bit 7 6 5 4 3 2 1 Bit 0 TEN TSWAI TSFRZ TFFCA 0 0 0 0 TOV7 TOV6 TOV5 TOV4 TOV3 TOV2 TOV1 TOV0 OM7 OL7 OM6 OL6 OM5 OL5 OM4 OL4 OM3 OL3 OM2 OL2 OM1 OL1 OM0 OL0 EDG7B EDG7A EDG6B EDG6A EDG5B EDG5A EDG4B EDG4A EDG3B EDG3A EDG2B EDG2A EDG1B EDG1A EDG0B EDG0A C7I C6I C5I C4I C3I C2I C1I C0I 0 0 0 TCRE PR2 PR1 PR0 C6F C5F C4F C3F C2F C1F C0F TOI C7F MC9S12DP512 Device Guide V01.25 $0040 - $007F Address ECT (Enhanced Capture Timer 16 Bit 8 Channels) Name $004F TFLG2 $0050 TC0 (hi) $0051 TC0 (lo) $0052 TC1 (hi) $0053 TC1 (lo) $0054 TC2 (hi) $0055 TC2 (lo) $0056 TC3 (hi) $0057 TC3 (lo) $0058 TC4 (hi) $0059 TC4 (lo) $005A TC5 (hi) $005B TC5 (lo) $005C TC6 (hi) $005D TC6 (lo) $005E TC7 (hi) $005F TC7 (lo) $0060 PACTL $0061 PAFLG $0062 PACN3 (hi) $0063 PACN2 (lo) $0064 PACN1 (hi) $0065 PACN0 (lo) $0066 MCCTL $0067 MCFLG Bit 7 Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 0 Bit 0 0 Bit 15 14 13 12 11 10 9 Bit 8 Bit 7 6 5 4 3 2 1 Bit 0 Bit 15 14 13 12 11 10 9 Bit 8 Bit 7 6 5 4 3 2 1 Bit 0 Bit 15 14 13 12 11 10 9 Bit 8 Bit 7 6 5 4 3 2 1 Bit 0 Bit 15 14 13 12 11 10 9 Bit 8 Bit 7 6 5 4 3 2 1 Bit 0 Bit 15 14 13 12 11 10 9 Bit 8 Bit 7 6 5 4 3 2 1 Bit 0 Bit 15 14 13 12 11 10 9 Bit 8 Bit 7 6 5 4 3 2 1 Bit 0 Bit 15 14 13 12 11 10 9 Bit 8 Bit 7 6 5 4 3 2 1 Bit 0 Bit 15 14 13 12 11 10 9 Bit 8 Bit 7 6 5 4 3 2 1 Bit 0 PAEN PAMOD PEDGE CLK1 CLK0 PAOVI PAI 0 0 0 0 0 0 PAOVF PAIF Bit 7 6 5 4 3 2 1 Bit 0 Bit 7 6 5 4 3 2 1 Bit 0 Bit 7 6 5 4 3 2 1 Bit 0 Bit 7 6 5 4 3 2 1 Bit 0 MCZI MODMC RDMCL MCPR1 MCPR0 0 0 FLMC POLF3 MCEN 0 0 ICLAT 0 POLF2 POLF1 POLF0 TOF 0 MCZF 31 MC9S12DP512 Device Guide V01.25 $0040 - $007F Address Name $0068 ICPAR $0069 DLYCT $006A ICOVW $006B ICSYS $006C Reserved $006D TIMTST Test Only $006E $006F Reserved $0070 PBCTL $0071 PBFLG $0072 PA3H $0073 PA2H $0074 PA1H $0075 PA0H $0076 MCCNT (hi) $0077 MCCNT (lo) $0078 TC0H (hi) $0079 TC0H (lo) $007A TC1H (hi) $007B TC1H (lo) $007C TC2H (hi) $007D TC2H (lo) $007E TC3H (hi) $007F TC3H (lo) ECT (Enhanced Capture Timer 16 Bit 8 Channels) Bit 7 Read: 0 Write: Read: 0 Write: Read: NOVW7 Write: Read: SH37 Write: Read: Write: Read: 0 Write: Read: Write: Read: 0 Write: Read: 0 Write: Read: Bit 7 Write: Read: Bit 7 Write: Read: Bit 7 Write: Read: Bit 7 Write: Read: Bit 15 Write: Read: Bit 7 Write: Read: Bit 15 Write: Read: Bit 7 Write: Read: Bit 15 Write: Read: Bit 7 Write: Read: Bit 15 Write: Read: Bit 7 Write: Read: Bit 15 Write: Read: Bit 7 Write: Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 Bit 2 Bit 1 Bit 0 PA3EN PA2EN PA1EN PA0EN 0 0 0 0 0 DLY1 DLY0 NOVW6 NOVW5 NOVW4 NOVW3 NOVW2 NOVW1 NOVW0 SH26 SH15 SH04 TFMOD PACMX BUFEN LATQ 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6 5 4 3 2 1 Bit 0 6 5 4 3 2 1 Bit 0 6 5 4 3 2 1 Bit 0 6 5 4 3 2 1 Bit 0 14 13 12 11 10 9 Bit 8 6 5 4 3 2 1 Bit 0 14 13 12 11 10 9 Bit 8 6 5 4 3 2 1 Bit 0 14 13 12 11 10 9 Bit 8 6 5 4 3 2 1 Bit 0 14 13 12 11 10 9 Bit 8 6 5 4 3 2 1 Bit 0 14 13 12 11 10 9 Bit 8 6 5 4 3 2 1 Bit 0 PBEN TCBYP PBOVI PBOVF 0 0 0 MC9S12DP512 Device Guide V01.25 $0080 - $009F Address Name $0080 ATD0CTL0 $0081 ATD0CTL1 $0082 ATD0CTL2 $0083 ATD0CTL3 $0084 ATD0CTL4 $0085 ATD0CTL5 $0086 ATD0STAT0 $0087 Reserved $0088 ATD0TEST0 $0089 ATD0TEST1 $008A Reserved $008B ATD0STAT1 $008C Reserved $008D ATD0DIEN $008E Reserved $008F PORTAD0 $0090 ATD0DR0H $0091 ATD0DR0L $0092 ATD0DR1H $0093 ATD0DR1L $0094 ATD0DR2H $0095 ATD0DR2L $0096 ATD0DR3H $0097 ATD0DR3L $0098 ATD0DR4H ATD0 (Analog to Digital Converter 10 Bit 8 Channel) Bit 7 Read: 0 Write: Read: 0 Write: Read: ADPU Write: Read: 0 Write: Read: SRES8 Write: Read: DJM Write: Read: SCF Write: Read: 0 Write: Read: 0 Write: Read: 0 Write: Read: 0 Write: Read: CCF7 Write: Read: 0 Write: Read: Bit 7 Write: Read: 0 Write: Read: Bit 7 Write: Read: Bit 15 Write: Read: Bit 7 Write: Read: Bit 15 Write: Read: Bit 7 Write: Read: Bit 15 Write: Read: Bit 7 Write: Read: Bit 15 Write: Read: Bit 7 Write: Read: Bit 15 Write: Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 0 Bit 0 0 0 0 0 0 0 0 0 AFFC AWAI ETRIG ASCIE S8C S4C S2C S1C FIFO FRZ1 FRZ0 SMP1 SMP0 PRS4 PRS3 PRS2 PRS1 PRS0 DSGN SCAN MULT CC CB CA ETORF FIFOR 0 CC2 CC1 CC0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CCF6 CCF5 CCF4 CCF3 CCF2 CCF1 CCF0 0 0 0 0 0 0 0 6 5 4 3 2 1 Bit 0 0 0 0 0 0 0 0 6 5 4 3 2 1 Bit 0 14 13 12 11 10 9 Bit 8 6 5 4 3 2 1 Bit 0 14 13 12 11 10 9 Bit 8 6 5 4 3 2 1 Bit 0 14 13 12 11 10 9 Bit 8 6 5 4 3 2 1 Bit 0 14 13 12 11 10 9 Bit 8 6 5 4 3 2 1 Bit 0 14 13 12 11 10 9 Bit 8 0 ETRIGLE ETRIGP 0 ASCIF SC 33 MC9S12DP512 Device Guide V01.25 $0080 - $009F Address Name $0099 ATD0DR4L $009A ATD0DR5H $009B ATD0DR5L $009C ATD0DR6H $009D ATD0DR6L $009E ATD0DR7H $009F ATD0DR7L $00A0 - $00C7 Address $00A0 $00A1 $00A2 $00A3 $00A4 $00A5 $00A6 $00A7 $00A8 $00A9 $00AA $00AB $00AC $00AD $00AE ATD0 (Analog to Digital Converter 10 Bit 8 Channel) Name Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Bit 7 Bit 7 Bit 6 6 Bit 5 5 Bit 4 4 Bit 3 3 Bit 2 2 Bit 1 1 Bit 0 Bit 0 Bit 15 14 13 12 11 10 9 Bit 8 Bit 7 6 5 4 3 2 1 Bit 0 Bit 15 14 13 12 11 10 9 Bit 8 Bit 7 6 5 4 3 2 1 Bit 0 Bit 15 14 13 12 11 10 9 Bit 8 Bit 7 6 5 4 3 2 1 Bit 0 PWM (Pulse Width Modulator 8 Bit 8 Channel) Bit 7 Read: PWME PWME7 Write: Read: PWMPOL PPOL7 Write: Read: PWMCLK PCLK7 Write: Read: 0 PWMPRCLK Write: Read: PWMCAE CAE7 Write: Read: PWMCTL CON67 Write: Read: 0 PWMTST Test Only Write: Read: 0 PWMPRSC Write: Read: PWMSCLA Bit 7 Write: Read: PWMSCLB Bit 7 Write: Read: 0 PWMSCNTA Write: Read: 0 PWMSCNTB Write: Read: Bit 7 PWMCNT0 Write: 0 Read: Bit 7 PWMCNT1 Write: 0 Read: Bit 7 PWMCNT2 Write: 0 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PWME6 PWME5 PWME4 PWME3 PWME2 PWME1 PWME0 PPOL6 PPOL5 PPOL4 PPOL3 PPOL2 PPOL1 PPOL0 PCLK6 PCLK5 PCLK4 PCLK3 PCLK2 PCLK1 PCLK0 PCKB2 PCKB1 PCKB0 PCKA2 PCKA1 PCKA0 CAE6 CAE5 CAE4 CAE3 CAE2 CAE1 CAE0 CON45 CON23 CON01 PSWAI PFRZ 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6 5 4 3 2 1 Bit 0 6 5 4 3 2 1 Bit 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6 0 6 0 6 0 5 0 5 0 5 0 4 0 4 0 4 0 3 0 3 0 3 0 2 0 2 0 2 0 1 0 1 0 1 0 Bit 0 0 Bit 0 0 Bit 0 0 0 MC9S12DP512 Device Guide V01.25 $00A0 - $00C7 Address Name $00AF PWMCNT3 $00B0 PWMCNT4 $00B1 PWMCNT5 $00B2 PWMCNT6 $00B3 PWMCNT7 $00B4 PWMPER0 $00B5 PWMPER1 $00B6 PWMPER2 $00B7 PWMPER3 $00B8 PWMPER4 $00B9 PWMPER5 $00BA PWMPER6 $00BB PWMPER7 $00BC PWMDTY0 $00BD PWMDTY1 $00BE PWMDTY2 $00BF PWMDTY3 $00C0 PWMDTY4 $00C1 PWMDTY5 $00C2 PWMDTY6 $00C3 PWMDTY7 $00C4 PWMSDN $00C5 $00C7 Reserved PWM (Pulse Width Modulator 8 Bit 8 Channel) Bit 7 Read: Bit 7 Write: 0 Read: Bit 7 Write: 0 Read: Bit 7 Write: 0 Read: Bit 7 Write: 0 Read: Bit 7 Write: 0 Read: Bit 7 Write: Read: Bit 7 Write: Read: Bit 7 Write: Read: Bit 7 Write: Read: Bit 7 Write: Read: Bit 7 Write: Read: Bit 7 Write: Read: Bit 7 Write: Read: Bit 7 Write: Read: Bit 7 Write: Read: Bit 7 Write: Read: Bit 7 Write: Read: Bit 7 Write: Read: Bit 7 Write: Read: Bit 7 Write: Read: Bit 7 Write: Read: PWMIF Write: Read: 0 Write: Bit 6 6 0 6 0 6 0 6 0 6 0 Bit 5 5 0 5 0 5 0 5 0 5 0 Bit 4 4 0 4 0 4 0 4 0 4 0 Bit 3 3 0 3 0 3 0 3 0 3 0 Bit 2 2 0 2 0 2 0 2 0 2 0 Bit 1 1 0 1 0 1 0 1 0 1 0 Bit 0 Bit 0 0 Bit 0 0 Bit 0 0 Bit 0 0 Bit 0 0 6 5 4 3 2 1 Bit 0 6 5 4 3 2 1 Bit 0 6 5 4 3 2 1 Bit 0 6 5 4 3 2 1 Bit 0 6 5 4 3 2 1 Bit 0 6 5 4 3 2 1 Bit 0 6 5 4 3 2 1 Bit 0 6 5 4 3 2 1 Bit 0 6 5 4 3 2 1 Bit 0 6 5 4 3 2 1 Bit 0 6 5 4 3 2 1 Bit 0 6 5 4 3 2 1 Bit 0 6 5 4 3 2 1 Bit 0 6 5 4 3 2 1 Bit 0 6 5 4 3 2 1 Bit 0 6 5 4 3 2 1 Bit 0 PWM7 INL 0 PWM7 ENA 0 PWMIE 0 PWM RSTRT 0 PWMLVL 0 0 0 PWM7IN 0 35 MC9S12DP512 Device Guide V01.25 $00C8 - $00CF Address Name $00C8 SCI0BDH $00C9 SCI0BDL $00CA SC0CR1 $00CB SCI0CR2 $00CC SCI0SR1 $00CD SC0SR2 $00CE SCI0DRH $00CF SCI0DRL SCI0 (Asynchronous Serial Interface) Bit 7 Bit 6 Read: 0 0 Write: Read: SBR7 SBR6 Write: Read: LOOPS SCISWAI Write: Read: TIE TCIE Write: Read: TDRE TC Write: Read: 0 0 Write: Read: R8 T8 Write: Read: R7 R6 Write: T7 T6 $00D0 - $00D7 Address Name $00D0 SCI1BDH $00D1 SCI1BDL $00D2 SC1CR1 $00D3 SCI1CR2 $00D4 SCI1SR1 $00D5 SC1SR2 $00D6 SCI1DRH $00D7 SCI1DRL Bit 7 Bit 6 Read: 0 0 Write: Read: SBR7 SBR6 Write: Read: LOOPS SCISWAI Write: Read: TIE TCIE Write: Read: TDRE TC Write: Read: 0 0 Write: Read: R8 T8 Write: Read: R7 R6 Write: T7 T6 SPI0CR1 $00D9 SPI0CR2 $00DA SPI0BR $00DB SPI0SR Bit 3 Bit 2 Bit 1 Bit 0 SBR12 SBR11 SBR10 SBR9 SBR8 SBR5 SBR4 SBR3 SBR2 SBR1 SBR0 RSRC M WAKE ILT PE PT RIE ILIE TE RE RWU SBK RDRF IDLE OR NF FE PF 0 0 0 BRK13 TXDIR 0 0 0 0 0 0 R5 T5 R4 T4 R3 T3 R2 T2 R1 T1 R0 T0 RAF Bit 5 0 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SBR12 SBR11 SBR10 SBR9 SBR8 SBR5 SBR4 SBR3 SBR2 SBR1 SBR0 RSRC M WAKE ILT PE PT RIE ILIE TE RE RWU SBK RDRF IDLE OR NF FE PF 0 0 0 BRK13 TXDIR 0 0 0 0 0 0 R5 T5 R4 T4 R3 T3 R2 T2 R1 T1 R0 T0 RAF SPI0 (Serial Peripheral Interface) Name $00D8 Bit 4 SCI1 (Asynchronous Serial Interface) $00D8 - $00DF Address Bit 5 0 Read: Write: Read: Write: Read: Write: Read: Write: Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SPIE SPE SPTIE MSTR CPOL CPHA SSOE LSBFE 0 0 0 SPISWAI SPC0 SPPR2 SPPR1 SPPR0 SPR2 SPR1 SPR0 0 SPTEF MODF 0 0 0 0 SPIF MODFEN BIDIROE 0 0 0 MC9S12DP512 Device Guide V01.25 $00D8 - $00DF Address SPI0 (Serial Peripheral Interface) Name $00DC Reserved $00DD SPI0DR $00DE $00DF Reserved Read: Write: Read: Write: Read: Write: $00E0 - $00E7 Address IBAD $00E1 IBFD $00E2 IBCR $00E3 IBSR $00E4 IBDR $00E5 $00E7 Reserved $00E8 - $00EF Address Name $00E8 DLCBCR1 $00E9 DLCBSVR $00EA DLCBCR2 $00EB DLCBDR $00EC DLCBARD $00ED DLCBRSR $00EE DLCSCR $00EF DLCBSTAT Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 0 Bit 0 0 Bit 7 6 5 4 3 2 1 Bit 0 0 0 0 0 0 0 0 0 IIC (Inter IC Bus) Name $00E0 Bit 7 0 Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ADR7 ADR6 ADR5 ADR4 ADR3 ADR2 ADR1 0 IBC7 IBC6 IBC5 IBC4 IBC3 IBC2 IBC1 IBC0 IBEN IBIE MS/SL TX/RX TXAK 0 TCF IAAS IBB 0 0 RSTA SRW D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 0 0 IBAL IBIF IBSWAI RXAK BDLC (Bytelevel Data Link Controller J1850) Bit 7 Read: IMSG Write: Read: 0 Write: Read: SMRST Write: Read: D7 Write: Read: 0 Write: Read: 0 Write: Read: 0 Write: Read: 0 Write: Bit 6 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 Bit 0 IE WCM 0 I3 I2 I1 I0 0 0 DLOOP RX4XE NBFS TEOD TSIFR TMIFR1 TMIFR0 D6 D5 D4 D3 D2 D1 D0 0 0 BO3 BO2 BO1 BO0 R5 R4 R3 R2 R1 R0 0 0 0 0 0 0 0 IDLE CLKS RXPOL 0 0 0 0 0 BDLCE 0 37 MC9S12DP512 Device Guide V01.25 $00F0 - $00F7 Address Name $00F0 SPI1CR1 $00F1 SPI1CR2 $00F2 SPI1BR $00F3 SPI1SR $00F4 Reserved $00F5 SPI1DR $00F6 $00F7 SPI1 (Serial Peripheral Interface) Reserved Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: $00F8 - $00FF Address SPI2CR1 $00F9 SPI2CR2 $00FA SPI2BR $00FB SPI2SR $00FC Reserved $00FD SPI2DR $00FE $00FF Reserved $0100 - $010F Address Name $0100 FCLKDIV $0101 FSEC $0102 FTSTMOD $0103 FCNFG $0104 FPROT $0105 FSTAT Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SPIE SPE SPTIE MSTR CPOL CPHA SSOE LSBFE 0 0 0 SPISWAI SPC0 SPPR2 SPPR1 SPPR0 SPR2 SPR1 SPR0 SPIF 0 SPTEF MODF 0 0 0 0 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 Bit 0 0 0 0 0 0 0 0 0 0 MODFEN BIDIROE 0 0 SPI2 (Serial Peripheral Interface) Name $00F8 Bit 7 Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SPIE SPE SPTIE MSTR CPOL CPHA SSOE LSBFE 0 0 0 SPISWAI SPC0 SPPR2 SPPR1 SPPR0 SPR2 SPR1 SPR0 SPIF 0 SPTEF MODF 0 0 0 0 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 Bit 0 0 0 0 0 0 0 0 0 Bit 3 Bit 2 Bit 1 Bit 0 FDIV3 FDIV2 FDIV1 FDIV0 NV3 NV2 SEC1 SEC0 0 0 0 0 0 FPHS0 FPLDIS 0 MODFEN BIDIROE 0 0 Flash Control Register (fts512k4) Bit 7 Bit 6 Bit 5 Bit 4 Read: FDIVLD PRDIV8 FDIV5 FDIV4 Write: Read: KEYEN1 KEYEN0 NV5 NV4 Write: Read: 0 0 0 WRALL Write: Read: 0 CBEIE CCIE KEYACC Write: Read: FPOPEN NV6 FPHDIS FPHS1 Write: Read: CCIF CBEIF PVIOL ACCERR Write: 0 BLANK 0 BKSEL1 BKSEL0 FPLS1 FPLS0 0 0 MC9S12DP512 Device Guide V01.25 $0100 - $010F Address Flash Control Register (fts512k4) Name $0106 FCMD $0107 Reserved $0108 FADDRHI $0109 FADDRLO $010A FDATAHI $010B FDATALO $010C $010F Reserved Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: $0110 - $011B Address Name $0110 ECLKDIV $0111 $0112 Reserved $0113 ECNFG $0114 EPROT $0115 ESTAT $0116 ECMD $0117 Reserved $0118 EADDRHI $0119 EADDRLO $011A EDATAHI $011B EDATALO Bit 5 Bit 4 0 Bit 3 0 CMDB6 CMDB5 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 Bit 8 Bit 7 6 5 4 3 2 1 Bit 0 Bit 15 14 13 12 11 10 9 Bit 8 Bit 7 6 5 4 3 2 1 Bit 0 0 0 0 0 0 0 0 0 Bit 7 Bit 6 Read: EDIVLD PRDIV8 Write: Read: 0 0 Write: Read: CBEIE CCIE Write: Read: NV6 EPOPEN Write: Read: CCIF CBEIF Write: Read: 0 CMDB6 Write: Read: 0 0 Write: Read: 0 0 Write: Read: Bit 7 6 Write: Read: Bit 15 14 Write: Read: Bit 7 6 Write: Bit 2 CMDB2 Bit 1 0 Bit 0 CMDB0 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 EDIV5 EDIV4 EDIV3 EDIV2 EDIV1 EDIV0 0 0 0 0 0 0 0 0 0 0 0 0 NV5 NV4 EPDIS EP2 EP1 EP0 PVIOL ACCERR 0 0 0 0 0 0 0 0 0 0 0 5 4 13 5 CMDB5 BLANK CMDB2 0 CMDB0 0 0 0 10 9 Bit 8 3 2 1 Bit 0 12 11 10 9 Bit 8 4 3 2 1 Bit 0 Bit 2 0 Bit 1 0 Bit 0 0 Reserved for RAM Control Register Name Reserved Bit 6 EEPROM Control Register (eets4k) $011C - $011F Address $011C $011F Bit 7 0 Read: Write: Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 39 MC9S12DP512 Device Guide V01.25 $0120 - $013F Address Name $0120 ATD1CTL0 $0121 ATD1CTL1 $0122 ATD1CTL2 $0123 ATD1CTL3 $0124 ATD1CTL4 $0125 ATD1CTL5 $0126 ATD1STAT0 $0127 Reserved $0128 ATD1TEST0 $0129 ATD1TEST1 $012A Reserved $012B ATD1STAT1 $012C Reserved $012D ATD1DIEN $012E Reserved $012F PORTAD1 $0130 ATD1DR0H $0131 ATD1DR0L $0132 ATD1DR1H $0133 ATD1DR1L $0134 ATD1DR2H $0135 ATD1DR2L $0136 ATD1DR3H $0137 ATD1DR3L $0138 ATD1DR4H ATD1 (Analog to Digital Converter 10 Bit 8 Channel) Bit 7 Read: 0 Write: Read: 0 Write: Read: ADPU Write: Read: 0 Write: Read: SRES8 Write: Read: DJM Write: Read: SCF Write: Read: 0 Write: Read: 0 Write: Read: 0 Write: Read: 0 Write: Read: CCF7 Write: Read: 0 Write: Read: Bit 7 Write: Read: 0 Write: Read: Bit 7 Write: Read: Bit 15 Write: Read: Bit 7 Write: Read: Bit 15 Write: Read: Bit 7 Write: Read: Bit 15 Write: Read: Bit 7 Write: Read: Bit 15 Write: Read: Bit 7 Write: Read: Bit 15 Write: Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 0 Bit 0 0 0 0 0 0 0 0 0 AFFC AWAI ETRIG ASCIE S8C S4C S2C S1C FIFO FRZ1 FRZ0 SMP1 SMP0 PRS4 PRS3 PRS2 PRS1 PRS0 DSGN SCAN MULT CC CB CA 0 ETORF FIFOR 0 CC2 CC1 CC0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CCF6 CCF5 CCF4 CCF3 CCF2 CCF1 CCF0 0 0 0 0 0 0 0 6 5 4 3 2 1 Bit 0 0 0 0 0 0 0 0 6 5 4 3 2 1 Bit 0 14 13 12 11 10 9 Bit 8 6 5 4 3 2 1 Bit 0 14 13 12 11 10 9 Bit 8 6 5 4 3 2 1 Bit 0 14 13 12 11 10 9 Bit 8 6 5 4 3 2 1 Bit 0 14 13 12 11 10 9 Bit 8 6 5 4 3 2 1 Bit 0 14 13 12 11 10 9 Bit 8 ETRIGLE ETRIGP 0 0 0 ASCIF SC MC9S12DP512 Device Guide V01.25 $0120 - $013F Address ATD1 (Analog to Digital Converter 10 Bit 8 Channel) Name $0139 ATD1DR4L $013A ATD1DR5H $013B ATD1DR5L $013C ATD1DR6H $013D ATD1DR6L $013E ATD1DR7H $013F ATD1DR7L Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: $0140 - $017F Address Name Read: $0140 CAN0CTL0 Write: Read: $0141 CAN0CTL1 Write: Read: $0142 CAN0BTR0 Write: Read: $0143 CAN0BTR1 Write: Read: $0144 CAN0RFLG Write: Read: $0145 CAN0RIER Write: Read: $0146 CAN0TFLG Write: Read: $0147 CAN0TIER Write: Read: $0148 CAN0TARQ Write: Read: $0149 CAN0TAAK Write: Read: $014A CAN0TBSEL Write: Read: $014B CAN0IDAC Write: Read: $014C Reserved $014D Write: Read: $014E CAN0RXERR Write: Read: $014F CAN0TXERR Write: $0150 - CAN0IDAR0 - Read: $0153 CAN0IDAR3 Write: Bit 7 Bit 7 Bit 6 6 Bit 5 5 Bit 4 4 Bit 3 3 Bit 2 2 Bit 1 1 Bit 0 Bit 0 Bit 15 14 13 12 11 10 9 Bit 8 Bit 7 6 5 4 3 2 1 Bit 0 Bit 15 14 13 12 11 10 9 Bit 8 Bit 7 6 5 4 3 2 1 Bit 0 Bit 15 14 13 12 11 10 9 Bit 8 Bit 7 6 5 4 3 2 1 Bit 0 CAN0 (Freescale Scalable CAN - FSCAN) Bit 7 RXFRM Bit 6 RXACT Bit 5 CSWAI Bit 4 SYNCH CANE CLKSRC LOOPB LISTEN SJW1 SJW0 BRP5 BRP4 SAMP Bit 3 Bit 2 Bit 1 Bit 0 TIME WUPE SLPRQ INITRQ SLPAK INITAK BRP1 BRP0 0 BRP3 WUPM BRP2 TSEG22 TSEG21 TSEG20 TSEG13 TSEG12 TSEG11 TSEG10 RSTAT1 RSTAT0 TSTAT1 WUPIF CSCIF WUPIE CSCIE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IDAM1 IDAM0 0 0 0 0 TSTAT0 OVRIF RXF OVRIE RXFIE TXE2 TXE1 TXE0 TXEIE2 TXEIE1 TXEIE0 RSTATE1 RSTATE0 TSTATE1 TSTATE0 ABTRQ2 ABTRQ1 ABTRQ0 ABTAK2 ABTAK1 ABTAK0 TX2 TX1 TX0 0 IDHIT2 IDHIT1 IDHIT0 0 0 0 0 RXERR7 RXERR6 RXERR5 RXERR4 RXERR3 RXERR2 RXERR1 RXERR0 TXERR7 TXERR6 TXERR5 TXERR4 TXERR3 TXERR2 TXERR1 TXERR0 AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0 41 MC9S12DP512 Device Guide V01.25 $0140 - $017F Address $0154 $0157 $0158 $015B $015C $015F $0160 $016F $0170 $017F Name CAN0IDMR0 CAN0IDMR3 CAN0IDAR4 CAN0IDAR7 CAN0IDMR4 CAN0IDMR7 CAN0RXFG CAN0TXFG CAN0 (Freescale Scalable CAN - MSCAN) Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0 AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0 AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0 FOREGROUND RECEIVE BUFFER see Table 1-2 FOREGROUND TRANSMIT BUFFER see Table 1-2 Table 1-2 Detailed MSCAN Foreground Receive and Transmit Buffer Layout Address Name Extended ID $xxx0 Standard ID CANxRIDR0 Extended ID $xxx1 Standard ID CANxRIDR1 Extended ID $xxx2 Standard ID CANxRIDR2 Extended ID $xxx3 Standard ID CANxRIDR3 $xxx4 - CANxRDSR0 $xxxB CANxRDSR7 $xxxC $xxxD $xxxE $xxxF $xx10 $xx11 $xx12 Read: Read: Write: Read: Read: Write: Read: Read: Write: Read: Read: Write: Read: Write: Read: CANRxDLR Write: Read: Reserved Write: Read: CANxRTSRH Write: Read: CANxRTSRL Write: Extended ID Read: CANxTIDR0 Write: Standard ID Read: Write: Extended ID Read: CANxTIDR1 Write: Standard ID Read: Write: Extended ID Read: CANxTIDR2 Write: Standard ID Read: Write: Bit 7 ID28 ID10 Bit 6 ID27 ID9 Bit 5 ID26 ID8 Bit 4 ID25 ID7 Bit 3 ID24 ID6 Bit 2 ID23 ID5 Bit 1 ID22 ID4 Bit 0 ID21 ID3 ID20 ID2 ID19 ID1 ID18 ID0 SRR=1 RTR IDE=1 IDE=0 ID17 ID16 ID15 ID14 ID13 ID12 ID11 ID10 ID9 ID8 ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0 RTR DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DLC3 DLC2 DLC1 DLC0 TSR15 TSR14 TSR13 TSR12 TSR11 TSR10 TSR9 TSR8 TSR7 TSR6 TSR5 TSR4 TSR3 TSR2 TSR1 TSR0 ID28 ID27 ID26 ID25 ID24 ID23 ID22 ID21 ID10 ID9 ID8 ID7 ID6 ID5 ID4 ID3 ID20 ID19 ID18 SRR=1 IDE=1 ID17 ID16 ID15 ID2 ID1 ID0 RTR IDE=0 ID14 ID13 ID12 ID11 ID10 ID9 ID8 ID7 MC9S12DP512 Device Guide V01.25 Table 1-2 Detailed FSCAN Foreground Receive and Transmit Buffer Layout Address $xx13 Name Extended ID CANxTIDR3 Standard ID $xx14 $xx1B CANxTDSR0 CANxTDSR7 $xx1C CANxTDLR $xx1D CANxTTBPR $xx1E CANxTTSRH $xx1F CANxTTSRL Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: $0180 - $01BF Address Name Read: $0180 CAN1CTL0 Write: Read: $0181 CAN1CTL1 Write: Read: $0182 CAN1BTR0 Write: Read: $0183 CAN1BTR1 Write: Read: $0184 CAN1RFLG Write: Read: $0185 CAN1RIER Write: Read: $0186 CAN1TFLG Write: Read: $0187 CAN1TIER Write: Read: $0188 CAN1TARQ Write: Read: $0189 CAN1TAAK Write: Read: $018A CAN1TBSEL Write: Read: $018B CAN1IDAC Write: Read: $018C Reserved $018D Write: Read: $018E CAN1RXERR Write: Read: $018F CAN1TXERR Write: $0190 - CAN1IDAR0 - Read: $0193 CAN1IDAR3 Write: Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ID6 ID5 ID4 ID3 ID2 ID1 ID0 RTR DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DLC3 DLC2 DLC1 DLC0 PRIO7 PRIO6 PRIO5 PRIO4 PRIO3 PRIO2 PRIO1 PRIO0 TSR15 TSR14 TSR13 TSR12 TSR11 TSR10 TSR9 TSR8 TSR7 TSR6 TSR5 TSR4 TSR3 TSR2 TSR1 TSR0 CAN1 (Freescale Scalable CAN - FSCAN) Bit 7 RXFRM Bit 6 RXACT Bit 5 CSWAI Bit 4 SYNCH CANE CLKSRC LOOPB LISTEN SJW1 SJW0 BRP5 BRP4 SAMP Bit 3 Bit 2 Bit 1 Bit 0 TIME WUPE SLPRQ INITRQ SLPAK INITAK BRP1 BRP0 0 BRP3 WUPM BRP2 TSEG22 TSEG21 TSEG20 TSEG13 TSEG12 TSEG11 TSEG10 RSTAT1 RSTAT0 TSTAT1 WUPIF CSCIF WUPIE CSCIE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IDAM1 IDAM0 0 0 0 0 TSTAT0 OVRIF RXF OVRIE RXFIE TXE2 TXE1 TXE0 TXEIE2 TXEIE1 TXEIE0 RSTATE1 RSTATE0 TSTATE1 TSTATE0 ABTRQ2 ABTRQ1 ABTRQ0 ABTAK2 ABTAK1 ABTAK0 TX2 TX1 TX0 0 IDHIT2 IDHIT1 IDHIT0 0 0 0 0 RXERR7 RXERR6 RXERR5 RXERR4 RXERR3 RXERR2 RXERR1 RXERR0 TXERR7 TXERR6 TXERR5 TXERR4 TXERR3 TXERR2 TXERR1 TXERR0 AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0 43 MC9S12DP512 Device Guide V01.25 $0180 - $01BF Address $0194 $0197 $0198 $019B $019C $019F $01A0 $01AF $01B0 $01BF Name CAN1IDMR0 CAN1IDMR3 CAN1IDAR4 CAN1IDAR7 CAN1IDMR4 CAN1IDMR7 CAN1RXFG CAN1TXFG CAN1 (Freescale Scalable CAN - FSCAN) Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: $01C0 - $01FF Address CAN2CTL0 $01C1 CAN2CTL1 $01C2 CAN2BTR0 $01C3 CAN2BTR1 $01C4 CAN2RFLG $01C5 CAN2RIER $01C6 CAN2TFLG $01C7 CAN2TIER $01C8 CAN2TARQ $01C9 CAN2TAAK $01CA CAN2TBSEL $01CB CAN2IDAC $01CC $01CD Reserved $01CE CAN2RXERR $01CF CAN2TXERR $01D0 $01D3 $01D4 $01D7 CAN2IDAR0 CAN2IDAR3 CAN2IDMR0 CAN2IDMR3 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0 AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0 AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0 FOREGROUND RECEIVE BUFFER see Table 1-2 FOREGROUND TRANSMIT BUFFER see Table 1-2 CAN2 (Freescale Scalable CAN - FSCAN) Name $01C0 Bit 7 Bit 7 Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: RXFRM Bit 6 RXACT Bit 5 CSWAI Bit 4 SYNCH CANE CLKSRC LOOPB LISTEN SJW1 SJW0 BRP5 BRP4 SAMP Bit 3 Bit 2 Bit 1 Bit 0 TIME WUPE SLPRQ INITRQ SLPAK INITAK BRP1 BRP0 0 BRP3 WUPM BRP2 TSEG22 TSEG21 TSEG20 TSEG13 TSEG12 TSEG11 TSEG10 RSTAT1 RSTAT0 TSTAT1 WUPIF CSCIF WUPIE CSCIE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IDAM1 IDAM0 0 0 0 0 TSTAT0 OVRIF RXF OVRIE RXFIE TXE2 TXE1 TXE0 TXEIE2 TXEIE1 TXEIE0 RSTATE1 RSTATE0 TSTATE1 TSTATE0 ABTRQ2 ABTRQ1 ABTRQ0 ABTAK2 ABTAK1 ABTAK0 TX2 TX1 TX0 0 IDHIT2 IDHIT1 IDHIT0 0 0 0 0 RXERR7 RXERR6 RXERR5 RXERR4 RXERR3 RXERR2 RXERR1 RXERR0 TXERR7 TXERR6 TXERR5 TXERR4 TXERR3 TXERR2 TXERR1 TXERR0 AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0 AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0 MC9S12DP512 Device Guide V01.25 $01C0 - $01FF Address $01D8 $01DB $01DC $01DF $01E0 $01EF $01F0 $01FF Name CAN2IDAR4 CAN2IDAR7 CAN2IDMR4 CAN2IDMR7 CAN2RXFG CAN2TXFG CAN2 (Freescale Scalable CAN - FSCAN) Read: Write: Read: Write: Read: Write: Read: Write: $0200 - $023F Address CAN3CTL0 $0201 CAN3CTL1 $0202 CAN3BTR0 $0203 CAN3BTR1 $0204 CAN3RFLG $0205 CAN3RIER $0206 CAN3TFLG $0207 CAN3TIER $0208 CAN3TARQ $0209 CAN3TAAK $020A CAN3TBSEL $020B CAN3IDAC $020C $020D Reserved $020E CAN3RXERR $020F CAN3TXERR $0210 $0213 $0214 $0217 $0218 $021B CAN3IDAR0 CAN3IDAR3 CAN3IDMR0 CAN3IDMR3 CAN3IDAR4 CAN3IDAR7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0 AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0 FOREGROUND RECEIVE BUFFER see Table 1-2 FOREGROUND TRANSMIT BUFFER see Table 1-2 CAN3 (Freescale Scalable CAN - FSCAN) Name $0200 Bit 7 Bit 7 Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: RXFRM Bit 6 RXACT Bit 5 CSWAI Bit 4 SYNCH CANE CLKSRC LOOPB LISTEN SJW1 SJW0 BRP5 BRP4 SAMP Bit 3 Bit 2 Bit 1 Bit 0 TIME WUPE SLPRQ INITRQ SLPAK INITAK BRP1 BRP0 0 BRP3 WUPM BRP2 TSEG22 TSEG21 TSEG20 TSEG13 TSEG12 TSEG11 TSEG10 RSTAT1 RSTAT0 TSTAT1 WUPIF CSCIF WUPIE CSCIE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IDAM1 IDAM0 0 0 0 0 TSTAT0 OVRIF RXF OVRIE RXFIE TXE2 TXE1 TXE0 TXEIE2 TXEIE1 TXEIE0 RSTATE1 RSTATE0 TSTATE1 TSTATE0 ABTRQ2 ABTRQ1 ABTRQ0 ABTAK2 ABTAK1 ABTAK0 TX2 TX1 TX0 0 IDHIT2 IDHIT1 IDHIT0 0 0 0 0 RXERR7 RXERR6 RXERR5 RXERR4 RXERR3 RXERR2 RXERR1 RXERR0 TXERR7 TXERR6 TXERR5 TXERR4 TXERR3 TXERR2 TXERR1 TXERR0 AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0 AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0 AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0 45 MC9S12DP512 Device Guide V01.25 $0200 - $023F Address Name $021C - CAN3IDMR4 $021F CAN3IDMR7 $0220 CAN3RXFG $022F $0230 CAN3TXFG $023F CAN3 (Freescale Scalable CAN - FSCAN) Read: Write: Read: Write: Read: Write: $0240 - $027F Address PTT $0241 PTIT $0242 DDRT $0243 RDRT $0244 PERT $0245 PPST $0246 $0247 Reserved $0248 PTS $0249 PTIS $024A DDRS $024B RDRS $024C PERS $024D PPSS $024E WOMS $024F Reserved $0250 PTM $0251 PTIM $0252 DDRM $0253 RDRM Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0 FOREGROUND RECEIVE BUFFER see Table 1-2 FOREGROUND TRANSMIT BUFFER see Table 1-2 PIM (Port Integration Module PIM_9DP256) Name $0240 Bit 7 Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PTT7 PTT6 PTT5 PTT4 PTT3 PTT2 PTT1 PTT0 PTIT7 PTIT6 PTIT5 PTIT4 PTIT3 PTIT2 PTIT1 PTIT0 DDRT7 DDRT7 DDRT5 DDRT4 DDRT3 DDRT2 DDRT1 DDRT0 RDRT7 RDRT6 RDRT5 RDRT4 RDRT3 RDRT2 RDRT1 RDRT0 PERT7 PERT6 PERT5 PERT4 PERT3 PERT2 PERT1 PERT0 PPST7 PPST6 PPST5 PPST4 PPST3 PPST2 PPST1 PPST0 0 0 0 0 0 0 0 0 PTS7 PTS6 PTS5 PTS4 PTS3 PTS2 PTS1 PTS0 PTIS7 PTIS6 PTIS5 PTIS4 PTIS3 PTIS2 PTIS1 PTIS0 DDRS7 DDRS7 DDRS5 DDRS4 DDRS3 DDRS2 DDRS1 DDRS0 RDRS7 RDRS6 RDRS5 RDRS4 RDRS3 RDRS2 RDRS1 RDRS0 PERS7 PERS6 PERS5 PERS4 PERS3 PERS2 PERS1 PERS0 PPSS7 PPSS6 PPSS5 PPSS4 PPSS3 PPSS2 PPSS1 PPSS0 WOMS7 WOMS6 WOMS5 WOMS4 WOMS3 WOMS2 WOMS1 WOMS0 0 0 0 0 0 0 0 0 PTM7 PTM6 PTM5 PTM4 PTM3 PTM2 PTM1 PTM0 PTIM7 PTIM6 PTIM5 PTIM4 PTIM3 PTIM2 PTIM1 PTIM0 DDRM7 DDRM7 DDRM5 DDRM4 DDRM3 DDRM2 DDRM1 DDRM0 RDRM7 RDRM6 RDRM5 RDRM4 RDRM3 RDRM2 RDRM1 RDRM0 MC9S12DP512 Device Guide V01.25 $0240 - $027F Address PIM (Port Integration Module PIM_9DP256) Name $0254 PERM $0255 PPSM $0256 WOMM $0257 MODRR $0258 PTP $0259 PTIP $025A DDRP $025B RDRP $025C PERP $025D PPSP $025E PIEP $025F PIFP $0260 PTH $0261 PTIH $0262 DDRH $0263 RDRH $0264 PERH $0265 PPSH $0266 PIEH $0267 PIFH $0268 PTJ $0269 PTIJ $026A DDRJ $026B RDRJ $026C PERJ Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PERM7 PERM6 PERM5 PERM4 PERM3 PERM2 PERM1 PERM0 PPSM7 PPSM6 PPSM5 PPSM4 PPSM3 PPSM2 PPSM1 PPSM0 WOMM7 WOMM6 WOMM5 WOMM4 WOMM3 WOMM2 WOMM1 WOMM0 0 MODRR6 MODRR5 MODRR4 MODRR3 MODRR2 MODRR1 MODRR0 PTP7 PTP6 PTP5 PTP4 PTP3 PTP2 PTP1 PTP0 PTIP7 PTIP6 PTIP5 PTIP4 PTIP3 PTIP2 PTIP1 PTIP0 DDRP7 DDRP7 DDRP5 DDRP4 DDRP3 DDRP2 DDRP1 DDRP0 RDRP7 RDRP6 RDRP5 RDRP4 RDRP3 RDRP2 RDRP1 RDRP0 PERP7 PERP6 PERP5 PERP4 PERP3 PERP2 PERP1 PERP0 PPSP7 PPSP6 PPSP5 PPSP4 PPSP3 PPSP2 PPSP1 PPSS0 PIEP7 PIEP6 PIEP5 PIEP4 PIEP3 PIEP2 PIEP1 PIEP0 PIFP7 PIFP6 PIFP5 PIFP4 PIFP3 PIFP2 PIFP1 PIFP0 PTH7 PTH6 PTH5 PTH4 PTH3 PTH2 PTH1 PTH0 PTIH7 PTIH6 PTIH5 PTIH4 PTIH3 PTIH2 PTIH1 PTIH0 DDRH7 DDRH7 DDRH5 DDRH4 DDRH3 DDRH2 DDRH1 DDRH0 RDRH7 RDRH6 RDRH5 RDRH4 RDRH3 RDRH2 RDRH1 RDRH0 PERH7 PERH6 PERH5 PERH4 PERH3 PERH2 PERH1 PERH0 PPSH7 PPSH6 PPSH5 PPSH4 PPSH3 PPSH2 PPSH1 PPSH0 PIEH7 PIEH6 PIEH5 PIEH4 PIEH3 PIEH2 PIEH1 PIEH0 PIFH7 PIFH6 PIFH5 PIFH4 PIFH3 PIFH2 PIFH1 PIFH0 PTJ7 PTJ6 0 0 0 0 PTJ1 PTJ0 PTIJ7 PTIJ6 0 0 0 0 PTIJ1 PTIJ0 DDRJ7 DDRJ7 0 0 0 0 DDRJ1 DDRJ0 RDRJ7 RDRJ6 0 0 0 0 RDRJ1 RDRJ0 PERJ7 PERJ6 0 0 0 0 PERJ1 PERJ0 47 MC9S12DP512 Device Guide V01.25 $0240 - $027F Address PIM (Port Integration Module PIM_9DP256) Name $026D PPSJ $026E PIEJ $026F PIFJ $0270 $027F Reserved Read: Write: Read: Write: Read: Write: CAN4CTL0 $0281 CAN4CTL1 $0282 CAN4BTR0 $0283 CAN4BTR1 $0284 CAN4RFLG $0285 CAN4RIER $0286 CAN4TFLG $0287 CAN4TIER $0288 CAN4TARQ $0289 CAN4TAAK $028A CAN4TBSEL $028B CAN4IDAC $028C $028D Reserved $028E CAN4RXERR $028F CAN4TXERR $0290 $0293 $0294 $0297 $0298 $029B CAN4IDAR0 CAN4IDAR3 CAN4IDMR0 CAN4IDMR3 CAN4IDAR4 CAN4IDAR7 PPSJ7 PPSJ6 PIEJ7 PIEJ6 PIFJ7 PIFJ6 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 0 0 0 0 0 0 0 0 0 Bit 1 Bit 0 PPSJ1 PPSJ0 PIEJ1 PIEJ0 PIFJ1 PIFJ0 CAN4 (Freescale Scalable CAN - FSCAN) Name $0280 Bit 6 Read: $0280 - $02BF Address Bit 7 Bit 7 Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: RXFRM Bit 6 RXACT Bit 5 CSWAI Bit 4 SYNCH CANE CLKSRC LOOPB LISTEN SJW1 SJW0 BRP5 BRP4 SAMP Bit 3 Bit 2 Bit 1 Bit 0 TIME WUPE SLPRQ INITRQ SLPAK INITAK BRP1 BRP0 0 BRP3 WUPM BRP2 TSEG22 TSEG21 TSEG20 TSEG13 TSEG12 TSEG11 TSEG10 RSTAT1 RSTAT0 TSTAT1 WUPIF CSCIF WUPIE CSCIE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IDAM1 IDAM0 0 0 0 0 TSTAT0 OVRIF RXF OVRIE RXFIE TXE2 TXE1 TXE0 TXEIE2 TXEIE1 TXEIE0 RSTATE1 RSTATE0 TSTATE1 TSTATE0 ABTRQ2 ABTRQ1 ABTRQ0 ABTAK2 ABTAK1 ABTAK0 TX2 TX1 TX0 0 IDHIT2 IDHIT1 IDHIT0 0 0 0 0 RXERR7 RXERR6 RXERR5 RXERR4 RXERR3 RXERR2 RXERR1 RXERR0 TXERR7 TXERR6 TXERR5 TXERR4 TXERR3 TXERR2 TXERR1 TXERR0 AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0 AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0 AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0 MC9S12DP512 Device Guide V01.25 $0280 - $02BF CAN4 (Freescale Scalable CAN - FSCAN) Address Name $029C - CAN4IDMR4 $029F CAN4IDMR7 $02A0 CAN4RXFG $02AF $02B0 CAN4TXFG $02BF Read: Write: Read: Write: Read: Write: $02C0 - $03FF Address $02C0 $03FF Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0 FOREGROUND RECEIVE BUFFER see Table 1-2 FOREGROUND TRANSMIT BUFFER see Table 1-2 Reserved Name Reserved Bit 7 Bit 7 0 Read: Write: Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 0 Bit 0 0 1.6 Part ID Assignments The part ID is located in two 8-bit registers PARTIDH and PARTIDL (addresses $001A and $001B after reset). The read-only value is a unique part ID for each revision of the chip. Table 1-3 shows the assigned part ID number. Table 1-3 Assigned Part ID Numbers Device Mask Set Number Part ID1 MC9S12DP512 0L00M $0400 MC9S12DP512 1L00M $0401 MC9S12DP512 2L00M $0402 MC9S12DP512 3L00M $0403 MC9S12DP512 4L00M $0404 NOTES: 1. The coding is as follows: Bit 15 - 12: Major family identifier Bit 11 - 8: Minor family identifier Bit 7 - 4: Major mask set revision number including FAB transfers Bit 3 - 0: Minor - non full - mask set revision 1.7 Memory Size Assignments The device memory sizes are located in two 8-bit registers MEMSIZ0 and MEMSIZ1 (addresses $001C and $001D after reset). Table 1-4 shows the read-only values of these registers. Refer to HCS12 Module Mapping Control (MMC) Block Guide for further details. Table 1-4 Memory size registers Register name Value MEMSIZ0 $26 MEMSIZ1 $82 49 MC9S12DP512 Device Guide V01.25 MC9S12DP512 Device Guide V01.25 Section 2 Signal Description This section describes signals that connect off-chip. It includes a pinout diagram, a table of signal properties, and detailed discussion of signals. It is built from the signal description sections of the Block Guides of the individual IP blocks on the device. 51 MC9S12DP512 Device Guide V01.25 2.1 Device Pinout MC9S12DP512 112LQFP 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 ADDR5/DATA5/PB5 ADDR6/DATA6/PB6 ADDR7/DATA7/PB7 SS2/KWH7/PH7 SCK2/KWH6/PH6 MOSI2/KWH5/PH5 MISO2/KWH4/PH4 XCLKS/NOACC/PE7 MODB/IPIPE1/PE6 MODA/IPIPE0/PE5 ECLK/PE4 VSSR VDDR RESET VDDPLL XFC VSSPLL EXTAL XTAL TEST SS1/KWH3/PH3 SCK1/KWH2/PH2 MOSI1/KWH1/PH1 MISO1/KWH0/PH0 LSTRB/TAGLO/PE3 R/W/PE2 IRQ/PE1 XIRQ/PE0 SS1/PWM3/KWP3/PP3 SCK1/PWM2/KWP2/PP2 MOSI1/PWM1/KWP1/PP1 MISO1/PWM0/KWP0/PP0 XADDR17/PK3 XADDR16/PK2 XADDR15/PK1 XADDR14/PK0 IOC0/PT0 IOC1/PT1 IOC2/PT2 IOC3/PT3 VDD1 VSS1 IOC4/PT4 IOC5/PT5 IOC6/PT6 IOC7/PT7 XADDR19/PK5 XADDR18/PK4 KWJ1/PJ1 KWJ0/PJ0 MODC/TAGHI/BKGD ADDR0/DATA0/PB0 ADDR1/DATA1/PB1 ADDR2/DATA2/PB2 ADDR3/DATA3/PB3 ADDR4/DATA4/PB4 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 PP4/KWP4/PWM4/MISO2 PP5/KWP5/PWM5/MOSI2 PP6/KWP6/PWM6/SS2 PP7/KWP7/PWM7/SCK2 PK7/ECS/ROMCTL VDDX VSSX PM0/RXCAN0/RXB PM1/TXCAN0/TXB PM2/RXCAN1/RXCAN0/MISO0 PM3/TXCAN1/TXCAN0/SS0 PM4/RXCAN2/RXCAN0/RXCAN4/MOSI0 PM5/TXCAN2/TXCAN0/TXCAN4/SCK0 PJ6/KWJ6/RXCAN4/SDA/RXCAN0 PJ7/KWJ7/TXCAN4/SCL/TXCAN0 VREGEN PS7/SS0 PS6/SCK0 PS5/MOSI0 PS4/MISO0 PS3/TXD1 PS2/RXD1 PS1/TXD0 PS0/RXD0 PM6/RXCAN3/RXCAN4 PM7/TXCAN3/TXCAN4 VSSA VRL The MC9S12DP512 is available in a 112-pin low profile quad flat pack (LQFP). Most pins perform two or more functions, as described in the Signal Descriptions. Figure 2-1 shows the pin assignments. Figure 2-1 Pin Assignments in 112-pin LQFP VRH VDDA PAD15/AN15/ETRIG1 PAD07/AN07/ETRIG0 PAD14/AN14 PAD06/AN06 PAD13/AN13 PAD05/AN05 PAD12/AN12 PAD04/AN04 PAD11/AN11 PAD03/AN03 PAD10/AN10 PAD02/AN02 PAD09/AN09 PAD01/AN01 PAD08/AN08 PAD00/AN00 VSS2 VDD2 PA7/ADDR15/DATA15 PA6/ADDR14/DATA14 PA5/ADDR13/DATA13 PA4/ADDR12/DATA12 PA3/ADDR11/DATA11 PA2/ADDR10/DATA10 PA1/ADDR9/DATA9 PA0/ADDR8/DATA8 MC9S12DP512 Device Guide V01.25 2.2 Signal Properties Summary Table 2-1 summarizes the pin functionality. Table 2-1 Signal Properties Pin Name Pin Name Pin Name Pin Name Pin Name Power Funct. 1 Funct. 2 Funct. 3 Funct. 4 Funct. 5 Supply EXTAL -- -- -- -- XTAL -- -- -- -- Internal Pull Resistor CTRL Reset State VDDPLL Description Oscillator Pins RESET -- -- -- -- VDDR TEST -- -- -- -- NA VREGEN -- -- -- -- VDDX XFC -- -- -- -- VDDPLL BKGD TAGHI MODC -- -- VDDR PAD15 AN15 ETRIG1 -- -- Port AD Input, Analog Input AN7 of ATD1, External Trigger Input of ATD1 PAD[14:8] AN[14:08] -- -- -- Port AD Inputs, Analog Inputs AN[6:0] of ATD1 PAD07 AN07 ETRIG0 -- -- Port AD Input, Analog Input AN7 of ATD0, External Trigger Input of ATD0 PAD[06:00] AN[06:00] -- -- -- Port AD Inputs, Analog Inputs AN[6:0] of ATD0 PA[7:0] ADDR[15:8]/ DATA[15:8] -- -- -- PB[7:0] ADDR[7:0]/ DATA[7:0] -- -- -- PUCR/ PUPBE PE7 NOACC XCLKS -- -- PUCR/ PUPEE PE6 IPIPE1 MODB -- -- VDDA IPIPE0 MODA -- -- None External Reset Test Input Voltage Regulator Enable Input PLL Loop Filter Always Up None PUCR/ PUPAE VDDR PE5 None Up None Background Debug, Tag High, Mode Input Port A I/O, Multiplexed Address/Data Disabled Port B I/O, Multiplexed Address/Data Up Port E I/O, Access, Clock Select While RESET pin is low: Down Port E I/O, Pipe Status, Mode Input While RESET pin is low: Down Port E I/O, Pipe Status, Mode Input PE4 ECLK -- -- -- Port E I/O, Bus Clock Output PE3 LSTRB TAGLO -- -- Port E I/O, Byte Strobe, Tag Low PE2 R/W -- -- -- PE1 IRQ -- -- -- Port E Input, Maskable Interrupt PE0 XIRQ -- -- -- Port E Input, Non Maskable Interrupt PUCR/ PUPEE Up Port E I/O, R/W in expanded modes 53 MC9S12DP512 Device Guide V01.25 Pin Name Pin Name Pin Name Pin Name Pin Name Power Funct. 1 Funct. 2 Funct. 3 Funct. 4 Funct. 5 Supply Internal Pull Resistor CTRL Reset State Description PH7 KWH7 SS2 -- -- Port H I/O, Interrupt, SS of SPI2 PH6 KWH6 SCK2 -- -- Port H I/O, Interrupt, SCK of SPI2 PH5 KWH5 MOSI2 -- -- Port H I/O, Interrupt, MOSI of SPI2 PH4 KWH4 MISO2 -- -- PH3 KWH3 SS1 -- -- PH2 KWH2 SCK1 -- -- Port H I/O, Interrupt, SCK of SPI1 PH1 KWH1 MOSI1 -- -- Port H I/O, Interrupt, MOSI of SPI1 PH0 KWH0 MISO1 -- -- Port H I/O, Interrupt, MISO of SPI1 PJ7 KWJ7 TXCAN4 SCL TXCAN0 PJ6 KWJ6 RXCAN4 SDA RXCAN0 PJ[1:0] KWJ[1:0] -- -- -- PK7 ECS ROMCTL -- -- PK[5:0] XADDR [19:14] -- -- -- PM7 TXCAN3 TXCAN4 -- -- PM6 RXCAN3 RXCAN4 -- -- VDDR PERH/ PPSH Disabled Port H I/O, Interrupt, MISO of SPI2 Port H I/O, Interrupt, SS of SPI1 Port J I/O, Interrupt, TX of CAN4, SCL of IIC, TX of CAN0 VDDX PERJ/ PPSJ Up Port J I/O, Interrupt, RX of CAN4, SDA of IIC, RX of CAN0 Port J I/O, Interrupts VDDX PUCR/ PUPKE Up Port K I/O, Emulation Chip Select, ROM Control Port K I/O, Extended Addresses Port M I/O, TX of CAN3, TX of CAN4 Port M I/O, RX of CAN3, RX of CAN4 Port M I/O, TX of CAN2, CAN0, CAN4, SCK of SPI0 PM5 TXCAN2 TXCAN0 TXCAN4 SCK0 PM4 RXCAN2 RXCAN0 RXCAN4 MOSI0 PM3 TXCAN1 TXCAN0 -- SS0 PM2 RXCAN1 RXCAN0 -- MISO0 PM1 TXCAN0 TXB -- -- PM0 RXCAN0 RXB -- -- Port M I/O, RX of CAN0, RX of BDLC VDDX Port M I/O, RX of CAN2, CAN0, CAN4, MOSI of SPI0 PERM/ Disabled PPSM Port M I/O, TX of CAN1, CAN0, SS of SPI0 Port M I/O, RX of CAN1, CAN0, MISO of SPI0 Port M I/O, TX of CAN0, RX of BDLC PP7 KWP7 PWM7 SCK2 -- Port P I/O, Interrupt, Channel 7 of PWM, SCK of SPI2 PP6 KWP6 PWM6 SS2 -- Port P I/O, Interrupt, Channel 6 of PWM, SS of SPI2 PP5 KWP5 PWM5 MOSI2 -- Port P I/O, Interrupt, Channel 5 of PWM, MOSI of SPI2 PP4 KWP4 PWM4 MISO2 -- PP3 KWP3 PWM3 SS1 -- PP2 KWP2 PWM2 SCK1 -- Port P I/O, Interrupt, Channel 2 of PWM, SCK of SPI1 PP1 KWP1 PWM1 MOSI1 -- Port P I/O, Interrupt, Channel 1 of PWM, MOSI of SPI1 PP0 KWP0 PWM0 MISO1 -- Port P I/O, Interrupt, Channel 0 of PWM, MISO2 of SPI1 VDDX PERP/ PPSP Disabled Port P I/O, Interrupt, Channel 4 of PWM, MISO2 of SPI2 Port P I/O, Interrupt, Channel 3 of PWM, SS of SPI1 MC9S12DP512 Device Guide V01.25 Pin Name Pin Name Pin Name Pin Name Pin Name Power Funct. 1 Funct. 2 Funct. 3 Funct. 4 Funct. 5 Supply Internal Pull Resistor CTRL Reset State Description PS7 SS0 -- -- -- Port S I/O, SS of SPI0 PS6 SCK0 -- -- -- Port S I/O, SCK of SPI0 PS5 MOSI0 -- -- -- Port S I/O, MOSI of SPI0 PS4 MISO0 -- -- -- PS3 TXD1 -- -- -- PS2 RXD1 -- -- -- Port S I/O, RXD of SCI1 PS1 TXD0 -- -- -- Port S I/O, TXD of SCI0 PS0 RXD0 -- -- -- Port S I/O, RXD of SCI0 PT[7:0] IOC[7:0] -- -- -- VDDX VDDX PERS/ PPSS PERT/ PPST Up Port S I/O, MISO of SPI0 Port S I/O, TXD of SCI1 Disabled Port T I/O, Timer channels 2.3 Detailed Signal Descriptions 2.3.1 EXTAL, XTAL -- Oscillator Pins EXTAL and XTAL are the crystal driver and external clock pins. On reset all the device clocks are derived from the EXTAL input frequency. XTAL is the crystal output. 2.3.2 RESET -- External Reset Pin An active low bidirectional control signal, it acts as an input to initialize the MCU to a known start-up state, and an output when an internal MCU function causes a reset. 2.3.3 TEST -- Test Pin This input only pin is reserved for test. NOTE: The TEST pin must be tied to VSS in all applications. 2.3.4 VREGEN -- Voltage Regulator Enable Pin This input only pin enables or disables the on-chip voltage regulator. 55 MC9S12DP512 Device Guide V01.25 2.3.5 XFC -- PLL Loop Filter Pin PLL loop filter. Please ask your Freescale representative for the interactive application note to compute PLL loop filter elements. Any current leakage on this pin must be avoided. XFC R0 MCU CP CS VDDPLL VDDPLL Figure 2-2 PLL Loop Filter Connections 2.3.6 BKGD / TAGHI / MODC -- Background Debug, Tag High, and Mode Pin The BKGD/TAGHI/MODC pin is used as a pseudo-open-drain pin for the background debug communication. In MCU expanded modes of operation when instruction tagging is on, an input low on this pin during the falling edge of E-clock tags the high half of the instruction word being read into the instruction queue. It is used as a MCU operating mode select pin during reset. The state of this pin is latched to the MODC bit at the rising edge of RESET. This pin has a permanently enabled pull-up device. 2.3.7 PAD15 / AN15 / ETRIG1 -- Port AD Input Pin of ATD1 PAD15 is a general purpose input pin and analog input AN7 of the analog to digital converter ATD1. It can act as an external trigger input for the ATD1. 2.3.8 PAD[14:08] / AN[14:08] -- Port AD Input Pins of ATD1 PAD14 - PAD08 are general purpose input pins and analog inputs AN[6:0] of the analog to digital converter ATD1. 2.3.9 PAD7 / AN07 / ETRIG0 -- Port AD Input Pin of ATD0 PAD7 is a general purpose input pin and analog input AN7 of the analog to digital converter ATD0. It can act as an external trigger input for the ATD0. 2.3.10 PAD[06:00] / AN[06:00] -- Port AD Input Pins of ATD0 PAD06 - PAD00 are general purpose input pins and analog inputs AN[6:0] of the analog to digital converter ATD0. MC9S12DP512 Device Guide V01.25 2.3.11 PA[7:0] / ADDR[15:8] / DATA[15:8] -- Port A I/O Pins PA7-PA0 are general purpose input or output pins. In MCU expanded modes of operation, these pins are used for the multiplexed external address and data bus. 2.3.12 PB[7:0] / ADDR[7:0] / DATA[7:0] -- Port B I/O Pins PB7-PB0 are general purpose input or output pins. In MCU expanded modes of operation, these pins are used for the multiplexed external address and data bus. 2.3.13 PE7 / NOACC / XCLKS -- Port E I/O Pin 7 PE7 is a general purpose input or output pin. During MCU expanded modes of operation, the NOACC signal, when enabled, is used to indicate that the current bus cycle is an unused or "free" cycle. This signal will assert when the CPU is not using the bus. The XCLKS is an input signal which controls whether a crystal in combination with the internal Colpitts (low power) oscillator is used or whether Pierce oscillator/external clock circuitry is used. The state of this pin is latched at the rising edge of RESET. If the input is a logic low the EXTAL pin is configured for an external clock drive or a Pierce Oscillator. If input is a logic high a Colpitts oscillator circuit is configured on EXTAL and XTAL. Since this pin is an input with a pull-up device during reset, if the pin is left floating, the default configuration is a Colpitts oscillator circuit on EXTAL and XTAL. EXTAL CDC * MCU C1 Crystal or ceramic resonator XTAL C2 VSSPLL * Due to the nature of a translated ground Colpitts oscillator a DC voltage bias is applied to the crystal Please contact the crystal manufacturer for crystal DC bias conditions and recommended capacitor value CDC. Figure 2-3 Colpitts Oscillator Connections (PE7=1) 57 MC9S12DP512 Device Guide V01.25 EXTAL C1 MCU XTAL Crystal or ceramic resonator RB RS* C2 VSSPLL * Rs can be zero (shorted) when used with higher frequency crystals. Refer to manufacturer's data. Figure 2-4 Pierce Oscillator Connections (PE7=0) EXTAL CMOS-COMPATIBLE EXTERNAL OSCILLATOR (VDDPLL-Level) MCU XTAL not connected Figure 2-5 External Clock Connections (PE7=0) 2.3.14 PE6 / MODB / IPIPE1 -- Port E I/O Pin 6 PE6 is a general purpose input or output pin. It is used as a MCU operating mode select pin during reset. The state of this pin is latched to the MODB bit at the rising edge of RESET. This pin is shared with the instruction queue tracking signal IPIPE1. This pin is an input with a pull-down device which is only active when RESET is low. 2.3.15 PE5 / MODA / IPIPE0 -- Port E I/O Pin 5 PE5 is a general purpose input or output pin. It is used as a MCU operating mode select pin during reset. The state of this pin is latched to the MODA bit at the rising edge of RESET. This pin is shared with the instruction queue tracking signal IPIPE0. This pin is an input with a pull-down device which is only active when RESET is low. 2.3.16 PE4 / ECLK -- Port E I/O Pin 4 PE4 is a general purpose input or output pin. It can be configured to drive the internal bus clock ECLK. ECLK can be used as a timing reference. MC9S12DP512 Device Guide V01.25 2.3.17 PE3 / LSTRB / TAGLO -- Port E I/O Pin 3 PE3 is a general purpose input or output pin. In MCU expanded modes of operation, LSTRB can be used for the low-byte strobe function to indicate the type of bus access and when instruction tagging is on, TAGLO is used to tag the low half of the instruction word being read into the instruction queue. 2.3.18 PE2 / R/W -- Port E I/O Pin 2 PE2 is a general purpose input or output pin. In MCU expanded modes of operations, this pin drives the read/write output signal for the external bus. It indicates the direction of data on the external bus. 2.3.19 PE1 / IRQ -- Port E Input Pin 1 PE1 is a general purpose input pin and the maskable interrupt request input that provides a means of applying asynchronous interrupt requests. This will wake up the MCU from STOP or WAIT mode. 2.3.20 PE0 / XIRQ -- Port E Input Pin 0 PE0 is a general purpose input pin and the non-maskable interrupt request input that provides a means of applying asynchronous interrupt requests. This will wake up the MCU from STOP or WAIT mode. 2.3.21 PH7 / KWH7 / SS2 -- Port H I/O Pin 7 PH7 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode. It can be configured as slave select pin SS of the Serial Peripheral Interface 2 (SPI2). 2.3.22 PH6 / KWH6 / SCK2 -- Port H I/O Pin 6 PH6 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode. It can be configured as serial clock pin SCK of the Serial Peripheral Interface 2 (SPI2). 2.3.23 PH5 / KWH5 / MOSI2 -- Port H I/O Pin 5 PH5 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode. It can be configured as master output (during master mode) or slave input pin (during slave mode) MOSI of the Serial Peripheral Interface 2 (SPI2). 2.3.24 PH4 / KWH4 / MISO2 -- Port H I/O Pin 2 PH4 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode. It can be configured as master input (during master mode) or slave output (during slave mode) pin MISO of the Serial Peripheral Interface 2 (SPI2). 59 MC9S12DP512 Device Guide V01.25 2.3.25 PH3 / KWH3 / SS1 -- Port H I/O Pin 3 PH3 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode. It can be configured as slave select pin SS of the Serial Peripheral Interface 1 (SPI1). 2.3.26 PH2 / KWH2 / SCK1 -- Port H I/O Pin 2 PH2 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode. It can be configured as serial clock pin SCK of the Serial Peripheral Interface 1 (SPI1). 2.3.27 PH1 / KWH1 / MOSI1 -- Port H I/O Pin 1 PH1 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode. It can be configured as master output (during master mode) or slave input pin (during slave mode) MOSI of the Serial Peripheral Interface 1 (SPI1). 2.3.28 PH0 / KWH0 / MISO1 -- Port H I/O Pin 0 PH0 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode. It can be configured as master input (during master mode) or slave output (during slave mode) pin MISO of the Serial Peripheral Interface 1 (SPI1). 2.3.29 PJ7 / KWJ7 / TXCAN4 / SCL / TXCAN0 -- PORT J I/O Pin 7 PJ7 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode. It can be configured as the transmit pin TXCAN for theFreescale Scalable Controller Area Network controller 0 or 4 (CAN0 or CAN4) or the serial clock pin SCL of the IIC module. 2.3.30 PJ6 / KWJ6 / RXCAN4 / SDA / RXCAN0 -- PORT J I/O Pin 6 PJ6 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode. It can be configured as the receive pin RXCAN for the Freescale Scalable Controller Area Network controller 0 or 4 (CAN 0 or CAN4) or the serial data pin SDA of the IIC module. 2.3.31 PJ[1:0] / KWJ[1:0] -- Port J I/O Pins [1:0] PJ1 and PJ0 are general purpose input or output pins. They can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode. 2.3.32 PK7 / ECS / ROMCTL -- Port K I/O Pin 7 PK7 is a general purpose input or output pin. During MCU expanded modes of operation, this pin is used as the emulation chip select output (ECS). During MCU normal expanded modes of operation, this pin is MC9S12DP512 Device Guide V01.25 used to enable the Flash EEPROM memory in the memory map (ROMCTL). At the rising edge of RESET, the state of this pin is latched to the ROMON bit. 2.3.33 PK[5:0] / XADDR[19:14] -- Port K I/O Pins [5:0] PK5-PK0 are general purpose input or output pins. In MCU expanded modes of operation, these pins provide the expanded address XADDR[19:14] for the external bus. 2.3.34 PM7 / TXCAN3 / TXCAN4 -- Port M I/O Pin 7 PM7 is a general purpose input or output pin. It can be configured as the transmit pin TXCAN of the Freescale Scalable Controller Area Network controllers 3 or 4 (CAN3 or CAN4). 2.3.35 PM6 / RXCAN3 / RXCAN4 -- Port M I/O Pin 6 PM6 is a general purpose input or output pin. It can be configured as the receive pin RXCAN of the Freescale Scalable Controller Area Network controllers 3 or 4 (CAN3 or CAN4). 2.3.36 PM5 / TXCAN2 / TXCAN0 / TXCAN4 / SCK0 -- Port M I/O Pin 5 PM5 is a general purpose input or output pin. It can be configured as the transmit pin TXCAN of the Freescale Scalable Controller Area Network controllers 2, 0 or 4 (CAN2, CAN0 or CAN4). It can be configured as the serial clock pin SCK of the Serial Peripheral Interface 0 (SPI0). 2.3.37 PM4 / RXCAN2 / RXCAN0 / RXCAN4/ MOSI0 -- Port M I/O Pin 4 PM4 is a general purpose input or output pin. It can be configured as the receive pin RXCAN of the Freescale Scalable Controller Area Network controllers 2, 0 or 4 (CAN2, CAN0 or CAN4). It can be configured as the master output (during master mode) or slave input pin (during slave mode) MOSI for the Serial Peripheral Interface 0 (SPI0). 2.3.38 PM3 / TXCAN1 / TXCAN0 / SS0 -- Port M I/O Pin 3 PM3 is a general purpose input or output pin. It can be configured as the transmit pin TXCAN of the Freescale Scalable Controller Area Network controllers 1 or 0 (CAN1 or CAN0). It can be configured as the slave select pin SS of the Serial Peripheral Interface 0 (SPI0). 2.3.39 PM2 / RXCAN1 / RXCAN0 / MISO0 -- Port M I/O Pin 2 PM2 is a general purpose input or output pin. It can be configured as the receive pin RXCAN of the Freescale Scalable Controller Area Network controllers 1 or 0 (CAN1 or CAN0). It can be configured as the master input (during master mode) or slave output pin (during slave mode) MISO for the Serial Peripheral Interface 0 (SPI0). 61 MC9S12DP512 Device Guide V01.25 2.3.40 PM1 / TXCAN0 / TXB -- Port M I/O Pin 1 PM1 is a general purpose input or output pin. It can be configured as the transmit pin TXCAN of the Freescale Scalable Controller Area Network controller 0 (CAN0). It can be configured as the transmit pin TXB of the BDLC. 2.3.41 PM0 / RXCAN0 / RXB -- Port M I/O Pin 0 PM0 is a general purpose input or output pin. It can be configured as the receive pin RXCAN of the Freescale Scalable Controller Area Network controller 0 (CAN0). It can be configured as the receive pin RXB of the BDLC. 2.3.42 PP7 / KWP7 / PWM7 / SCK2 -- Port P I/O Pin 7 PP7 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode. It can be configured as Pulse Width Modulator (PWM) channel 7 output or an input for the PWM emergency shutdown. It can be configured as serial clock pin SCK of the Serial Peripheral Interface 2 (SPI2). 2.3.43 PP6 / KWP6 / PWM6 / SS2 -- Port P I/O Pin 6 PP6 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode. It can be configured as Pulse Width Modulator (PWM) channel 6 output. It can be configured as slave select pin SS of the Serial Peripheral Interface 2 (SPI2). 2.3.44 PP5 / KWP5 / PWM5 / MOSI2 -- Port P I/O Pin 5 PP5 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode. It can be configured as Pulse Width Modulator (PWM) channel 5 output. It can be configured as master output (during master mode) or slave input pin (during slave mode) MOSI of the Serial Peripheral Interface 2 (SPI2). 2.3.45 PP4 / KWP4 / PWM4 / MISO2 -- Port P I/O Pin 4 PP4 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode. It can be configured as Pulse Width Modulator (PWM) channel 4 output. It can be configured as master input (during master mode) or slave output (during slave mode) pin MISO of the Serial Peripheral Interface 2 (SPI2). 2.3.46 PP3 / KWP3 / PWM3 / SS1 -- Port P I/O Pin 3 PP3 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode. It can be configured as Pulse Width Modulator (PWM) channel 3 output. It can be configured as slave select pin SS of the Serial Peripheral Interface 1 (SPI1). MC9S12DP512 Device Guide V01.25 2.3.47 PP2 / KWP2 / PWM2 / SCK1 -- Port P I/O Pin 2 PP2 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode. It can be configured as Pulse Width Modulator (PWM) channel 2 output. It can be configured as serial clock pin SCK of the Serial Peripheral Interface 1 (SPI1). 2.3.48 PP1 / KWP1 / PWM1 / MOSI1 -- Port P I/O Pin 1 PP1 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode. It can be configured as Pulse Width Modulator (PWM) channel 1 output. It can be configured as master output (during master mode) or slave input pin (during slave mode) MOSI of the Serial Peripheral Interface 1 (SPI1). 2.3.49 PP0 / KWP0 / PWM0 / MISO1 -- Port P I/O Pin 0 PP0 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode. It can be configured as Pulse Width Modulator (PWM) channel 0 output. It can be configured as master input (during master mode) or slave output (during slave mode) pin MISO of the Serial Peripheral Interface 1 (SPI1). 2.3.50 PS7 / SS0 -- Port S I/O Pin 7 PS6 is a general purpose input or output pin. It can be configured as the slave select pin SS of the Serial Peripheral Interface 0 (SPI0). 2.3.51 PS6 / SCK0 -- Port S I/O Pin 6 PS6 is a general purpose input or output pin. It can be configured as the serial clock pin SCK of the Serial Peripheral Interface 0 (SPI0). 2.3.52 PS5 / MOSI0 -- Port S I/O Pin 5 PS5 is a general purpose input or output pin. It can be configured as master output (during master mode) or slave input pin (during slave mode) MOSI of the Serial Peripheral Interface 0 (SPI0). 2.3.53 PS4 / MISO0 -- Port S I/O Pin 4 PS4 is a general purpose input or output pin. It can be configured as master input (during master mode) or slave output pin (during slave mode) MOSI of the Serial Peripheral Interface 0 (SPI0). 2.3.54 PS3 / TXD1 -- Port S I/O Pin 3 PS3 is a general purpose input or output pin. It can be configured as the transmit pin TXD of Serial Communication Interface 1 (SCI1). 63 MC9S12DP512 Device Guide V01.25 2.3.55 PS2 / RXD1 -- Port S I/O Pin 2 PS2 is a general purpose input or output pin. It can be configured as the receive pin RXD of Serial Communication Interface 1 (SCI1). 2.3.56 PS1 / TXD0 -- Port S I/O Pin 1 PS1 is a general purpose input or output pin. It can be configured as the transmit pin TXD of Serial Communication Interface 0 (SCI0). 2.3.57 PS0 / RXD0 -- Port S I/O Pin 0 PS0 is a general purpose input or output pin. It can be configured as the receive pin RXD of Serial Communication Interface 0 (SCI0). 2.3.58 PT[7:0] / IOC[7:0] -- Port T I/O Pins [7:0] PT7-PT0 are general purpose input or output pins. They can be configured as input capture or output compare pins IOC7-IOC0 of the Enhanced Capture Timer (ECT). 2.4 Power Supply Pins MC9S12DP512 power and ground pins are described below. Table 2-2 MC9S12DP512 Power and Ground Connection Summary Pin Number 112-pin QFP Nominal Voltage VDD1, 2 13, 65 2.5 V VSS1, 2 14, 66 0V VDDR 41 5.0 V VSSR 40 0V VDDX 107 5.0 V VSSX 106 0V VDDA 83 5.0 V VSSA 86 0V VRL 85 0V VRH 84 5.0 V VDDPLL 43 2.5 V VSSPLL 45 0V VREGEN 97 5V Mnemonic Description Internal power and ground generated by internal regulator External power and ground, supply to pin drivers and internal voltage regulator. External power and ground, supply to pin drivers. Operating voltage and ground for the analog-to-digital converters and the reference for the internal voltage regulator, allows the supply voltage to the A/D to be bypassed independently. Reference voltages for the analog-to-digital converter. Provides operating voltage and ground for the Phased-Locked Loop. This allows the supply voltage to the PLL to be bypassed independently. Internal power and ground generated by internal regulator. Internal Voltage Regulator enable/disable MC9S12DP512 Device Guide V01.25 NOTE: All VSS pins must be connected together in the application. 2.4.1 VDDX,VSSX -- Power & Ground Pins for I/O Drivers External power and ground for I/O drivers. Because fast signal transitions place high, short-duration current demands on the power supply, use bypass capacitors with high-frequency characteristics and place them as close to the MCU as possible. Bypass requirements depend on how heavily the MCU pins are loaded. 2.4.2 VDDR, VSSR -- Power & Ground Pins for I/O Drivers & Internal Voltage Regulator External power and ground for I/O drivers and input to the internal voltage regulator. Because fast signal transitions place high, short-duration current demands on the power supply, use bypass capacitors with high-frequency characteristics and place them as close to the MCU as possible. Bypass requirements depend on how heavily the MCU pins are loaded. 2.4.3 VDD1, VDD2, VSS1, VSS2 -- Internal Logic Power Supply Pins Power is supplied to the MCU through VDD and VSS. Because fast signal transitions place high, short-duration current demands on the power supply, use bypass capacitors with high-frequency characteristics and place them as close to the MCU as possible. This 2.5V supply is derived from the internal voltage regulator. There is no static load on those pins allowed. The internal voltage regulator is turned off, if VREGEN is tied to ground. NOTE: No load allowed except for bypass capacitors. 2.4.4 VDDA, VSSA -- Power Supply Pins for ATD and VREG VDDA, VSSA are the power supply and ground input pins for the voltage regulator and the analog to digital converter. It also provides the reference for the internal voltage regulator. This allows the supply voltage to the ATD and the reference voltage to be bypassed independently. 2.4.5 VRH, VRL -- ATD Reference Voltage Input Pins VRH and VRL are the reference voltage input pins for the analog to digital converter. 2.4.6 VDDPLL, VSSPLL -- Power Supply Pins for PLL Provides operating voltage and ground for the Oscillator and the Phased-Locked Loop. This allows the supply voltage to the Oscillator and PLL to be bypassed independently. This 2.5V voltage is generated by the internal voltage regulator. NOTE: No load allowed except for bypass capacitors. 65 MC9S12DP512 Device Guide V01.25 2.4.7 VREGEN -- On Chip Voltage Regulator Enable Enables the internal 5V to 2.5V voltage regulator. If this pin is tied low, VDD1,2 and VDDPLL must be supplied externally. MC9S12DP512 Device Guide V01.25 Section 3 System Clock Description 3.1 Overview The Clock and Reset Generator provides the internal clock signals for the core and all peripheral modules. Figure 3-1 shows the clock connections from the CRG to all modules. Consult the CRG Block Guide and OSC Block Guide for details on clock generation. Core Clock HCS12 CORE MEBI CPU INT MMC BDM BKP Flash RAM EEPROM ECT EXTAL ATD0, 1 OSC CRG Bus Clock PWM SCI0, SCI1 Oscillator Clock SPI0, 1, 2 XTAL CAN0, 1, 2, 3, 4 IIC BDLC PIM Figure 3-1 Clock Connections 67 MC9S12DP512 Device Guide V01.25 MC9S12DP512 Device Guide V01.25 Section 4 Modes of Operation 4.1 Overview Eight possible modes determine the operating configuration of the MC9S12DP512. Each mode has an associated default memory map and external bus configuration controlled by a further pin. Three low power modes exist for the device (Section 4.4 Low Power Modes). 4.2 Chip Configuration Summary The operating mode out of reset is determined by the states of the MODC, MODB, and MODA pins during reset (Table 4-1). The MODC, MODB, and MODA bits in the MODE register show the current operating mode and provide limited mode switching during operation. The states of the MODC, MODB, and MODA pins are latched into these bits on the rising edge of the reset signal. The ROMCTL signal allows the setting of the ROMON bit in the MISC register thus controlling whether the internal Flash is visible in the memory map. ROMON = 1 means the Flash is visible in the memory map. The state of the ROMCTL pin is latched into the ROMON bit in the MISC register on the rising edge of the reset signal. Table 4-1 Mode Selection BKGD = MODC PE6 = MODB PE5 = MODA PK7 = ROMCTL ROMON Bit 0 0 0 X 1 0 0 1 0 1 1 0 0 1 0 X 0 0 1 1 0 X 1 0 0 1 1 X 1 0 0 1 1 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 Mode Description Special Single Chip, BDM allowed and ACTIVE. BDM is allowed in all other modes but a serial command is required to make BDM active. Emulation Expanded Narrow, BDM allowed Special Test (Expanded Wide), BDM allowed Emulation Expanded Wide, BDM allowed Normal Single Chip, BDM allowed Normal Expanded Narrow, BDM allowed Peripheral; BDM allowed but bus operations would cause bus conflicts (must not be used) Normal Expanded Wide, BDM allowed For further explanation on the modes refer to the HCS12 Multiplexed External Bus Interface (MEBI) Block Guide. 69 MC9S12DP512 Device Guide V01.25 Table 4-2 Clock Selection Based on PE7 PE7 = XCLKS Description 1 Colpitts Oscillator selected 0 Pierce Oscillator/external clock selected Table 4-3 Voltage Regulator VREGEN VREGEN Description 1 Internal Voltage Regulator enabled 0 Internal Voltage Regulator disabled, VDD1,2 and VDDPLL must be supplied externally with 2.5V 4.3 Security The device will make available a security feature preventing the unauthorized read and write of the memory contents. This feature allows: * Protection of the contents of FLASH, * Protection of the contents of EEPROM, * Operation in single-chip mode, * Operation from external memory with internal FLASH and EEPROM disabled. The user must be reminded that part of the security must lie with the user's code. An extreme example would be user's code that dumps the contents of the internal program. This code would defeat the purpose of security. At the same time the user may also wish to put a back door in the user's program. An example of this is the user downloads a key through the SCI which allows access to a programming routine that updates parameters stored in EEPROM. 4.3.1 Securing the Microcontroller Once the user has programmed the FLASH and EEPROM (if desired), the part can be secured by programming the security bits located in the FLASH module. These non-volatile bits will keep the part secured through resetting the part and through powering down the part. The security byte resides in a portion of the Flash array. Check the Flash Block Guide for more details on the security configuration. 4.3.2 Operation of the Secured Microcontroller 4.3.2.1 Normal Single Chip Mode This will be the most common usage of the secured part. Everything will appear the same as if the part was not secured with the exception of BDM operation. The BDM operation will be blocked. MC9S12DP512 Device Guide V01.25 4.3.2.2 Executing from External Memory The user may wish to execute from external space with a secured microcontroller. This is accomplished by resetting directly into expanded mode. The internal FLASH and EEPROM will be disabled. BDM operations will be blocked. 4.3.3 Unsecuring the Microcontroller In order to unsecure the microcontroller, the internal FLASH and EEPROM must be erased. This can be done through an external program in expanded mode or via a sequence of BDM commands. Unsecuring is also possible via the Backdoor Key Access. Refer to Flash Block Guide for details.. Once the user has erased the FLASH and EEPROM, the part can be reset into special single chip mode. This invokes a program that verifies the erasure of the internal FLASH and EEPROM. Once this program completes, the user can erase and program the FLASH security bits to the unsecured state. This is generally done through the BDM, but the user could also change to expanded mode (by writing the mode bits through the BDM) and jumping to an external program (again through BDM commands). Note that if the part goes through a reset before the security bits are reprogrammed to the unsecure state, the part will be secured again. 4.4 Low Power Modes The microcontroller features three main low power modes. Consult the respective Block Guide for information on the module behavior in Stop, Pseudo Stop, and Wait Mode. An important source of information about the clock system is the Clock and Reset Generator Block Guide (CRG). 4.4.1 Stop Executing the CPU STOP instruction stops all clocks and the oscillator thus putting the chip in fully static mode. Wake up from this mode can be done via reset or external interrupts. 4.4.2 Pseudo Stop This mode is entered by executing the CPU STOP instruction. In this mode the oscillator is still running and the Real Time Interrupt (RTI) or Watchdog (COP) sub module can stay active. Other peripherals are turned off. This mode consumes more current than the full STOP mode, but the wake up time from this mode is significantly shorter. 4.4.3 Wait This mode is entered by executing the CPU WAI instruction. In this mode the CPU will not execute instructions. The internal CPU signals (address and databus) will be fully static. All peripherals stay active. For further power consumption the peripherals can individually turn off their local clocks. 71 MC9S12DP512 Device Guide V01.25 4.4.4 Run Although this is not a low power mode, unused peripheral modules should not be enabled in order to save power. MC9S12DP512 Device Guide V01.25 Section 5 Resets and Interrupts 5.1 Overview Consult the Exception Processing section of the CPU12 Reference Manual for information on resets and interrupts. 5.2 Vectors 5.2.1 Vector Table Table 5-1 lists interrupt sources and vectors in default order of priority. Table 5-1 Interrupt Vector Locations Interrupt Source CCR Mask Local Enable HPRIO Value to Elevate $FFFE, $FFFF Reset None None - $FFFC, $FFFD Clock Monitor fail reset None PLLCTL (CME, SCME) - $FFFA, $FFFB COP failure reset None COP rate select - $FFF8, $FFF9 Unimplemented instruction trap None None - $FFF6, $FFF7 SWI None None - $FFF4, $FFF5 XIRQ X-Bit None - $FFF2, $FFF3 IRQ I-Bit IRQCR (IRQEN) $F2 $FFF0, $FFF1 Real Time Interrupt I-Bit CRGINT (RTIE) $F0 $FFEE, $FFEF Enhanced Capture Timer channel 0 I-Bit TIE (C0I) $EE Vector Address $FFEC, $FFED Enhanced Capture Timer channel 1 I-Bit TIE (C1I) $EC $FFEA, $FFEB Enhanced Capture Timer channel 2 I-Bit TIE (C2I) $EA $FFE8, $FFE9 Enhanced Capture Timer channel 3 I-Bit TIE (C3I) $E8 $FFE6, $FFE7 Enhanced Capture Timer channel 4 I-Bit TIE (C4I) $E6 $FFE4, $FFE5 Enhanced Capture Timer channel 5 I-Bit TIE (C5I) $E4 $FFE2, $FFE3 Enhanced Capture Timer channel 6 I-Bit TIE (C6I) $E2 $FFE0, $FFE1 Enhanced Capture Timer channel 7 I-Bit TIE (C7I) $E0 $FFDE, $FFDF Enhanced Capture Timer overflow I-Bit TSRC2 (TOI) $DE $FFDC, $FFDD Pulse accumulator A overflow I-Bit PACTL (PAOVI) $DC $FFDA, $FFDB Pulse accumulator input edge I-Bit PACTL (PAI) $DA $FFD8, $FFD9 SPI0 I-Bit SPICR1 (SPIE, SPTIE) $D8 $D6 $FFD6, $FFD7 SCI0 I-Bit SCICR2 (TIE, TCIE, RIE, ILIE) $FFD4, $FFD5 SCI1 I-Bit SCICR2 (TIE, TCIE, RIE, ILIE) $D4 $FFD2, $FFD3 ATD0 I-Bit ATDCTL2 (ASCIE) $D2 $FFD0, $FFD1 ATD1 I-Bit ATDCTL2 (ASCIE) $D0 $FFCE, $FFCF Port J I-Bit PIEJ (PIEJ7, PIEJ6, PIEJ1, PIEJ0) $CE $FFCC, $FFCD Port H I-Bit PIEH (PIEH7-0) $CC 73 MC9S12DP512 Device Guide V01.25 $FFCA, $FFCB Modulus Down Counter underflow I-Bit MCCTL (MCZI) $CA $FFC8, $FFC9 Pulse Accumulator B Overflow $FFC6, $FFC7 CRG PLL lock I-Bit PBCTL (PBOVI) $C8 I-Bit CRGINT (LOCKIE) $C6 $FFC4, $FFC5 $FFC2, $FFC3 CRG Self Clock Mode I-Bit CRGINT (SCMIE) $C4 BDLC I-Bit DLCBCR1 (IE) $C2 $FFC0, $FFC1 IIC Bus I-Bit IBCR (IBIE) $C0 $FFBE, $FFBF SPI1 I-Bit SPICR1 (SPIE, SPTIE) $BE $FFBC, $FFBD SPI2 I-Bit SPICR1 (SPIE, SPTIE) $BC $FFBA, $FFBB EEPROM I-Bit ECNFG (CCIE, CBEIE) $BA $FFB8, $FFB9 FLASH I-Bit FCNFG (CCIE, CBEIE) $B8 $FFB6, $FFB7 CAN0 wake-up I-Bit CANRIER (WUPIE) $B6 $FFB4, $FFB5 CAN0 errors I-Bit CANRIER (CSCIE, OVRIE) $B4 $FFB2, $FFB3 CAN0 receive I-Bit CANRIER (RXFIE) $B2 $FFB0, $FFB1 CAN0 transmit I-Bit CANTIER (TXEIE2-TXEIE0) $B0 $FFAE, $FFAF CAN1 wake-up I-Bit CANRIER (WUPIE) $AE $FFAC, $FFAD CAN1 errors I-Bit CANRIER (CSCIE, OVRIE) $AC $FFAA, $FFAB CAN1 receive I-Bit CANRIER (RXFIE) $AA $FFA8, $FFA9 CAN1 transmit I-Bit CANTIER (TXEIE2-TXEIE0) $A8 $FFA6, $FFA7 CAN2 wake-up I-Bit CANRIER (WUPIE) $A6 $FFA4, $FFA5 CAN2 errors I-Bit CANRIER (CSCIE, OVRIE) $A4 $FFA2, $FFA3 CAN2 receive I-Bit CANRIER (RXFIE) $A2 $FFA0, $FFA1 CAN2 transmit I-Bit CANTIER (TXEIE2-TXEIE0) $A0 $FF9E, $FF9F CAN3 wake-up I-Bit CANRIER (WUPIE) $9E $FF9C, $FF9D CAN3 errors I-Bit CANRIER (CSCIE, OVRIE) $9C $FF9A, $FF9B CAN3 receive I-Bit CANRIER (RXFIE) $9A $FF98, $FF99 CAN3 transmit I-Bit CANTIER (TXEIE2-TXEIE0) $98 $FF96, $FF97 CAN4 wake-up I-Bit CANRIER (WUPIE) $96 $FF94, $FF95 CAN4 errors I-Bit CANRIER (CSCIE, OVRIE) $94 $FF92, $FF93 CAN4 receive I-Bit CANRIER (RXFIE) $92 $FF90, $FF91 CAN4 transmit I-Bit CANTIER (TXEIE2-TXEIE0) $90 $FF8E, $FF8F Port P Interrupt I-Bit PIEP (PIEP7-0) $8E $FF8C, $FF8D PWM Emergency Shutdown I-Bit PWMSDN (PWMIE) $8C $FF80 to $FF8B Reserved 5.3 Effects of Reset When a reset occurs, MCU registers and control bits are changed to known start-up states. Refer to the respective module Block Guides for register reset states. 5.3.1 I/O pins Refer to the HCS12 Multiplexed External Bus Interface (MEBI) Block Guide for mode dependent pin configuration of port A, B, E and K out of reset. Refer to the PIM Block Guide for reset configurations of all peripheral module ports. MC9S12DP512 Device Guide V01.25 5.3.2 Memory Refer to Table 1-1 for locations of the memories depending on the operating mode after reset. The RAM array is not automatically initialized out of reset. 75 MC9S12DP512 Device Guide V01.25 MC9S12DP512 Device Guide V01.25 Section 6 HCS12 Core Block Description 6.1 CPU12 Block Description Consult the HCS12 CPU Reference Manual for information on the CPU. 6.1.1 Device-specific information When the HCS12 CPU Reference Manual refers to cycles this is equivalent to Bus Clock periods. So 1 cycle is equivalent to 1 Bus Clock period. 6.2 HCS12 Module Mapping Control (MMC) Block Description Consult the MMC Block Guide for information on the HCS12 Module Mapping Control module. 6.2.1 Device-specific information * * INITEE - Reset state: $01 - Bits EE11-EE15 are "Write once in Normal and Emulation modes and write anytime in Special modes". PPAGE - Reset state: $00 - Register is "Write anytime in all modes" 6.3 HCS12 Multiplexed External Bus Interface (MEBI) Block Description Consult the MEBI Block Guide for information on HCS12 Multiplexed External Bus Interface module. 6.3.1 Device-specific information * PUCR - Reset state: $90 6.4 HCS12 Interrupt (INT) Block Description Consult the INT Block Guide for information on the HCS12 Interrupt module. 77 MC9S12DP512 Device Guide V01.25 6.5 HCS12 Background Debug (BDM) Block Description Consult the BDM Block Guide for information on the HCS12 Background Debug module. 6.5.1 Device-specific information When the BDM Block Guide refers to alternate clock this is equivalent to Oscillator Clock. 6.6 HCS12 Breakpoint (BKP) Block Description Consult the BKP Block Guide for information on the HCS12 Breakpoint module. Section 7 Clock and Reset Generator (CRG) Block Description Consult the CRG Block Guide for information about the Clock and Reset Generator module. 7.1 Device-specific information The Low Voltage Reset feature of the CRG is not available on this device. Section 8 Oscillator (OSC) Block Description 8.1 Device-specific information The XCLKS input signal is active low (see 2.3.13 PE7 / NOACC / XCLKS -- Port E I/O Pin 7). Section 9 Enhanced Capture Timer (ECT) Block Description Consult the ECT_16B8C Block Guide for information about the Enhanced Capture Timer module. When the ECT_16B8C Block Guide refers to freeze mode this is equivalent to active BDM mode. Section 10 Analog to Digital Converter (ATD) Block Description MC9S12DP512 Device Guide V01.25 There are two Analog to Digital Converters (ATD1 and ATD0) implemented on the MC9S12DP512. Consult the ATD_10B8C Block Guide for information about each Analog to Digital Converter module. When the ATD_10B8C Block Guide refers to freeze mode this is equivalent to active BDM mode. Section 11 Inter-IC Bus (IIC) Block Description Consult the IIC Block Guide for information about the Inter-IC Bus module. Section 12 Serial Communications Interface (SCI) Block Description There are two Serial Communications Interfaces (SCI1 and SCI0) implemented on the MC9S12DP512 device. Consult the SCI Block Guide for information about each Serial Communications Interface module. Section 13 Serial Peripheral Interface (SPI) Block Description There are three Serial Peripheral Interfaces (SPI2, SPI1 and SPI0) implemented on MC9S12DP512. Consult the SPI Block Guide for information about each Serial Peripheral Interface module. Section 14 J1850 (BDLC) Block Description Consult the BDLC Block Guide for information about the J1850 module. Section 15 Pulse Width Modulator (PWM) Block Description Consult the PWM_8B6C Block Guide for information about the Pulse Width Modulator module. When the PWM_8B8C Block Guide refers to freeze mode this is equivalent to active BDM mode. Section 16 Flash EEPROM 512K Block Description Consult the FTS512K4 Block Guide for information about the flash module. 79 MC9S12DP512 Device Guide V01.25 The "S12 LRAE" is a generic Load RAM and Execute (LRAE) program which will be programmed into the flash memory of this device during manufacture. This LRAE program will provide greater programming flexibility to the end users by allowing the device to be programmed directly using CAN or SCI after it is assembled on the PCB. Use of the LRAE program is at the discretion of the end user and, if not required, it must simply be erased prior to flash programming. For more details of the S12 LRAE and its implementation, please see the S12 LREA Application Note (AN2546/D). It is planned that most HC9S12 devices manufactured after Q1 of 2004 will be shipped with the S12 LRAE programmed in the Flash. Exact details of the changeover (i.e. blank to programmed) for each product will be communicated in advance via GPCN and will be traceable by the customer via datecode marking on the device. Please contact Freescale Sales if you have any additional questions. Section 17 EEPROM 4K Block Description Consult the EETS4K Block Guide for information about the EEPROM module. Section 18 RAM Block Description This module supports single-cycle misaligned word accesses. Section 19 MSCAN Block Description There are five MSCAN modules (CAN4, CAN3, CAN2, CAN1 and CAN0) implemented on the MC9S12DP512. Consult the MSCAN Block Guide for information about the Freescale Scalable CAN Module. Section 20 Port Integration Module (PIM) Block Description Consult the functionally equivalent PIM_9DP256 Block Guide for information about the Port Integration Module. Section 21 Voltage Regulator (VREG) Block Description Consult the VREG Block Guide for information about the dual output linear voltage regulator. MC9S12DP512 Device Guide V01.25 Section 22 Printed Circuit Board Layout Proposal Table 22-1 Suggested External Component Values Component Purpose Type Value C1 VDD1 filter cap ceramic X7R 100 ... 220nF C2 VDD2 filter cap ceramic X7R 100 ... 220nF C3 VDDA filter cap ceramic X7R 100nF C4 VDDR filter cap X7R/tantalum >= 100nF C5 VDDPLL filter cap ceramic X7R 100nF C6 VDDX filter cap X7R/tantalum >= 100nF C7 OSC load cap C8 OSC load cap C9 / CS PLL loop filter cap C10 / CP PLL loop filter cap C11 / CDC DC cutoff cap Colpitts mode only, if recommended by quartz manufacturer R1 / R PLL loop filter res See PLL Specification chapter See PLL specification chapter R2 / RB Pierce mode only R3 / RS Q1 Quartz The PCB must be carefully laid out to ensure proper operation of the voltage regulator as well as of the MCU itself. The following rules must be observed: * Every supply pair must be decoupled by a ceramic capacitor connected as near as possible to the corresponding pins (C1 - C6). * Central point of the ground star should be the VSSR pin. * Use low ohmic low inductance connections between VSS1, VSS2 and VSSR. * VSSPLL must be directly connected to VSSR. * Keep traces of VSSPLL, EXTAL and XTAL as short as possible and occupied board area for C7, C8, C11 and Q1 as small as possible. * Do not place other signals or supplies underneath area occupied by C7, C8, C10 and Q1 and the connection area to the MCU. * Central power input should be fed in at the VDDA/VSSA pins. 81 MC9S12DP512 Device Guide V01.25 Figure 22-1 Recommended PCB Layout for 112LQFP Colpitts Oscillator VREGEN C6 VDDX VSSX VSSA C3 VDDA VDD1 C1 VSS1 VSS2 C2 VDD2 VSSR C4 C7 C8 C10 C9 R1 C11 C5 VDDR Q1 VSSPLL VDDPLL MC9S12DP512 Device Guide V01.25 Figure 22-2 Recommended PCB Layout for 112LQFP Pierce Oscillator VREGEN C6 VDDX VSSX VSSA C3 VDDA VDD1 C1 VSS1 VSS2 C2 VDD2 VSSR VSSPLL C4 R3 C5 VDDR R2 Q1 C7 C8 C10 C9 VDDPLL R1 83 MC9S12DP512 Device Guide V01.25 MC9S12DP512 Device Guide V01.25 Appendix A Electrical Characteristics A.1 General NOTE: The electrical characteristics given in this section are preliminary and should be used as a guide only. Values cannot be guaranteed by Freescale and are subject to change without notice. This supplement contains the most accurate electrical information for the MC9S12DP512 microcontroller available at the time of publication. The information should be considered PRELIMINARY and is subject to change. This introduction is intended to give an overview on several common topics like power supply, current injection etc. A.1.1 Parameter Classification The electrical parameters shown in this supplement are guaranteed by various methods. To give the customer a better understanding the following classification is used and the parameters are tagged accordingly in the tables where appropriate. NOTE: This classification is shown in the column labeled "C" in the parameter tables where appropriate. P: Those parameters are guaranteed during production testing on each individual device. C: Those parameters are achieved by the design characterization by measuring a statistically relevant sample size across process variations. T: Those parameters are achieved by design characterization on a small sample size from typical devices under typical conditions unless otherwise noted. All values shown in the typical column are within this category. D: Those parameters are derived mainly from simulations. A.1.2 Power Supply The MC9S12DP512 utilizes several pins to supply power to the I/O ports, A/D converter, oscillator, PLL and internal logic. The VDDA, VSSA pair supplies the A/D converter and the resistor ladder of the internal voltage regulator. 85 MC9S12DP512 Device Guide V01.25 The VDDX, VSSX, VDDR and VSSR pairs supply the I/O pins, VDDR supplies also the internal voltage regulator. VDD1, VSS1, VDD2 and VSS2 are the supply pins for the digital logic, VDDPLL, VSSPLL supply the oscillator and the PLL. VSS1 and VSS2 are internally connected by metal. VDDA, VDDX, VDDR as well as VSSA, VSSX, VSSR are connected by anti-parallel diodes for ESD protection. NOTE: In the following context VDD5 is used for either VDDA, VDDR and VDDX; VSS5 is used for either VSSA, VSSR and VSSX unless otherwise noted. IDD5 denotes the sum of the currents flowing into the VDDA, VDDX and VDDR pins. VDD is used for VDD1, VDD2 and VDDPLL, VSS is used for VSS1, VSS2 and VSSPLL. IDD is used for the sum of the currents flowing into VDD1 and VDD2. A.1.3 Pins There are four groups of functional pins. A.1.3.1 5V I/O pins Those I/O pins have a nominal level of 5V. This class of pins is comprised of all port I/O pins, the analog inputs, BKGD and the RESET pins.The internal structure of all those pins is identical, however some of the functionality may be disabled. E.g. for the analog inputs the output drivers, pull-up and pull-down resistors are disabled permanently. A.1.3.2 Analog Reference This group is made up by the VRH and VRL pins. A.1.3.3 Oscillator The pins XFC, EXTAL, XTAL dedicated to the oscillator have a nominal 2.5V level. They are supplied by VDDPLL. A.1.3.4 TEST This pin is used for production testing only. A.1.3.5 VREGEN This pin is used to enable the on chip voltage regulator. MC9S12DP512 Device Guide V01.25 A.1.4 Current Injection Power supply must maintain regulation within operating VDD5 or VDD range during instantaneous and operating maximum current conditions. If positive injection current (Vin > VDD5) is greater than IDD5, the injection current may flow out of VDD5 and could result in external power supply going out of regulation. Ensure external VDD5 load will shunt current greater than maximum injection current. This will be the greatest risk when the MCU is not consuming power; e.g. if no system clock is present, or if clock rate is very low which would reduce overall power consumption. A.1.5 Absolute Maximum Ratings Absolute maximum ratings are stress ratings only. A functional operation under or outside those maxima is not guaranteed. Stress beyond those limits may affect the reliability or cause permanent damage of the device. This device contains circuitry protecting against damage due to high static voltage or electrical fields; however, it is advised that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (e.g., either VSS5 or VDD5). Table A-1 Absolute Maximum Ratings1 Num Rating Symbol Min Max Unit 1 I/O, Regulator and Analog Supply Voltage VDD5 -0.3 6.0 V 2 Digital Logic Supply Voltage 2 VDD -0.3 3.0 V 3 PLL Supply Voltage (2) VDDPLL -0.3 3.0 V 4 Voltage difference VDDX to VDDR and VDDA VDDX -0.3 0.3 V 5 Voltage difference VSSX to VSSR and VSSA VSSX -0.3 0.3 V 6 Digital I/O Input Voltage VIN -0.3 6.0 V 7 Analog Reference VRH, VRL -0.3 6.0 V 8 XFC, EXTAL, XTAL inputs VILV -0.3 3.0 V 9 TEST input VTEST -0.3 10.0 V 10 Instantaneous Maximum Current Single pin limit for all digital I/O pins 3 ID -25 +25 mA 11 Instantaneous Maximum Current Single pin limit for XFC, EXTAL, XTAL4 IDL -25 +25 mA 12 Instantaneous Maximum Current Single pin limit for TEST 5 IDT -0.25 0 mA 13 Storage Temperature Range T - 65 155 C stg NOTES: 1. Beyond absolute maximum ratings device might be damaged. 87 MC9S12DP512 Device Guide V01.25 2. The device contains an internal voltage regulator to generate the logic and PLL supply out of the I/O supply. The absolute maximum ratings apply when the device is powered from an external source. 3. All digital I/O pins are internally clamped to VSSX and VDDX, VSSR and VDDR or VSSA and VDDA. 4. Those pins are internally clamped to VSSPLL and VDDPLL. 5. This pin is clamped low to VSSX, but not clamped high. This pin must be tied low in applications. A.1.6 ESD Protection and Latch-up Immunity All ESD testing is in conformity with CDF-AEC-Q100 Stress test qualification for Automotive Grade Integrated Circuits. During the device qualification ESD stresses were performed for the Human Body Model (HBM), the Machine Model (MM) and the Charge Device Model. A device will be defined as a failure if after exposure to ESD pulses the device no longer meets the device specification. Complete DC parametric and functional testing is performed per the applicable device specification at room temperature followed by hot temperature, unless specified otherwise in the device specification. Table A-2 ESD and Latch-up Test Conditions Model Human Body Machine Description Symbol Value Unit Series Resistance R1 1500 Ohm Storage Capacitance C 100 pF Number of Pulse per pin positive negative - 3 3 Series Resistance R1 0 Ohm Storage Capacitance C 200 pF Number of Pulse per pin positive negative - 3 3 Minimum input voltage limit -2.5 V Maximum input voltage limit 7.5 V Latch-up Table A-3 ESD and Latch-up Protection Characteristics Num C Rating Symbol Min Max Unit 1 C Human Body Model (HBM) VHBM 2000 - V 2 C Machine Model (MM) VMM 200 - V 3 C Charge Device Model (CDM) VCDM 500 - V 4 Latch-up Current at TA = 125C C positive negative ILAT +100 -100 - mA 5 Latch-up Current at TA = 27C C positive negative ILAT +200 -200 - mA MC9S12DP512 Device Guide V01.25 A.1.7 Operating Conditions This chapter describes the operating conditions of the device. Unless otherwise noted those conditions apply to all the following data. NOTE: Please refer to the temperature rating of the device (C, V, M) with regards to the ambient temperature TA and the junction temperature TJ. For power dissipation calculations refer to Section A.1.8 Power Dissipation and Thermal Characteristics. Table A-4 Operating Conditions Rating Symbol Min Typ Max Unit I/O, Regulator and Analog Supply Voltage VDD5 4.5 5 5.25 V Digital Logic Supply Voltage 1 VDD 2.35 2.5 2.75 V PLL Supply Voltage (1) VDDPLL 2.35 2.5 2.75 V Voltage Difference VDDX to VDDR and VDDA VDDX -0.1 0 0.1 V Voltage Difference VSSX to VSSR and VSSA VSSX -0.1 0 0.1 V fbus 0.25 2 - 25 MHz Operating Junction Temperature Range T J -40 - 100 C Operating Ambient Temperature Range 3 T A -40 27 85 C Operating Junction Temperature Range TJ -40 - 120 C Operating Ambient Temperature Range (3) TA -40 27 105 C Operating Junction Temperature Range TJ -40 - 140 C Operating Ambient Temperature Range (3) TA -40 27 125 C Bus Frequency (MC9S12DP512C, V, M) MC9S12DP512C MC9S12DP512V MC9S12DP512M NOTES: 1. The device contains an internal voltage regulator to generate the logic and PLL supply out of the I/O supply. The given operating range applies when this regulator is disabled and the device is powered from an external source. 2. Some blocks e.g. ATD (conversion) and NVMs (program/erase) require higher bus frequencies for proper operation. 3. Please refer to Section A.1.8 Power Dissipation and Thermal Characteristics for more details about the relation between ambient temperature TA and device junction temperature TJ. A.1.8 Power Dissipation and Thermal Characteristics Power dissipation and thermal characteristics are closely related. The user must assure that the maximum operating junction temperature is not exceeded. The average chip-junction temperature (TJ) in C can be obtained from: 89 MC9S12DP512 Device Guide V01.25 T J = T A + ( P D * JA ) T J = Junction Temperature, [C ] T A = Ambient Temperature, [C ] P D = Total Chip Power Dissipation, [W] JA = Package Thermal Resistance, [C/W] The total power dissipation can be calculated from: P D = P INT + P IO P INT = Chip Internal Power Dissipation, [W] Two cases with internal voltage regulator enabled and disabled must be considered: 1. Internal Voltage Regulator disabled P INT = I DD V DD + I DDPLL V DDPLL + I DDA V DDA 2 P IO = R DSON I IO i i PIO is the sum of all output currents on I/O ports associated with VDDX and VDDR. For RDSON is valid: V OL R DSON = ------------ ;for outputs driven low I OL respectively V DD5 - V OH R DSON = ------------------------------------ ;for outputs driven high I OH 2. Internal voltage regulator enabled P INT = I DDR V DDR + I DDA V DDA IDDR is the current shown in Table A-7 and not the overall current flowing into VDDR, which additionally contains the current flowing into the external loads with output high. 2 P IO = R DSON I IO i i PIO is the sum of all output currents on I/O ports associated with VDDX and VDDR. MC9S12DP512 Device Guide V01.25 Table A-5 Thermal Package Characteristics1 Num C Rating Symbol Min Typ Max Unit 1 T Thermal Resistance LQFP112, single sided PCB2 JA - - 54 oC/W 2 T Thermal Resistance LQFP112, double sided PCB with 2 internal planes3 JA - - 41 o C/W NOTES: 1. The values for thermal resistance are achieved by package simulations 2. PC Board according to EIA/JEDEC Standard 51-2 3. PC Board according to EIA/JEDEC Standard 51-7 A.1.9 I/O Characteristics This section describes the characteristics of all 5V I/O pins. All parameters are not always applicable, e.g. not all pins feature pull up/down resistances. 91 MC9S12DP512 Device Guide V01.25 Table A-6 5V I/O Characteristics Conditions are shown in Table A-4 unless otherwise noted Num C 1 2 Rating Symbol Min Typ Max Unit 0.65*VDD5 - - V P Input High Voltage V T Input High Voltage VIH - - VDD5 + 0.3 V P Input Low Voltage V - - 0.35*VDD5 V T Input Low Voltage VIL VSS5 - 0.3 - - V - 250 - mV -1 - 1 A VDD5 - 0.8 - - V IH IL V 3 C Input Hysteresis 4 Input Leakage Current (pins in high impedance input P mode) V =V or VSS5 in DD5 5 Output High Voltage (pins in output mode) P Partial Drive IOH = -2mA Full Drive IOH = -10mA V 6 Output Low Voltage (pins in output mode) P Partial Drive IOL = +2mA Full Drive IOL = +10mA V OL - - 0.8 V 7 Internal Pull Up Device Current, P tested at V Max. IPUL - - -130 A Internal Pull Up Device Current, C tested at V Min. IPUH -10 - - A 9 Internal Pull Down Device Current, P tested at V Min. IH IPDH - - 130 A 10 Internal Pull Down Device Current, C tested at V Max. IPDL 10 - - A 11 D Input Capacitance Cin - 6 - pF 12 Injection current1 T Single Pin limit Total Device Limit. Sum of all injected currents IICS IICP -2.5 -25 - 2.5 25 mA 13 P Port H, J, P Interrupt Input Pulse filtered2 tPIGN - - 3 s 14 P Port H, J, P Interrupt Input Pulse passed(2) tPVAL 10 - - s IL 8 IH IL HYS Iin OH NOTES: 1. Refer to Section A.1.4 Current Injection, for more details 2. Parameter only applies in STOP or Pseudo STOP mode. A.1.10 Supply Currents This section describes the current consumption characteristics of the device as well as the conditions for the measurements. MC9S12DP512 Device Guide V01.25 A.1.10.1 Measurement Conditions All measurements are without output loads. Unless otherwise noted the currents are measured in single chip mode, internal voltage regulator enabled and at 25MHz bus frequency using a 4MHz oscillator in Colpitts mode. Production testing is performed using a square wave signal at the EXTAL input. A.1.10.2 Additional Remarks In expanded modes the currents flowing in the system are highly dependent on the load at the address, data and control signals as well as on the duty cycle of those signals. No generally applicable numbers can be given. A very good estimate is to take the single chip currents and add the currents due to the external loads. Table A-7 Supply Current Characteristics Conditions are shown in Table A-4 unless otherwise noted Num C Rating Symbol Run supply currents Single Chip, Internal regulator enabled IDD5 1 P 2 P P All modules enabled, PLL on only RTI enabled (1) C P C C P C P C P Pseudo Stop Current (RTI and COP disabled) 1, 2 -40C 27C 70C 85C "C" Temp Option 100C 105C "V" Temp Option 120C 125C "M" Temp Option 140C C C C C C C C Pseudo Stop Current (RTI and COP enabled) (1), (2) -40C 27C 70C 85C 105C 125C 140C Min Typ - - - - Max 65 Unit mA Wait Supply current 3 4 IDDW IDDPS IDDPS - - 370 400 450 550 600 650 800 850 1200 570 600 650 750 850 1200 1500 40 5 mA 500 1600 A 2100 5000 - A Stop Current (2) 5 C P C C P C P C P -40C 27C 70C 85C "C" Temp Option 100C 105C "V" Temp Option 120C 125C "M" Temp Option 140C IDDS - 12 25 100 130 160 200 350 400 600 100 1200 A 1700 5000 93 MC9S12DP512 Device Guide V01.25 NOTES: 1. PLL off 2. At those low power dissipation levels TJ = TA can be assumed MC9S12DP512 Device Guide V01.25 A.2 ATD Characteristics This section describes the characteristics of the analog to digital converter. A.2.1 ATD Operating Characteristics The Table A-8 shows conditions under which the ATD operates. The following constraints exist to obtain full-scale, full range results: VSSA VRL VIN VRH VDDA. This constraint exists since the sample buffer amplifier can not drive beyond the power supply levels that it ties to. If the input level goes outside of this range it will effectively be clipped. Table A-8 ATD Operating Characteristics Conditions are shown in Table A-4 unless otherwise noted Num C Rating Symbol Min Typ Max Unit VRL VRH VSSA VDDA/2 - VDDA/2 VDDA V V Reference Potential 1 D Low High 2 C Differential Reference Voltage1 VRH-VRL 4.50 5.00 5.25 V 3 D ATD Clock Frequency fATDCLK 0.5 - 2.0 MHz 4 D NCONV10 TCONV10 14 7 - 28 14 Cycles s 5 D NCONV8 TCONV8 12 6 - 26 13 Cycles s 6 D Recovery Time (VDDA=5.0 Volts) tREC - - 20 s 7 P Reference Supply current 2 ATD blocks on IREF - - 0.750 mA 8 P Reference Supply current 1 ATD block on IREF - - 0.375 mA ATD 10-Bit Conversion Period Clock Cycles2 Conv, Time at 2.0MHz ATD Clock fATDCLK ATD 8-Bit Conversion Period Clock Cycles(2) Conv, Time at 2.0MHz ATD Clock fATDCLK NOTES: 1. Full accuracy is not guaranteed when differential voltage is less than 4.50V 2. The minimum time assumes a final sample period of 2 ATD clocks cycles while the maximum time assumes a final sample period of 16 ATD clocks. A.2.2 Factors influencing accuracy Three factors - source resistance, source capacitance and current injection - have an influence on the accuracy of the ATD. A.2.2.1 Source Resistance Due to the input pin leakage current as specified in Table A-6 in conjunction with the source resistance there will be a voltage drop from the signal source to the ATD input. The maximum source resistance RS 95 MC9S12DP512 Device Guide V01.25 specifies results in an error of less than 1/2 LSB (2.5mV) at the maximum leakage current. If device or operating conditions are less than worst case or leakage-induced error is acceptable, larger values of source resistance is allowed. A.2.2.2 Source Capacitance When sampling an additional internal capacitor is switched to the input. This can cause a voltage drop due to charge sharing with the external and the pin capacitance. For a maximum sampling error of the input voltage 1LSB, then the external filter capacitor, Cf 1024 * (CINS- CINN). A.2.2.3 Current Injection There are two cases to consider. 1. A current is injected into the channel being converted. The channel being stressed has conversion values of $3FF ($FF in 8-bit mode) for analog inputs greater than VRH and $000 for values less than VRL unless the current is higher than specified as disruptive condition. 2. Current is injected into pins in the neighborhood of the channel being converted. A portion of this current is picked up by the channel (coupling ratio K), This additional current impacts the accuracy of the conversion depending on the source resistance. The additional input voltage error on the converted channel can be calculated as VERR = K * RS * IINJ, with IINJ being the sum of the currents injected into the two pins adjacent to the converted channel. Table A-9 ATD Electrical Characteristics Conditions are shown in Table A-4 unless otherwise noted Num C Rating Symbol Min Typ Max Unit RS - - 1 K CINN CINS - - 10 22 pF 1 C Max input Source Resistance 2 Total Input Capacitance T Non Sampling Sampling 3 C Disruptive Analog Input Current INA -2.5 - 2.5 mA 4 C Coupling Ratio positive current injection Kp - - 10-4 A/A 5 C Coupling Ratio negative current injection Kn - - 10-2 A/A MC9S12DP512 Device Guide V01.25 A.2.3 ATD accuracy Table A-10 specifies the ATD conversion performance excluding any errors due to current injection, input capacitance and source resistance. Table A-10 ATD Conversion Performance Conditions are shown in Table A-4 unless otherwise noted VREF = VRH - VRL = 5.12V. Resulting to one 8 bit count = 20mV and one 10 bit count = 5mV fATDCLK = 2.0MHz Num C Rating Symbol Min Typ Max Unit 1 P 10-Bit Resolution LSB - 5 - mV 2 P 10-Bit Differential Nonlinearity DNL -1 - 1 Counts 3 P 10-Bit Integral Nonlinearity INL -2.5 1.5 2.5 Counts 4 P 10-Bit Absolute Error1 AE -3 2.0 3 Counts 5 P 8-Bit Resolution LSB - 20 - mV 6 P 8-Bit Differential Nonlinearity DNL -0.5 - 0.5 Counts 7 P 8-Bit Integral Nonlinearity INL -1.0 0.5 1.0 Counts 8 P 8-Bit Absolute Error(1) AE -1.5 1.0 1.5 Counts NOTES: 1. These values include the quantization error which is inherently 1/2 count for any A/D converter. For the following definitions see also Figure A-1. Differential Non-Linearity (DNL) is defined as the difference between two adjacent switching steps. Vi - Vi - 1 DNL ( i ) = ------------------------ - 1 1LSB The Integral Non-Linearity (INL) is defined as the sum of all DNLs: n INL ( n ) = i=1 Vn - V0 DNL ( i ) = -------------------- - n 1LSB 97 MC9S12DP512 Device Guide V01.25 DNL 10-Bit Absolute Error Boundary LSB Vi-1 Vi $3FF 8-Bit Absolute Error Boundary $3FE $3FD $3FC $FF $3FB $3FA $3F9 $3F8 $FE $3F7 $3F6 $3F4 8-Bit Resolution 10-Bit Resolution $3F5 $FD $3F3 9 Ideal Transfer Curve 8 2 7 10-Bit Transfer Curve 6 5 4 1 3 8-Bit Transfer Curve 2 1 0 5 10 15 20 25 30 35 40 45 5055 5060 5065 5070 5075 5080 5085 5090 5095 5100 5105 5110 5115 5120 Vin mV Figure A-1 ATD Accuracy Definitions NOTE: Figure A-1 shows only definitions, for specification values refer to Table A-10. MC9S12DP512 Device Guide V01.25 A.3 NVM, Flash and EEPROM NOTE: Unless otherwise noted the abbreviation NVM (Non Volatile Memory) is used for both Flash and EEPROM. A.3.1 NVM timing The time base for all NVM program or erase operations is derived from the oscillator. A minimum oscillator frequency fNVMOSC is required for performing program or erase operations. The NVM modules do not have any means to monitor the frequency and will not prevent program or erase operation at frequencies above or below the specified minimum. Attempting to program or erase the NVM modules at a lower frequency a full program or erase transition is not assured. The Flash and EEPROM program and erase operations are timed using a clock derived from the oscillator using the FCLKDIV and ECLKDIV registers respectively. The frequency of this clock must be set within the limits specified as fNVMOP. The minimum program and erase times shown in Table A-11 are calculated for maximum fNVMOP and maximum fbus. The maximum times are calculated for minimum fNVMOP and a fbus of 2MHz. A.3.1.1 Single Word Programming The programming time for single word programming is dependant on the bus frequency as a well as on the frequency fNVMOP and can be calculated according to the following formula. 1 1 t swpgm = 9 --------------------- + 25 ---------f NVMOP f bus A.3.1.2 Row Programming This applies only to the Flash where up to 64 words in a row can be programmed consecutively by keeping the command pipeline filled. The time to program a consecutive word can be calculated as: 1 1 t bwpgm = 4 --------------------- + 9 ---------f NVMOP f bus The time to program a whole row is: t brpgm = t swpgm + 63 t bwpgm Row programming is more than 2 times faster than single word programming. A.3.1.3 Sector Erase Erasing a 1024 byte Flash sector or a 4 byte EEPROM sector takes: 1 t era 4000 --------------------f NVMOP 99 MC9S12DP512 Device Guide V01.25 The setup time can be ignored for this operation. A.3.1.4 Mass Erase Erasing a NVM block takes: 1 t mass 20000 --------------------f NVMOP The setup time can be ignored for this operation. A.3.1.5 Blank Check The time it takes to perform a blank check on the Flash or EEPROM is dependant on the location of the first non-blank word starting at relative address zero. It takes one bus cycle per word to verify plus a setup of the command. t check location t cyc + 10 t cyc Table A-11 NVM Timing Characteristics Conditions are shown in Table A-4 unless otherwise noted Num C Rating Symbol Min Typ Max Unit 1 D External Oscillator Clock fNVMOSC 0.5 - 50 1 MHz 2 D Bus frequency for Programming or Erase Operations fNVMBUS 1 - - MHz 3 D Operating Frequency fNVMOP 150 - 200 kHz 4 P Single Word Programming Time tswpgm 46 2 - 74.5 3 s 5 D Flash Row Programming consecutive word 4 tbwpgm 20.4 (2) - 31 (3) s 6 D Flash Row Programming Time for 64 Words (4) tbrpgm 1331.2 (2) - 2027.5 (3) s 7 P Sector Erase Time tera 20 5 - 26.7 (3) ms 8 P Mass Erase Time tmass 100 (5) - 133 (3) ms 9 D Blank Check Time Flash per block tcheck 11 6 - 65546 7 tcyc 10 D Blank Check Time EEPROM per block tcheck 11 (6) - 2058 (7) tcyc NOTES: 1. Restrictions for oscillator in crystal mode apply! 2. Minimum Programming times are achieved under maximum NVM operating frequency fNVMOP and maximum bus frequency fbus. 3. Maximum Erase and Programming times are achieved under particular combinations of fNVMOP and bus frequency fbus. Refer to formulae in Sections Section A.3.1.1 Single Word Programming- Section A.3.1.4 Mass Erasefor guidance. 4. Row Programming operations are not applicable to EEPROM 5. Minimum Erase times are achieved under maximum NVM operating frequency fNVMOP. 6. Minimum time, if first word in the array is not blank 7. Maximum time to complete check on an erased block MC9S12DP512 Device Guide V01.25 A.3.2 NVM Reliability The reliability of the NVM blocks is guaranteed by stress test during qualification, constant process monitors and burn-in to screen early life failures. The program/erase cycle count on the sector is incremented every time a sector or mass erase event is executed Table A-12 NVM Reliability Characteristics1 Conditions are shown in Table A-4 unless otherwise noted Num C Rating Symbol Min Typ Max 15 1002 -- Unit Flash Reliability Characteristics Data retention after 10,000 program/erase cycles at an average junction temperature of TJavg 85C 1 C 2 Data retention with <100 program/erase cycles at an C average junction temperature TJavg 85C 3 C 4 Number of program/erase cycles C (0C TJ 140C) Number of program/erase cycles (-40C TJ 0C) tFLRET Years 20 1002 -- 10,000 -- -- 10,000 100,0003 -- 1002 -- nFL Cycles EEPROM Reliability Characteristics 5 Data retention after up to 100,000 program/erase C cycles at an average junction temperature of TJavg 85C 6 Data retention with <100 program/erase cycles at an C average junction temperature TJavg 85C 7 C 8 Number of program/erase cycles C (0C < TJ 140C) Number of program/erase cycles (-40C TJ 0C) 15 tEEPRET Years 20 1002 -- 10,000 -- -- 100,000 300,0003 nEEP Cycles -- NOTES: 1. TJavg will not exeed 85C considering a typical temperature profile over the lifetime of a consumer, industrial or automotive application. 2. Typical data retention values are based on intrinsic capability of the technology measured at high temperature and de-rated to 25C using the Arrhenius equation. For additional information on how Freescale defines Typical Data Retention, please refer to Engineering Bulletin EB618. 3. Spec table quotes typical endurance evaluated at 25C for this product family, typical endurance at various temperature can be estimated using the graph below. For additional information on how Freescale defines Typical Endurance, please refer to Engineering Bulletin EB619. 101 MC9S12DP512 Device Guide V01.25 Figure A-2 Typical Endurance vs Temperature 500 Typical Endurance [103 Cycles] 450 400 350 300 250 200 150 100 50 0 -40 -20 0 20 40 60 80 Operating Temperature TJ [C] ------ Flash ------ EEPROM 100 120 140 MC9S12DP512 Device Guide V01.25 A.4 Voltage Regulator The on-chip voltage regulator is intended to supply the internal logic and oscillator circuits. No external DC load is allowed. Table A-13 Voltage Regulator Recommended Load Capacitances Rating Symbol Min Typ Max Unit Load Capacitance on VDD1, 2 CLVDD - 220 - nF Load Capacitance on VDDPLL CLVDDfcPLL - 220 - nF 103 MC9S12DP512 Device Guide V01.25 MC9S12DP512 Device Guide V01.25 A.5 Reset, Oscillator and PLL This section summarizes the electrical characteristics of the various startup scenarios for Oscillator and Phase-Locked-Loop (PLL). A.5.1 Startup Table A-14 summarizes several startup characteristics explained in this section. Detailed description of the startup behavior can be found in the Clock and Reset Generator (CRG) Block Guide. Table A-14 Startup Characteristics Conditions are shown in Table A-4 unless otherwise noted Num C Rating Symbol Min Typ Max Unit 1 T POR release level VPORR - - 2.07 V 2 T POR assert level VPORA 0.97 - - V 3 D Reset input pulse width, minimum input time PWRSTL 2 - - tosc 4 D Startup from Reset nRST 192 - 196 nosc 5 D Interrupt pulse width, IRQ edge-sensitive mode PWIRQ 20 - - ns 6 D Wait recovery startup time tWRS - - 14 tcyc A.5.1.1 POR The release level VPORR and the assert level VPORA are derived from the VDD Supply. They are also valid if the device is powered externally. After releasing the POR reset the oscillator and the clock quality check are started. If after a time tCQOUT no valid oscillation is detected, the MCU will start using the internal self clock. The fastest startup time possible is given by nuposc. A.5.1.2 SRAM Data Retention Provided an appropriate external reset signal is applied to the MCU, preventing the CPU from executing code when VDD5 is out of specification limits, the SRAM contents integrity is guaranteed if after the reset the PORF bit in the CRG Flags Register has not been set. A.5.1.3 External Reset When external reset is asserted for a time greater than PWRSTL the CRG module generates an internal reset, and the CPU starts fetching the reset vector without doing a clock quality check, if there was an oscillation before reset. A.5.1.4 Stop Recovery Out of STOP the controller can be woken up by an external interrupt. A clock quality check as after POR is performed before releasing the clocks to the system. 105 MC9S12DP512 Device Guide V01.25 A.5.1.5 Pseudo Stop and Wait Recovery The recovery from Pseudo STOP and Wait are essentially the same since the oscillator was not stopped in both modes. The controller can be woken up by internal or external interrupts. After twrs the CPU starts fetching the interrupt vector. A.5.2 Oscillator The device features an internal Colpitts and Pierce oscillator. The selection of Colpitts oscillator or Pierce oscillator/external clock depends on the XCLKS signal which is sampled during reset. Pierce oscillator/external clock mode allows the input of a square wave. Before asserting the oscillator to the internal system clocks the quality of the oscillation is checked for each start from either power-on, STOP or oscillator fail. tCQOUT specifies the maximum time before switching to the internal self clock mode after POR or STOP if a proper oscillation is not detected. The quality check also determines the minimum oscillator start-up time tUPOSC . The device also features a clock monitor. A Clock Monitor Failure is asserted if the frequency of the incoming clock signal is below the Assert Frequency fCMFA. Table A-15 Oscillator Characteristics Conditions are shown in Table A-4 unless otherwise noted Num C Rating Symbol Min Typ Max Unit 1a C Crystal oscillator range (Colpitts) fOSC 0.5 - 16 MHz 1b C Crystal oscillator range (Pierce) 1 fOSC 0.5 - 40 MHz 2 P Startup Current iOSC 100 - - A 3 C Oscillator start-up time (Colpitts) tUPOSC - 82 1003 ms 4 D Clock Quality check time-out tCQOUT 0.45 - 2.5 s 5 P Clock Monitor Failure Assert Frequency fCMFA 50 100 200 KHz 6 P External square wave input frequency 4 fEXT 0.5 - 50 MHz 7 D External square wave pulse width low 4 tEXTL 9.5 - - ns 8 D External square wave pulse width high 4 tEXTH 9.5 - - ns 9 D External square wave rise time 4 tEXTR - - 1 ns 10 D External square wave fall time 4 tEXTF - - 1 ns 11 D Input Capacitance (EXTAL, XTAL pins) CIN - 7 - pF 12 C VDCBIAS - 1.1 - V 13 P EXTAL Pin Input High Voltage 4 VIH,EXTAL 0.75*VDDPLL - - V T EXTAL Pin Input High Voltage 4 VIH,EXTAL - - VDDPLL + 0.3 V P EXTAL Pin Input Low Voltage 4 VIL,EXTAL - - 0.25*VSSPLL V T EXTAL Pin Input Low Voltage 4 VIL,EXTAL VSSPLL - 0.3 - - V VHYS,EXTAL - 250 - mV 14 15 DC Operating Bias in Colpitts Configuration on EXTAL Pin C EXTAL Pin Input Hysteresis 4 MC9S12DP512 Device Guide V01.25 NOTES: 1. Depending on the crystal a damping series resistor might be necessary 2. fosc = 4MHz, C = 22pF. 3. Maximum value is for extreme cases using high Q, low frequency crystals 4. Only valid if Pierce oscillator/external clock mode is selected A.5.3 Phase Locked Loop The oscillator provides the reference clock for the PLL. The PLLs Voltage Controlled Oscillator (VCO) is also the system clock source in self clock mode. A.5.3.1 XFC Component Selection This section describes the selection of the XFC components to achieve a good filter characteristics. Cp VDDPLL R Phase Cs fosc 1 refdv+1 fref fcmp XFC Pin VCO K KV fvco Detector Loop Divider 1 synr+1 1 2 Figure A-3 Basic PLL functional diagram The following procedure can be used to calculate the resistance and capacitance values using typical values for K1, f1 and ich from Table A-16. The grey boxes show the calculation for fVCO = 50MHz and fref = 1MHz. E.g., these frequencies are used for fOSC = 4MHz and a 25MHz bus clock. The VCO Gain at the desired VCO frequency is approximated by: KV = K1 e ( f 1 - f vco ) ----------------------K 1 1V = - 100 e ( 60 - 50 ) ------------------------ 100 = -90.48MHz/V 107 MC9S12DP512 Device Guide V01.25 The phase detector relationship is given by: K = - i ch K V = 316.7Hz/ ich is the current in tracking mode. The loop bandwidth fC should be chosen to fulfill the Gardner's stability criteria by at least a factor of 10, typical values are 50. = 0.9 ensures a good transient response. 2 f ref f ref 1 f C < ------------------------------------------ ------ f C < -------------- ;( = 0.9 ) 4 10 2 10 + 1 + fC < 25kHz And finally the frequency relationship is defined as f VCO n = ------------- = 2 ( synr + 1 ) f ref = 50 With the above values the resistance can be calculated. The example is shown for a loop bandwidth fC=10kHz: 2 n fC R = ----------------------------- = 2**50*10kHz/(316.7Hz/)=9.9k=~10k K The capacitance Cs can now be calculated as: 2 0.516 2 C s = ---------------------- --------------- ;( = 0.9 ) = 5.19nF =~ 4.7nF fC R fC R The capacitance Cp should be chosen in the range of: C s 20 C p C s 10 Cp = 470pF A.5.3.2 Jitter Information The basic functionality of the PLL is shown in Figure A-3. With each transition of the clock fcmp, the deviation from the reference clock fref is measured and input voltage to the VCO is adjusted accordingly.The adjustment is done continuously with no abrupt changes in the clock output frequency. Noise, voltage, temperature and other factors cause slight variations in the control loop resulting in a clock jitter. This jitter affects the real minimum and maximum clock periods as illustrated in Figure A-4. MC9S12DP512 Device Guide V01.25 1 0 2 3 N-1 N tmin1 tnom tmax1 tminN tmaxN Figure A-4 Jitter Definitions The relative deviation of tnom is at its maximum for one clock period, and decreases towards zero for larger number of clock periods (N). Defining the jitter as: t min ( N ) t max ( N ) J ( N ) = max 1 - --------------------- , 1 - --------------------- N t nom N t nom For N < 100, the following equation is a good fit for the maximum jitter: j1 J ( N ) = -------- + j 2 N J(N) 1 5 10 20 N Figure A-5 Maximum bus clock jitter approximation 109 MC9S12DP512 Device Guide V01.25 This is very important to notice with respect to timers, serial modules where a pre-scaler will eliminate the effect of the jitter to a large extent. Table A-16 PLL Characteristics Conditions are shown in Table A-4 unless otherwise noted Num C Rating Symbol Min Typ Max Unit 1 P Self Clock Mode frequency fSCM 1 - 5.5 MHz 2 D VCO locking range fVCO 8 - 50 MHz 3 D |trk| 3 - 4 %1 4 D Lock Detection |Lock| 0 - 1.5 %(1) 5 D Un-Lock Detection |unl| 0.5 - 2.5 %(1) 6 D |unt| 6 - 8 %(1) 7 C PLLON Total Stabilization delay (Auto Mode) 2 tstab - 0.5 - ms 8 D PLLON Acquisition mode stabilization delay (2) tacq - 0.3 - ms 9 D PLLON Tracking mode stabilization delay (2) tal - 0.2 - ms 10 D Fitting parameter VCO loop gain K1 - -100 - MHz/V 11 D Fitting parameter VCO loop frequency f1 - 60 - MHz 12 D Charge pump current acquisition mode | ich | - 38.5 - A 13 D Charge pump current tracking mode | ich | - 3.5 - A 14 C Jitter fit parameter 1(2) j1 - - 1.1 % 15 C Jitter fit parameter 2(2) j2 - - 0.13 % Lock Detector transition from Acquisition to Tracking mode Lock Detector transition from Tracking to Acquisition mode NOTES: 1. % deviation from target frequency 2. fOSC = 4MHz, fBUS = 25MHz equivalent fVCO = 50MHz: REFDV = #$03, SYNR = #$018, Cs = 4.7nF, Cp = 470pF, Rs = 10K. MC9S12DP512 Device Guide V01.25 A.6 MSCAN Table A-17 MSCAN Wake-up Pulse Characteristics Conditions are shown in Table A-4 unless otherwise noted Num C Rating Symbol Min Typ Max Unit 1 P MSCAN Wake-up dominant pulse filtered tWUP - - 2 s 2 P MSCAN Wake-up dominant pulse pass tWUP 5 - - s 111 MC9S12DP512 Device Guide V01.25 MC9S12DP512 Device Guide V01.25 A.7 SPI This section provides electrical parametrics and ratings for the SPI. In Table A-18 the measurement conditions are listed. Table A-18 Measurement Conditions Description Value Unit full drive mode -- 50 pF (20% / 80%) VDDX V Drive mode Load capacitance CLOAD, on all outputs Thresholds for delay measurement points A.7.1 Master Mode In Figure A-6 the timing diagram for master mode with transmission format CPHA=0 is depicted. SS1 (OUTPUT) 2 1 SCK (CPOL = 0) (OUTPUT) 13 12 13 3 4 SCK (CPOL = 1) (OUTPUT) 5 MISO (INPUT) 6 MSB IN2 10 MOSI (OUTPUT) 12 4 BIT 6 . . . 1 LSB IN 9 MSB OUT2 BIT 6 . . . 1 11 LSB OUT 1.if configured as an output. 2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB. Figure A-6 SPI Master Timing (CPHA=0) In Figure A-7 the timing diagram for master mode with transmission format CPHA=1 is depicted. 113 MC9S12DP512 Device Guide V01.25 SS1 (OUTPUT) 1 2 12 13 12 13 3 SCK (CPOL = 0) (OUTPUT) 4 4 SCK (CPOL = 1) (OUTPUT) 5 MISO (INPUT) 6 MSB IN2 BIT 6 . . . 1 LSB IN 11 9 MOSI (OUTPUT) PORT DATA MASTER MSB OUT2 BIT 6 . . . 1 MASTER LSB OUT PORT DATA 1.If configured as output 2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB. Figure A-7 SPI Master Timing (CPHA=1) In Table A-19 the timing characteristics for master mode are listed. Table A-19 SPI Master Mode Timing Characteristics Num Characteristic Symbol Min Typ Max Unit 1 SCK Frequency fsck 1/2048 -- 1/2 fbus 1 SCK Period tsck 2 -- 2048 tbus 2 Enable Lead Time tlead -- 1/2 -- tsck 3 Enable Lag Time tlag -- 1/2 -- tsck 4 Clock (SCK) High or Low Time twsck -- 1/2 -- tsck 5 Data Setup Time (Inputs) tsu 8 -- -- ns 6 Data Hold Time (Inputs) thi 8 -- -- ns 9 Data Valid after SCK Edge tvsck -- -- 30 ns 10 Data Valid after SS fall (CPHA=0) tvss -- -- 15 ns 11 Data Hold Time (Outputs) tho 20 -- -- ns Rise and Fall Time Inputs trfi -- -- 8 ns Rise and Fall Time Outputs trfo -- -- 8 ns 12 13 MC9S12DP512 Device Guide V01.25 A.7.2 Slave Mode In Figure A-8 the timing diagram for slave mode with transmission format CPHA=0 is depicted. SS (INPUT) 1 12 13 12 13 3 SCK (CPOL = 0) (INPUT) 4 2 4 SCK (CPOL = 1) (INPUT) 10 8 7 MISO (OUTPUT) 9 see note SLAVE MSB 5 MOSI (INPUT) BIT 6 . . . 1 11 11 SLAVE LSB OUT SEE NOTE 6 MSB IN BIT 6 . . . 1 LSB IN NOTE: Not defined! Figure A-8 SPI Slave Timing (CPHA=0) In Figure A-9 the timing diagram for slave mode with transmission format CPHA=1 is depicted. 115 MC9S12DP512 Device Guide V01.25 SS (INPUT) 3 1 2 12 13 12 13 SCK (CPOL = 0) (INPUT) 4 4 SCK (CPOL = 1) (INPUT) see note SLAVE 7 MSB OUT 5 MOSI (INPUT) 8 11 9 MISO (OUTPUT) BIT 6 . . . 1 SLAVE LSB OUT 6 MSB IN BIT 6 . . . 1 LSB IN NOTE: Not defined! Figure A-9 SPI Slave Timing (CPHA=1) In Table A-20 the timing characteristics for slave mode are listed. Table A-20 SPI Slave Mode Timing Characteristics Num Characteristic Symbol Min Typ Max Unit 1 SCK Frequency fsck DC -- 1/4 fbus 1 SCK Period tsck 4 -- tbus 2 Enable Lead Time tlead 4 -- -- tbus 3 Enable Lag Time tlag 4 -- -- tbus 4 Clock (SCK) High or Low Time twsck 4 -- -- tbus 5 Data Setup Time (Inputs) tsu 8 -- -- ns 6 Data Hold Time (Inputs) thi 8 -- -- ns Slave Access Time (time to data active) ta -- -- 20 ns Slave MISO Disable Time tdis -- -- 22 7 8 9 Data Valid after SCK Edge tvsck -- -- ns 30 + tbus 1 ns 30 + tbus 1 ns 10 Data Valid after SS fall tvss -- -- 11 Data Hold Time (Outputs) tho 20 -- -- ns 12 Rise and Fall Time Inputs trfi -- -- 8 ns 13 Rise and Fall Time Outputs trfo -- -- 8 ns NOTES: 1. tbus added due to internal synchronization delay MC9S12DP512 Device Guide V01.25 A.8 External Bus Timing A timing diagram of the external multiplexed-bus is illustrated in Figure A-10 with the actual timing values shown on table Table A-21. All major bus signals are included in the diagram. While both a data write and data read cycle are shown, only one or the other would occur on a particular bus cycle. A.8.1 General Muxed Bus Timing The expanded bus timings are highly dependent on the load conditions. The timing parameters shown assume a balanced load across all outputs. 117 MC9S12DP512 Device Guide V01.25 1, 2 3 4 ECLK PE4 5 9 Addr/Data (read) PA, PB 6 data 16 15 7 data 8 14 13 data addr 17 11 data addr 12 Addr/Data (write) PA, PB 10 19 18 Non-Multiplexed Addresses PK5:0 20 21 22 23 ECS PK7 24 25 26 27 28 29 30 31 32 33 34 R/W PE2 LSTRB PE3 NOACC PE7 35 36 IPIPE0 IPIPE1, PE6,5 Figure A-10 General External Bus Timing MC9S12DP512 Device Guide V01.25 Table A-21 Expanded Bus Timing Characteristics Conditions are shown in Table A-4 unless otherwise noted, CLOAD = 50pF Num C Rating Symbol Min Typ Max Unit fo 0 - 25.0 MHz tcyc 40 - - ns 1 P Frequency of operation (E-clock) 2 P Cycle time 3 D Pulse width, E low PWEL 19 - - ns 4 D Pulse width, E high1 PWEH 19 - - ns 5 D Address delay time tAD - - 8 ns 6 D Address valid time to E rise (PWEL-tAD) tAV 11 - - ns 7 D Muxed address hold time tMAH 2 - - ns 8 D Address hold to data valid tAHDS 7 - - ns 9 D Data hold to address tDHA 2 - - ns 10 D Read data setup time tDSR 13 - - ns 11 D Read data hold time tDHR 0 - - ns 12 D Write data delay time tDDW - - 7 ns 13 D Write data hold time tDHW 2 - - ns 14 D Write data setup time(1) (PWEH-tDDW) tDSW 12 - - ns 15 D Address access time(1) (tcyc-tAD-tDSR) tACCA 19 - - ns 16 D E high access time(1) (PWEH-tDSR) tACCE 6 - - ns 17 D Non-multiplexed address delay time tNAD - - 6 ns 18 D Non-muxed address valid to E rise (PWEL-tNAD) tNAV 13 - - ns 19 D Non-multiplexed address hold time tNAH 2 - - ns 20 D Chip select delay time tCSD - - 16 ns 21 D Chip select access time(1) (tcyc-tCSD-tDSR) tACCS 11 - - ns 22 D Chip select hold time tCSH 2 - - ns 23 D Chip select negated time tCSN 8 - - ns 24 D Read/write delay time tRWD - - 7 ns 25 D Read/write valid time to E rise (PWEL-tRWD) tRWV 14 - - ns 26 D Read/write hold time tRWH 2 - - ns 27 D Low strobe delay time tLSD - - 7 ns 28 D Low strobe valid time to E rise (PWEL-tLSD) tLSV 14 - - ns 29 D Low strobe hold time tLSH 2 - - ns 30 D NOACC strobe delay time tNOD - - 7 ns 31 D NOACC valid time to E rise (PWEL-tNOD) tNOV 14 - - ns 119 MC9S12DP512 Device Guide V01.25 Table A-21 Expanded Bus Timing Characteristics Conditions are shown in Table A-4 unless otherwise noted, CLOAD = 50pF Num C Rating Symbol Min Typ Max Unit 32 D NOACC hold time tNOH 2 - - ns 33 D IPIPE[1:0] delay time tP0D 2 - 7 ns 34 D IPIPE[1:0] valid time to E rise (PWEL-tP0D) tP0V 11 - - ns 35 D IPIPE[1:0] delay time(1) (PWEH-tP1V) tP1D 2 - 7 ns 36 D IPIPE[1:0] valid time to E fall tP1V 11 - - ns NOTES: 1. Affected by clock stretch: add N x tcyc where N=0,1,2 or 3, depending on the number of clock stretches. MC9S12DP512 Device Guide V01.25 Appendix B Package Information B.1 General This section provides the physical dimensions of the MC9S12DP512 packages. 121 MC9S12DP512 Device Guide V01.25 B.2 112-pin LQFP package 0.20 T L-M N 4X PIN 1 IDENT 0.20 T L-M N 4X 28 TIPS 112 J1 85 4X P J1 1 CL 84 VIEW Y 108X G X X=L, M OR N VIEW Y B L V M B1 28 57 29 F D 56 0.13 N S1 A S C2 VIEW AB 2 0.050 0.10 T 112X SEATING PLANE 3 T R R2 R 0.25 R1 GAGE PLANE (K) C1 E (Y) (Z) VIEW AB M BASE METAL T L-M N SECTION J1-J1 ROTATED 90 COUNTERCLOCKWISE A1 C AA J V1 1 NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. DIMENSIONS IN MILLIMETERS. 3. DATUMS L, M AND N TO BE DETERMINED AT SEATING PLANE, DATUM T. 4. DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE, DATUM T. 5. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.25 PER SIDE. DIMENSIONS A AND B INCLUDE MOLD MISMATCH. 6. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL NOT CAUSE THE D DIMENSION TO EXCEED 0.46. DIM A A1 B B1 C C1 C2 D E F G J K P R1 R2 S S1 V V1 Y Z AA 1 2 3 MILLIMETERS MAX MIN 20.000 BSC 10.000 BSC 20.000 BSC 10.000 BSC --1.600 0.050 0.150 1.350 1.450 0.270 0.370 0.450 0.750 0.270 0.330 0.650 BSC 0.090 0.170 0.500 REF 0.325 BSC 0.100 0.200 0.100 0.200 22.000 BSC 11.000 BSC 22.000 BSC 11.000 BSC 0.250 REF 1.000 REF 0.090 0.160 8 0 7 3 13 11 11 13 Figure B-1 112-pin LQFP mechanical dimensions (case no. 987) MC9S12DP512 Device Guide V01.25 User Guide End Sheet 123 MC9S12DP512 Device Guide V01.25