HM538253B Series
HM538254B Series
262,144-word × 8-bit Multiport CMOS Video RAM
Description
The HM538253B/HM538254B is a 2-Mbit multiport video RAM equipped with a 256-kword × 8-bit dynamic
RAM and a 512-word × 8-bit SAM (full-sized SAM). Its RAM and SAM operate independently and
asynchronously. The HM538253B/HM538254B is upwardly compatible with the HM534253B/HM538123B
except that the pseudo-write-transfer cycle is replaced with masked-write-transfer cycle, which has been
approved by JEDEC. Furthermore, several new features have been added to the HM538253B/HM538254B
which do not conflict with the conventional features. The stopping column feature realizes allows greater
flexibility for split SAM register lengths. Persistent mask is also installed according to the TMS34020
features. The HM538254B has Hyper page mode which enables fast page cycle.
Features
• Multiport organization:RAM and SAM can operate asynchronously and simultaneously:
RAM: 256-kword × 8-bit
SAM: 512-word × 8-bit
• Access time
RAM: 70 ns/80 ns/100 ns max
SAM: 20 ns/23 ns/25 ns max
• Cycle time
RAM: 130 ns/150 ns/180 ns min
SAM: 25 ns/28 ns/30 ns min
• Low power
Active RAM: 605 mW/550 mW/495 mW
SAM: 358 mW/330 mW/303 mW
Standby 38.5 mW max
• Masked-write-transfer cycle capability
• Stopping column feature capability
• Persistent mask capability
HM538253B/HM538254B Series
2
• Fast page mode capability (HM538253B)
Cycle time: 45 ns/50 ns/55 ns
Power RAM: 605 mW/578 mW/550 mW
• Hyper page mode capability (HM538254B)
Cycle time: 35 ns/40 ns/45 ns
Power RAM: 715 mW/660 mW/605 mW
• Mask write mode capability
• Bidirectional data transfer cycle between RAM and SAM capability
• Split transfer cycle capability
• Block write mode capability
• Flash write mode capability
• 3 variations of refresh (8 ms/512 cycles)
RAS-only refresh
CAS-before-RAS refresh
Hidden refresh
• TTL compatible
Ordering Information
Type No. Access Time Package
HM538253BJ-7
HM538253BJ-8
HM538253BJ-10
70 ns
80 ns
100 ns
400-mil, 40-pin plastic SOJ (CP-40D)
HM538254BJ-7
HM538254BJ-8
HM538254BJ-10
70 ns
80 ns
100 ns
HM538253BTT-7
HM538253BTT-8
HM538253BTT-10
70 ns
80 ns
100 ns
44-pin thin small outline package (TTP-44/40DA)
HM538254BTT-7
HM538254BTT-8
HM538254BTT-10
70 ns
80 ns
100 ns
HM538253B/HM538254B Series
3
Pin Arrangement
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
V
SI/O7
SI/O6
SI/O5
SI/O4
SE
I/O7
I/O6
I/O5
I/O4
V
DSF1
NC
CAS
QSF
A0
A1
A2
A3
V
V
SC
SI/O0
SI/O1
SI/O2
SI/O3
DT/OE
I/O0
I/O1
I/O2
I/O3
V
WE
RAS
A8
A7
A6
A5
A4
V
SS
CC
SS
SS
(Top view)
CC
SS
(Top view)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
V
SI/O7
SI/O6
SI/O5
SI/O4
SE
I/O7
I/O6
I/O5
I/O4
NL
NL
V
DSF1
NC
CAS
QSF
A0
A1
A2
A3
V
V
SC
SI/O0
SI/O1
SI/O2
SI/O3
DT/OE
I/O0
I/O1
I/O2
NL
NL
I/O3
V
WE
RAS
A8
A7
A6
A5
A4
V
SS
CC
SS
SS
CC
SS
HM538253BJ Series
HM538254BJ Series HM538253BTT Series
HM538254BTT Series
HM538253B/HM538254B Series
4
Pin Description
Pin Name Function
A0-A8 Address inputs
I/O0-I/O7 RAM port data inputs/outputs
SI/O0-SI/O7 SAM port data inputs/outputs
RAS Row address strobe
CAS Column address strobe
WE Write enable
DT/OE Data transfer/output enable
SC Serial clock
SE SAM port enable
DSF1 Special function input flag
QSF Special function output flag
VCC Power supply
VSS Ground
NL No lead
NC No connection
HM538253B/HM538254B Series
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Block Diagram
A0 – A8
A0 – A8 A0 – A8
SI/O0 – SI/O7
I/O0 – I/O7
RAS
CAS
DT/OE
WE
DSF1
SC
SE
Timing Generator
Output
Buffer
Input
Buffer
Mask
Register
Input Data
Control Serial Output
Buffer Serial Input
Buffer
Column Decoder
Sense Amplifier & I/O Bus
SAM I/O Bus
SAM Column Decoder
Data
Register
Serial Address
Counter
Refresh
Counter
Row Address
Buffer
Column Address
Buffer
Row Decoder
Memory Array
Data
Register
Transfer
Gate
Transfer
Gate
0
511 511
0
Flash Write
Control
Block Write
Control
Color
Resister
Address Mask
Register
QSF
HM538253B/HM538254B Series
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Pin Functions
RAS (input pin): RAS is a basic RAM signal. It is active in low level and standby in high level. Row address
and signals as shown in table 1 are input at the falling edge of RAS. The input level of these signals
determines the operation cycle of the HM538253B/HM538254B.
CAS (input pin): Column address and DSF1 signals are fetched into the chip at the falling edge of CAS,
which determines the operation mode of the HM538253B/HM538254B.
A0–A8 (input pins): Row address (AX0–AX8) is determined by A0–A8 level at the falling edge of RAS.
Column address (AY0–AY8) is determined by A0–A8 level at the falling edge of CAS. In transfer cycles,
row address is the address on the word line which transfers data with the SAM data register, and column
address is the SAM start address after transfer.
WE: The WE pin has two functions at the falling edge of RAS and after. When WE is low at the falling edge
of RAS, the HM538253B/ HM538254B turns to mask write mode. According to the I/O level at the time,
write on each I/O can be masked. (WE level at the falling edge of RAS is don’t care in read cycle.) When
WE is high at the falling edge of RAS, a no mask write cycle is executed. After that, WE switches to
read/write cycles. In a transfer cycle, the direction of transfer is determined by WE level at the falling edge of
RAS. When WE is low, data is transferred from SAM to RAM (data is written into RAM), and when WE is
high, data is transferred from RAM to SAM (data is read from RAM).
I/O0–I/O7 (input/output pins): I/O pins function as mask data at the falling edge of RAS (in mask write
mode). Data is written only to high I/O pins. Data on low I/O pins is masked and internal data is retained.
After that, they function as input/output pins as those of a standard DRAM. In block write cycle, the data
functions as column mask data at the falling edges of CAS and WE.
DT/OE (input pin): The DT/OE pin functions as a DT (data transfer) pin at the falling edge of RAS and as
an OE (output enable) pin after that. When DT is low at the falling edge of RAS, this cycle becomes a transfer
cycle. When DT is high at the falling edge of RAS, RAM and SAM operate independently.
SC (input pin): SC is a basic SAM clock. In a serial read cycle, data outputs from an SI/O pin synchronously
with the rising edge of SC. In a serial write cycle, data on an SI/O pin at the rising edge of SC is fetched into
the SAM data register.
SE (input pin): SE pin activates SAM. When SE is high, SI/O is in the high impedance state in serial read
cycle and data on SI/O is not fetched into the SAM data register in serial write cycle. SE can be used as a
mask for serial write because the internal pointer is incremented at the rising edge of SC.
SI/O0–SI/O7 (input/output pins): SI/Os are SAM input/output pins. I/O direction is determined by the
previous transfer cycle. If it was a read transfer cycle, SI/O outputs data. If it was a masked write transfer
cycle, SI/O inputs data.
DSF1 (input pin): DSF1 is a special function data input flag pin. It is set to high at the falling edge of RAS
when new functions such as color register and mask register read/write, split transfer, and flash write, are
used.
HM538253B/HM538254B Series
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DSF2 (input pin): DSF2 is also a special function data input flag pin. This pin is fixed to low level in all
operations of the HM538253B/HM538254B.
QSF (output pin): QSF outputs data of address A8 in SAM. QSF is switched from low to high by accessing
address 255 in SAM, and from high to low by accessing address 511 in SAM.
Table 1 Operation Cycles of the HM538253B/HM538254B
RAS CAS Address I/On Input
Mnemonic
Code CAS DT/OE WE DSF1 DSF2 DSF1 DSF2 RAS CAS RAS CAS/WE
CBRS 0 — 0 1 0 — 0 Stop — — —
CBRR 0 — 1 0 0 — 0 ————
CBRN 0 — 1 1 0 — 0 ————
MWT 1 0 0 0 0 — 0 Row TAP WM —
MSWT 1 0 0 1 0 — 0 Row TAP WM —
RT 1 0 1 0 0 — 0 Row TAP — —
SRT 1 0 1 1 0 — 0 Row TAP — —
RWM 11 00000RowColumn WM Input data
BWM 11 00010RowColumn WM Column Mask
RW (No) 1 1 1 0000RowColumn — Input Data
BW (No) 1 1 1 0010RowColumn — Column Mask
FWM 1 1 0 1 0 — 0 Row — WM —
LMR and
Old Mask Set 11 11000(Row) — — Mask Data
LCR 11 11010(Row) — — Color
Option 0 0 0 0 0 — 0 Mode — Data —
HM538253B/HM538254B Series
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Table 1 Operation Cycles of the HM538253B/HM538254B (cont)
Register
Mnemonic
Code Write
Mask Pers
W.M. WM Color No. Of
Bndry Function
CBRS — — — — Set CBR refresh with stop register set
CBRR — Reset Reset — Reset CBR refresh with register reset
CBRN — — — — — CBR refresh (no reset)
MWT Yes No
Yes Load/use
Use — — Masked write transfer (new/old mask)
MSWT Yes No
Yes Load/use
Use — Use Masked split write transfer (new/old mask)
RT — — — — — Read transfer
SRT — — — — Use Split read transfer
RWM Yes No
Yes Load/use
Use — — Read/write (new/old mask)
BWM Yes No
Yes Load/use
Use — Block write (new/old mask)
RW (no) No No — — — Read/write (no mask)
BW (no) No No — Use — Block write (no mask)
FWM Yes No
Yes Load/use
Use Use — Masked flash write (new/old mask)
LMR and
Old Mask Set — Set Load — — Load mask register and old mask set
LCR — — — Load — Load color resister set
Option — — — — —
Notes: 1. With CBRS, all SAM operations use stop register.
2. After LMR, RWM, BWM, FWM, MWT, and MSWT, use old mask which can be reset by CBRR
3. DSF2 is fixed low in all operation (for the addition of operation modes in future).
Operation of HM538253B/HM538254B
RAM Port Operation
RAM Read Cycle (DT/OE high, CAS high and DSF1 low at the falling edge of RAS, DSF1 low at the falling
edge of CAS: Mnemonic Code; R) Row address is entered at the RAS falling edge and column address at the
C AS falling edge to the device as in standard DRAM operation. Then, when WE is high and DT /OE is low
while C AS is low, the selected address data outputs through the I/O pin. At the falling edge of RAS , DT /OE
and CAS become high to distinguish RAM read cycle from transfer cycle and CBR refresh cycle. Address
access time (tAA) and RAS to column address delay time (tRAD) specifications are added to enable fast page
mode/hyper page mode.
HM538253B/HM538254B Series
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RAM Write Cycle (Early Write, Delayed Write, Read-Modify-Write)(DT/OE high, CAS high and DSF1
are low at the falling edge of R AS, and DSF1 is low at the falling edge of CAS): Mnemonic Code; W
No Mask Write Cycle (WE high at the falling edge of RAS): When CAS is set low and WE is set low after
RAS low, a write cycle is executed. If WE is set low before the CAS falling edge, this cycle becomes an early
write cycle and all I/O become in high impedance. If WE is set low after the CAS falling edge, this cycle
becomes a delayed write cycle. I/O does not become high impedance in this cycle, so data should be entered
with OE in high. If WE is set low after tCWD (min) and tAWD (min) after the CAS falling edge, this cycle
becomes a read-modify-write cycle and enables read/write at the same address in one cycle. In this cycle also,
to avoid I/O contention, data should be input after reading data and driving OE high.
Mask Write Mode (WE low at the falling edge of RAS):If WE is set low at the falling edge of RAS, two
modes of mask write cycle are possible.
In new mask mode, mask data is loaded from I/O pin and used. Whether or not an I/O is written depends on
I/O level at the falling edge of RAS. The data is written in high level I/Os, and the data is masked and retained
in low level I/Os. This mask data is effective during the RAS cycle. So, in page mode cycles the mask data is
retained during the page access.
If a load mask register cycle (LMR) has been performed, Mask write cycle (RAM write cycle, flash write
cycle, block write cycle, masked write transfer cycle and masked sprit write transfer cycle) becomes all
persistent mask mode. The mask data is not loaded from I/O pins and the mask data stored in mask registers
persistently are used. This operation known as persistent write mask is reset by CBRR cycle, and become a
new mask.
Fast Page Mode Cycle (HM538253B) (DT /OE high, CAS high and DSF1 low at the falling edge of RAS):
Fast page mode cycle reads/writes the data of the same row address at high speed by toggling CAS while
RAS is low. Its cycle time is one third of the random read/write cycle. In this cycle, read, write, and block
write cycles can be mixed. Note that address access time (tAA), RAS to column address delay time (tRAD), and
access time from CAS precharge (tACP) are added. In one RAS cycle, 512-word memory cells of the same row
address can be accessed. It is necessary to specify access frequency within tRASP max (100 µs).
Hyper Page Mode Cycle (HM538254B) (DT/OE high, CAS high and DSF1 low at the falling edge of RAS):
Hyper page mode cycle reads/writes the data of the same row address at high speed by toggling CAS while
RAS is low. Its cycle time is one forth of the random read/write cycle. In this cycle, read, write, and block
write cycles can be mixed. Note that address access time (tAA), RAS to column address delay time (tRAD), and
access time from CAS precharge (tACP) are added. column address is latched by CAS low edge triger, access
time from CAS is determined by tCAC (tAA from column address, tACP from CAS high edge). Dout data is held
during CAS high and is sustained until next Dout. Data output enable/disable is controlled by DT /OE and
when both RAS and CAS become high, Data output become High-Z. In one RAS cycle, 512-word memory
cells of the same row address can be accessed. It is necessary to specify access frequency within tRASP max
(100 µs).
Color Register Set/Read Cycle (CAS high, DT/OE high, WE high and DSF1 high at the falling edge of
RAS: Mnemonic Code; LCR) In color register set cycle, color data is set to the internal color register used in
flash write cycle or block write cycle. 8 bits of internal color register are provided at each I/O. This register is
composed of static circuits, so once it is set, it retains the data until reset. Since color register set cycle is the
HM538253B/HM538254B Series
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same as the usual read and write cycle, so read, early write, and delayed write cycle can be executed. In this
cycle, the HM538253B/ HM538254B refreshes the row address fetched at the falling edge of RAS.
Mask Register Set/Read Cycle (CAS high, DT/OE high, WE high, and DSF1 low at the falling edge of R AS:
Mnemonic Code; LMR) In this cycle, mask data is set to the internal mask register persistently used in mask
write cycle, block write cycle, flash write cycle, masked write transfer, and masked split write transfer. 8 bits
of internal mask register are provided at each I/O. This mask register is composed of static circuits. So once it
is reset by CBRR cycle, it retains the data until reset or reselect. Once LMR is set, mask write cycle data is
written by persistent mask data. Since mask register set cycle is just the same as the usual read and write
cycle, so read, early write, and delayed write cycle can be executed.
Flash Write Cycle (CAS high, DT/OE high, WE low, and DSF1 high at the falling edge of RAS:
Mnemonic; FW) In a flash write cycle, a row of data (512 word × 8 bit) is cleared to 0 or 1 at each I/O
according to the data in the color register mentioned before. It is also necessary to mask I/O in this cycle.
When CAS and DT/OE is set high, WE is low, and DSF1 is high at the falling edge of RAS, this cycle starts.
Then, the row address to clear is given to row address. Mask data is the same as that of a RAM write cycle.
Cycle time is the same as those of RAM read/write cycles, so all bits can be cleared in 1/512 of the usual
cycle time. (See figure 1.)
Block Write Cycle (CAS high, DT/OE high and DSF1 low at the falling edge of RAS, DSF1 high and WE
low at the falling edge of CAS: Mnemonic; BW) In a block write cycle, 4 columns of data (4 column × 8 bit)
are cleared to 0 or 1 at each I/O according to the data of color register. Column addresses A0 and A1 are
disregarded. The mask data on I/Os and the mask data on column address can be determined independently.
I/O level at the falling edge of CAS determines the address to be cleared. (See figure 2.) The block write cycle
is as the same as the usual write cycle, so early and delayed write, read-modify-write, and page mode write
cycle can be executed.
No Mask Mode Block Write Cycle (WE high at the falling edge of RAS): The data on 8 I/Os are all cleared
when WE is high at the falling edge of RAS.
Mask Block Write Cycle (WE low at the falling edge of RAS):When WE is low at the falling edge of RAS,
the HM538253B/HM538254B starts mask block write cycle to clear the data on an optional I/O. The mask
data is the same as that of a RAM write cycle. High I/O is cleared, low I/O is not cleared and the internal data
is retained. In new mask mode, the mask data is available in the RAS cycle. In persistent mask mode, I/O
don’t care about mask mode.
HM538253B/HM538254B Series
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RAS
CAS
Address
WE
DT/OE
DSF1
I/O
Color Register Set Cycle Flash Write Cycle Flash Write Cycle
Row Xi Xj
*1 *1Color Data
Set color register Execute flash write into each
I/O on row address Xi using
color register.
Execute flash write into
each I/O on row address
Xj using color register.
Note: 1. I/O Mask Data (In new mask mode)
Low: Mask
High: Non Mask
In persistent mask mode, I/O don't care
Figure 1 Use of Flash Write
HM538253B/HM538254B Series
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Persistent
mask mode
Color Register Set Cycle Block Write Cycle Block Write Cycle
Row Row
Column A2–A8
Row
Column A2–A8
*1 *1
*1*1
Color Data
Column Mask Column Mask
RAS
CAS
Address
WE
DT/OE
DSF1
I/O
*1
I/O Mask Data (In new mask mode)
Low: Mask
High: Non Mask
In persistent mask mode, I/O H or L
Column Mask Data
Low: Mask
High: Non Mask
I/O0
I/O1
I/O2
I/O3
Column0 (A0 = 0, A1 = 0) Mask Data
Column1 (A0 = 1, A1 = 0) Mask Data
Column2 (A0 = 0, A1 = 1) Mask Data
Column3 (A0 = 1, A1 = 1) Mask Data
WE
Low
High
I/O data/RAS
H or L
(mask register used)
No mask
New mask mode
Mode Mask
H or L
Figure 2 Use of Block Write
Transfer Operation
The HM538253B/HM538254B provides the read transfer cycle, split read transfer cycle, masked write
transfer cycle and masked split write transfer cycle as data transfer cycles. These transfer cycles are set by
driving CAS high and DT/OE low at the falling edge of RAS. They have following functions:
• Transfer data between row address and SAM data register
Read transfer cycle and split read transfer cycle: RAM to SAM
Masked write transfer cycle and masked split write transfer cycle: SAM to RAM
• Determine SI/O state (except for split read transfer and masked split write transfer cycle)
Read transfer cycle: SI/O output
Masked write transfer cycle: SI/O input
HM538253B/HM538254B Series
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• Determine first SAM address to access after transferring at column address (SAM start address).
SAM start address must be determined by read transfer cycle or masked write transfer cycle (split
transfer cycle isn’t available) before SAM access, after power on, and determined for each transfer
cycle.
• Use the stopping columns (boundaries) in the serial shift register. If the stopping columns have been set,
split transfer cycles use the stopping columns, but any boundaries cannot be set as the start address.
• Load/use mask data in masked write transfer cycle and masked split write transfer cycle.
Read Transfer Cycle (CAS high, DT/OE low, WE high and DSF1 low at the falling edge of RAS):
Mnemonic; RT
This cycle becomes read transfer cycle by driving DT/OE low, WE high and DSF1 low at the falling edge of
RAS. The row address data (512 × 8 bits) determined by this cycle is transferred to SAM data register
synchronously at the rising edge of DT/OE. After the rising edge of DT/OE, the new address data outputs
from SAM start address determined by column address. In read transfer cycle, DT/OE must rise to transfer
data from RAM to SAM.
This cycle can access SAM even during transfer (real time read transfer). In this case, the timing tSDD (min)
specified between the last SAM access before transfer and DT/OE rising edge and tSDH (min) specified
between the first SAM access and DT/OE rising edge must be satisfied. (See figure 3.)
RAS
CAS
Address
DT/OE
SC
SI/O
SAM Data before Transfer SAM Data after Transfer
tSDD tSDH
L
Xi Yj
Yj Yj + 1
DSF1
Figure 3 Real Time Read Transfer
When read transfer cycle is executed, SI/O becomes output state by first SAM access. Input must be set high
impedance before tSZS (min) of the first SAM access to avoid data contention.
Masked Write Transfer cycle (CAS high, DT/OE low, WE low, and DSF1 low at the falling edge of RAS):
Masked write transfer cycle can transfer only selected I/O data in a row of data input by serial write cycle to
HM538253B/HM538254B Series
14
RAM. Whether I/O data is transferred or not depends on the corresponding I/O level (mask data) at the falling
edge of RAS. This mask transfer operation is the same as a mask write operation in RAM cycles, so the
persistent mode can be supported.
The row address of data transferred into RAM is determined by the address at the falling edge of RAS. The
column address is specified as the first address for serial write after terminating this cycle. Also in this cycle,
SAM access becomes enabled after tSRD (min) after RAS becomes high. SAM access is inhibited during RAS
low. In this period, SC must not be risen.
Data transferred to SAM by read transfer cycle or split read transfer cycle can be written to other addresses of
RAM by write transfer cycle. However, the address to write data must be the same as that of the read transfer
cycle or the split read transfer cycle (row address AX8). Figure 4 shows the example of row bit data transfer.
In case AX8 is 0, data cannot be transferred RAM address within the range of 100000000 to 111111111.
Same as the case of AX8 = 1.
A8 A0
000000000
100000000
011111111
111111111
(Row address)
........
A8 A0
000000000
100000000
011111111
111111111
........ Possible
Impossible
(Read transfer cycle) (Write transfer cycle)
SAM
RAM
RAM
SAM
(Row address) SAM
RAM
RAM
SAM
........
Figure 4 Example of Row Bit Data Transfer
Split Read Transfer Cycle (CAS high, DT /OE low, WE high and DSF1 high at the falling edge of RAS): To
execute a continuous serial read by real-time read transfer, the HM538253B/HM538254B must satisfy SC and
DT/OE timings and requires an external circuit to detect SAM last address. Split read transfer cycle makes it
possible to execute a continuous serial read without the above timing limitation.
The HM538253B/HM538254B supports two types of split register operation. One is the normal split register
operation to split the data register into two halves. The other is the boundary split register operation using
stopping columns described later.
Figure 5 shows the block diagram for the normal split register operation. SAMdata register (DR) consists of 2
split buffers, whose organizations are 256-word × 8-bit each. Suppose that data is read from upper data
register DR1. (The row address AX8 is 0 and SAM address A8 is 1.) When split read transfer is executed
setting row address AX8 to 0 and SAM start addresses A0 to A7, 256-word × 8-bit data is transferred from
RAM to the lower data register DR0 (SAM address A8 is 0) automatically. After data is read from data
register DR1, data read begins from SAM start addresses of data register DR0. If the next split read transfer
isn’t executed while data is read from data register DR0, data read begins from SAM start address 0 of DR1
HM538253B/HM538254B Series
15
after data is read from data register DR0. If split read transfer is executed setting row address AX8 to 1 and
SAM start addresses A0 to A7 while data is read from data register DR1, 256-word × 8-bit data is transferred
to data register DR2. After data is read from data register DR1, data read begins from the SAM start addresses
of data register DR2. If the next split read transfer isn’t executed while data is read from data register DR2,
data read begins from SAM start address 0 of data register DR1 after data is read from data register DR2. In
split read data transfer, the SAM start address A8 is automatically set in the data register, which isn’t used.
The data on SAM address A8, which will be accessed next, outputs to QSF. QSF is switched from low to high
by accessing SAM last address 255 and from high to low by accessing address 511.
Memory
Array
AX8 = 0
Memory
Array
DR1
SAM I/O Bus
SAM Column Decoder
DR0
SAM I/O Bus
DR3DR2
SAM I/O Buffer
SI/O
AX8 = 1
Figure 5 Split Transfer Block Diagram
Split read transfer cycle is set when CAS is high, DT/OE is low, WE is high and DSF1 is high at the falling
edge of RAS. The cycle can be executed asyncronously with SC. However, HM538253B/ HM538254B must
be satisfied tSTS (min) timing specified between SC rising (boundary address) and RAS falling. In split transfer
cycle, the HM538253B/HM538254B must satisfy tRST (min), tCST (min) and tAST(min) timings specified
between RAS or CAS falling and column address. (See figure 6.)
In split read transfer, SI/O isn’t switched to output state. Therefore, read transfer must be executed to switch
SI/O to output state when the previous transfer cycle is masked write transfer cycle or masked split write
transfer cycle.
Masked Split Write Transfer Cycle (CAS high, DT/OE low, WE low and DSF1 high at the falling edge of
RAS): A continuous serial write cannot be executed because accessing SAM is inhibited during RAS low in
write transfer. Masked split write transfer cycle makes it possible. In this cycle, tSTS (min), tRST (min), tCST
(min) and tAST (min) timings must be satisfied like split read transfer cycle. And it is impossible to switch
SI/O to input state in this cycle. If SI/O is in output state, masked write transfer cycle should be executed to
HM538253B/HM538254B Series
16
switch SI/O into input state. Data transferred to SAM by read transfer cycle or split read transfer cycle can be
written to other addresses of RAM by masked split write transfer cycle. However masked write transfer cycle
must be executed before masked split write transfer cycle. And in this masked split write transfer cycle, the
MSB of row address (AX8) to write data must be the same as that of the read transfer cycle or the split read
transfer cycle. In this cycle, the boundary split register operation using stopping columns is possible as with
split read transfer cycle.
RAS
CAS
Address
DT/OE
DSF1
SC
t (min)
STS t (min)
RST
t (min)
CST
t (min)
AST
Bi Ym Bj – 1
YjXi
Bj Yj
Note: Ym is the SAM start address in before SRT. Bi and Bj initiate the boundary address.
Figure 6 Split Transfer Limitation
Table 2 Stopping Column Boundary Table
Stop Address
Boundary Code Column Size A2 A3 A4 A5 A6 A7
B2 4 0 ×××××
B3 8 1 0 ××××
B4 16 1 1 0 ×××
B5 32 1 1 1 0 ××
B6 64 11110×
B7 128 111110
B8 256 111111
Notes: 1. A0, A1, and A8: H or L
2. ×: H or L
HM538253B/HM538254B Series
17
Stopping Column in Split Transfer Cycle: The HM538253B/HM538254B has the boundary split register
operation using stopping columns. If a CBRS cycle has been performed, split transfer cycle performs the
boundary operation. Figure 7 shows an example of boundary split register. (Boundary code is B7.)
First a read data transfer cycle is executed, and SAM start addresses A0 to A8 are set. The RAM data is
transferred to the SAM, and SAM serial read starts from the start address (Y1) on the lower SAM. After that,
a split read transfer cycle is executed, and the next start address (Y2) is set. The RAM data is transferred to
the upper SAM. When the serial read arrive at the first boundary after the split read transfer cycle, the next
read jumps to the start address (Y2) on the upper SAM (jump 1) and continues. Then the second split read
transfer cycle is executed, and another start address (Y3) is set. The RAM data is transferred to the lower
SAM. When the serial read arrive at the other boundary again, the next read jumps to the start address (Y3)
on the lower SAM. In stopping column, split transfer is needed for jump operation between lower SAM and
upper SAM.
Stopping Column Set Cycle (CBRS): Start a stopping column set cycle by driving CAS low, WE low, and
DSF1 high at the falling edge of R AS. Stopping column data (boundaries) are latched from address inputs on
the falling edge of RAS. To determine the boundary, A2 to A7 can be used, and A0, A1, and A8 don’t care.
In the HM538253B/HM538254B, 7 types of boundary (B2 to B8) can be set including the default case. (See
stopping column boundary table.) If A2 to A6 are set high and A7 is set low, the boundaries (B7) are
selected. Figure 6 shows the example. Once a CBRS is executed, next sprit transfer cycle data become
stopping columm data. Stopping columm is reset by CBBR.
Boundaries (B7)
Start Jump 1 Jump 2
Column size
128 bit
(Y1) (Y3) (Y2)
Lower SAM
256 bit Upper SAM
256 bit
Figure 7 Example of Boundary Split Register
Register Reset Cycle (CBRR): Start a register reset cycle (CBRR) by driving CAS low, WE high, and
DSF1 low at the falling edge of R AS. A CBRR can reset the persistent mask operation and stopping column
operation, so the HM538253B/HM538254B becomes the new mask operation and boundary code B8. When
a CBRR is executed for stopping column operation reset and split transfer operation, it needs to satisfy t STS
(min) and tRST (min) between RAS falling and SC rising.
HM538253B/HM538254B Series
18
No Reset CBR cycle (CBRN): This cycle becomes no reset CBR cycle (CBRN) by driving CAS low, WE
high and DSF1 high at the falling edge of RAS. The CBRN can only execute the refresh operation.
SAM Port Operation
Serial Read Cycle
SAM port is in read mode when the previous data transfer cycle is a read transfer cycle. Access is
synchronized with SC rising, and SAM data is output from SI/O. When SE is set high, SI/O becomes high
impedance, and the internal pointer is incremented by the SC rising. After indicating the last address (address
511), the internal pointer indicates address 0 at the next access.
Serial Write Cycle
If the previous data transfer cycle is a masked write transfer cycle, SAM port goes into write mode. In this
cycle, SI/O data is fetched into the data register at the SC rising edge like in the serial read cycle. If SE is
high, SI/O data isn’t fetched into the data register. The internal pointer is incremented by the SC rising, so SE
high can be used as mask data for SAM. After indicating the last address (address 511), the internal pointer
indicates address 0 at the next access.
Refresh
RAM Refresh
RAM, which is composed of dynamic circuits, requires refresh cycles to retain data. Refresh is executed by
accessing all 512 row addresses within 8 ms. There are three refresh cycles: (1) RAS-only refresh cycle, (2)
CAS-before-R AS (CBRN, CBRS, and CBRR) refresh cycle, and (3) Hidden refresh cycle. The cycles which
activate RAS, such as read/write cycles or transfer cycles, can also refresh the row address. Therefore, no
refresh cycle is required when all row addresses are accessed within 8 ms.
RAS-Only Refresh Cycle: R AS-only refresh cycle is executed by activating only the RAS cycle with C AS
fixed high after inputting the row address (refresh address) from external circuits. To distinguish this cycle
from a data transfer cycle, DT/OE must be high at the falling edge of RAS.
CBR Refresh Cycle: CBR refresh cycle (CBRN, CBRS and CBRR) are set by activating CAS before RAS.
In this cycle, the refresh address need not be input through external circuits because it is input through an
internal refresh counter. In this cycle, output is high impedance and power dissipation is low because CAS
circuits are not operating.
Hidden Refresh Cycle: Hidden refresh cycle executes CBR refresh with the data output by reactivating RAS
when DT/OE and CAS keep low in normal RAM read cycles.
SAM Refresh
SAM parts (data register, shift resister and selector), organized as fully static circuitry, require no refresh.
HM538253B/HM538254B Series
19
Absolute Maximum Ratings
Parameter Symbol Value Unit
Voltage on any pin relative to VSS VT–1.0 to +7.0 V
Supply voltage relative to VSS VCC –0.5 to +7.0 V
Short circuit output current Iout 50 mA
Power dissipation PT1.0 W
Operating temperature Topr 0 to +70 °C
Storage temperature Tstg –55 to +125 °C
Recommended DC Operating Conditions (Ta = 0 to +70°C)
Parameter Symbol Min Typ Max Unit Notes
Supply voltage VCC 4.5 5.0 5.5 V 1
Input high voltage VIH 2.4 — 6.5 V 1
Input low voltage VIL –0.5*2 — 0.8 V 1
Notes: 1. All voltage referred to VSS
2 –3.0 V for pulse width ≤ 10 ns.
HM538253B/HM538254B Series
20
DC Characteristics (Ta = 0 to +70°C, VCC = 5 V ± 10%, VSS = 0 V)
HM538253B/HM538254B
-7 -8 -10
Parameter Symbol Min Max Min Max Min Max Unit Test Conditions
Operating current ICC1 — 110 — 100 — 90 mA RAS, CAS
cycling
tRC = min
SC = VIL, SE =
VIH
ICC7 — 165 — 150 — 140 mA SE = VIL,
SC cycling
tSCC = min
Block write current ICC1BW — 115 — 105 — 90 mA RAS, CAS
cycling
tRC = min
SC = VIL, SE =
VIH
ICC7BW — 170 — 155 — 140 mA SE = VIL,
SC cycling
tSCC = min
Standby current ICC2 —7 —7 —7 mARAS, CAS = VIH SC = VIL, SE =
VIH
ICC8 —65—60— 55mA SE = VIL,
SC cycling
tSCC = min
RAS-only refresh
current ICC3 — 110 — 100 — 90 mA RAS cycling
CAS = VIH
tRC = min
SC = VIL, SE =
VIH
ICC9 — 165 — 150 — 135 mA SE = VIL,
SC cycling
tSCC = min
Fast page mode
current
(HM538253B) *3
ICC4 — 110 — 105 — 100 mA CAS cycling
RAS = VIL
tPC = min
SC = VIL, SE =
VIH
ICC10 — 160 — 155 — 150 mA SE = VIL,
SC cycling
tSCC = min
Fast page mode
block write current *3 ICC4BW — 130 — 125 — 120 mA CAS cycling
RAS = VIL
tPC = min
SC = VIL, SE =
VIH
ICC10BW — 185 — 175 — 165 mA SE = VIL,
SC cycling
tSCC = min
HM538253B/HM538254B Series
21
DC Characteristics (Ta = 0 to +70°C, VCC = 5 V ± 10%, VSS = 0 V) (cont)
HM538253B/HM538254B
-7 -8 -10
Parameter Symbol Min Max Min Max Min Max Unit Test Conditions
Hyper page mode
current
(HM538254B) *3
ICC4 — 130 — 120 — 110 mA CAS cycling
RAS = VIL
tPC = min
SC = VIL, SE =
VIH
ICC10 — 185 — 170 — 160 mA SE = VIL,
SC cycling
tSCC = min
Hyper page mode
block write current *3 ICC4BW — 155 — 140 — 130 mA
mA CAS cycling
RAS = VIL
tPC = min
SC = VIL, SE =
VIH
ICC10BW — 210 — 190 — 175 175 SE = VIL,
SC cycling
tSCC = min
CAS-before-RAS
refresh current ICC5 —85—75— 65mARAS cycling
tRC = min SC = VIL, SE =
VIH
ICC11 — 140 — 130 — 120 mA SE = VIL,
SC cycling
tSCC = min
Data transfer current ICC6 — 130 — 115 — 100 mA RAS, CAS
cycling
tRC = min
SC = VIL, SE =
VIH
ICC12 — 180 — 165 — 145 mA SE = VIL,
SC cycling
tSCC = min
Input leakage
current ILI –10 10 –10 10 –10 10 µA
Output leakage
current ILO –10 10 –10 10 –10 10 µA
Output high voltage VOH 2.4 — 2.4 — 2.4 — V IOH = –1 mA
Output low voltage VOL — 0.4 — 0.4 — 0.4 V IOL = 2.1 mA
Notes: 1. ICC depends on output load condition when the device is selected. ICC max is specified at the output
open condition.
2. Address can be changed once while RAS is low and CAS is high.
3. Address can be changed once in 1 page cycle (tPC).
HM538253B/HM538254B Series
22
Capacitance (Ta = 25°C, VCC = 5 V ± 10%, f = 1 MHz, Bias: Clock, I/O = VCC, Address =
VSS)
Parameter Symbol Typ Max Unit Note
Input capacitance (Address) CI1 — 5 pF 1
Input capacitance (Clocks) CI2 — 5 pF 1
Output capacitance (I/O, SI/O, QSF) CI/O — 7 pF 1
Note: 1. This parameter is sampled and not 100% tested.
AC Characteristics (Ta = 0 to +70°C, VCC = 5 V ± 10%, VSS = 0 V)*1, *16
Test Conditions
• Input rise and fall time: 5 ns
• Input pulse levels: VSS to 3.0 V
• Input timing reference levels: 0.8 V, 2.4 V
• Output timing reference levels: 0.8 V, 2.0 V
• Output load: RAM 1 TTL + CL (50 pF)
SAM, QSF 1 TTL + CL (30 pF) (Including scope and jig)
HM538253B/HM538254B Series
23
Common Parameter
HM538253B/HM538254B
-7 -8 -10
Parameter Symbol Min Max Min Max Min Max Unit Notes
Random read or write cycle time tRC 130 — 150 — 180 — ns
RAS precharge time tRP 50 — 60 — 70 — ns
RAS pulse width tRAS 70 10000 80 10000 100 10000 ns
CAS pulse width tCAS 20 — 20 — 25 — ns
Row address setup time tASR 0— 0— 0— ns
Row address hold time tRAH 10 — 10 — 10 — ns
Column address setup time tASC 0— 0— 0— ns
Column address hold time tCAH 12 — 15 — 15 — ns
RAS to CAS delay time tRCD 20 50 20 60 20 75 ns 2
RAS hold time referred to CAS tRSH 20 — 20 — 25 — ns
CAS hold time referred to RAS tCSH 70 — 80 — 100 — ns
CAS to RAS precharge time tCRP 10 — 10 — 10 — ns
Transition time (rise to fall) tT350 350 350 ns3
Refresh period tREF —8 —8 —8 ms
DT to RAS setup time tDTS 0— 0— 0— ns
DT to RAS hold time tDTH 10 — 10 — 10 — ns
DSF1 to RAS setup time tFSR 0— 0— 0— ns
DSF1 to RAS hold time tRFH 10 — 10 — 10 — ns
DSF1 to CAS setup time tFSC 0— 0— 0— ns
DSF1 to CAS hold time tCFH 12 — 15 — 15 — ns
Data-in to CAS delay time tDZC 0— 0— 0— ns4
Data-in to OE delay time tDZO 0— 0— 0— ns4
Output buffer turn-off delay referred to
CAS tOFF1 —15 —20 —20 ns5
Output buffer turn-off delay referred to
OE tOFF2 —15 —20 —20 ns5
HM538253B/HM538254B Series
24
Read Cycle (RAM), Page Mode Read Cycle
HM538253B/HM538254B
-7 -8 -10
Parameter Symbol Min Max Min Max Min Max Unit Notes
Access time from RAS tRAC — 70 — 80 — 100 ns 6, 7
Access time from CAS tCAC — 20 — 20 — 25 ns 7, 8
Access time from OE tOAC —20 —20 —25 ns7
Address access time tAA — 35 — 40 — 45 ns 7, 9
Read command setup time tRCS 0— 0— 0— ns
Read command hold time tRCH 0— 0— 0— ns10
Read command hold time referred to
RAS tRRH 0— 5— 10— ns10
RAS to column address delay time tRAD 15 35 15 40 15 55 ns 2
Column address to RAS lead time tRAL 35 — 40 — 45 — ns
Column address to CAS lead time tCAL 35 — 40 — 45 — ns
Page mode cycle time tPC 45 — 50 — 55 — ns
CAS precharge time tCP 7 — 10 — 10 — ns
Access time from CAS precharge tACP —40 —45 —50 ns
Page mode RAS pulse width tRASP 70 100000 80 100000 100 100000 ns
HM538253B/HM538254B Series
25
Write Cycle (RAM), Page Mode Write Cycle, Color Register Set Cycle
HM538253B/HM538254B
-7 -8 -10
Parameter Symbol Min Max Min Max Min Max Unit Notes
Write command setup time tWCS 0— 0— 0— ns11
Write command hold time tWCH 12 — 15 — 15 — ns
Write command pulse width tWP 12 — 15 — 15 — ns
Write command to RAS lead time tRWL 20 — 20 — 20 — ns
Write command to CAS lead time tCWL 20 — 20 — 20 — ns
Data-in setup time tDS 0— 0— 0— ns12
Data-in hold time tDH 12 — 15 — 15 — ns 12
WE to RAS setup time tWS 0— 0— 0— ns
WE to RAS hold time tWH 10 — 10 — 10 — ns
Mask data to RAS setup time tMS 0— 0— 0— ns
Mask data to RAS hold time tMH 10 — 10 — 10 — ns
OE hold time referred to WE tOEH 15 — 20 — 20 — ns
Page mode cycle time tPC 45 — 50 — 55 — ns
CAS precharge time tCP 7 — 10 — 10 — ns
CAS to data-in delay time tCDD 15 — 20 — 20 — ns 13
Page mode RAS pulse width tRASP 70 100000 80 100000 100 100000 ns
HM538253B/HM538254B Series
26
Read-Modify-Write Cycle
HM538253B/HM538254B
-7 -8 -10
Parameter Symbol Min Max Min Max Min Max Unit Notes
Read-modify-write cycle time tRWC 180 — 200 — 230 — ns
RAS pulse width (read-modify-write
cycle) tRWS 120 10000 130 10000 150 10000 ns
CAS to WE delay time tCWD 40 — 45 — 50 — ns 14
Column address to WE delay time tAWD 60 — 65 — 70 — ns 14
OE to data-in delay time tODD 15 — 20 — 20 — ns 12
Access time from RAS tRAC — 70 — 80 — 100 ns 6, 7
Access time from CAS tCAC — 20 — 20 — 25 ns 7, 8
Access time from OE tOAC —20 —20 —25 ns7
Address access time tAA — 35 — 40 — 45 ns 7, 9
RAS to column address delay time tRAD 15 35 15 40 15 55 ns
Read command setup time tRCS 0— 0— 0— ns
Write command to RAS lead time tRWL 20 — 20 — 20 — ns
Write command to CAS lead time tCWL 20 — 20 — 20 — ns
Write command pulse width tWP 12 — 15 — 15 — ns
Data-in setup time tDS 0— 0— 0— ns12
Data-in hold time tDH 12 — 15 — 15 — ns 12
OE hold time referred to WE tOEH 15 — 20 — 20 — ns
Refresh Cycle
HM538253B/HM538254B
-7 -8 -10
Parameter Symbol Min Max Min Max Min Max Unit Notes
CAS setup time (CAS-before-RAS
refresh) tCSR 10 — 10 — 10 — ns
CAS hold time (CAS-before-RAS
refresh) tCHR 10 — 10 — 10 — ns
RAS precharge to CAS hold time tRPC 10 — 10 — 10 — ns
HM538253B/HM538254B Series
27
Flash Write Cycle, Block Write Cycle, and Register Read Cycle
HM538253B/HM538254B
-7 -8 -10
Parameter Symbol Min Max Min Max Min Max Unit Notes
CAS to data-in delay time tCDD 15 — 20 — 20 — ns 13
OE to data-in delay time tODD 15 — 20 — 20 — ns 13
CBR Refresh with Register Reset
HM538253B/HM538254B
-7 -8 -10
Parameter Symbol Min Max Min Max Min Max Unit Notes
Split transfer setup time tSTS 20 — 20 — 25 — ns
Split transfer hold time referred to RAS tRST 70 — 80 — 100 — ns
Hyper Page Mode Cycle (HM538254B)
HM538254B
-7 -8 -10
Parameter Symbol Min Max Min Max Min Max Unit Notes
Column address to CAS lead time tCAL 25 — 30 — 35 — ns
Hyper page mode cycle time tPC 35 — 40 — 45 — ns
Hyper page CAS precharge time tCP 5 — 10 — 10 — ns
Hyper page data out hold time tDOH 4— 5— 5— ns
Data-out buffer turn-off time (RAS)t
RHZ —15 —20 —20 ns5
Data-out buffer turn-off time (CAS)t
CHZ —15 —20 —20 ns5
RAS to data-in delay time tRDD 20 — 20 — 20 — ns 13
HM538253B/HM538254B Series
28
Read Transfer Cycle
HM538253B/HM538254B
-7 -8 -10
Parameter Symbol Min Max Min Max Min Max Unit Notes
DT hold time referred to RAS tRDH 60 10000 65 10000 80 10000 ns
DT hold time referred to CAS tCDH 20 — 20 — 25 — ns
DT hold time referred to tADH 25 — 30 — 30 — ns
DT precharge time tDTP 20 — 20 — 30 — ns
DT to RAS delay time tDRD 60 — 70 — 80 — ns
SC to RAS setup time tSRS 15 — 20 — 30 — ns
1st SC to RAS hold time tSRH 70 — 80 — 100 — ns
1st SC to CAS hold time tSCH 25 — 25 — 25 — ns
1st SC to column address hold time tSAH 40 — 45 — 50 — ns
Last SC to DT delay time tSDD 5— 5— 5— ns
1st SC to DT hold time tSDH 10 — 13 — 15 — ns
DT to QSF delay time tDQD —30 —35 —35 ns15
QSF hold time referred to DT tDQH 5— 5— 5— ns
Serial data-in to 1st SC delay time tSZS 0— 0— 0— ns
Serial clock cycle time tSCC 25 — 28 — 30 — ns
SC pulse width tSC 5 — 10 — 10 — ns
SC precharge time tSCP 10 — 10 — 10 — ns
SC access time tSCA —20 —23 —25 ns15
Serial data-out hold time tSOH 5— 5— 5— ns
Serial data-in setup time tSIS 0— 0— 0— ns
Serial data-in hold time tSIH 15 — 15 — 15 — ns
RAS to column address delay time tRAD 15 35 15 40 15 55 ns
Column address to RAS lead time tRAL 35 — 40 — 45 — ns
RAS to QSF delay time tRQD —70 —75 —85 ns15
CAS to QSF delay time tCQD —35 —35 —35 ns15
QSF hold time referred to RAS tRQH 20 — 20 — 25 — ns
QSF hold time referred to CAS tCQH 5— 5— 5— ns
HM538253B/HM538254B Series
29
Masked Write Transfer Cycle
HM538253B/HM538254B
-7 -8 -10
Parameter Symbol Min Max Min Max Min Max Unit Notes
SC setup time referred to RAS tSRS 15 — 20 — 30 — ns
RAS to SC delay time tSRD 20 — 25 — 25 — ns
Serial output buffer turn-off time
referenced to RAS tSRZ 10 30 10 35 10 50 ns
RAS to serial data-in delay time tSID 30 — 35 — 50 — ns
RAS to QSF delay time tRQD —70 —75 —85 ns15
CAS to QSF delay time tCQD —35 —35 —35 ns15
QSF hold time referred to RAS tRQH 20 — 20 — 25 — ns
QSF hold time referred to CAS tCQH 5— 5— 5— ns
Serial clock cycle time tSCC 25 — 28 — 30 — ns
SC pulse width tSC 5 — 10 — 10 — ns
SC precharge time tSCP 10 — 10 — 10 — ns
SC access time tSCA —20 —23 —25 ns15
Serial data-out hold time tSOH 5— 5— 5— ns
Serial data-in setup time tSIS 0— 0— 0— ns
Serial data-in hold time tSIH 15 — 15 — 15 — ns
HM538253B/HM538254B Series
30
Split Read Transfer Cycle, Masked Split Write Transfer Cycle
HM538253B/HM538254B
-7 -8 -10
Parameter Symbol Min Max Min Max Min Max Unit Notes
Split transfer setup time tSTS 20 — 20 — 25 — ns
Split transfer hold time referred to RAS tRST 70 — 80 — 100 — ns
Split transfer hold time referred to CAS tCST 20 — 20 — 25 — ns
Split transfer hold time referred to
column address tAST 35 — 40 — 45 — ns
SC to QSF delay time tSQD —30 —30 —30 ns15
QSF hold time referred to SC tSQH 5— 5— 5— ns
Serial clock cycle time tSCC 25 — 28 — 30 — ns
SC pulse width tSC 5 — 10 — 10 — ns
SC precharge time tSCP 10 — 10 — 10 — ns
SC access time tSCA —20 —23 —25 ns15
Serial data-out hold time tSOH 5— 5— 5— ns
Serial data-in setup time tSIS 0— 0— 0— ns
Serial data-in hold time tSIH 15 — 15 — 15 — ns
RAS to column address delay time tRAD 15 35 15 40 15 55 ns
Column address to RAS lead time tRAL 35 — 40 — 45 — ns
Serial Read Cycle, Serial Write Cycle
HM538253B/HM538254B
-7 -8 -10
Parameter Symbol Min Max Min Max Min Max Unit Notes
Serial clock cycle time tSCC 25 — 28 — 30 — ns
SC pulse width tSC 5 — 10 — 10 — ns
SC precharge width tSCP 10 — 10 — 10 — ns
Access time from SC tSCA —20 —23 —25 ns15
Access time from SE tSEA —17 —20 —25 ns15
Serial data-out hold time tSOH 5— 5— 5— ns
Serial output buffer turn-off time referred
to SE tSHZ — 15 — 20 — 20 ns 5,17
SE to serial output in low-Z tSLZ 0 — 0 — 0 — ns 5,17
Serial data-in setup time tSIS 0— 0— 0— ns
HM538253B/HM538254B Series
31
Serial Read Cycle, Serial Write Cycle (cont)
HM538253B/HM538254B
-7 -8 -10
Parameter Symbol Min Max Min Max Min Max Unit Notes
Serial data-in hold time tSIH 15 — 15 — 15 — ns
Serial write enable setup time tSWS 0— 0— 0— ns
Serial wrtie enable hold time tSWH 15 — 15 — 15 — ns
Serial write disable setup time tSWIS 0— 0— 0— ns
Serial write disable hold time tSWIH 15 — 15 — 15 — ns
Notes: 1. AC measurements assume tT = 5 ns.
2. When tRCD > tRCD (max) and tRAD > tRAD (max), access time is specified by tCAC or tAA.
3. VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Transition time tT
is measured between VIH and VIL.
4. Data input must be floating before output buffer is turned on. In read cycle, read-modify-write cycle
and delayed write cycle, either tDZC (min) or tDZO (min) must be satisfied.
5. tRHZ (max), tCHZ (max), tOFF1 (max), tOFF2 (max), tSHZ (max) and tSLZ (min) are defined as the time at
which the output acheives the open circuit condition (VOH – 100 mV, VOL + 100 mV). This parameter
is sampled and not 100% tested.
6. Assume that tRCD ≤ tRCD (max) and tRAD ≤ tRAD (max). If tRCD or tRAD is greater than the maximum
recommended value shown in this table, tRAC exceeds the value shown.
7. Measured with a load circuit equivalent to 1 TTL loads and 50 pF.
8. When tRCD ≥ tRCD (max) and tRAD ≤ tRAD (max), access time is specified by tCAC.
9. When tRCD ≤ tRCD (max) and tRAD ≥ tRAD (max), access time is specified by tAA.
10.If either tRCH or tRRH is satisfied, operation is guaranteed. (HM538253)
If both tRCH and tRRH are satisfied, operation is guaranteed, (HM538254)
11.When tWCS ≥ tWCS (min), the cycle is an early write cycle, and I/O pins remain in an open circuit (high
impedance) condition.
12.These parameters are specified by the later falling edge of CAS or WE.
13.Either tCDD (min) or tODD (min) must be satisfied because output buffer must be turned off by CAS or
OE prior to applying data to the device when output buffer is on. (HM538253B)
Either tCDD (min), tODD (min) or tRDD (min) must be satisfied because the output buffer must be turned
off by CAS, OE or RAS prior to applying data to the device when output buffer is on. (HM538254B)
14.When tAWD ≥ tAWD (min) and tCWD ≥ tCWD (min) in read-modify-write cycle, the data of the selected
address outputs to an I/O pin and input data is written into the selected address. tODD (min) must be
satisfied because output buffer must be turned off by OE prior to applying data to the device.
15.Measured with a load circuit equivalent to 1 TTL loads and 30 pF.
16.After power-up, pause for 100 µs or more and execute at least 8 initialization cycle (normal memory
cycle or refresh cycle), then start operation. Hitachi recommends that least 8 initialization cycle is
CBRR for internal register reset.
17.When tSHZ and tSLZ are measured in the same VCC and Ta condition and tr and tf of SE are less than
5 ns, tSHZ < tSLZ + 5 ns.
18.After power-up, QSF output may be High-Z, so 1SC cycle is needed to be Low-Z it.
19.DSF 2 pin is open pin, but Hitachi recommends it is fixed low in all operation for the addition mode
in future.
HM538253B/HM538254B Series
32
20.XXX: H or L (H : VIH (min) ≤ VIN ≤ VIH (max), L : VIL (min) ≤ VIN ≤ VIL (max)
///////: Invalid Dout
Timing Waveforms*20
Read Cycle (HM538253B)
tRC
tRAS
tCSH
tRCD tRSHtCAS
tRAL tCAL
tCAH
tASC
tRAH
tASR
tRCS
tCAC
tAA
tRAC
tOAC
tDZC
tDZO
tDTH
tDTS
tFSR tRFH tFSC tCFH
tCDD
tOFF1
tOFF2
tRRH tRCH
tRP
tCRP
RAS
CAS
Address
WE
I/O
(Output)
DT/OE
DSF1
I/O
(Input)
Row Column
Valid Dout
tRAD
HM538253B/HM538254B Series
33
Fast Page Mode Read Cycle (HM538253B)
RAS
CAS
Address
WE
I/O
(Output)
DT/OE
DSF1
I/O
(Input)
tRC
tRASP tRP
tCRP
tRSH
tCAS
tCP
tPC
tCP
tRCD
tCSH
tRAD tCAL
tCAH
tRAH
tASR
tRCS tRCH tRCS tRCS
tRCH
tCAH
tASC tCAL tASC
tRAL tCAL
tCAH
tRRH
tRCH
tCAS
tCAS
tAA tOFF1
tACP
tCAC
tAA
tACP tOFF1
tCDD
tOAC
tDZC
tCDD
tOAC tOFF2
tDZC
tCDD
tOFF2
tOAC
tDZC
tDZO
tDTH
tFSR
tDTS
tRFH tFSC tCFH tFSC tCFH tFSC tCFH
tRAC
tAA
tCAC
tOFF1
tASC
tCAC
Row
Column
Valid
Dout Valid
Dout Valid Dout
Column Column
HM538253B/HM538254B Series
34
Write Cycle
Table 3 below applies to early write, delayed write, page mode write, and read-modify write.
Table 3 Write Cycle State
RAS CAS RAS RAS CAS
DSF1 DSF1 WE I/O I/O
Menu Cycle W1 W2 W3 W4 W5
RWM Write mask (new/old)
Write DQs to I/Os 0 0 0 Write mask*1 Valid data
BWM Write mask (new/old)
Block write 0 1 0 Write mask*2 Column mask*2
RW Normal write (no mask) 0 0 1 Don’t care*1 Valid data
BW Block write (no mask) 0 1 1 Don’t care*2 Column mask*2
LMR*4 Load write mask resister 1 0 1 Don’t care Write mask data*3
LCR*4 Load color resister 1 1 1 Don’t care Color data
Notes: 1.
WE Mode I/O data/RAS
Low New mask mode Mask
Persistent mask mode H or L (mask register used)
High No mask H or L
I/O Mask data (In new mask mode)
Low: Mask
High: Non mask
In persistent mask mode, I/O H or L
2. Reference Figure 2 use of block write.
3. I/O write mask data
Low: Mask
High: Non mask
4. Column Address: H or L
HM538253B/HM538254B Series
35
Early Write Cycle
tRC
RAS
CAS
Address
WE
I/O
(Output)
DT/OE
DSF1
I/O
(Input)
tRAS tRP
tCRP
tCSH tRSH
tCAS
tCAH
tASC
tRAH
tASR
tWS tWH tWCS tWCH
tDTS
tMH tDS tDH
tMS
tDTH
tFSR tFSC
tRFH tCFH
tRCD
High-Z
W3
Row Column
W5W4
W2W1
WI to W5: See write cycle state table for the logic states.
HM538253B/HM538254B Series
36
Delayed Write Cycle
RAS
CAS
Address
WE
I/O
(Output)
DT/OE
DSF1
I/O
(Input)
Row Column
W3
W5
W4
tRC
tRAS tRP
tCRP
tCSH
tRSH
tRCD tCAS
tASR tRAH tCAH
tRWL tCWL
tWP
tWS tWH
tMS tMH tDS
tDZC
tDTS tDTH
tFSR tRFH tFSC tCFH
tOEH
tDH
tOFF2
tODD
tASC
W1 W2
WI to W5: See write cycle state table for the logic states.
Fast/Hyper Page Mode Write Cycle (Early Write)
RAS
CAS
Address
WE
I/O
(Output)
DT/OE
DSF1
I/O
(Input)
tRC
tRASP
tCSH
tCAS
tRCD tCP tCAS
tPC tCP tRSH
tCAS tCRP
tRP
tCAH
tASC
tCAH
tASC
tCAH
tASC
tRAH
tASR
tWS tWH tWCS tWCH tWCS tWCH tWCH
tWCS
tDS tDH
tDH
tDS
tDH
tDS
tMH
tMS
tDTS tDTH
tFSR tRFHFSC tCFH tFSC tCFH tFSC tCFH
Row Column Column Column
W3
W5W4 W5 W5
W2W1 W2 W2
t
High-Z
WI to W5: See write cycle state table for the logic states.
HM538253B/HM538254B Series
37
Fast/Hyper Page Mode Write Cycle (Delayed Write)
RAS
CAS
Address
WE
I/O
(Output)
DT/OE
DSF1
I/O
(Input)
tRC
tRASP
tCSH
tRCD tCAS
tPC
tCP tCAS tCP tRSH
tCAS
tRP
tCRP
tCAH
tASC
tRWL tCWL
tWP
tCWL
tWP
tCWL
tWP
tCAH
tASC
tCAH
tASC
tRAH
tASR
tWS tWH
tMH
tMS
tDTS
tFSR tRFH tCFH
tFSC tFSC tCFH tFSC tCFH
tOEH
tDH
tDS tDH tDS tDH tDS
Row Column Column Column
W3
W4 W5 W5 W5
W1 W2 W2 W2
High-Z
WI to W5: See write cycle state table for the logic states.
Read-Modify-Write Cycle
RAS
CAS
Address
WE
I/O
(Output)
DT/OE
I/O
(Input)
Row Column
Valid Dout
W4
tRWC
W5
W3
tRWS tRP
tCRP
tRWL
tCWL
tWP
tAWD
tCWD
tRCS
tWS tWH
tCAC
tAA
tRAC
tOAC
tDZC
tMH
tMS
tOFF2
tODD
tDS tDH
tOEH
tDTS tDTH tDZO
tFSC
tRFH
tFSR tCFH
tRAD
tRCD
tASR tRAH tASC tCAH
DSF1 W2
W1
WI to W5: See write cycle state table for the logic states.
HM538253B/HM538254B Series
38
RAS-Only Refresh Cycle (HM538253B)
RAS
CAS
Address
I/O
(Output)
DT/OE
DSF1
I/O
(Input)
tRC
tRAS tRP
tRPC
tASR tRAH
tCRP
tCDD
tOFF1
tOFF2 tODD
tDTS tDTH
tFSR tRFH
Row
WE : H or L
CAS-Before-RAS Refresh Cycle (CBRN) (HM538253B)
RAS
CAS
Address
I/O
(Output)
DT/OE
DSF1
tRC
tRAS tRP
tRPC tCSR
tCHR
tRP
tRPC tCSR
tCP
tOFF1 High-Z
WE
tWS tWH
tFSR tRFH
Inhibit Falling Transition
SC : H or L
HM538253B/HM538254B Series
39
Hidden Refresh Cycle (HM538253B)
RAS
CAS
Address
I/O
(Output)
DT/OE
DSF1
I/O
(Input)
tRC
WE
tRAS
tRCD tRSH
tRAL
tRAD
tASR tASC tCAH
tRCS tRRH
tCAC
tAA
tCHR
tRAS
tRP
tRC
tRP
tCRP
tOFF1
tOFF2
tDZC tOAC
tDZO
tDTH
tDTS
tFSR tRFH tFSC tCFH
tRAH
Valid Dout
Row Column
tRAC
tFSR tRFH
tWS tWH
CAS-Before-RAS Set Cycle (CBRS)
RAS
CAS
Address
(A2-A7)
WE
I/O
(Output)
I/O
(Input)
DT/OE
DSF1
tRP
tRPC tCSR tCHR
tRAS tRP
tRC
tCRP
tASR tRAH
tWS tWH
tFSR tRFH
Stop Address
High-Z
*1
Inhibit falling transition
Note: A0, A1, A8: H or L
SC: H or L
HM538253B/HM538254B Series
40
CAS-Before-RAS Reset Cycle (CBRR)
RAS
CAS
Address
WE
I/O
(Output)
I/O
(Input)
DT/OE
DSF1
tRP
SC
tRPC tCSR tCHR
tRC
tRAS tRP
tCRP
tWS tWH
High-Z
tFSR tRFH
tSTS tRST
Bi*1 Bj-2 Bj-1 Bj*1
Inhibit falling transition
Notes: 1. Bi, Bj initiate the boundary addresses.
When a CBRR is executed for stopping column operation reset and split transfer
operation, it needs to satisfy tSTS (min) and tRST (min) between RAS falling and
SC rising.
2. Ym, Yn are the SAM start address in before SRT/MSWT.
HM538253B/HM538254B Series
41
Flash Write Cycle (HM538253B)
tRAS
RAS
CAS
Address
WE
I/O
(Output)
I/O
(Input)
DT/OE
DSF1
tRC tRP
tRCD
tCRP
tASR tRAH
tWH
tWS
tCDD
tOFF2 tODD tMS
tDTS tDTH
tMH
tRFH
tFSR
High-Z
Row
Mask Data
tOFF1
HM538253B/HM538254B Series
42
Register Read Cycle (Mask data, Color data) (HM538253B)
RAS
CAS
Address
I/O
(Output)
I/O
(Input)
DT/OE
DSF1
tRAS tRP
tRC
tCSH
tRCD tRSH
tCAS
tCRP
tASR tRAH
tWS tWH tRCS
tCAC
tRAC
tDZC tOAC
tDZO
tDTS tDTH
tFSR tRFH tFSC tCFH
tOFF2 tODD
tCDD
tOFF1
tRRH tRCH
WE
Valid Out
Row
*1
Note: 1. State of DFS1 at falling edge of CAS
State 01
Accessed
data Mask data
(LMR) Color data
(LCR)
HM538253B/HM538254B Series
43
Read Transfer Cycle 1
tRC
tRAS
tCSH
tRCD tRSH
tCAS
tCAH
tASC tRAL
tRAD
tASR tRAH
tWH
tWS
tDTS tCDH
tADH
tRDH
tDRD
tDTP
tSCC
tSCC
tSCC
tSCC tSDH
tSOH
tSCA tSCA
tSOH tSOH
tSCA
tSDD
tSCA tSOH
Previous Row New Row
tRP
RAS
CAS
Address
WE
I/O
(Output)
DT/OE
SC
SI/O
(Output)
SI/O
(Input)
tSOH
Valid Sout Valid Sout Valid Sout Valid Sout
High-Z
Row SAM Start
Address
tCRP
tFSR tRFH
tDQD
tDQH
DSF1
QSF SAM Address MSB
tSC tSCP
High-Z
Valid Sout
HM538253B/HM538254B Series
44
Read Transfer Cycle 2
tRAS
RAS
CAS
Address
WE
I/O
(Output)
DT/OE
DSF1
SC
SI/O
(Output)
QSF
SI/O
(Input)
tRC
tRSH
tCAS
tCSH
tRCD
tRAD
tRAH
tASR tASC tCAH
tWH
tWS
tRP
tCRP
tRAL
tDTS
tRFH
tFSR
tDRD
tDTP
tSRS
tSC tSAH
tSCH
tSDH tSCC
tSC tSCP
tSCA
tSCP
tSCA
tSOH
tSZS
tDQD
tDQH
tSRH
tSIH
tSIS Valid Sout
Row SAM Start
Address
High-Z
SAM Address MSB
Valid
Sin
tDTH
tRQD
tRQH
tCQD
tCQH
Inhibit Rising Transition
HM538253B/HM538254B Series
45
Masked Write Transfer Cycle
RAS
CAS
Address
WE
I/O
(Output)
QSF
DT/OE
DSF1
tRC
Note: 1. I/O mask data (In new mask mode)
Low: Mask
High: Non mask
I/O: H or L in persistent mask mode.
SC
SI/O
(Output)
SI/O
(Input)
I/O
(Input)
tRP
tCRP
tCSH
tRAS
tRSH
tCAS
tRCD
tASR tRAH tASC tCAH
Row SAM Start
Address
tWS tWH
tDTS tDTH
tFSR tRFH
tSRS
tSC
tSCA tSRZ tSID
tSOH High-Z
ValidValid
tCQD
tCQH
tRQH
SAM Address MSB
tMS tMH
I/O Mask Data*1
Valid Sin Valid Sin
tSRD tSCC
tSCP
tSC
tSCP
tSIS tSIH tSIS tSIH
tRQD
High-Z
Inhibit Rising Transition
HM538253B/HM538254B Series
46
Split Read Transfer Cycle (HM538253B)
t
RC
RAS
CAS
Address
WE
I/O
(Output)
DT/OE
DSF1
SI/O
(Output)
QSF
SI/O
(Input)
SC
t
RAS
t
RP
t
CSH
t
RSH
t
RCD
t
CAS
t
ASC
t
RAH
t
ASR
t
WS
t
WH
t
OFF1
t
DTS
t
DTH
t
FSR
t
RFH
t
RST
t
AST
t
CST
t
SCC
t
SC
t
SCP
t
STS
t
SQD
t
SQH
t
SQD
t
SQH
SAM Address MSB
Valid
Sout Valid
Sout Valid
Sout Valid
Sout
Valid Sout
Bi
High-Z
Row
SAM Start
Address Yi
t
CAH
t
RAL
t
RAD
t
SCA
t
SOH
t
SOH
t
SCA
Valid
Sout
t
CRP
t
CRP
*2
Ym
*1
Ym + 1 Ym + 2 Bj – 2 Bj – 1 Bj
*2
Yi
High-Z
Notes: 1. Ym is the SAM start address in before SRT.
2. Bi, Bj initiate the boundary address.
3. A8: H or L, and upper SAM or lower SAM is set automatically by the internal circuit.
SAM start address can’t set on the boundary address.
HM538253B/HM538254B Series
47
Masked Split Write Transfer Cycle (HM538253B)
RAS
Address
WE
I/O
(Output)
I/O
(Input)
DT/OE
tRC
SC
CAS
DSF1
SI/O
(Output)
QSF
SI/O
(Input)
tRP
tRAS
tCSH tRSH
tCAS
tRCD
tASR tRAH tASC tCAH
tWS tWH
Row SAM Start
Address Yi
tOFF1
tDTS tDTH
tFSR tRFH
tCST
tAST
tRST
tSCC
tSCP
tSC
tSTS
tSIHtSIS tSIH
tSIS tSIH
tSIS
Valid
Sin Valid
Sin Valid
Sin Valid
Sin Valid
Sin Valid
Sin
tSQD
tSQH
tMH
tMS
tCDD
SAM Address MSB
I/O Mask Data
*3
High-Z
Bi*2
Ym*1 Ym+1 Ym+2
Bj-2 Bj-1 Bj*2 Yi
Valid
Sin
tSQD
tSQH
Notes: 1.
2.
3.
4.
Ym is the SAM start address in before MSWT.
Bi, Bj initiate the boundary address.
I/O Mask data (In new mask mode)
Low: Mask
High: Non mask
I/O: H or L in persistent mask mode.
A8: H or L, and upper SAM or lower SAM is set automatically by the internal circuit.
SAM start address can’t set on the boundary address.
HM538253B/HM538254B Series
48
Serial Read Cycle
SE
SC
SI/O
(Output)
tSCC
tSCP
tSC
tSCA
tSOH tSHZ
tSC tSCP tSC
tSEA
tSCA
tSCP tSC
tSCA
tSOH
Valid Sout Valid Sout Valid Sout Valid
Sout
tSCC tSCC
tSLZ
Serial Write Cycle
SE
SC
SI/O
(Input) Valid Sin Valid Sin Valid Sin
tSWH tSWIS tSWIH tSWS
tSCC
tSC tSCP
tSIS tSIH
tSCC tSCP
tSC tSCC
tSC tSCP tSC
tSIS tSIH
tSIH
tSIS
Read Cycle (HM538254B)
tRC
tRAS
tCSH
tRCD tRSHtCAS
tRAL tCAL
tCAH
tASC
tRAH
tASR
tRCS
tCAC
tAA
tRAC
tOAC
tDZC
tDZO
tDTH
tDTS
tFSR tRFH tFSC tCFH
tCDD
tCHZ
tOFF2
tRRH tRCH
tRP
tCRP
RAS
CAS
Address
WE
I/O
(Output)
DT/OE
DSF1
I/O
(Input)
Row Column
Valid Dout
tRAD
tODD
tRDD
tRHZ
HM538253B/HM538254B Series
49
Hyper Page Mode Read Cycle (HM538254B)
RAS
CAS
Address
WE
I/O
(Output)
DT/OE
DSF1
I/O
(Input)
tRC
tRASP tRP
tCRP
tRSH
tCAS
tCP
tPC
tCP
tRCD
tCSH
tRAD tCAL
tCAH
tRAH
tASR
tRCS
tCAH
tASC tCAL tASC
tRAL tCAL
tCAH
tRRH tRCH
tCAS
tCAS
tAA
tACP
tCAC
tAA
tACP
tRHZ
tCDD
tOAC
tDZC
tDZO
tDTH
tFSR
tDTS
tRFH tFSC tCFH tFSC tCFH tFSC tCFH
tRAC
tAA
tCAC
tASC
tCAC
Row
Column
Valid Dout Valid Dout
Column Column
Valid Dout
tCHZ
tODD
tRDD
tDOH tDOH
tOFF2
RAS-Only Refresh Cycle (HM538254B)
RAS
CAS
Address
I/O
(Output)
DT/OE
DSF1
I/O
(Input)
tRC
tRAS tRP
tRPC
tASR tRAH
tCRP
tCDD
tCHZ
tOFF2 tODD
tDTS tDTH
tFSR tRFH
Row
WE : H or L
HM538253B/HM538254B Series
50
CAS-Before-RAS Refresh Cycle (CBRN) (HM538254B)
RAS
CAS
Address
I/O
(Output)
DT/OE
DSF1
tRC
tRAS tRP
tRPC tCSR
tCHR
tRP
tRPC tCSR
tCP
tCHZ High-Z
WE
tWS tWH
tFSR tRFH
tRHZ
Inhibit Falling Transition
SC : H or L
Hidden Refresh Cycle (HM538254B)
RAS
CAS
Address
I/O
(Output)
DT/OE
DSF1
I/O
(Input)
tRC
WE
tRAS
tRCD tRSH
tRAL
tRAD
tASR tASC tCAH
tRCS tRRH
tCAC
tAA
tCHR
tRAS
tRP
tRC
tRP
tCRP
tRHZ
tOFF2
tDZC tOAC
tDZO
tDTH
tDTS
tFSR tRFH tFSC tCFH
tRAH
Valid Dout
Row Column
tRAC
tFSR tRFH
tWS tWH
tCHZ
HM538253B/HM538254B Series
51
Flash Write Cycle (HM538254B)
tRAS
RAS
CAS
Address
WE
I/O
(Output)
I/O
(Input)
DT/OE
DSF1
tRC tRP
tRCD
tCRP
tASR tRAH
tWH
tWS
tCDD
tOFF2 tODD tMS
tDTS tDTH
tMH
tRFH
tFSR
High-Z
Row
Mask Data
tCHZ
HM538253B/HM538254B Series
52
Register Read Cycle (Mask data, Color data) (HM538254B)
RAS
CAS
Address
I/O
(Output)
I/O
(Input)
DT/OE
DSF1
tRAS tRP
tRC
tCSH
tRCD tRSH
tCAS
tCRP
tASR tRAH
tWS tWH tRCS
tCAC
tRAC
tDZC tOAC
tDZO
tDTS tDTH
tFSR tRFH tFSC tCFH
tOFF2
tODD
tCDD
tRHZ
tRRH tRCH
WE
Valid Out
Row
*1
tCHZ
tRDD
Note: 1. State of DFS1 at falling edge of CAS
State 01
Accessed
data Mask data
(LMR) Color data
(LCR)
HM538253B/HM538254B Series
53
Split Read Transfer Cycle (HM538254B)
t
RC
RAS
CAS
Address
WE
I/O
(Output)
DT/OE
DSF1
SI/O
(Output)
QSF
SI/O
(Input)
SC
t
RAS
t
RP
t
CSH
t
RSH
t
RCD
t
CAS
t
ASC
t
RAH
t
ASR
t
WS
t
WH
t
CHZ
t
DTS
t
DTH
t
FSR
t
RFH
t
RST
t
AST
t
CST
t
SCC
t
SC
t
SCP
t
STS
t
SQD
t
SQH
t
SQD
t
SQH
SAM Address MSB
Valid
Sout Valid
Sout Valid
Sout Valid
Sout
Valid Sout
Bi
High-Z
Row
SAM Start
Address Yi
t
CAH
t
RAL
t
RAD
t
SCA
t
SOH
t
SOH
t
SCA
Valid
Sout
t
CRP
t
CRP
*2
Ym
*1
Ym + 1 Ym + 2 Bj – 2 Bj – 1 Bj
*2
Yi
High-Z
Notes: 1. Ym is the SAM start address in before SRT.
2. Bi, Bj initiate the boundary address.
3. A8: H or L, and upper SAM or lower SAM is set automatically by the internal circuit.
SAM start address can’t on the boundary address.
HM538253B/HM538254B Series
54
Masked Split Write Transfer Cycle (HM538254B)
RAS
Address
WE
I/O
(Output)
I/O
(Input)
DT/OE
tRC
SC
CAS
DSF1
SI/O
(Output)
QSF
SI/O
(Input)
tRP
tRAS
tCSH tRSH
tCAS
tRCD
tASR tRAH tASC tCAH
tWS tWH
Row SAM Start
Address Yi
tCHZ
tDTS tDTH
tFSR tRFH
tCST
tAST
tRST
tSCC
tSCP
tSC
tSTS
tSIH
tSIS tSIH
tSIS tSIH
tSIS
Valid
Sin Valid
Sin Valid
Sin Valid
Sin Valid
Sin Valid
Sin
tSQD
tSQH
tMH
tMS
tCDD
SAM Address MSB
I/O Mask Data
*3
High-Z
Bi*2
Ym*1 Ym+1 Ym+2
Bj-2 Bj-1 Bj*2 Yi
Valid
Sin
tSQD
tSQH Invalid
Dout
Notes: 1.
2.
3.
4.
Ym is the SAM start address in before MSWT.
Bi, Bj initiate the boundary address.
I/O Mask data (In new mask mode)
Low: Mask
High: Non mask
I/O: H or L in persistent mask mode.
A8: H or L, and upper SAM or lower SAM is set automatically by the internal circuit.
SAM start address can’t set or the boundary address.
HM538253B/HM538254B Series
55
Package Dimensions
HM538253BJ/HM538254BJ Series (CP-40D) Unit: mm
9.40 ± 0.25
120
0.43 ± 0.10
3.50 ± 0.26
+ 0.31
– 0.14
2.30
21
40 26.16 Max
25.80
0.74
10.16 ± 0.13
11.18 ± 0.13
1.30 Max
0.10
0.80 +0.25
–0.17
1.27
HM638253BTT/HM538254BTT Series (TTP-44/40DA) Unit: mm
0.21 M
44 23
122
18.41
18.81 Max
0.30 ± 0.10
1.20 Max
10.16
11.76 ± 0.20
0 – 5°
1.005 Max
0.17 ± 0.05
10 13
3235
0.80
0.50 ± 0.10
0.80
0.10
2.40
0.13 ± 0.05
