ISL8484IUZ-T - Intersil Corporation

FN6128.5

ISL8484

Ultra Low ON-Resistance, +1.65V to +4.5V,

Single Supply, Dual SPDT Analog Switch

The Intersil ISL8484 device is a low ON-resist ance, low

voltage, bidirectional, dual single-pole/double-throw (SPDT)

analog switch designed to operate from a single +1.65V to

+4.5V supply. Targeted applications include battery powered

equipment that benefit from low rON (0.29Ω) and fast

switching speeds (tON = 40ns, tOFF = 20ns). The digital logic

input is 1.8V logi c-comp atible when using a single +3V supp ly.

With a supply voltage of 4.2V and logic high voltage of 2.85V

at both logic inputs, the part draws only 12µA max of I+

current.

Cell phones, for example, often face ASIC function ality

limitations. The number of analog inpu t or GPIO pins may be

limited and digital ge ometri es are not w ell suited to analog

switch performance. This part may be use d to “mux-in”

additional functionality wh ile reducin g ASIC design risk. The

ISL8484 is of fered in small form factor p ackag es, alleviating

board space limi t ations.

The ISL8484 is a committed dual single-pole/doub le-thro w

(SPDT) that consist of two normally open (NO) and two

normally closed (NC) switches. This configuration can be

used as a dual 2-to-1 multi-plexer. The ISL8484 is pin

compatible with the MAX4684 and MAX4685.

Features

• Pin Compatible Replacement for the MAX4684 and

MAX4685

• ON-Resistance (rON)

- V+ = +4.3V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.29Ω

- V+ = +3.0V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.33Ω

- V+ = +1.8V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.55Ω

•r

ON Matching Between Channels . . . . . . . . . . . . . . . . .0.06Ω

•r

ON Flatness Across Signal Range. . . . . . . . . . . . . . . .0.03Ω

• Single Supply Operation . . . . . . . . . . . . . . . +1.65V to +4.5V

• Low Power Consumption (PD). . . . . . . . . . . . . . .<0.45µW

• Fast Switching Action (V+ = +4.3V)

-t

ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40ns

-t

OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20ns

• ESD HBM Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>8kV

• Guaranteed Break-Before-Make

• 1.8V Logic Compatible (+3V supply)

• Low I+ Current when VINH is not at the V+ Rail

• Available in 10 Ld 3x3 TDFN and 10 Ld MSOP

• Pb-Free Available (RoHS Compliant)

Applications

• Battery-powered, Handheld, and Portable Equipment

- Cellular/mobile Phones

- Pagers

- Laptops, Notebooks, Palmtops

• Portable Test and Measurement

• Medical Equipment

• Audio and Video Switching

Related Literature

• Technical Brief TB3 63 “Guidelines for Handling and

Processing Moisture Sensitive Surface Mount Devices

(SMDs)”

• Application Note AN557 “Recommended Test Procedures

for Analog Switches”

TABLE 1. FEATURES AT A GLANCE

ISL8484

NUMBER OF SWITCHES 2

SW SPDT or 2-1 MUX

4.3V rON 0.29Ω

4.3V tON/tOFF 40ns/20ns

3V rON 0.33Ω

3V tON/tOFF 50ns/27ns

1.8V rON 0.55Ω

1.8V tON/tOFF 70ns/54ns

Packages 10 Ld 3x3 Thin DFN, 10 Ld MSOP

Data Sheet May 12, 2008

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774 |Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

2FN6128.5

May 12, 2008

Pinout (Note 1)

ISL8484

(10 LD TDFN, MSOP)

TOP VIEW

NOTE:

1. Switches Shown for Logic “0” Input.

V+

NO1

COM1

IN1

NC1

NO2

COM2

IN2

NC2

GND

Truth Table

LOGIC NC1 and NC2 NO1 and NO2

0ONOFF

1OFFON

NOTE: Logic “0” ≤0.5V. Logic “1” ≥1.4V with a 3V supply.

Pin Descriptions

PIN FUNCTION

V+ System Power Supply Input (+1.65V to +4.5V)

GND Ground Connection

INx Digital Control Input

COMx Analog Switch Common Pin

NOx Analog Switch Normally Open Pin

NCx Analog Switch Normally Closed Pin

Ordering Information

PART NUMBER PART MARKING TEMP. RANGE

(°C) PACKAGE PKG.

DWG. #

ISL8484IR* 484 -40 to +85 10 Ld 3x3 TDFN L10.3x3A

ISL8484IU* 8484 -40 to +85 10 Ld MSOP M10.118

ISL8484IRZ*

(Note) 484Z -40 to +85 10 Ld 3x3 TDFN

(Pb-free) L10.3x3A

ISL8484IUZ*

(Note) 8484Z -40 to +85 10 Ld MSOP

(Pb-free) M10.118

*Add “-T” suffix for tape and reel. Please refer to TB347 for details on reel specifications.

NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and 100%

matte tin plate PLUS ANNEAL - e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations.

Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J

STD-020.

ISL8484

3FN6128.5

May 12, 2008

Absolute Maximum Ratings Thermal Information

V+ to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 5.5V

Input Voltages

NO, NC, IN (Note 2). . . . . . . . . . . . . . . . . . . . . -0.5 to ((V+) + 0.5V)

Output Voltages

COM (Note 2). . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to ((V+) + 0.5V)

Continuous Current NO, NC, or COM . . . . . . . . . . . . . . . . . ±300mA

Peak Current NO, NC, or COM

(Pulsed 1ms, 10% Duty Cycle, Max) . . . . . . . . . . . . . . . . . . ±500mA

ESD Rating:

Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>8kV

Machine Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>500V

Charged Device Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . >1.4kV

Thermal Resistance (Typical) θJA (°C/W) θJC (°C/W)

10 Ld 3x3 TDFN Package (Notes 3, 4) 52 11

10 Ld MSOP Package (Note 5) . . . . . . 140 N/A

Maximum Junction Temperature (Plastic Package). . . . . . . +150°C

Maximum Storage Temperature Rang e . . . . . . . . . . . -65°C to +150°C

Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below

http://www.intersil.com/pbfree/Pb-FreeReflow.asp

Operating Conditions

Temperature Range. . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C

CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and

result in failures not covered by warranty.

NOTES:

2. Signals on NC, NO, IN, or COM exceeding V+ or GND are clamped by internal diodes. Limit forward diode current to maximum current ratings.

3. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See

Tech Brief TB379.

4. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside.

5. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.

Electrical Specifications - 4.3V Supply Test Conditions: V+ = +3.9V to +4.5V, GND = 0V, VINH = 1.4V, VINL = 0.5V (Note 6),

Unless otherwise specified.

PARAMETER TEST CONDITIONS TEMP

(°C) MIN

(Notes 7, 1 1) TYP MAX

(Notes 7, 1 1) UNITS

ANALOG SWITCH CHARACTERISTICS

Analog Signal Range, VANALOG Full 0 - V+ V

ON-Resistance, rON V+ = 3.9V, ICOM = 100mA, VNO or VNC = 0V to V+

(Figure 5, Note 9) 25 - 0.30 0.5 Ω

Full - 0.35 0.7 Ω

rON Matching Between Channels,

ΔrON V+ = 3.9V, ICOM = 100mA, VNO or VNC = Voltage

at max RON (Note 9, 10) 25 - 0.06 0.07 Ω

Full - 0.08 0.08 Ω

rON Flatness, rFLAT(ON) V+ = 3.9V, ICOM = 100mA, VNO or VNC = 0V to V+

(Note 8, 9) 25 - 0.03 0.15 Ω

Full - 0.04 0.15 Ω

NO or NC OFF Leakage Current,

INO(OFF) or INC(OFF) V+ = 4.5V, VCOM = 0.3V , 3V , VNO or VNC = 3V, 0.3V 25 -100 - 100 nA

Full -195 - 195 nA

COM ON Leakage Current,

ICOM(ON) V+ = 4.5V , VCOM = 0.3V , 3V , or VNO or VNC = 0.3V,

3V, or Floating 25 -100 - 100 nA

Full -195 - 195 nA

DYNAMIC CHARACTERISTICS

Turn-ON Time, tON V+ = 3.9V , VNO or VNC = 3.0V , RL = 50Ω, CL = 35pF

(Figure 1) 25 - 40 - ns

Full - 50 - ns

Turn-OFF Time, tOFF V+ = 3.9V, VNO or VNC = 3. 0V , RL = 50Ω, CL = 35pF

(Figure 1) 25 - 20 - ns

Full - 30 - ns

Break-Before-Make Time Delay, tDV+ = 4.5V, VNO or VNC = 3.0V, RL = 50Ω, CL = 35pF

(Figure 3) Full - 8 - ns

Charge Injection, Q CL = 1.0nF, VG = 0V, RG = 0Ω (Figure 2) 25 - 170 - pC

OFF Isolation RL = 50Ω, CL = 5pF, f = 100kH z, VCOM = 1VRMS

(Figure 4) 25 - 62 - dB

Crosstalk (Channel-to-Channel) RL = 50Ω, CL = 5pF, f = 100kHz, VCOM = 1VRMS

(Figure 6) 25 - -85 - dB

ISL8484

4FN6128.5

May 12, 2008

Total Harmonic Distortion f = 20Hz to 20kHz, VCOM = 2VP-P, RL = 600Ω 25 - 0.005 - %

NO or NC OFF Capacitance, COFF f = 1MHz, VNO or VNC = VCOM = 0V (Figure 7) 25 - 62 - pF

COM ON Capacitance, CCOM(ON) f = 1MHz, VNO or VNC = VCOM = 0V (Figure 7) 25 - 176 - pF

POWER SUPPLY CHARACTERISTICS

Power Supply Range Full 1.65 - 4.5 V

Positive Supply Current, I+ V+ = +4.5V, VIN = 0V or V+ 25 - - 0.1 µA

Full - - 1 µA

Positive Supply Current, I+ V+ = +4.2V, VIN = 2.85V 25 - - 12 µA

DIGITAL INPUT CHARACTERISTICS

Input Voltage Low, VINL Full - - 0.5 V

Input Voltage High, VINH Full 1.4 - - V

Input Current, IINH, IINL V+ = 4.5V, VIN = 0V or V+ (Note 9) Full -0.5 - 0.5 µA

Electrical Specifications - 3V Supply Test Conditions: V+ = +2.7V to +3.3V, GND = 0V, VINH = 1.4V, VINL = 0.5V (Note 6),

Unless otherwise specified.

PARAMETER TEST CONDITIONS TEMP

(°C) MIN

(Notes 7, 1 1) TYP MAX

(Notes 7, 11) UNITS

ANALOG SWITCH CHARACTERISTICS

Analog Signal range, VANALOG Full 0 - V+ V

ON-Resistance, rON V+ = 2.7V , ICOM = 100mA, VNO or VNC = 0V to V+

(Figure 5) 25 - 0.35 0.5 Ω

Full - - 0.7 Ω

rON Matching Between Channels,

ΔrON V+ = 2.7V, ICOM = 100mA, VNO or VNC = Voltage

at max RON (Note 10) 25 - 0.06 0.07 Ω

Full - - 0.08 Ω

rON Flatness, rFLAT(ON) V+ = 2.7V, ICOM = 100mA, VNO or VNC = 0V to V+

(Note 8) 25 - 0.03 0.15 Ω

Full - - 0.15 Ω

NO or NC OFF Leakage Current,

INO(OFF) or INC(OFF) V+ = 3.3V , VCOM = 0.3V, 3V, VNO or VNC = 3V, 0.3V 25 - 0.9 - nA

Full - 30 - nA

COM ON Leakage Current,

ICOM(ON) V+ = 3.3V, VCOM = 0.3V , 3V, or VNO or VNC = 0.3V,

3V, or Floating 25 - 0.8 - nA

Full - 30 - nA

DYNAMIC CHARACTERISTICS

Turn-ON Time, tON V+ = 2.7V , VNO or VNC = 1.5V , RL = 50Ω, CL = 35pF

(Figure 1) 25 - 50 - ns

Full - 60 - ns

Turn-OFF Time, tOFF V+ = 2.7V , VNO or VNC = 1.5V , RL = 50Ω, CL = 35pF

(Figure 1) 25 - 27 - ns

Full - 35 - ns

Break-Before-Make Time Delay, tDV+ = 3.3V , VNO or VNC = 1.5V , RL = 50Ω, CL = 35pF

(Figure 3) Full - 9 - ns

Charge Injection, Q CL = 1.0nF, VG = 0V, RG = 0Ω (Figure 2) 25 - 94 - pC

OFF Isolation RL = 50Ω, CL = 5pF, f = 100kHz, VCOM = 1VRMS

(Figure 4) 25 - 62 - dB

Crosstalk (Channel-to-Channel) RL = 50Ω, CL = 5pF, f = 100kHz, VCOM = 1VRMS,

(Figure 6) 25 - -85 - dB

Total Harmonic Distortion f = 20Hz to 20kHz, VCOM = 2VP-P, RL = 600Ω 25 - 0.005 - %

Electrical Specifications - 4.3V Supply Test Conditions: V+ = +3.9V to +4.5V, GND = 0V, VINH = 1.4V, VINL = 0.5V (Note 6),

Unless otherwise specified.

PARAMETER TEST CONDITIONS TEMP

(°C) MIN

(Notes 7, 1 1) TYP MAX

(Notes 7, 1 1) UNITS

ISL8484

5FN6128.5

May 12, 2008

NO or NC OFF Capacitance, COFF f = 1MHz, VNO or VNC = VCOM = 0V (Figure 7) 25 - 65 - pF

COM ON Capacitance, CCOM(ON) f = 1MHz, VNO or VNC = VCOM = 0V (Figure 7) 25 - 181 - pF

POWER SUPPLY CHARACTERISTICS

Positive Supply Current, I+ V+ = +3.6V, VIN = 0V or V+ 25 - 0.01 - µA

Full - 0.52 - µA

DIGITAL INPUT CHARACTERISTICS

Input Voltage Low, VINL 25 - - 0.5 V

Input Voltage High, VINH 25 1.4 - - V

Input Current, IINH, IINL V+ = 3.3V, VIN = 0V or V+ (Note 9) Full -0.5 - 0.5 µA

Electrical Specifications - 1.8V Supply Test Conditions: V+ = +1.65V to +2V, GND = 0V, VINH = 1.0V, VINL = 0.4V (Note 6),

Unless otherwise specified.

PARAMETER TEST CONDITIONS TEMP

(°C) MIN

(Notes 7, 1 1) TYP MAX

(Notes 7, 11) UNITS

ANALOG SWITCH CHARACTERISTICS

Analog Signal Range, VANALOG Full 0 - V+ V

ON-Resistance, rON V+ = 1.65V, ICOM = 100mA, VNO or VNC = 0V to V+

(Figure 5) 25 - 0.7 0.8 Ω

Full - - 0.85 Ω

DYNAMIC CHARACTERISTICS

Turn-ON Time, tON V+ = 1.65V, VNO or VNC = 1.0V , RL = 50Ω, CL = 35pF

(Figure 1) 25 - 70 - ns

Full - 80 - ns

Turn-OFF Time, tOFF V+ = 1.65V , VNO or VNC = 1.0V , RL = 50Ω, CL = 35pF

(Figure 1) 25 - 54 - ns

Full - 65 - ns

Break-Before-Make Time Delay, tDV+ = 2.0V, VNO or VNC = 1.0V, RL = 50Ω, CL = 35pF

(Figure 3) Full - 10 - ns

Charge Injection, Q CL = 1.0nF, VG = 0V, RG = 0Ω (Figure 2) 25 - 42 - pC

NO or NC OFF Capacitance, COFF f = 1MHz, VNO or VNC = VCOM = 0V (Figure 7) 25 - 70 - pF

COM ON Capacitance, CCOM(ON) f = 1MHz, VNO or VNC = VCOM = 0V (Figure 7) 25 - 186 - pF

DIGITAL INPUT CHARACTERISTICS

Input Voltage Low, VINL 25 - - 0.4 V

Input Voltage High, VINH 25 1.0 - - V

Input Current, IINH, IINL V+ = 2.0V, VIN = 0V or V+ (Note 9) Full -0.5 - 0.5 µA

NOTES:

6. VIN = input voltage to perform proper function.

7. The algebraic convention, whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet.

8. Flatness is defined as the difference between maximum and minimum value of ON-resistance over the specified analog signal range.

9. Limits established by characterization and are not production tested.

10. RON matching between channels is calculated by subtracting the channel with the highest max rON value from the channel with lowest max rON

value, between NC1 and NC2 or between NO1 and NO2.

1 1. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits est ablished by characterization

and are not production tested.

Electrical Specifications - 3V Supply Test Conditions: V+ = +2.7V to +3.3V, GND = 0V, VINH = 1.4V, VINL = 0.5V (Note 6),

Unless otherwise specified. (Continued)

PARAMETER TEST CONDITIONS TEMP

(°C) MIN

(Notes 7, 1 1) TYP MAX

(Notes 7, 11) UNITS

ISL8484

6FN6128.5

May 12, 2008

Test Circuits and Waveforms

Logic input waveform is inverted for switches that have the opposite

logic sense.

FIGURE 1A. MEASUREMENT POINTS

Repeat test for all switches. CL includes fixture and stray

capacitance.

FIGURE 1B. TEST CIRCUIT

FIGURE 1. SWITCHING TIMES

FIGURE 2A. MEASUREMENT POINTS FIGURE 2B. TEST CIRCUIT

FIGURE 2. CHARGE INJECTION

FIGURE 3A. MEASUREMENT POINTS

Repeat test for all switches. CL includes fixture and stray

capacitance. FIGURE 3B. TEST CIRCUIT

FIGURE 3. BREAK-BEFORE-MAKE TIME

50%

tr < 5ns

tf < 5ns

tOFF

90%

V+

VNO

tON

LOGIC

INPUT

SWITCH

INPUT

SWITCH

OUTPUT

90%

VOUT

VOUT V(NO or NC) rL

rLrON()

--------------------------

SWITCH

INPUT

LOGIC

INPUT

VOUT

RL CL

COM

NO OR NC

50Ω35pF

GND

V+ C

VOUT

ΔVOUT

ON OFF ON

Q = ΔVOUT x CL

SWITCH

OUTPUT

LOGIC

INPUT

V+

VOUT

VGGND

COM

NO OR NC

V+ C

LOGIC

INPUT

Repeat test for all switches.

90%

V+

LOGIC

INPUT

SWITCH

OUTPUT 0V

VOUT

LOGIC

INPUT

COM

RLCL

VOUT

35pF

50Ω

V+

GND

VNX

ISL8484

7FN6128.5

May 12, 2008

Detailed Description

The ISL8484 is a bidirectional, dual single pole/double throw

(SPDT) analog switch that offers precise switching capability

from a single 1.65V to 4.5V supply with low on-resistance

(0.29Ω) and high speed operation (tON =40ns, t

OFF = 20ns).

The device is especially well suited for portable

battery-powered equipment due to its low operating supply

voltage (1.65V), low power consumption (4.5µW max), low

leakage currents (1 95nA ma x), and the tiny DFN and MSOP

packages. The ul tra lo w on-resi st ance an d rON flatne ss

provide very low insertion loss and distortion to applicatio ns

that require signal reproduction.

External V+ Series Resistor

For improved ESD and latch-up immunity Intersil

recommends adding a 100Ω resistor in series with the V+

power supply pin of the ISL8484 IC (see Figure 8).

During an overvolt age transient event, such a s occurs during

system level IEC 61000 ESD testing, substrate currents ca n

be generated in the IC th at can trigg er parasitic SCR

structures to turn ON, creating a low impedance path from the

V+ power supply to ground. This will result in a significan t

amount of current flow in the IC which can potentially create a

latch-up state or permanently damage the IC. The external V+

resistor limits the current durin g th is over-stress situation and

has been found to prevent l atch-up or destructi ve damage for

many overvoltage tran sient eve nt s.

Under normal operation the sub-microamp IDD current of the

IC produces an insignificant voltage drop across the 100Ω

series resistor resulting in no impact to switch operation or

performance.

FIGURE 4. OFF-ISOLATION TEST CIRCUIT FIGURE 5. rON TEST CIRCUIT

FIGURE 6. CROSSTALK TEST CIRCUIT FIGURE 7. CAPACITANCE TEST CIRCUIT

Test Circuits and Waveforms (Continued)

ANALYZER

SIGNAL

GENERATOR

V+ C

0V OR V+

NO OR NC

COM

GND

Signal direction through switch is reversed, worst case values

are recorded. Repeat test for all switches.

V+

0V OR V+

NO OR NC

COM

GND

VNX

RON = V1/100mA

100mA

Repeat test for all switches.

0V OR V+

ANALYZER

V+

NO OR NC

SIGNAL

GENERATOR

RLGND

IN1

COM 50Ω

N C

COM NC or NO

Signal direction through switch is reversed, worst case values

are recorded. Repeat test for all switches.

V+ C

GND

NO OR NC

COM

IMPEDANCE

ANALYZER

0V OR V+

Repeat test for all switches.

ISL8484

8FN6128.5

May 12, 2008

Supply Sequencing and Overvoltage Protection

With any CMOS device, proper power supply sequencing is

required to protect the device from excessive input currents

which might permanently damage the IC. All I/O pins contain

ESD protection diodes from the pin to V+ and to GND (see

Figure 9). To prevent forward biasing these diodes, V+ must

be applied before any input signals, and the input signal

voltages must remain between V+ and GND.

If these conditions cannot be guaranteed, then precautions

must be implemented to prohibit the current and voltage at

the logic pin and signal pins from exceeding the maximum

ratings of the switch. The following two methods can be used

to provided additional protection to limit the current in the

event that the voltage at a signal pin or logic pin goes below

ground or above the V+ rail.

Logic inputs can be protected by adding a 1kΩ resistor in

series with the logic input (see Figure 9). The resistor limits

the input current below th e threshold that produces

permanent damage, and the sub-microamp input current

produces an insignificant voltage drop during normal

operation.

This method is not acceptable for the signal path inputs.

Adding a series resistor to the switch input defeats the

purpose of using a low rON switch. Connecting Schottky

diodes to the signal pins as shown in Figure 8 will shunt the

fault current to the supply or to ground thereby protecting the

switch. These Schottky diodes must be sized to handle the

expected faul t cu rre nt .

Power-Supply Considerations

The ISL8484 construction is typical of most single supply

CMOS analog switches, in that they have two supply pins:

V+ and GND. V+ and GND drive the internal CMOS

switches and set their analog voltage limits. Unlike switches

with a 4V maximum supply voltage, the ISL8484 5.5V

maximum supply voltage provides plenty of room for the

10% tolerance of 4.3V supplies, as well as room for

overshoot and noise spikes.

The minimum recommended supply voltage is 1.65V. It is

important to note that the input signal range, switching times,

and on-resistance degrade at lower supply voltages. Refer

to the “Electrical S pecifications” tables, beginning on page 3,

and “Typical Performance Curves”, beginning on page 9, for

details.

V+ and GND also power the internal logic and level shiftiers.

The level shiftiers convert the input logic levels to switched

V+ and GND signals to drive the analog switch gate

terminals.

This family of switches cannot be operated with bipolar

supplies, because the input switching point becomes

negative in this configuration.

Logic-Level Thresholds

This switch family is 1.8V CMOS compatible (0.5V and 1.4V)

over a supply range of 2.7V to 4.5V (see Figure18). At 2.7V

the VIL level is about 0.53V. This is still above the 1.8V

CMOS guaranteed low output maximum level of 0.5V, but

noise margin is reduced.

The digital input stages draw supply current whenever the

digital input voltage is not at one of the supply rails. Driving

the digital input signals from GND to V+ with a fast transition

time minimizes power dissipation.

The ISL8484 has been designed to minimize the supply

current whenever the digital input voltage is not driven to the

supply rails (0V to V+). For example driving the device with

2.85V logic (0V to 2.85V) while operating with a 4.2V supply

the device draws only 12µA of current

(see Figure17 for VIN = 2.85V).

High-Frequency Performance

In 50Ω systems, the signal response is reasonably flat even

past 30MHz with a -3dB bandwidth of 120MHz (see

Figure 22). The frequency response is very consistent over a

wide V+ range, and for varying analog signal levels.

FIGURE 8. V+ SERIES RESISTOR FOR ENHANCED ESD AND

LATCH- UP IMMUNITY

FIGURE 9. OVERVOLTAGE PROTECTION

COM

100Ω

V+

GND

OPTIONAL

PROTECTION

RESISTOR

GND

VCOM

VNX

V+

INX

OPTIONAL

PROTECTION

RESISTOR

OPTIONAL

SCHOTTKY

DIODE

OPTIONAL

SCHOTTKY

DIODE

ISL8484

9FN6128.5

May 12, 2008

An OFF switch acts like a capacitor and passes higher

frequencies with less attenuation, resulting in signal

feedthrough from a switch’s input to its output. Of f Isolation is

the resistance to this feedthrough, while crosstalk indicates

the amount of feedthrough from one switch to another.

Figure 23 details the high off isolation and crosstalk rejection

provided by this part. At 100kHz, off isolation is about 62dB

in 50Ω systems, decreasing approximately 20dB per decade

as frequency increases. Higher load impedances decrease

off isolation and crosstalk rejection due to the voltage divider

action of the switch OFF impedance and the load

impedance.

Leakage Considerations

Reverse ESD protection diodes are internally connected

between each analog-signal pin and both V+ and GND. One of

these diodes conducts if any analog signal exceeds V+ or

GND.

Virtually all the analog leakage current comes from the ESD

diodes to V+ or GND. Although the ESD diodes on a given

signal pin are identical and therefore fairly well balanced,

they are reverse biased differently. Each is biased by either

V+ or GND and the analog signal. This means their leakages

will vary as the signal varies. The difference in the two diode

leakages to the V+ and GND pins constitutes th e

analog-signal-path leakage current. All analog leakage

current flows between each pin and one of the supply

terminals, not to the other switch terminal. This is why both

sides of a given switch can show leakage currents of the

same or opposite polarity. There is no connection between

the analog signal paths and V+ or GND.

Typical Performance Curves TA = +25°C, Unless Otherwise Specified.

FIGURE 10. ON-RESIST ANCE vs SUPPLY VOL TAGE vs

SWITCH VOLTAGE FIGURE 11. ON-RESISTANCE vs SUPPLY VOLTAGE vs

SWITCH VOLTAGE

FIGURE 12. ON-RESISTANCE vs SUPPLY VOLTAGE vs

SWITCH VOLTAGE FIGURE 13. ON-RESISTANCE vs SWITCH VOLTAGE

012345

rON (Ω)

VCOM (V)

ICOM = 100mA

0.25

0.26

0.27

0.28

0.29

0.30

V+ = 4.5V

V+ = 4.3V

V+ = 3.9V

rON (Ω)

VCOM (V)

0 0.5 1.0 1.5 2.0 2.5 3.0 3.5

ICOM = 100mA

0.28

0.29

0.3

0.31

0.32

0.33

0.34

0.35

V+ = 3.3V

V+ = 3V

V+ = 2.7V

0 0.5 1.0 1.5 2.0

rON (Ω)

VCOM (V)

ICOM = 100mA

0.30

0.35

0.40

0.45

0.50

0.55

0.60

0.65

0.70

V+ = 2V

V+ = 1.65V

V+ = 1.8V

0 1.0 2.0 3.0 4.0 5.0

rON (Ω)

VCOM (V)

V+ = 4.3V

ICOM = 100mA

+85°C

-40°C

+25°C

0.20

0.25

0.30

0.35

ISL8484

10 FN6128.5

May 12, 2008

FIGURE 14. ON RESISTANCE vs SWITCH VOLTAGE FIGURE 15. ON-RESISTANCE vs SWITCH VOLTAGE

FIGURE 16. ON-RESISTANCE vs SWITCH VOLTAGE FIGURE 17. SUPPLY CURRENT vs VLOGIC VOLTAGE

FIGURE 18. CHARGE INJECTION vs SWITCH VOLTAGE FIGURE 19. DIGITAL SWITCHING POINT vs SUPPLY VOLTAGE

Typical Performance Curves TA = +25°C, Unless Otherwise Specified. (Continued)

0 0.5 1.0 1.5 2.0 2.5 3.0 3.5

rON (Ω)

VCOM (V)

+85°C

-40°C

V+ = 3.3V

ICOM = 100mA

+25°C

0.20

0.25

0.30

0.35

0.40

0 0.5 1.0 1.5 2.0 2.5 3.0

rON (Ω)

VCOM (V)

+85°C

-40°C

V+ = 2.7V

+25°C

ICOM = 100mA

0.25

0.30

0.35

0.40

00.51.01.52.0

rON (Ω)

VCOM (V)

+85°C

-40°C

V+ = 1.8V

ICOM = 100mA

+25°C

0.25

0.30

0.35

0.40

0.45

0.50

0.55

0.60

ION (mA)

VIN 1 AND 2 (V)

V+ = 4.2V

12345

100

150

200

SWEEPING BOTH LOGIC INPUTS

Q (pC)

VCOM (V)

012345

-100

-50

100

150

200

V+ = 3V

V+ = 1.8V

V+ = 4.3V

V+ (V)

VINH AND VINL (V)

1.5 2.0 2.5 3.0 3.5 4.0 4.5

VINH

VINL

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.0

1.1

ISL8484

11 FN6128.5

May 12, 2008

Die Characteristics

SUBSTRATE POTENTIAL (POWERED UP):

GND (DFN Paddle Connection: Tie to GND or Float)

TRANSISTOR COUNT:

114

PROCESS:

Submicron CMOS

FIGURE 20. TURN-ON TIME vs SUPPLY VOLTAGE FIGURE 21. TURN-OFF TIME vs SUPPLY VOLTAGE

FIGURE 22. FREQUENCY RESPONSE FIGURE 23. CROSSTALK AND OFF ISOLATION

Typical Performance Curves TA = +25°C, Unless Otherwise Specified. (Continued)

(

)

V+ (V)

1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5

100

150

200

250

+85°C

-40°C

+25°C

tOFF (ns)

V+ (V)

1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5

100

150

200

+85°C

-40°C

+25°C

FREQUENCY (MHz)

-20

NORMALIZED GAIN (dB)

GAIN

PHASE

V+ = 3V

100

PHASE (°)

1 10 100 600

VIN = 0.2VP-P to 2VP-P

RL = 50Ω

FREQUENCY (Hz)

1k 100k 1M 100M 500M10k 10M

-110

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

CROSSTALK (dB)

OFF ISOLATION (dB)

110

100

ISOLATION

CROSSTALK

V+ = 4.3V

ISL8484

12 FN6128.5

May 12, 2008

ISL8484

Thin Dual Flat No-Lead Plastic Package (TDFN)

NX (b)

SECTION "C-C"

FOR ODD TERMINAL/SIDE

TERMINAL TIP

(A1)

BOTTOM VIEW

AREA

INDEX

0.10

0.08

SIDE VIEW

0.10

C0.10

TOP VIEW

AREA

INDEX

NX L

E2/2

REF.

(Nd-1)Xe

(DATUM A)

(DATUM B)

0.10

BAC

N-1

PLANE

SEATING

NX b

D2/2

NX k

L1 9L

L10.3x3A

10 LEAD THIN DUAL FLAT NO-LEAD PLASTIC PACKAGE

SYMBOL

MILLIMETERS

NOTESMIN NOMINAL MAX

0.70 0.75 0.80

- - 0.05

0.20 REF

0.20 0.25 0.30

5, 8

2.95 3.0 3.05

2.25 2.30 2.35

7, 8

2.95 3.0 3.05

1.45 1.50 1.55

7, 8

0.50 BSC

0.25 - -

0.25 0.30 0.35

Rev. 3 3/06

NOTES:

1. Dimensioning and tolerancing conform to ASME Y14.5-1994.

2. N is the number of terminals.

3. Nd refers to the number of terminals on D.

4. All dimensions are in millimeters. Angles are in degrees.

5. Dimension b applies to the metallized terminal and is measured

between 0.15mm and 0.30mm from the terminal tip.

6. The configuration of the pin #1 identifier is optional, but must be

located wi thin the zone indicated. The pin #1 identif ier may be

either a mold or mark feature.

7. Dimensions D2 and E2 are for the exposed pads which provide

improved electrical and thermal performance.

8. Nominal dimensions are provided to assist with PCB Land

Pattern Design efforts, see Intersil Technical Brief TB389.

9. Compliant to JEDEC MO-229-WEED-3 except for D2

dimensions.

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without

notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and

reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result

from its use. No lice nse is gran t ed by i mpli catio n or other wise u nder an y p a tent or patent rights of I nter sil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

FN6128.5

May 12, 2008

ISL8484

Mini Small Outline Plastic Packages

(MSOP)

NOTES:

1. These package dimensions are within allowable dimensions of

JEDEC MO-187BA.

2. Dimensioning and tolerancing per ANSI Y14.5M-1994.

3. Dimension “D” does not include mold flash, protrusions or gate

burrs and are measured at Da tum Plane. Mold flash, p rotrusion

and gate burrs shall not exceed 0.15mm (0.006 inch) per side.

4. Dimension “E1” does not include interlead flash or protrusions

and are measured at Datum Plane. Interlead flash and

protrusions shall not exceed 0.15mm (0.006 inch) per side.

5. Formed leads shall be planar with respect to one another within

0.10mm (.004) at seating Plane.

6. “L” is the length of terminal for soldering to a substrate.

7. “N” is the number of terminal positions.

8. Terminal numbers are shown for reference only.

9. Dimension “b” does not include dambar protrusion. Allowable

dambar protrusion shall be 0.08mm (0.003 inch) total in excess

of “b” dimension at maximum material condition. Minimum space

between protrusion and adjacent lead is 0.07mm (0.0027 inch).

10. Datums and to be determined at Datum plane

11. Controlling dimension: MILLIMETER. Converted inch dimen-

sions are for reference only

0.25

(0.010)

4X θ

GAUGE

PLANE

SEATING

PLANE

EE1

TOP VI EW

INDEX

AREA

-C-

-B-

0.20 (0.008) ABC

SEATING

PLANE

0.20 (0.008) C

0.10 (0.004) C

-A-

-H-

SIDE VIEW

-B-

END VIEW

0.20 (0.008) CD

- H -

-A - - B -

- H -

M10.118 (JEDEC MO-187BA)

10 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE

SYMBOL

INCHES MILLIMETERS

NOTESMIN MAX MIN MAX

A0.037 0.043 0.94 1.10 -

A1 0.002 0.006 0.05 0.15 -

A2 0.030 0.037 0.75 0.95 -

b0.007 0.011 0.18 0.27 9

c0.004 0.008 0.09 0.20 -

D0.116 0.120 2.95 3.05 3

E1 0.116 0.120 2.95 3.05 4

e 0.020 BSC 0.50 BSC -

E0.187 0.199 4.75 5.05 -

L0.016 0.028 0.40 0.70 6

L1 0.037 REF 0.95 REF -

N10 107

R0.003 - 0.07 - -

R1 0.003 - 0.07 - -

5o15o5o15o-

α0o6o0o6o-

Rev. 0 12/02