TPS54678
EN PH
VSENSE
PWRGD
RT/CLK
COMP
VOUT
BOOTVIN
VIN
SS
AGND
GND
Exposed thermal pad
85
86
87
88
89
90
91
92
93
94
95
1 2 3 4 5 6
Current (A)
Efficiency (%)
VIN = 3.3 V
VIN = 5 V
VOUT = 1.8 V
Fsw = 500 KHz
DCR = 7.5 mΩ
G020
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TPS54678
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2.95-V to 6-V Input, 6-A Output, 2-MHz, Synchronous Step-Down
SWIFT
™
Switcher
1 Features 3 Description
TPS54678 device is a full-featured 6-V, 6-A,
1• Two 12-mΩ(Typical) MOSFETs for High- synchronous step-down current mode converter with
Efficiency 6-A Continuous Output Current two integrated MOSFETs.
• 200-kHz to 2-MHz Switching Frequency TPS54678 enables small designs by integrating the
• 0.6-V ±1% Voltage Reference Over Temperature MOSFETs, implementing current mode control to
(–40°C to 150°C) reduce external component count, reducing inductor
• Synchronizes to External Clock size by enabling up to 2-MHz switching frequency,
and minimizing the IC footprint with a small 3-mm ×
• Start-Up With Prebiased Voltage 3-mm thermally enhanced WQFN package.
• Power Good Output TPS54678 provides accurate regulation for a variety
• Adjustable Slow Start and Sequencing of loads with an accurate ±1% voltage reference
• Cycle-by-Cycle Current Limit and Hiccup Current (VREF) over temperature.
Protection Efficiency is maximized through the integrated 12-mΩ
• Adjustable Input Voltage UVLO MOSFETs. Using the enable pin, shutdown supply
• Thermally Enhanced 16-Pin 3-mm × 3-mm WQFN current is reduced by disabling the device.
(RTE) The output voltage start-up ramp is controlled by the
soft-start pin that can also be configured for
2 Applications sequencing or tracking. Monotonic start-up is
• Low-Voltage, High-Density Power Systems achieved with prebiased voltage. Undervoltage
lockout can be increased by programming the
• Point-of-Load Regulation for High-Performance threshold with a resistor divider on the enable pin. An
DSPs, FPGAs, ASICs, and Microprocessors open-drain power good signal indicates the output is
• Broadband, Networking, and Optical within 93% to 105% of its nominal voltage.
• Communications Infrastructure Cycle-by-cycle current limit, hiccup overcurrent
• Gaming, DTV, and Set-Top Boxes protection and thermal shutdown protect the device
during an overcurrent condition.
Device Information(1)
PART NUMBER PACKAGE BODY SIZE (NOM)
TPS54678 WQFN (16) 3.00 mm × 3.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Schematic Efficiency vs Output Current
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS54678
SLVSBF3A –JUNE 2012–REVISED NOVEMBER 2015
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Table of Contents
1 Features.................................................................. 18 Application and Implementation ........................ 21
8.1 Application Information............................................ 21
2 Applications ........................................................... 18.2 Typical Application.................................................. 21
3 Description............................................................. 19 Power Supply Recommendations...................... 31
4 Revision History..................................................... 210 Layout................................................................... 31
5 Pin Configuration and Functions......................... 310.1 Layout Guidelines ................................................. 31
6 Specifications......................................................... 410.2 Layout Example .................................................... 32
6.1 Absolute Maximum Ratings ...................................... 410.3 Power Dissipation Estimate .................................. 32
6.2 ESD Ratings ............................................................ 411 Device and Documentation Support................. 34
6.3 Recommended Operating Conditions....................... 411.1 Device Support .................................................... 34
6.4 Thermal Information.................................................. 411.2 Documentation Support ........................................ 34
6.5 Electrical Characteristics........................................... 511.3 Community Resources.......................................... 34
6.6 Typical Characteristics.............................................. 711.4 Trademarks........................................................... 34
7 Detailed Description............................................ 11 11.5 Electrostatic Discharge Caution............................ 34
7.1 Overview................................................................. 11 11.6 Glossary................................................................ 34
7.2 Functional Block Diagram....................................... 12 12 Mechanical, Packaging, and Orderable
7.3 Feature Description................................................. 12 Information........................................................... 34
7.4 Device Functional Modes........................................ 17
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (June 2012) to Revision A Page
• Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional
Modes,Application and Implementation section, Power Supply Recommendations section, Layout section, Device
and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1
• Changed Thermal Information table values............................................................................................................................ 4
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VIN
GND
GND
VIN
PH
PH
SS/TR
EN
PWRGD
BOOT
PH
RT/CLK
COMP
AGND
VSENSE
1
4
3
2
16 15 14 13
12
9
10
11
5678
Thermal
Pad
VIN
TPS54678
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SLVSBF3A –JUNE 2012–REVISED NOVEMBER 2015
5 Pin Configuration and Functions
RTE Package
16-Pin WQFN
Top View
Pin Functions
PIN I/O(1) DESCRIPTION
NAME NO.
AGND 5 G Analog ground should be electrically connected to GND close to the device.
A bootstrap capacitor is required between BOOT and PH. If the voltage on this capacitor is below the
BOOT 13 I minimum required by the BOOT UVLO, the output is forced to switch off until the capacitor is refreshed.
Error amplifier output, and input to the output switch current comparator. Connect frequency
COMP 7 O compensation components to this pin.
Enable pin, internal pullup current source. Pull below 1.2 V to disable. Float to enable. Can be used to
EN 15 I set the on and off threshold (adjust UVLO) with two additional resistors.
3
GND G Power ground. This pin should be electrically connected directly to the thermal pad under the device.
4
10 The source of the internal high-side power MOSFET, and drain of the internal low-side (synchronous)
PH 11 O rectifier MOSFET.
12 An open-drain output asserts low if output voltage is low due to thermal shutdown, overvoltage,
PWRGD 14 O undervoltage, or EN shut down.
RT/CLK 8 I/O Resistor Timing or External Clock input pin
Slow-start and Tracking. An external capacitor connected to this pin sets the output voltage rise time.
SS/TR 9 I/O This pin can also be used for tracking.
1
VIN 2 I Input supply voltage, 2.95 V to 6 V
16
VSENSE 6 I Inverting node of the transconductance (gm) error amplifier
GND pin should be connected to the exposed thermal pad for proper operation. This thermal pad should
Thermal Pad – be connected to any internal PCB ground plane using multiple vias for good thermal performance.
(1) I = Input, O = Output, G = Ground
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN MAX UNIT
VIN, EN –0.3 7
Input voltage RT/CLK, PWRGD –0.3 6 V
COMP, SS/TR, VSENSE –0.3 3
BOOT-PH 7
PH –0.7 7
Output voltage V
PH (20 ns transent) –2 10
PH (5 ns transient) –4 12
Source current EN, RT/CLK 100 µA
COMP, SS 100 µA
Sink current PWRGD 10 mA
Operating junction temperature, TJ–40 150 °C
Storage temperature, Tstg –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings VALUE UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) ±2000 V
Electrostatic
V(ESD) discharge Charged device model (CDM), per JEDEC specification JESD22-C101, all pins(2) ±500 V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT
VIN Input voltage 3 6 V
TJOperating junction temperature –40 150 °C
6.4 Thermal Information(1)
TPS54678
THERMAL METRIC(2) RTE (WQFN) UNIT
16 PINS
RθJA Junction-to-ambient thermal resistance 43.4 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 44.2 °C/W
RθJB Junction-to-board thermal resistance 14.6 °C/W
ψJT Junction-to-top characterization parameter 0.6 °C/W
ψJB Junction-to-board characterization parameter 14.5 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 4.1 °C/W
(1) Unless otherwise specified, metrics listed in this table refer to JEDEC high-K board measurements
(2) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
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6.5 Electrical Characteristics
TJ= –40°C to +150°C, VIN = 2.95 to 6 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY VOLTAGE (VIN PIN)
Operating input voltage 2.95 6 V
Shutdown supply current EN = 0 V, 25°C, 2.95 V ≤VIN ≤6 V 1 3 µA
Operating non-switching supply current VSENSE = 0.6 V, VIN = 5 V, 25°C, fSW = 500 kHz 570 800 µA
ENABLE AND UVLO (EN PIN)
Enable threshold Rising 1.3 V
Enable threshold Falling 1.18 V
Input current Enable threshold + 50 mV –3.5 µA
Input current Enable threshold – 50 mV –0.70 µA
VOLTAGE REFERENCE
Voltage reference 2.95 V ≤VIN ≤6 V, –40°C < TJ< 150°C 0.594 0.600 0.606 V
MOSFET
High-side switch resistance BOOT-PH = 5 V 12 25 mΩ
High-side switch resistance BOOT-PH = 2.95 V 17 33
Low-side switch resistance BOOT-PH = 5 V 12 25 mΩ
Low-side switch resistance BOOT-PH = 2.95 V 17 33
ERROR AMPLIFIER
Input current 7 nA
Error amplifier transconductance (gm) –2 µA < I(COMP) < 2 µA V(COMP) = 1 V 245 umhos
Error amplifier transconductance (gm) –2 µA < I(COMP) < 2 µA V(COMP) = 1 V, V(VSENSE) = 0.4 V 80 umhos
during slow-start
Error amplifier source and sink V(COMP) = 1 V 100-mV Overdrive ±20 µA
COMP to Iswitch gm 20 A/V
CURRENT LIMIT
Current limit threshold Fs = 500 KHz 9.5 10.5 11.5 A
Cycles before entering hiccup during 512 cycles
overcurrent
Hiccup cycles 16384 cycles
Low-side sourcing current threshold 7 8.5 10.5 A
Low-side FET reverse current 4 A
protection
THERMAL SHUTDOWN
Thermal shutdown 170 °C
Hysteresis 15 °C
TIMING RESISTOR AND EXTERNAL CLOCK (RT/CLK PIN)
Switching frequency range using RT 200 2000 kHz
mode
Switching frequency Rt= 82.5 kΩ400 500 600 kHz
Switching frequency range using CLK 300 2000 kHz
mode
Minimum CLK pulse width 75 ns
RT/CLK voltage R(RT/CLK) = 82.5 kΩ0.5 V
RT/CLK high threshold 1.6 2.2 V
RT/CLK low threshold 0.4 0.6 V
RT/CLK falling edge to PH rising edge Measure at 500 kHz with RT resistor in series 55 ns
delay
PLL lock in time Measure at 500 kHz 40 µs
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Electrical Characteristics (continued)
TJ= –40°C to +150°C, VIN = 2.95 to 6 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
PH (PH PIN)
Measured at 50% points on PH. IOUT = 3 A 85 110 ns
Minimum ON-time Measured at 50% points on PH. IOUT = 0 A 100 ns
Prior to skipping off pulses,
Minimum OFF-time 70 ns
BOOT-PH = 3 V, IOUT = 3 A
Rise and fall dV/dT BOOT-PH = 3 V; IO= 6 A 1.5 V/ns
BOOT (BOOT PIN)
Charging resistor VIN = 6 V, BOOT-PH = 6 V 7 Ω
BOOT-PH UVLO VIN = 3.3 V 2.2 V
SLOW START AND TRACKING (SS/TR PIN)
V(SS/TR) < 0.15 V 47
Charge current µA
V(SS/TR) > 0.15 V 2.2
SS/TR to VSENSE matching VIN = 3.3 V 60 mV
SS/TR to reference crossover 98% nominal 0.8 V
SS/TR discharge voltage (overload) VSENSE = 0 V 4.5 mV
SS/TR discharge to current (overload) VSENSE = 0 V; V(SS/TR) = 4 V 95 µA
SS/TR discharge current (UVLO, EN, VIN = 3 V; V(SS/TR) = 4 V 925 µA
thermal fault)
POWER GOOD (PWRGD PIN)
VSENSE falling (Fault) 91 % VREF
VSENSE rising (Good) 93 % VREF
VSENSE threshold VSENSE rising (Fault) 105 % VREF
VSENSE falling (Good) 103 % VREF
Output high leakage VSENSE = VREF, V(PWRGD) = 5.5 V 2 nA
ON-Resistance VIN = 5 V 65 120 Ω
Output low I(PWRGD) = 2.5 mA 0.2 0.3 V
Minimum VIN for valid output V(PWRGD) < 0.5 V at 100 µA 1.2 1.5 V
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599.5
599.6
599.7
599.8
599.9
600
600.1
600.2
−40 0 40 80 120 160
Temperature (°C)
Voltage Reference (mV)
VIN = 5 V
G005
12.25
14.25
16.25
18.25
20.25
22.25
−40 0 40 80 120 160
Temperature (°C)
MOSFET Rds(on) (mΩ)
Lowside, VIN = 3.3 V
Highside, VIN = 3.3 V
Lowside, VIN = 5 V
Highside, VIN = 5 V
G006
1.18
1.2
1.22
1.24
1.26
1.28
1.3
1.32
−40 0 40 80 120 160
Temperature (°C)
EN Pin Voltage (V)
Rising, VIN = 3.3 V
Rising, VIN = 5 V
Falling, VIN = 3.3 V
Falling, VIN = 5 V
G003
−4
−3.5
−3
−2.5
−2
−1.5
−1
−0.5
−40 0 40 80 120 160
Temperature (°C)
EN Pin Current (µA)
Threshold−50 mV, VIN = 3.3 V
Threshold−50 mV, VIN = 5 V
Threshold+50 mV, VIN = 3.3 V
Threshold+50 mV, VIN = 5 V
G004
0.6
0.7
0.8
0.9
1
1.1
1.2
1.3
1.4
−40 0 40 80 120 160
Temperature (°C)
Shutdown Supply Current (µA)
VIN = 5 V
VIN = 3.3 V
G001
550
560
570
580
590
−40 0 40 80 120 160
Temperature (°C)
Operating Current (µA)
VIN =5 V
VIN = 3.3 V
G002
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6.6 Typical Characteristics
Figure 1. Shutdown Supply Current vs Junction Figure 2. VIN Operating Current vs Junction Temperature
Temperature
Figure 3. EN Pin Voltage vs Junction Temperature Figure 4. EN Pin Current vs Junction Temperature
Figure 5. Voltage Reference vs Junction Temperature Figure 6. MOSFET Rds(on) vs Junction Temperature
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152
152.2
152.4
152.6
152.8
−40 0 40 80 120 160
Temperature (°C)
VSS Voltage Threshold VSSTHR (mV)
VIN = 3.3 V
VIN = 5 V
G011
−2.28
−2.27
−2.26
−2.25
−2.24
−2.23
−2.22
−2.21
−40 0 40 80 120 160
Temperature (°C)
SS Charge Current (µA)
VIN = 3.3 V
VIN = 5 V
VSS TR > 0.15 V
G012
480
482
484
486
488
490
−40 0 40 80 120 160
Temperature (°C)
Switching Frequency (kHz)
VIN = 5 V
RT = 85 kΩ
G010
218
228
238
248
258
−40 0 40 80 120 160
Temperature (°C)
Transconductance (µA/V)
VIN = 3.3 V
VIN = 5 V
G007
10.1
10.1
10.2
10.2
10.2
10.3
−40 0 40 80 120 160
Temperature (°C)
High Side FET Current Limit (A)
VIN = 3.3 V
G008
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Typical Characteristics (continued)
Figure 7. Transconductance vs Junction Temperature Figure 8. High-Side FET Current Limit vs Junction
Temperature
Figure 10. Switching Frequency vs Junction Temperature
Figure 9. Switching Frequency vs RT Pin Resistance
Figure 11. VSS Voltage Threshold vs Junction Temperature Figure 12. SS Charge Current vs Junction Temperature
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78
80
82
84
86
88
90
92
94
96
98
1 2 3 4 5 6
Current (A)
Efficiency (%)
VOUT = 3.3 V
VOUT = 1.8 V
VOUT = 1.2 V
VOUT = 1 V
VIN = 5 V
Fsw = 500 KHz
DCR = 7.5 mΩ
TA = 25°C
G017
78
80
82
84
86
88
90
92
94
96
1 2 3 4 5 6
Current (A)
Efficiency (%)
VOUT = 1.8 V
VOUT = 1.2 V
VOUT = 1 V
VIN = 3.3 V
Fsw = 500 KHz
DCR = 7.5 mΩ
TA = 25°C
G018
91
93
95
97
99
101
103
105
107
−40 0 40 80 120 160
Temperature (°C)
PWRGD Threshold (% of vref)
Fault Rising
Good Rising
Fault Falling
Good Falling
G015
−2
−1
0
1
2
3
4
−40 0 40 80 120 160
Temperature (°C)
PWRGD Leakage Current (nA)
VIN = 5 V
G016
−48
−47.5
−47
−46.5
−46
−45.5
−45
−44.5
−40 0 40 80 120 160
Temperature (°C)
SS Charge Current (µA)
VIN = 3.3 V
VIN = 5 V
VSS TR = < 0.15 V
G013
55
60
65
70
75
80
−40 0 40 80 120 160
Temperature (°C)
PWRGD Rdson (Ω)
VIN = 5 V
G014
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Typical Characteristics (continued)
Figure 13. SS Charge Current vs Junction Temperature Figure 14. PWRGD Rds(on) vs Junction Temperature
Figure 15. PWRGD Threshold vs Junction Temperature Figure 16. PWRGD Leakage Current vs Junction
Temperature
Figure 17. Efficiency vs Load Current Figure 18. Efficiency vs Load Current
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78
80
82
84
86
88
90
92
94
96
98
1 2 3 4 5 6
Current (A)
Efficiency (%)
VOUT = 3.3 V
VOUT = 1.8 V
VOUT = 1.2 V
VOUT = 1 V
VIN = 5 V
Fsw = 1 MHz
DCR = 7.5 mΩ
TA = 25°C
G019
78
80
82
84
86
88
90
92
94
96
1 2 3 4 5 6
Current (A)
Efficiency (%)
VOUT = 1.8 V
VOUT = 1.2 V
VOUT = 1 V
VIN = 3.3 V
Fsw = 1 MHz
DCR = 7.5 mΩ
TA = 25°C
G020
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Typical Characteristics (continued)
Figure 19. Efficiency vs Load Current Figure 20. Efficiency vs Load Current
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7 Detailed Description
7.1 Overview
The TPS54678 is a 6-V, 6-A, synchronous step-down (buck) converter with two integrated N-channel MOSFETs.
To improve the performance during line and load transients the device implements a constant frequency, peak
current mode control which reduces output capacitance and simplifies external frequency compensation design.
The wide switching frequency range of 200 kHz to 2000 kHz allows for efficiency and size optimization when
selecting the output filter components. The switching frequency is adjusted using a resistor to ground on the
RT/CLK pin. The device has an internal phase lock loop (PLL) on the RT/CLK pin that is used to synchronize the
power switch turn on to a falling edge of an external system clock.
The TPS54678 has a typical default start-up voltage of 2.4 V. The EN pin has an internal pullup current source
that can be used to adjust the input voltage undervoltage lockout (UVLO) with two external resistors. In addition,
the pullup current provides a default condition when the EN pin is floating for the device to operate. The total
operating current for the TPS54678 is typically 570 µA when not switching and under no load. When the device
is disabled, the supply current is less than 3 µA.
The integrated 12-mΩMOSFETs allow for high-efficiency power supply designs with continuous output currents
up to 6 amperes. The TPS54678 reduces the external component count by integrating the boot recharge diode.
The bias voltage for the integrated high-side MOSFET is supplied by a capacitor between the BOOT and PH
pins. The boot capacitor voltage is monitored by an UVLO circuit and turns off the high-side MOSFET when the
voltage falls below a preset threshold. This BOOT circuit allows the TPS54678 to operate approaching 100%.
The output voltage can be stepped down to as low as the 0.60-V reference.
TPS54678 features monotonic start-up under prebias conditions. The low-side FET turns on for a short time
period every cycle before the output voltage reaches the prebiased voltage. This ensures the boot cap has
enough charge to turn on the top FET when the output voltage reaches the prebiased voltage.
The TPS54678 has a power good comparator (PWRGD) with 2% hysteresis.
The TPS54678 minimizes excessive output overvoltage transients by taking advantage of the overvoltage power
good comparator. When the regulated output voltage is greater than 105% of the nominal voltage, the
overvoltage comparator is activated, and the high-side MOSFET is turned off and masked from turning on until
the output voltage is lower than 103%.
The SS/TR (slow-start or tracking) pin is used to minimize inrush currents or provide power supply sequencing
during power up. A small value capacitor should be coupled to the pin for slow-start. The SS/TR pin is
discharged before the output power up to ensure a repeatable restart after an overtemperature fault, UVLO fault
or disabled condition. To optimize the output startup waveform, two levels of SS current are implemented.
To reduce the power dissipation of TPS54678 during overcurrent event, the hiccup protection is implemented
beyond the cycle-by-cycle protection.
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BOOT
PH
GND
PWRGD
COMP
SS
VSENSE
Logic93%
105%
Voltage
Reference
+
+
EN
i1iHYS
Enable
Threshold
Enable
Comparator
Minimum
COMP Clamp
Shutdown
Logic
Thermal
Shutdown UVLO
VIN
Boot
Charge
Boot
UVLO
Frequency
Shift
Logic and
PWM Latch
Slope
Compensation
Overload
Recovery Maximum
Clamp
Logic
OSC with
PLL
AGND PowerPad RT/CLK
Shutdown
PWM
Comparator
TPS54678
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7.2 Functional Block Diagram
7.3 Feature Description
7.3.1 Fixed Frequency PWM Control
The TPS54678 uses a settable fixed frequency, peak current mode control. The output voltage is compared
through external resistors on the VSENSE pin to an internal voltage reference by an error amplifier which drives
the COMP pin. An internal oscillator initiates the turn on of the high-side power switch. The error amplifier output
is compared to the high-side power switch current. When the power switch current reaches the COMP voltage
level the high-side power switch is turned off and the low-side power switch is turned on. The COMP pin voltage
will increase and decrease as the output current increases and decreases. The device implements a current limit
by clamping the COMP pin voltage to a maximum level and implements a sleep mode with a minimum clamp.
7.3.2 Slope Compensation and Output Current
The TPS54678 adds a compensating ramp to the switch current signal. This slope compensation prevents sub-
harmonic oscillations. The available peak inductor current maintains constant over the full duty cycle range.
7.3.3 Bootstrap Voltage (Boot) and Low Dropout Operation
The TPS54678 has an integrated boot regulator and requires a small ceramic capacitor between the BOOT and
PH pin to provide the gate drive voltage for the high-side MOSFET. The value of the ceramic capacitor should be
0.1 µF. A ceramic capacitor with an X7R or X5R grade dielectric is recommended because of the stable
characteristics over temperature and voltage.
To improve dropout, the TPS54678 is designed to operate at 100% duty cycle as long as the BOOT to PH pin
voltage is greater than 2.2 V. The high-side MOSFET is turned off using an UVLO circuit, allowing for the low-
side MOSFET to conduct, when the voltage from BOOT to PH drops below 2.2 V. Because the supply current
sourced from the BOOT pin is low, the high-side MOSFET can remain on for more switching cycles than are
required to refresh the capacitor, thus the effective duty of the switching regulator is high.
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TPS54678
VOUT
VSENSE
R1
R2
+
0.6 V
O
0.6 V
R2 = R1 × V - 0.6 V
æ ö
ç ÷
ç ÷
è ø
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Feature Description (continued)
7.3.4 Error Amplifier
The TPS54678 has a transconductance amplifier for the error amplifier. The error amplifier compares the
VSENSE voltage to the lower of the SS/TR pin voltage or the internal 0.6-V voltage reference. The
transconductance of the error amplifier is 245 µA/V during normal operation. During the slow-start operation, the
transconductance is a fraction of the normal operating gm. The frequency compensation components are added
to the COMP pin to ground.
7.3.5 Voltage Reference
The voltage reference system produces a precise ±1% voltage reference over temperature by scaling the output
of a temperature stable bandgap circuit. During production, the bandgap and scaling circuits are trimmed to
produce 0.6 V at the amplifier output.
7.3.6 Adjusting the Output Voltage
The output voltage is set with a resistor divider from the output node to the VSENSE pin. TI recommends using
1% tolerance or better divider resistors. Start with a 20-kΩresistor for R1 and use Equation 1 to calculate R2. To
improve efficiency at light loads, consider using larger value resistors. If the values are too high, the regulator will
be more susceptible to noise and voltage errors from the VSENSE input current will be noticeable.
(1)
Figure 21. Voltage Divider Circuit
7.3.7 Enable and Adjusting Undervoltage Lockout
The EN pin provides electrical on and off control of the device. Once the EN pin voltage exceeds the threshold
voltage, the device starts operation. If the EN pin voltage is pulled below the threshold voltage, the regulator
stops switching and enters low Iq state. If an application requires controlling the EN pin, use open drain or open
collector output logic to interface with the pin.
For input undervoltage lockout (UVLO), use the EN pin as shown in Figure 22 to set up the UVLO by using the
two external resistors. Once the EN pin voltage exceeds 1.3 V, an additional 2.8 µA of hysteresis is added. This
additional current facilitates input voltage hysteresis. Use Equation 2 to set the external hysteresis for the input
voltage. Use Equation 3 to set the input startup voltage. TI recommends that the minimum input shutdown
voltage be set at 2.45 V or higher to ensure proper operation before shutdown.
Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback 13
Product Folder Links: TPS54678
Css nF 3 Tss mS( ) ( )= ´
EN_FALLING
STOP EN_FALLING
R1 × V
R2 = V - V + R1 × (I + I )
ph
EN_FALLING
START STOP
EN_RISING
EN_FALLING
EN_RISING
V
V ( ) - V
V
R1 = V
I (1 - ) + I
ph
V
TPS54678
VIN
EN
R1
R2
Ih
2.8 µA
+
Ip
0.7 µA
TPS54678
SLVSBF3A –JUNE 2012–REVISED NOVEMBER 2015
www.ti.com
Feature Description (continued)
Figure 22. Set Up Input Undervoltage Lockout.
(2)
where
• R1and R2are in Ω
• Ih= 2.8 µA
• Ip= 0.7 µA
• VEN_RISING = 1.3 V
• VEN_FALLING = 1.18 V (3)
7.3.8 Soft-Start Pin
TPS54678 effectively uses the lower voltage of the internal voltage reference or the SS/TR pin voltage as the
reference voltage of the power supply and regulates the output accordingly. A capacitor on the SS/TR pin to
ground will implement a slow-start time. The TPS54678 has an internal pullup current source of 47 µA when
V(SS/TR) is less than 0.15 V and 2.2 µA when V(SS/TR) is higher than 0.15 V. The ISS charges the external slow-
start capacitor. The equation for the slow-start time is shown in Equation 4 considering the fact the first 47 µA
charges the SS to 0.15 V. The 2.2 µA then charges the SS from 0.15 V to about 0.8 V for the handoff of the SS
voltage to reference voltage.
(4)
If during normal operation, the VIN UVLO is exceeded, EN pin pulled below 1.2 V, or a thermal shutdown event
occurs, the TPS54678 will stop switching and the SS/TR must be discharged to about 60 mV before reinitiating a
powering-up sequence.
The VSENSE voltage will follow the SS/TR pin voltage up to 90% of the internal voltage reference. When the
SS/TR voltage is greater than 90% of the internal voltage, the effective system reference voltage will transit from
the SS/TR voltage to the internal voltage reference.
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Product Folder Links: TPS54678
0
200
1200
1400
1800
0 40 80 100 180 200
RT Resistance (KΩ)
Switching Frequency (KHz)
G009
1000
160
400
600
800
1600
1401206020
1.052
56183
R (kΩ) =
TF (KHz)
SW
é ù
ë û
EN
TPS54678
SS
CSS
PWRGD
EN
TPS54678
SS/TR
PWRGD
CSS
TPS54678
www.ti.com
SLVSBF3A –JUNE 2012–REVISED NOVEMBER 2015
Feature Description (continued)
7.3.9 Sequencing
Many of the common power supply sequencing methods can be implemented using the SS/TR, EN and PWRGD
pins. The sequential method can be implemented using an open-drain or collector output of a power on reset pin
of another device. The sequential method is shown in Figure 23. The power good is coupled to the EN pin on the
TPS54678, which will enable the second power supply once the primary supply reaches regulation.
Figure 23. Sequential Start-Up Sequence
7.3.10 Constant Switching Frequency and Timing Resistor (RT/CLK Pin)
The switching frequency of the TPS54678 is adjustable over a wide range from approximately 200 kHz to
2000 kHz by placing a maximum of 210 kΩand minimum of 18 kΩ, respectively, on the RT/CLK pin. The
RT/CLK is typically 0.5 V. To determine the timing resistance for a given switching frequency, use the curve in
Figure 24. To reduce the solution size one would typically set the switching frequency as high as possible, but
tradeoffs of the supply efficiency, maximum input voltage and minimum controllable on time should be
considered.
The minimum controllable on time is typically 85 ns at 3-A current load and 100 ns at no load, and will limit the
maximum operating input voltage or output voltage.
(5)
Figure 24. Switching Frequency vs RT Set Resistor
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Feature Description (continued)
7.3.11 Overcurrent Protection
The TPS54678 implements current mode control which uses the COMP pin voltage to turn off the high-side
MOSFET and turn on the low-side MOSFET on a cycle-by-cycle basis. Each cycle the switch current and the
COMP pin voltage are compared, when the peak switch current intersects the COMP voltage the high-side
switch is turned off.
7.3.11.1 High-Side Overcurrent Protection
During overcurrent conditions that pull the output voltage low, the error amplifier will respond by driving the
COMP pin high, increasing the switch current. The error amplifier output is clamped internally. This clamp
functions as a high-side switch current limit. When the high-side switch current limit occurs consecutively for 512
CLK cycles, the converter enters hiccup mode in which no switching action happens for about 16000 cycles. This
helps to reduce the power consumption during an overcurrent event.
7.3.11.2 Low-Side Overcurrent Protection
The conduction current of the low-side MOSFET is also monitored by TPS54678. During normal operation, the
low-side sources current into the load. When the sourcing current reaches the internally set low-side sourcing
(forward) current limit, the high-side is not turned on and skipped during the next clock cycle. Under this
condition, the low-side is kept on until the sourcing current becomes less than the internally set current limit and
then the high-side is turned on at the beginning of the following clock cycle. This ensures protection under an
output short condition; thereby, preventing current run-away.
The low-side can also sink current from the load. If the low-side sinking (reverse) current limit is exceeded, the
low-side is turned off immediately for the rest of the clock cycle. Under this condition, both the high-side and low-
side are off until the start of the next cycle.
7.3.12 Safe Start-Up into Prebiased Outputs
The TPS54678 allows monotonic start-up into prebiased output. The low-side FET turns on for a short time
period every cycle before the output voltage reaches the prebiased voltage. This ensures the boot cap has
enough charge to turn on the top FET when the output voltage reaches the prebiased voltage.
The TPS54678 also implements low-side current protection by detecting the voltage over the low-side MOSFET.
When the converter sinks current through the low side FET and if the current exceeds 4 A, the control circuit
turns the low-side FET off. Due to the implemented prebias function, the low-side FET reverse current protection
should not be reached, but it provides another layer of protection.
7.3.13 Synchronize Using the RT/CLK Pin
The RT/CLK pin is used to synchronize the converter to an external system clock. See Figure 25. To implement
the synchronization feature in a system connect a square wave to the RT/CLK pin with on time at least 75 ns.
The square wave amplitude at this pin must transition lower than 0.6 V and higher than 1.6 V. The
synchronization frequency range is 300 kHz to 2000 kHz. The rising edge of the PH will be synchronized to the
falling edge of RT/CLK pin.
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TPS54678
RT/CLK
RRT
PLL
TPS54678
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SLVSBF3A –JUNE 2012–REVISED NOVEMBER 2015
Feature Description (continued)
Figure 25. Synchronizing to a System Clock
7.3.14 Power Good (PWRGD Pin)
The PWRGD pin is an open-drain output and pulls the PWRGD pin low when the VSENSE voltage is less than
91% or greater than 105% of the nominal internal reference voltage.
There is a 2% hysteresis, so once the VSENSE pin is within 93% to 103% of the internal voltage reference the
PWRGD pin is de-asserted and the pin floats. TI recommends to use a pullup resistor between the values of
1 kΩand 100 kΩto a voltage source that is 5.5 V or less. The PWRGD is in a valid state once the VIN input
voltage is greater than 1.2 V.
7.3.15 Overvoltage Transient Protection
The TPS54678 incorporates an overvoltage transient protection (OVTP) circuit to minimize voltage overshoot
when recovering from output fault conditions or strong unload transients. The OVTP feature minimizes the output
overshoot by implementing a circuit to compare the VSENSE pin voltage to OVTP threshold which is 105% of
the internal voltage reference. If the VSENSE pin voltage is greater than the OVTP threshold, the high-side
MOSFET is disabled preventing current from flowing to the output and minimizing output overshoot. When the
VSENSE voltage drops lower than the OVTP threshold the high-side MOSFET is allowed to turn on the next
clock cycle.
7.3.16 Thermal Shutdown
The device implements an internal thermal shutdown to protect itself if the junction temperature exceeds 170°C.
The thermal shutdown forces the device to stop switching when the junction temperature exceeds thermal trip
threshold. When the die temperature decreases below 155°C, the device reinitiates the power-up sequence by
discharging the SS/TR pin to about 60 mV. The thermal shutdown hysteresis is 15°C.
7.4 Device Functional Modes
7.4.1 Small Signal Model for Loop Response
The Figure 26 shows an equivalent model for the TPS54678 control loop that can be modeled in a circuit
simulation program to check frequency response and dynamic load response. The error amplifier is a
transconductance amplifier with a gm of 245 µA/V. The error amplifier can be modeled using an ideal voltage
controlled current source. The resistor ROand capacitor COmodel the open loop gain and frequency response of
the amplifier.
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Product Folder Links: TPS54678
RESR
COUT RLOAD
VC
gm(ps)
TPS54678
VSENSE
COMP
R3 0.6 V
PH
C1
C2 COUT(ea) +
Power Stage
20 A/V
ROUT(ea) gM
245 µA/V
R1
R2
RESR
COUT
RLOAD
VOUT
a
b
c
TPS54678
SLVSBF3A –JUNE 2012–REVISED NOVEMBER 2015
www.ti.com
Device Functional Modes (continued)
Figure 26. Small Signal Model for Loop Response
7.4.2 Simple Small Signal Model for Peak Current Mode Control
Figure 26 is a simple small signal model that can be used to understand how to design the frequency
compensation. The TPS54678 power stage can be approximated to a voltage controlled current source (duty
cycle modulator) supplying current to the output capacitor and load resistor. The control to output transfer
function is shown in Equation 6 and consists of a DC gain, one dominant pole and one ESR zero. The quotient of
the change in switch current and the change in COMP pin voltage (node c in Figure 26) is the power stage
transconductance. The gm for the TPS54678 is 20 A/V. The low-frequency gain of the power stage frequency
response is the product of the transconductance and the load resistance as shown in Equation 7. As the load
current increases and decreases, the low-frequency gain decreases and increases, respectively. This variation
with load may seem problematic at first glance, but fortunately the dominant pole moves with load current (see
Equation 8). The combined effect is highlighted by the dashed line in Figure 28. As the load current decreases,
the gain increases and the pole frequency lowers, keeping the 0-dB crossover frequency the same for the
varying load conditions, which makes it easier to design the frequency compensation.
Figure 27. Small Signal Model For Peak Current Mode Control
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OUT ESR
1
z
C R 2
f=
´ ´ p
L
OUT
1
pC R 2
f=
´ ´ p
L
Adc gm R
ps
= ´
O
C
s
1
V2 z
Adc x
Vs
12 p
f
f
æ ö
ç ÷
è ø
æ ö
ç ÷
è ø
+p ´
=
+p ´
fP
Adc
fZ
Frequency
Gain
TPS54678
www.ti.com
SLVSBF3A –JUNE 2012–REVISED NOVEMBER 2015
Device Functional Modes (continued)
Figure 28. Frequency Response Model for Peak Current Mode Control
(6)
(7)
(8)
(9)
7.4.3 Small Signal Model for Frequency Compensation
The TPS54678 uses a transconductance amplifier for the error amplifier and readily supports two of the
commonly used frequency compensation circuits. The compensation circuits are shown in Figure 29. The Type 2
circuits are normally implemented in high-bandwidth power supply designs using low ESR output capacitors. In
Type 2A, one additional high-frequency pole is added to attenuate high-frequency noise.
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Product Folder Links: TPS54678
ESR OUT
R C
C2
R3
´
=
LOUT
R C
C1
R3
´
=
L
OUT
1
pC R 2
f=
´ ´ p
O OUT
REF
2 fc V C
R3 gm V gm
ea ps
p ´ ´ ´
=
´ ´
TPS54678
VSENSE COMP
R3
VREF
C1
C2
COUT(ea)
5 pF
+
ROUT(ea)
gM(ea)
R1
R2
VOUT
Type IIA
R3
C1
Type IIB
TPS54678
SLVSBF3A –JUNE 2012–REVISED NOVEMBER 2015
www.ti.com
Device Functional Modes (continued)
Figure 29. Types of Frequency Compensation
The design guidelines for TPS54678 loop compensation are as follows:
1. Set up crossover frequency fc.
2. R3 can be determined by Equation 10:
where
• gmea is the GM amplifier gain,
• gmPS is the power stage gain (20 A/V). (10)
3. Place a compensation zero at the dominant pole C1 can be determined by
Equation 11:
(11)
4. C2 is optional. It can be used to cancel the zero from ESR of the Co in Equation 12:
(12)
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U1
TPS54678RTE
PWPD
VIN
VIN
VIN
EN
VSNS
COMP
RT/CLK
SS/TR
PH
PH
PH
BOOT
PWRGD
GND
GND
AGND
C3
47 PFC4
0.1 PF
R2
12.7k
C6
2200 pF
R3
26.7k
R4
82.5k C7
0.01 PF
L1
1.2 H
C10
47 PFC13
47 PF
R8
51.1
R10
20.0k
C9
47 PF
C8
0.1 PF
R7
100k
VIN = 3-6V VOUT = 1.2V, 6A
10
1
2
15
6
7
8
9
11
12
13
14
3
4
5
16
17
VSNS
VSNS
VIN
PWRGD
VOUT
C12
47 PFC11
47 PF
C2
47 PF
C1
47 PF
C16
220 PF
C14
220 pF
C5
Open
R1
14.7k
EN
VIN
EN
R9
20.0k C15
150 pF
TPS54678
www.ti.com
SLVSBF3A –JUNE 2012–REVISED NOVEMBER 2015
8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
This example details the design of a high-frequency switching regulator design using ceramic output capacitors.
This design is available as the TPS54678EVM-155 (PWR155) evaluation module (EVM).
8.2 Typical Application
This section details a high-frequency, 1.2-V output power supply design application with adjusted UVLO.
Figure 30. Typical Application Schematic, TPS54678
8.2.1 Design Requirements
Table 1 lists the design parameters of the TPS54678.
Table 1. Design Parameters
PARAMETER NOTES AND CONDITIONS MIN TYP MAX UNIT
VIN Input voltage Operating 3 5 6 V
VOUT Output voltage 1.2 V
ΔVOUT Transient response 3-A load step 5%
IOUT(max) Maximum output current 6 A
VOUT(ripple) Output voltage ripple 30 mVP-P
fSW Switching frequency 500 kHz
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RIPPLE
IND _ peak o
I
I I 2
= +
( )
OUT IN _ MAX OUT
IND _ RMS o
IN _ MAX SW
2
2
V V V
1
I I 12 V L1 F
æ ö
´ -
ç ÷
= + ´ ç ÷
´ ´
è ø
IN _ MAX OUT OUT
RIPPLE
IN _ MAX SW
V V V
I L1 V F
-
= ´
´
IN _ MAX OUT OUT
o IND IN _ MAX SW
V V V
L1 I K V F
-
= ´
´ ´
1.052 1.052
SW
56183 56183
R (kΩ) = = = 81.34 kΩ
T(F ) (500)
TPS54678
SLVSBF3A –JUNE 2012–REVISED NOVEMBER 2015
www.ti.com
8.2.2 Detailed Design Procedure
8.2.2.1 Step One: Select the Switching Frequency
The first step is to decide on a switching frequency for the regulator. Typically, it is desirable to choose the
highest switching frequency possible since this produces the smallest component solution size. The high
switching frequency allows for lower value inductors and smaller output capacitors compared to a power supply
that switches at a lower frequency. However, the higher switching frequency causes extra switching losses,
which degrade the performance of the converter. This SWIFT™ converter is capable of running from 200 kHz to
2 MHz. Unless a small solution size is the top priority, a moderate switching frequency of 500 kHz is selected to
achieve both a small solution size and high-efficiency operation. Using Equation 13, RTis calculated to be
81.34 kΩ. A standard 1% 82.5-kΩvalue was chosen for the design.
where
• RTis in kΩ
• FSW is in kHz (13)
8.2.2.2 Step Two: Select the Output Inductor
The inductor selected works for the entire TPS54678 input voltage range. To calculate the value of the output
inductor, use Equation 14. KIND is a coefficient that represents the amount of inductor ripple current relative to the
maximum output current. The inductor ripple current is filtered by the output capacitor. Therefore, choosing high-
inductor ripple currents impacts the selection of the output capacitor because the output capacitor must have a
ripple current rating equal to or greater than the inductor ripple current. In general, the inductor ripple value is at
the discretion of the designer, however KIND is usually chosen between 0.1 to 0.3 for the majority of applications.
For this design example, a value of KIND = 0.3 was used at 6 VIN and 6 AOUT, and the inductor value is calculated
to be 1.06 μH. For this design, the nearest standard value of 1.2 μH was chosen. For the output filter inductor, it
is important that the RMS current and saturation current ratings not be exceeded. The RMS and peak inductor
current can be found from Equation 16 and Equation 17.
For this design, the RMS inductor current is 6.02 A and the peak inductor current is 6.8 A. The chosen inductor is
a Coilcraft XAL5030-122ME. It has a saturation current rating 0f 11.8 A (20% inductance loss) and a RMS
current rating of 8.7 A (20°C temperature rise). The series resistance is 6.78 mΩtypical.
The current flowing through the inductor is the inductor ripple current plus the output current. During power up,
faults or transient load conditions, the inductor current can increase above the calculated peak inductor current
level calculated above. In transient conditions, the inductor current can increase up to the switch current limit of
the device. For this reason, the most conservative approach is to specify an inductor with a saturation current
rating equal to or greater than the switch current limit rather than the peak inductor current.
(14)
(15)
(16)
(17)
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Product Folder Links: TPS54678
RIPPLE
ESR
RIPPLE
V
R
I
<
( )
Bank
RIPPLE
SW
RIPPLE
1 1
C 13.33 F
V
8 F
I
= ´ = m
´
( )
Bank
5.4 J
C 73.17 F
0.7938 0.72
m
= = m
-
( )
CAPInitial
CAPFinal IND
2 2
2
2
Energy 0.5 C V 0.5 C 1.2
Energy 0.5 C 1.2 Energy 0.5 C 1.2 0.06
= ´ ´ = ´ ´
= ´ ´ + = ´ ´ +
IND 2 2
Energy 0.5 L I 0.5 1.2 3 5.4 Joule= ´ ´ = ´ m ´ = m
TPS54678
www.ti.com
SLVSBF3A –JUNE 2012–REVISED NOVEMBER 2015
8.2.2.3 Step Three: Choose the Output Capacitor
There are three primary considerations for selecting the value of the output capacitor. Along with the inductor, the
output capacitor determines the output voltage ripple, and also how the regulator responds to a large change in
load current. The output capacitance needs to be selected based on the more stringent of these two criteria.
The desired response to a large change in the load current is the first criteria. The output capacitor needs to
supply the load with current when the regulator can not due to limited control speed. The regulator is temporarily
not able to supply sufficient change in output current if there is a large, fast increase or decrease in the current
needs of the load such as transitioning from no load to full load. The regulator usually needs two or more clock
cycles for the control loop to see the change in load current and output voltage and adjust the duty cycle to react
to the change. The output capacitor must be sized to supply the extra current to the load until the control loop
responds to the load change, or conversely, absorb the excess current from the inductor. Because the output
voltage is less than half the input voltage, the worst-case deviation in output voltage occurs when the load has an
extremely rapid reduction in current, or a load dump. The desired specification is a 50% or 3-A load step, and a
resulting voltage deviation of no more than 5%, or 60mV. When a load dump occurs, the excess stored current in
the inductor will tend to charge the output capacitors, and the best the converter can achieve to limit the increase
in output voltage is to fold back the duty cycle to zero. Under these circumstances, the amount of rise in output
voltage is defined by the energy from the choke being fully absorbed by the capacitor bank. Equation 18 through
Equation 20 can be used to calculate the required capacitor bank value.
For this example, the transient load response is specified as a 5% change in Vout for a 50% load step from 3 A
to 0 A. So, ΔIOUT = 3 A and ΔVOUT = 0.05 × 1.2 = 0.06 V. Using these numbers gives a minimum capacitance of
73.2 μF. This calculation does not take the ESR of the output capacitor into account in the output voltage
change, and it does not account for latency in control loop speed. For ceramic capacitors, the ESR is usually
small enough to ignore in this calculation.
(18)
(19)
Solving for C:
(20)
This 73.17 µF defines the minimum capacitance required to meet the transient spec; however, because the
control loop speed is finite, more capacitance than this will be required to meet desired performance.
Equation 21 calculates the minimum output capacitance needed to meet the output voltage ripple specification.
In this case, the maximum output voltage ripple is 60 mV. Under this requirement, Equation 21 yields 13.33 µF.
where
• FSW is the switching frequency,
• VRIPPLE is the maximum allowable output voltage ripple,
• and Iripple is the inductor ripple current. (21)
Equation 22 calculates the maximum ESR for the capacitor bank to meet the output voltage ripple specification.
Equation 22 indicates the ESR should be less than 37.5 mΩ. In this case, the ESR of the ceramic capacitor bank
is less than 37.5 mΩ.
(22)
Additional capacitance de-ratings for aging, temperature and DC bias should be factored in which increases the
minimum value calculated in Equation 20. For this example, five 47-μF 10-V X5R ceramic capacitors with 3 mΩ
of ESR are used. The estimated capacitance after derating is 5 × 47 μF × 0.9 = 211.5 μF.
Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback 23
Product Folder Links: TPS54678
OUT
9 10
REF
V
R R 1
V
æ ö
= ´ -
ç ÷
è ø
SS SS
C 3 T= ´
OUT _ MAX
IN
IN SW
I 0.25
VC F
´
D =
´
( )
IN _ MIN OUT
OUT
RMS OUT
IN _ MIN IN _ MIN
V V
V
I I V V
-
= ´ ´
TPS54678
SLVSBF3A –JUNE 2012–REVISED NOVEMBER 2015
www.ti.com
8.2.2.4 Step Four: Select the Input Capacitor
The TPS54678 requires a high-quality ceramic, type X5R or X7R, input-decoupling capacitor of at least 10 μF of
effective capacitance and in some applications a bulk capacitance. The effective capacitance includes any DC
bias effects. The voltage rating of the input capacitor must be greater than the maximum input voltage. The
capacitor must also have a ripple current rating greater than the maximum input current ripple of the TPS54678.
The input ripple current can be calculated using Equation 23.
(23)
The value of a ceramic capacitor varies significantly over temperature and the amount of DC bias applied to the
capacitor. The capacitance variations due to temperature can be minimized by selecting a dielectric material that
is stable over temperature. X5R and X7R ceramic dielectrics are usually selected for power regulator capacitors
because they have a high capacitance to volume ratio and are fairly stable over temperature. The output
capacitor must also be selected with the DC bias taken into account. The capacitance value of a capacitor
decreases as the DC bias across a capacitor increases.
For this example design, a ceramic capacitor with at least a 10-V voltage rating is required to support the
maximum input voltage. For this example, three 47-μF and one 0.10-μF 10-V capacitors in parallel have been
selected. In addition to these low ESR capacitors, an input bulk cap of 220-µF electrolytic is included so as to
provide low source impedance at low frequencies for instances where the input voltage source is connected with
a lossy feed.
The input capacitance value determines the input ripple voltage of the regulator. The input voltage ripple can be
calculated using Equation 24. Using the design example values, IOUT_MAX =6A,CIN = 141 μF (neglecting the
electrolytic due to high ESR), FSW = 500 kHz, yields an input voltage ripple of 21.3 mV and an rms input ripple
current of 2.94 A.
(24)
8.2.2.5 Step Five: Choose the Soft-Start Capacitor
The slow-start capacitor determines the minimum amount of time it takes for the output voltage to reach the
nominal programmed value during power up. This is useful if a load requires a controlled voltage slew rate. This
is also used if the output capacitance is very large and would require large amounts of current to quickly charge
the capacitor to the output voltage level. The large currents necessary to charge the capacitor may cause the
TPS54678 to trip OCP, or excessive current draw from the input power supply may cause the input voltage rail to
sag. Limiting the output voltage slew rate mitigates both of these issues.
The slow-start capacitor value can be calculated using Equation 25. For the example circuit, the slow-start time is
not critical because the output capacitor value is 5 × 47 μF which does not require much current to charge to
1.2 V. The example circuit has the slow-start time set to an arbitrary value of 3.33 ms, which requires a 10-nF
capacitor.
(25)
8.2.2.6 Step Six: Select the Bootstrap Capacitor
A 0.1-μF ceramic capacitor must be connected between the BOOT and PH pins for proper operation. TI
recommends to use a ceramic capacitor with X5R or better grade dielectric. The capacitor should have 10 V or
higher voltage rating.
8.2.2.7 Step Eight: Select Output Voltage and Feedback Resistors
For the example design, 20 kΩwas selected for R10. Using Equation 26, R9 is calculated also as 20 kΩ.
(26)
24 Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated
Product Folder Links: TPS54678
PMOD
OUT LOAD
1
F
2 C R
=
p
( ) ( )
OFF _ MAX
OUT _ MAX OUT _ MAX DS(ON)MAX L OUT _ MAX DS(ON)MAX
DEAD
t
V V 1 I R R 0.7 I R
IN Period
t
Period
æ ö
= ´ - - ´ + - - ´
ç ÷
ç ÷
è ø
æ ö
´ç ÷
è ø
( ) ( )
OUT _ MIN ON _ MIN SW _ MAX IN _ MAX OUT _ MIN DS(ON)MIN OUT _ MIN L DS(ON)MIN
V t F V I R I R R= ´ - ´ - ´ +
TPS54678
www.ti.com
SLVSBF3A –JUNE 2012–REVISED NOVEMBER 2015
8.2.2.7.1 Output Voltage Limitations
Due to the internal design of the TPS54678, there is a minimum output voltage limit for any given input voltage.
The output voltage can never be lower than the internal voltage reference of 0.6 V. Above 0.6 V, the output
voltage may be limited by the minimum controllable ON-time. The minimum output voltage in this case is given
by Equation 27.
where
• VOUT_MIN = minimum achievable output voltage
• tON_MIN = minimum controllable ON-time (100 ns typical, 120 ns no load)
• FSW_MAX = maximum switching frequency including tolerance
• VIN_MAX = maximum input voltage
• IOUT_MIN = minimum load current
• RDS(ON)_MIN = minimum high-side MOSFET ON-resistance (see Electrical Characteristics)
• RL= series resistance of output inductor (27)
There is also a maximum achievable output voltage which is limited by the minimum off time. The maximum
output voltage is given by Equation 28.
where
• VOUT_MAX = maximum achievable output voltage
• VIN = minimum input voltage
• tOFF_MAX = maximum OFF-time (180 ns typical for adequate margin)
• Period = 1/Fs
• IOUT_MAX = maximum current
• RDS(ON)_MAX = maximum high-side MOSFET ON-resistance (see Electrical Characteristics)
• RL= DCR of the inductor
• tDEAD = dead time (40 ns) (28)
8.2.2.8 Step Nine: Select Loop Compensation Components
There are several possible methods to design closed-loop compensation for DC–DC converters. For the ideal
current mode control, the design equations can be easily simplified. The power stage gain is constant at low
frequencies, and rolls off at –20 dB/decade above the modulator pole frequency. The power stage phase is zero
degrees at low frequencies and starts to fall one decade below the modulator pole frequency reaching a
minimum of –90 degrees one decade above the modulator pole frequency. In this case the modulator pole is a
simple pole shown in Equation 29.
(29)
For the TPS54678 most circuits will have relatively high amounts of slope compensation. As more slope
compensation is applied, the power stage characteristics will deviate from the ideal approximations. The phase
loss of the power stage will extend beyond –90 degrees and can approach –180 degrees, making compensation
more difficult. The power stage transfer function can be solved but it is a tedious hand calculation that does not
lend itself to simple approximations. It is easier to either simulate the circuit or to actually measure the plant
transfer function so that a reliable compensation circuit can be designed. The latter technique used in this design
procedure. The power stage plant was measured and is shown in Figure 31.
Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback 25
Product Folder Links: TPS54678
( )
p
15 9 10
1
F2 C R || R
=p
z
15 9
1
F
2 C R
=
p
5
3 pole
1
C2 R F
=
p
6
3 plantpole
1
C2 R F
=
p
Plant
3
EA REF
OUT
G
20 V
10
Rgm V
-
æ ö
ç ÷
è ø
= ´
100 1000 10000 100000 1000000
−50
−40
−30
−20
−10
0
10
20
30
−225
−180
−135
−90
−45
0
45
90
135
Frequency (Hz)
Gain (dB)
Phase (°)
Gain
Phase
G001
TPS54678
SLVSBF3A –JUNE 2012–REVISED NOVEMBER 2015
www.ti.com
Figure 31. Measured Plant Bode
For this design, the desired crossover frequency Fc is 50 kHz. From the power stage gain and phase plot above,
the gain at 50 kHz is –10.6 dB and the phase is –123.3 degrees. Because the plant phase loss is greater than
–90 degrees, to achieve at least 60 degrees of phase margin, additional phase boost from a feedforward
capacitor in parallel with the upper resistor of the voltage set point divider is required.
See the schematic in Figure 30. R3 sets the gain of the compensated error amplifier to be equal and opposite (in
dB) to the power stage gain at Fc, so 10.6 dB is needed. The required value of R3 can be calculated from
Equation 30.
(30)
The compensator zero formed by R3 and C6 is placed at the plant pole, as shown approximately 2.5 kHz. The
required value for C6 is given by Equation 31.
(31)
The high-frequency noise pole formed by C5 and R3 is not used in this design. If the resulting design shows
noise susceptibility, the value of C5 can be calculated per Equation 32.
(32)
To avoid a penalty in loop phase, the Fpole in Equation 32 should be placed a decade above Fc or higher, and is
intended to reject noise at FSW.
The feedforward capacitor C15 is used to increase the phase boost at crossover above what is normally
available from Type II compensation. It places an additional zero/pole pair with the zero located at Equation 33
and the pole at Equation 34.
(33)
(34)
This zero and pole pair is not independent since R9 and R10 are set by the desired VOUT. Once the zero location
is chosen, the pole is fixed as well. For optimum performance, the zero and pole should be located symmetrically
about the intended crossover frequency. The required value for C15 can be calculated from Equation 35.
26 Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated
Product Folder Links: TPS54678
15
9 c
O
R
U
F
T
E
1
C
V
2 R F
V
=
p
TPS54678
www.ti.com
SLVSBF3A –JUNE 2012–REVISED NOVEMBER 2015
(35)
Table 2 lists the values the compensation equations yield.
Table 2. Frequency Compensation Component Values
REF DES CALCULATED VALUE CHOSEN VALUE
R3 19.6 kΩ26.7 kΩ
C6 2.38 nF 2.2 nF
C15 225 pF 150 pF
8.2.3 Application Curves
Figure 32 through Figure 47 were measured on the TPS54678 Evaluation Module. More explanation of
waveforms, as well as a schematic document can be found in the TPS54678EVM-155 6-A, SWIFT™ Regulator
Evaluation Module user guide, SLVU747.
8.2.3.1 Additional Information About Application Curves
8.2.3.1.1 Efficiency
System efficiency may be lower than shown in Figure 32 at higher ambient temperatures, due to temperature
variation in the drain-to-source resistance RDS(ON) of the internal MOSFETs.
8.2.3.1.2 Voltage Ripple Measurements
Probe placement and noise pickup can give unreliable voltage ripple results. Figure 37 and Figure 38 show the
output voltage ripple of the converter, measured directly across the output capacitors. Likewise, Figure 39 and
Figure 40 show the input voltage ripple of the converter, measured directly across the input capacitors.
8.2.3.1.3 Start-Up and Shutdown Waveforms
Figure 41 and Figure 42 show the start-up waveforms for the TPS54678EVM-155. In Figure 41, the output
voltage ramps up as soon as the input voltage reaches the UVLO threshold as set by the R1 and R2 resistor
divider network. In Figure 42, the input voltage is initially applied and the output is inhibited by using a jumper at
JP1 to tie EN to GND. When the jumper is removed, EN is released. When the EN voltage reaches the enable-
threshold voltage, the start-up sequence begins and the output voltage ramps up to the externally set value of
1.2 V.
The TPS54678 is designed to start up into prebiased outputs. Figure 43 shows the output voltage start-up
waveform when the output is prebiased with 550 mV at no load.
Figure 44 and Figure 45 show the shutdown waveforms for the TPS54678EVM-155. In Figure 44, the output
voltage ramps down as soon as the input voltage falls below the UVLO stop threshold as set by the R1 and R2
resistor divider network. At the point of shutdown, the input voltage rises slightly due to the resistive drop in the
input feed impedance. In Figure 45, the output is inhibited by using a jumper at JP1 to tie EN to GND.
8.2.3.1.4 Hiccup Mode Current Limit
The TPS54678 has hiccup mode current limit. When the peak switch current exceeds the current limit threshold,
the device shuts down and restarts. Hiccup mode current limit operation is shown in Figure 46 and Figure 47.
Figure 46 shows the hiccup mode current limit with a slight resistive overload. When the peak current limit is
exceeded, the output voltage is disabled. Figure 47 shows the operation of the TPS54678 with the output
shorted to ground. The device continuously resets until the fault condition is removed.
Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback 27
Product Folder Links: TPS54678
V = 20 mV / div (ac coupled)
OUT
Time = 500 ns/div
SW Node = 5 V / div
V = 3 V
I = 6 A
IN
OUT
100 1000 10000 100000 1000000
−20
−10
0
10
20
30
40
50
−60
−30
0
30
60
90
120
150
Frequency (Hz)
Gain (dB)
Phase (°)
Gain
Phase
G005
1.2050
1.2055
1.2060
1.2065
1.2070
1.2075
1.2080
1.2085
1.2090
1.2095
1.2100
3 3.5 4 4.5 5 5.5 6
Input Voltage (V)
Output Voltage (V)
3 A
4 A
5 A
6 A
G003
V = 50 mV / div (ac coupled)
OUT
Time = 100 s/divm
I = 1 A / div
OUT
Load step = 0 - 3 A
80
82
84
86
88
90
92
94
96
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6
Output Current (A)
Efficiency (%)
3 V
4 V
5 V
6 V
G002
1.2050
1.2055
1.2060
1.2065
1.2070
1.2075
1.2080
1.2085
1.2090
1.2095
1.2100
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6
Output Current (A)
Output Voltage (V)
3 V
4 V
5 V
6 V
G003
TPS54678
SLVSBF3A –JUNE 2012–REVISED NOVEMBER 2015
www.ti.com
Figure 32. Efficiency vs Load Current Figure 33. Load Regulation
Figure 35. Transient Response
Figure 34. Line Regulation
VIN = 3 V, IOUT = 6 A
Figure 36. Loop Response Figure 37. Output Ripple
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Product Folder Links: TPS54678
I = 1 A / div
(inverted for clarity)
OUT
Time = 500 s/divm
V = 200 mV / div
OUT
V = 1 V / div
IN
I = 4.6 A
OUT
I = 1 A / div
(inverted for clarity)
OUT
Time = 500 s/divm
V = 200 mV / div
OUT
V = 1 V / div
IN
I = 4.6 A
OUT
V = 50 mV / div (ac coupled)
20 MHZ BW Limited
IN
Time = 500 ns/div
SW Node = 5 V / div
V = 6 V
I = 6 A
IN
OUT
I = 1 A / div (inverted for clarity)
OUT
Time = 500 s/divm
V = 200 mV / div
OUT
V = 1 V / div
IN
I = 4.6 A
OUT
V = 20 mV / div (ac coupled)
OUT
Time = 500 ns/div
SW Node = 5 V / div
V = 6 V
I = 6 A
IN
OUT
V = 50 mV / div
(ac coupled)
20 MHZ BW Limited
IN
Time = 500 ns/div
SW Node = 5 V / div
V = 3 V
I = 6 A
IN
OUT
TPS54678
www.ti.com
SLVSBF3A –JUNE 2012–REVISED NOVEMBER 2015
VIN = 6 V, IOUT = 6 A VIN = 3 V, IOUT = 6 A
Figure 38. Output Ripple Figure 39. Input Ripple
VIN = 6 V, IOUT = 6 A Figure 41. Start-Up Relative to VIN
Figure 40. Input Ripple
Figure 42. Start-Up Relative to Enable Figure 43. Start-Up into Prebias
Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback 29
Product Folder Links: TPS54678
Time = 5 ms/div
V = 200 mV / div
OUT
V = 1 V / div
IN
V = 5 V
I = 9.2 A
IN
OUT
I = 1 A / div
OUT
Time = 5 ms/div
V = 100 mV / div
OUT
V = 6 V
I = short
IN
OUT
I = 5 A / div
OUT
Time = 100 s/divm
V = falling, 200 mV / div
OUT
V = 1 V / div (near 2.7 V)
IN
I = 6.6 A
OUT
I = 1 A / div (invertey for clarity)
OUT
Time = 100 s/divm
V = falling, 200 mV / div
OUT
V = 1 V / div
IN
V = 5 V
I = 6.6 A
IN
OUT
I = 1 A / div (inverted for clarity)
OUT
TPS54678
SLVSBF3A –JUNE 2012–REVISED NOVEMBER 2015
www.ti.com
Figure 44. Shutdown Relative to VIN Figure 45. Shutdown Relative to Enable
Figure 46. Hiccup Mode Current Limit Shutdown Figure 47. Hiccup Mode Current Limit Restart into Short
Circuit
30 Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated
Product Folder Links: TPS54678
TPS54678
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SLVSBF3A –JUNE 2012–REVISED NOVEMBER 2015
9 Power Supply Recommendations
These devices are designed to operate from an input voltage supply between 2.95 V and 6 V. This supply must
be well regulated. Proper bypassing of input supplies and internal regulators is also critical for noise
performance, as is PCB layout and grounding scheme. See the recommendations in the Layout Guidelines
section.
10 Layout
10.1 Layout Guidelines
Layout is a critical portion of good power supply design. There are several signal paths that conduct fast
changing currents or voltages that can interact with stray inductance or parasitic capacitance to generate noise
or degrade the power supplies performance.
• Minimize the loop area formed by the bypass capacitor connections and the VIN pins. See Figure 48 for a
PCB layout example.
• The GND pins and AGND pin should be tied directly to the thermal pad under the TPS54678 device. The
thermal pad should be connected to any internal PCB ground planes using multiple vias directly under the
device. Additional vias can be used to connect the top-side ground area to the internal planes near the input
and output capacitors. For operation at full rated load, the top-side ground area along with any additional
internal ground planes must provide adequate heat dissipating area.
• Place the input bypass capacitor as close as possible to the device.
• Route the PH pin to the output inductor. Because the PH connection is the switching node, place the output
inductor close to the PH pins. Minimize the area of the PCB conductor to prevent excessive capacitive
coupling.
• The boot capacitor must also be located close to the device.
• The sensitive analog ground connections for the feedback voltage divider, compensation components, soft-
start capacitor and frequency set resistor should be connected to a separate analog ground trace as shown in
Figure 48.
• The RT/CLK pin is particularly sensitive to noise so the RT resistor should be located as close as possible to
the device and routed with minimal trace lengths.
• The additional external components can be placed approximately as shown. It is possible to obtain
acceptable performance with alternate PCB layouts, however, this layout has been shown to produce good
results and can be used as a guide.
Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback 31
Product Folder Links: TPS54678
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www.ti.com
10.2 Layout Example
Figure 48. TPS54678 Layout Example
10.3 Power Dissipation Estimate
The following formulas show how to estimate the IC power dissipation under continuous conduction mode (CCM)
operation. The power dissipation of the IC (Ptot) includes conduction loss (Pcon), dead time loss (Pd), switching
loss (Psw), gate drive loss (Pgd) and supply current loss (Pq).
Pcon = IO2× RDS(on) (temperature dependent)
where
• IOis the output current (A)
• RDS(on) is the on-resistance of the high-side MOSFET with given temperature (Ω) (36)
Pd = ƒsw × IO× 0.7 × (20 nS + 20 nS)
where
• IOis the output current (A)
• ƒsw is the switching frequency (Hz) (37)
Psw = 0.5 × VIN × IO× ƒsw× 7 × 10–9
where
• IOis the output current (A)
• VIN is the input voltage (V)
• ƒsw is the switching frequency (Hz) (38)
Pgd = 2 × VIN × ƒsw× 6 × 10–9
where
• VIN is the input voltage (V)
• ƒsw is the switching frequency (Hz) (39)
Pq= VIN × 500 × 10–6
where
• VIN is the input voltage (V) (40)
32 Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated
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SLVSBF3A –JUNE 2012–REVISED NOVEMBER 2015
Power Dissipation Estimate (continued)
So Ptot = Pcon + Pd+ Psw + Pgd + Pq
where
• Ptot is the total device power dissipation (W) (41)
For given TA,
TJ= TA+ Rth × Ptot
where
• Ptot is the total device power dissipation (W)
• TAis the ambient temperature (°C)
• TJis the junction temperature (°C)
• Rth is the thermal resistance of the package (°C/W) (42)
For given TJmax = 150°C
TAmax = TJmax – Rth × Ptot
where
• Ptot is the total device power dissipation (W)
• Rth is the thermal resistance of the package (°C/W)
• TJmax is maximum junction temperature (°C)
• TAmax is maximum ambient temperature (°C) (43)
There are additional power losses in the regulator circuit due to the inductor AC and DC losses and trace
resistance that impact the overall efficiency of the regulator.
Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback 33
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
11.1.2 Development Support
The TPS54618 device is supported in the SwitcherPro™ Software Tool at www.ti.com/switcherpro.
For more SWIFTTM documentation, see the TI website at www.ti.com/swift.
11.2 Documentation Support
11.2.1 Related Documentation
For related documentation, see the following:
TPS54678EVM-155 6-A, SWIFT™ Regulator Evaluation Module (SLVU747)
11.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.4 Trademarks
SWIFT, SwitcherPro, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.6 Glossary
SLYZ022 —TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
34 Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated
Product Folder Links: TPS54678
PACKAGE OPTION ADDENDUM
www.ti.com 17-Jan-2018
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
TPS54678RTER ACTIVE WQFN RTE 16 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 150 54678
TPS54678RTET ACTIVE WQFN RTE 16 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 150 54678
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 17-Jan-2018
Addendum-Page 2
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TPS54678RTER WQFN RTE 16 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
TPS54678RTET WQFN RTE 16 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
PACKAGE MATERIALS INFORMATION
www.ti.com 7-Sep-2017
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPS54678RTER WQFN RTE 16 3000 367.0 367.0 35.0
TPS54678RTET WQFN RTE 16 250 210.0 185.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 7-Sep-2017
Pack Materials-Page 2
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TI’s provision of technical, application or other design advice, quality characterization, reliability data or other services or information,
including, but not limited to, reference designs and materials relating to evaluation modules, (collectively, “TI Resources”) are intended to
assist designers who are developing applications that incorporate TI products; by downloading, accessing or using TI Resources in any
way, Designer (individually or, if Designer is acting on behalf of a company, Designer’s company) agrees to use any particular TI Resource
solely for this purpose and subject to the terms of this Notice.
TI’s provision of TI Resources does not expand or otherwise alter TI’s applicable published warranties or warranty disclaimers for TI
products, and no additional obligations or liabilities arise from TI providing such TI Resources. TI reserves the right to make corrections,
enhancements, improvements and other changes to its TI Resources. TI has not conducted any testing other than that specifically
described in the published documentation for a particular TI Resource.
Designer is authorized to use, copy and modify any individual TI Resource only in connection with the development of applications that
include the TI product(s) identified in such TI Resource. NO OTHER LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE
TO ANY OTHER TI INTELLECTUAL PROPERTY RIGHT, AND NO LICENSE TO ANY TECHNOLOGY OR INTELLECTUAL PROPERTY
RIGHT OF TI OR ANY THIRD PARTY IS GRANTED HEREIN, including but not limited to any patent right, copyright, mask work right, or
other intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information
regarding or referencing third-party products or services does not constitute a license to use such products or services, or a warranty or
endorsement thereof. Use of TI Resources may require a license from a third party under the patents or other intellectual property of the
third party, or a license from TI under the patents or other intellectual property of TI.
TI RESOURCES ARE PROVIDED “AS IS” AND WITH ALL FAULTS. TI DISCLAIMS ALL OTHER WARRANTIES OR
REPRESENTATIONS, EXPRESS OR IMPLIED, REGARDING RESOURCES OR USE THEREOF, INCLUDING BUT NOT LIMITED TO
ACCURACY OR COMPLETENESS, TITLE, ANY EPIDEMIC FAILURE WARRANTY AND ANY IMPLIED WARRANTIES OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT OF ANY THIRD PARTY INTELLECTUAL
PROPERTY RIGHTS. TI SHALL NOT BE LIABLE FOR AND SHALL NOT DEFEND OR INDEMNIFY DESIGNER AGAINST ANY CLAIM,
INCLUDING BUT NOT LIMITED TO ANY INFRINGEMENT CLAIM THAT RELATES TO OR IS BASED ON ANY COMBINATION OF
PRODUCTS EVEN IF DESCRIBED IN TI RESOURCES OR OTHERWISE. IN NO EVENT SHALL TI BE LIABLE FOR ANY ACTUAL,
DIRECT, SPECIAL, COLLATERAL, INDIRECT, PUNITIVE, INCIDENTAL, CONSEQUENTIAL OR EXEMPLARY DAMAGES IN
CONNECTION WITH OR ARISING OUT OF TI RESOURCES OR USE THEREOF, AND REGARDLESS OF WHETHER TI HAS BEEN
ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
Unless TI has explicitly designated an individual product as meeting the requirements of a particular industry standard (e.g., ISO/TS 16949
and ISO 26262), TI is not responsible for any failure to meet such industry standard requirements.
Where TI specifically promotes products as facilitating functional safety or as compliant with industry functional safety standards, such
products are intended to help enable customers to design and create their own applications that meet applicable functional safety standards
and requirements. Using products in an application does not by itself establish any safety features in the application. Designers must
ensure compliance with safety-related requirements and standards applicable to their applications. Designer may not use any TI products in
life-critical medical equipment unless authorized officers of the parties have executed a special contract specifically governing such use.
Life-critical medical equipment is medical equipment where failure of such equipment would cause serious bodily injury or death (e.g., life
support, pacemakers, defibrillators, heart pumps, neurostimulators, and implantables). Such equipment includes, without limitation, all
medical devices identified by the U.S. Food and Drug Administration as Class III devices and equivalent classifications outside the U.S.
TI may expressly designate certain products as completing a particular qualification (e.g., Q100, Military Grade, or Enhanced Product).
Designers agree that it has the necessary expertise to select the product with the appropriate qualification designation for their applications
and that proper product selection is at Designers’ own risk. Designers are solely responsible for compliance with all legal and regulatory
requirements in connection with such selection.
Designer will fully indemnify TI and its representatives against any damages, costs, losses, and/or liabilities arising out of Designer’s non-
compliance with the terms and provisions of this Notice.
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