128Mb: x4, x8, x16 SDRAM Features SDRAM MT48LC32M4A2 - 8 Meg x 4 x 4 banks MT48LC16M8A2 - 4 Meg x 8 x 4 banks MT48LC8M16A2 - 2 Meg x 16 x 4 banks For the latest data sheet, refer to Micron's Web site: www.micron.com Features Figure 1: * PC100- and PC133-compliant * Fully synchronous; all signals registered on positive edge of system clock * Internal pipelined operation; column address can be changed every clock cycle * Internal banks for hiding row access/precharge * Programmable burst lengths (BL): 1, 2, 4, 8, or full page * Auto precharge, includes concurrent auto precharge, and auto refresh modes * Self refresh mode; standard and low power * 64ms, 4,096-cycle refresh (commercial & industrial) * 16ms, 4,096-cycle refresh (Automotive) * LVTTL-compatible inputs and outputs * Single +3.3 0.3V power supply Options Notes: 1. 2. 3. 4. x4 x8 x16 NC DQ0 NC NC NC DQ1 NC NC - 32M4 16M8 8M16 A2 Notes: TG P FB3 BB3 F44 B44 VDD DQ0 DQ0 - VDDQ NC DQ1 DQ1 DQ2 - VssQ NC DQ3 DQ2 DQ4 - VDDQ NC DQ5 DQ3 DQ6 - VssQ NC DQ7 VDD NC DQML - WE# - CAS# - RAS# CS# BA0 BA1 A10 A0 A1 A2 A3 VDD - x16 x8 x4 NC DQ3 NC NC NC DQ2 NC DQM - 32 Meg x 4 16 Meg x 8 8 Meg x 16 8 Meg x 4 x 4 banks 4 Meg x 8 x 4 banks 2 Meg x 16 x 4 banks 4K 4K 4K Row addressing 4K (A0-A11) 4K (A0-A11) 4K (A0-A11) Bank addressing 4 (BA0, BA1) 4 (BA0, BA1) 4 (BA0, BA1) 2K (A0-A9, A11) 1K (A0-A9) 512 (A0-A8) Refresh count Column addressing Table 2: None L :G NC Address Table Configuration -75 -7E -6A Vss DQ15 DQ7 VssQ DQ14 NC DQ13 DQ6 VDDQ DQ12 NC DQ11 DQ5 VssQ DQ10 NC DQ9 DQ4 VDDQ DQ8 NC Vss NC DQMH DQM CLK CKE NC A11 A9 A8 A7 A6 A5 A4 Vss - 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 1. The # symbol indicates signal is active LOW. A dash (-) indicates x8 and x4 pin function is same as x16 pin function. Table 1: Key Timing Parameters CL = CAS (Read) latency Access Time Speed Grade None IT3 AT3 Refer to Micron technical note: TN-48-05. Off-center parting line. Consult Micron for availability. x16 only. PDF: 09005aef8091e66d/Source: 09005aef8091e625 128MSDRAM_1.fm - Rev. N 1/09 EN - NC Designator * Configurations - 32 Meg x 4 (8 Meg x 4 x 4 banks) - 16 Meg x 8 (4 Meg x 8 x 4 banks) - 8 Meg x 16 (2 Meg x 16 x 4 banks) * Write recovery (tWR) - tWR = "2 CLK"1 * Package/Pinout - Plastic package - OCPL2 - 54-pin TSOP II (400 mil) - 54-pin TSOP II (400 mil) Pb-free - 60-ball FBGA (8mm x 16mm) - 60-ball FBGA (8mm x 16mm) Pb-free - 54-ball VFBGA (8mm x 8mm) - 54-ball VFBGA (8mm x 8mm) Pb-free * Timing (cycle time) - 7.5ns @ CL = 3 (PC133) - 7.5ns @ CL = 2 (PC133) - 6.0ns @ CL = 3 (x16 only) * Self refresh - Standard - Low power * Design revision * Operating temperature range - Commercial (0C to +70C) - Industrial (-40C to +85C) - Automotive (-40C to +105C) 54-Pin TSOP Pin Assignment (Top View) 1 Clock Frequency CL = 2 CL = 3 Setup Time Hold Time -6A 167 MHz - 5.4ns 1.5ns 0.8ns -7E 143 MHz - 5.4ns 1.5ns 0.8ns -7E 133 MHz 5.4ns - 1.5ns 0.8ns -75 133 MHz - 5.4ns 1.5ns 0.8ns -75 100 MHz 6ns - 1.5ns 0.8ns Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)1999 Micron Technology, Inc. All rights reserved. Products and specifications discussed herein are subject to change by Micron without notice. 128Mb: x4, x8, x16 SDRAM General Description Table 3: 128Mb SDRAM Part Numbers Part Number Architecture 32 Meg x 4 32 Meg x 4 16 Meg x 8 16 Meg x 8 16 Meg x 8 16 Meg x 8 8 Meg x 16 8 Meg x 16 8 Meg x 16 8 Meg x 16 MT48LC32M4A2TG MT48LC32M4A2P MT48LC16M8A2TG MT48LC16M8A2P MT48LC16M8A2FB1 MT48LC16M8A2BB1 MT48LC8M16A2TG MT48LC8M16A2P MT48LC8M16A2B41 MT48LC8M16A2F41 Notes: 1. FBGA Device Decode: http://www.micron.com/support/FBGA/FBGA.asp General Description The Micron(R) 128Mb SDRAM is a high-speed CMOS, dynamic random access memory containing 134,217,728 bits. It is internally configured as a quad-bank DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Each of the x4's 33,554,432-bit banks is organized as 4,096 rows by 2,048 columns by 4 bits. Each of the x8's 33,554,432-bit banks is organized as 4,096 rows by 1,024 columns by 8 bits. Each of the x16's 33,554,432-bit banks is organized as 4,096 rows by 512 columns by 16 bits. Read and write accesses to the SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command, which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command are used to select the bank and row to be accessed (BA0, BA1 select the bank; A0-A11 select the row). The address bits registered coincident with the READ or WRITE command are used to select the starting column location for the burst access. The SDRAM provides for programmable read or write burst lengths of 1, 2, 4, or 8 locations, or the full page, with a burst terminate option. An auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst sequence. The 128Mb SDRAM uses an internal pipelined architecture to achieve high-speed operation. This architecture is compatible with the 2n rule of prefetch architectures, but it also allows the column address to be changed on every clock cycle to achieve a high-speed, fully random access. Precharging one bank while accessing one of the other three banks will hide the precharge cycles and provide seamless high-speed, random-access operation. The 128Mb SDRAM is designed to operate in 3.3V memory systems. An auto refresh mode is provided along with a power-saving, power-down mode. All inputs and outputs are LVTTL-compatible. SDRAMs offer substantial advances in DRAM operating performance, including the ability to synchronously burst data at a high data rate with automatic column-address generation, the ability to interleave between internal banks to hide precharge time, and the capability to randomly change column addresses on each clock cycle during a burst access. PDF: 09005aef8091e66d/Source: 09005aef8091e625 128MSDRAM_1.fm - Rev. N 1/09 EN 2 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)1999 Micron Technology, Inc. All rights reserved. 128Mb: x4, x8, x16 SDRAM Automotive Temperature Automotive Temperature The automotive temperature (AT) option adheres to the following specifications: * 16ms refresh rate * Self refresh not supported * Ambient and case temperature cannot be less than -40C or greater than +105C PDF: 09005aef8091e66d/Source: 09005aef8091e625 128MSDRAM_1.fm - Rev. N 1/09 EN 3 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)1999 Micron Technology, Inc. All rights reserved. 128Mb: x4, x8, x16 SDRAM Table of Contents Table of Contents Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 Automotive Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 FBGA Ball Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 Functional Block Diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 Pin/Ball Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 Mode Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 Burst Length (BL). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 Burst Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 CAS Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 Operating Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 Write Burst Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 COMMAND INHIBIT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 NO OPERATION (NOP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 LOAD MODE REGISTER (LMR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 ACTIVE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 PRECHARGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 BURST TERMINATE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 AUTO REFRESH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 SELF REFRESH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 Bank/row Activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 Reads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 WRITEs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 PRECHARGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 Power-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 Clock Suspend. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 BURST READ/SINGLE WRITE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 Concurrent Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 READ with Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 WRITE with Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 Electrical Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 Temperature and Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 Timing Diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72 PDF: 09005aef8091e66d/Source: 09005aef8091e625 128MSDRAMTOC.fm - Rev. N 1/09 EN 4 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)1999 Micron Technology, Inc. All rights reserved. 128Mb: x4, x8, x16 SDRAM List of Figures List of Figures Figure 1: Figure 2: Figure 3: Figure 4: Figure 5: Figure 6: Figure 7: Figure 8: Figure 9: Figure 10: Figure 11: Figure 12: Figure 13: Figure 14: Figure 15: Figure 16: Figure 17: Figure 18: Figure 19: Figure 20: Figure 21: Figure 22: Figure 23: Figure 24: Figure 25: Figure 26: Figure 27: Figure 28: Figure 29: Figure 30: Figure 31: Figure 32: Figure 33: Figure 34: Figure 35: Figure 36: Figure 37: Figure 38: Figure 39: Figure 40: Figure 41: Figure 42: Figure 43: Figure 44: Figure 45: Figure 46: Figure 47: Figure 48: Figure 49: Figure 50: Figure 51: Figure 52: Figure 53: Figure 54: Figure 55: Figure 56: 54-Pin TSOP Pin Assignment (Top View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 60-Ball FBGA Ball Assignments (Top View), 16 Meg x 8, 8mm x 16mm . . . . . . . . . . . . . . . . . . . . . . . . . .8 54-Ball VFBGA Assignments (Top View), 8 Meg x 16, 8mm x 8mm . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 32 Meg x 4 SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 16 Meg x 8 SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 8 Meg x 16 SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Mode Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 CAS Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 Activating a Specific Row in a Specific Bank . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 Example: Meeting tRCD (MIN) When 2 < tRCD (MIN)/tCK 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 READ Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 CAS Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 Consecutive READ Bursts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 Random READ Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 READ-to-WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 READ-to-WRITE with Extra Clock Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 READ-to-PRECHARGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 Terminating a READ Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 WRITE Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 WRITE Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 WRITE-to-WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 Random WRITE Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 WRITE-to-READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 WRITE-to-PRECHARGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 Terminating a WRITE Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 PRECHARGE Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 Power-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 Clock Suspend During WRITE Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 Clock Suspend During READ Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 READ With Auto Precharge Interrupted by a READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 READ With Auto Precharge Interrupted by a WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 WRITE With Auto Precharge Interrupted by a READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 WRITE With Auto Precharge Interrupted by a WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 Example Temperature Test Point Location, 54-Pin TSOP: Top View . . . . . . . . . . . . . . . . . . . . . . . . . . .48 Example Temperature Test Point Location, 54-Ball VFBGA: Top View . . . . . . . . . . . . . . . . . . . . . . . . .48 Example Temperature Test Point Location, 60-Ball FBGA: Top View . . . . . . . . . . . . . . . . . . . . . . . . . .48 Initialize and Load Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 Power-Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 Clock Suspend Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 Auto Refresh Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 Self Refresh Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 READ - Without Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 READ - With Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 Single READ - Without Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 Single READ - With Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 Alternating Bank Read Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 READ - Full-Page Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 READ - DQM Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 WRITE - Without Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 WRITE - With Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66 Single WRITE - Without Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 Single WRITE - With Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68 Alternating Bank Write Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69 WRITE - Full-Page Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70 WRITE - DQM Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71 54-Pin Plastic TSOP (400 mil) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72 PDF: 09005aef8091e66d/Source: 09005aef8091e625 128MSDRAMLOF.fm - Rev. N 1/09 EN 5 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)1999 Micron Technology, Inc. All rights reserved. 128Mb: x4, x8, x16 SDRAM List of Figures Figure 57: Figure 58: 60-Ball FBGA "FB/BB" Package (x8 device), 8mm x 16mm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73 54-Ball VFBGA "F4/B4" Package (x16 device), 8mm x 8mm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74 PDF: 09005aef8091e66d/Source: 09005aef8091e625 128MSDRAMLOF.fm - Rev. N 1/09 EN 6 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)1999 Micron Technology, Inc. All rights reserved. 128Mb: x4, x8, x16 SDRAM List of Tables List of Tables Table 1: Table 2: Table 3: Table 4: Table 5: Table 6: Table 7: Table 8: Table 9: Table 10: Table 11: Table 12: Table 13: Table 14: Table 15: Table 16: Table 17: Table 18: Address Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Key Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 128Mb SDRAM Part Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 Pin/Ball Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Burst Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 CAS Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 Truth Table 1 - Commands and DQM Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 Truth Table 2 - CKE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 Truth Table 3 - Current State Bank n, Command to Bank n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 Truth Table 4 - Current State Bank n, Command to Bank m . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 Temperature Limits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 Thermal Impedance Simulated Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 DC Electrical Characteristics and Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 IDD Specifications and Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 Electrical Characteristics and Recommended AC Operating Conditions . . . . . . . . . . . . . . . . . . . . . . .50 AC Functional Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 PDF: 09005aef8091e66d/Source: 09005aef8091e625 128MSDRAMLOT.fm - Rev. N 1/09 EN 7 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)1999 Micron Technology, Inc. All rights reserved. 128Mb: x4, x8, x16 SDRAM FBGA Ball Assignments FBGA Ball Assignments Figure 2: 60-Ball FBGA Ball Assignments (Top View), 16 Meg x 8, 8mm x 16mm 7 8 Vss VDD DQ0 NC VssQ VDDQ NC C VDDQ DQ6 DQ1 VssQ D DQ5 NC NC DQ2 E NC VssQ VDDQ NC F VDDQ DQ4 DQ3 VssQ G NC NC NC NC H NC Vss VDD NC J NC DQM WE# CAS# K NC CK RAS# NC L NC CKE NC CS# M A11 A9 BA1 BA0 N A8 A7 A0 A10 P A6 A5 A2 A1 R A4 Vss VDD A3 1 2 A DQ7 B 3 4 5 6 Depopulated Balls PDF: 09005aef8091e66d/Source: 09005aef8091e625 128MSDRAM_2.fm - Rev. N 1/09 EN 8 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)1999 Micron Technology, Inc. All rights reserved. 128Mb: x4, x8, x16 SDRAM FBGA Ball Assignments Figure 3: 54-Ball VFBGA Assignments (Top View), 8 Meg x 16, 8mm x 8mm 1 2 3 A VSS DQ15 B DQ14 C 4 5 6 7 8 9 VSSQ VDDQ DQ0 VDD DQ13 VDDQ VSSQ DQ2 DQ1 DQ12 DQ11 VSSQ VDDQ DQ4 DQ3 D DQ10 DQ9 VDDQ VSSQ DQ6 DQ5 E DQ8 NC VSS VDD DQML DQ7 F DQMH CLK CKE CAS# RAS# WE# G NC/A12 A11 A9 BA0 BA1 CS# H A8 A7 A6 A0 A1 A10 J VSS A5 A4 A3 A2 VDD Top View (Ball Down) Notes: PDF: 09005aef8091e66d/Source: 09005aef8091e625 128MSDRAM_2.fm - Rev. N 1/09 EN 1. The balls at A4, A5, and A6 are not in the physical package. They are included in the drawing to illustrate that rows 4, 5, and 6 exist but contain no solder balls. 9 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)1999 Micron Technology, Inc. All rights reserved. 128Mb: x4, x8, x16 SDRAM Functional Block Diagrams Functional Block Diagrams Figure 4: 32 Meg x 4 SDRAM CKE CLK COMMAND DECODE CS# WE# CAS# RAS# CONTROL LOGIC BANK3 BANK2 BANK1 MODE REGISTER REFRESH 12 COUNTER 12 ROWADDRESS MUX 12 12 BANK0 ROWADDRESS 4,096 LATCH & DECODER BANK0 MEMORY ARRAY (4,096 x 2,048 x 4) 1 DQM SENSE AMPLIFIERS 4 4,096 I/O GATING DQM MASK LOGIC READ DATA LATCH WRITE DRIVERS 2 A0-A11, BA0, BA1 14 ADDRESS REGISTER 2 BANK CONTROL LOGIC DATA OUTPUT REGISTER 4 4 2,048 (x4) 1 DQ0- DQ3 DATA INPUT REGISTER COLUMN DECODER 11 PDF: 09005aef8091e66d/Source: 09005aef8091e625 128MSDRAM_2.fm - Rev. N 1/09 EN COLUMNADDRESS COUNTER/ LATCH 11 10 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)1999 Micron Technology, Inc. All rights reserved. 128Mb: x4, x8, x16 SDRAM Functional Block Diagrams Figure 5: 16 Meg x 8 SDRAM CKE CLK COMMAND DECODE CS# WE# CAS# RAS# CONTROL LOGIC BANK3 BANK2 BANK1 MODE REGISTER REFRESH 12 COUNTER 12 ROWADDRESS MUX 12 12 BANK0 ROWADDRESS LATCH & DECODER 4,096 BANK0 MEMORY ARRAY (4,096 x 1,024 x 8) 1 DQM SENSE AMPLIFIERS 8 4,096 I/O GATING DQM MASK LOGIC READ DATA LATCH WRITE DRIVERS 2 A0-A11, BA0, BA1 14 ADDRESS REGISTER 2 BANK CONTROL LOGIC DATA OUTPUT REGISTER 8 8 1,024 (x8) 1 DQ0- DQ7 DATA INPUT REGISTER COLUMN DECODER 10 PDF: 09005aef8091e66d/Source: 09005aef8091e625 128MSDRAM_2.fm - Rev. N 1/09 EN COLUMNADDRESS COUNTER/ LATCH 10 11 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)1999 Micron Technology, Inc. All rights reserved. 128Mb: x4, x8, x16 SDRAM Functional Block Diagrams Figure 6: 8 Meg x 16 SDRAM CKE CLK COMMAND DECODE CS# WE# CAS# RAS# CONTROL LOGIC BANK3 BANK2 BANK1 MODE REGISTER REFRESH 12 COUNTER 12 ROWADDRESS MUX 12 12 BANK0 ROWADDRESS 4,096 LATCH & DECODER BANK0 MEMORY ARRAY (4,096 x 512 x 16) 2 DQML, DQMH SENSE AMPLIFIERS 16 4,096 I/O GATING DQM MASK LOGIC READ DATA LATCH WRITE DRIVERS 2 A0-A11, BA0, BA1 14 ADDRESS REGISTER 2 BANK CONTROL LOGIC DATA OUTPUT REGISTER 16 16 512 (x16) 2 DQ0- DQ15 DATA INPUT REGISTER COLUMN DECODER 9 PDF: 09005aef8091e66d/Source: 09005aef8091e625 128MSDRAM_2.fm - Rev. N 1/09 EN COLUMNADDRESS COUNTER/ LATCH 9 12 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)1999 Micron Technology, Inc. All rights reserved. 128Mb: x4, x8, x16 SDRAM Pin/Ball Descriptions Pin/Ball Descriptions Table 4: Pin/Ball Descriptions 54-Pin TSOP 54-Ball VFBGA 60-Ball FBGA Symbol Type Description 38 F2 K2 CLK Input 37 F3 L2 CKE Input 19 G9 L8 CS# Input 16, 17, 18 F9, F7, F8 J7, J8, K7 Input 39 - J2 15, 39 E8, F1 - WE#, CAS#, RAS# x4, x8: DQM x16: DQML, DQMH Clock: CLK is driven by the system clock. All SDRAM input signals are sampled on the positive edge of CLK. CLK also increments the internal burst counter and controls the output registers. Clock enable: CKE activates (HIGH) and deactivates (LOW) the CLK signal. Deactivating the clock provides PRECHARGE power-down and SELF REFRESH operation (all banks idle), ACTIVE power-down (row active in any bank), or CLOCK SUSPEND operation (burst/access in progress). CKE is synchronous except after the device enters power-down and self refresh modes, where CKE becomes asynchronous until after exiting the same mode. The input buffers, including CLK, are disabled during power-down and self refresh modes, providing low standby power. CKE may be tied HIGH. Chip select: CS# enables (registered LOW) and disables (registered HIGH) the command decoder. All commands are masked when CS# is registered HIGH, but READ/WRITE bursts already in progress will continue and DQM operation will retain its DQ mask capability while CS# is HIGH. CS# provides for external bank selection on systems with multiple banks. CS# is considered part of the command code. Command inputs: WE#, CAS#, and RAS# (along with CS#) define the command being entered. 20, 21 G7, G8 M8, M7 BA0, BA1 Input 23-26, 29- 34, 22, 35 H7, H8, J8, J7, J3, J2, H3, H2, H1, G3, H9, G2 N7, P8, P7, R8, R1, P2, P1, N2, N1, M2, N8, M1 A0-A11 Input PDF: 09005aef8091e66d/Source: 09005aef8091e625 128MSDRAM_2.fm - Rev. N 1/09 EN Input 13 Input/Output mask: DQM is an input mask signal for write accesses and an output enable signal for read accesses. Input data is masked when DQM is sampled HIGH during a WRITE cycle. The output buffers are placed in a High-Z state (2-clock latency) when DQM is sampled HIGH during a READ cycle. On the x4 and x8, DQML (pin 15) is a NC and DQMH is DQM. On the x16, DQML corresponds to DQ0- DQ7, and DQMH corresponds to DQ8-DQ15. DQML and DQMH are considered same state when referenced as DQM. Bank address inputs: BA0 and BA1 define to which bank the ACTIVE, READ, WRITE, or PRECHARGE command is being applied. Address inputs: A0-A11 are sampled during the ACTIVE command (row-address A0-A11) and READ/WRITE command (column-address A0-A9, A11 [x4]; A0-A9 [x8]; A0-A8 [x16]; with A10 defining auto precharge) to select one location out of the memory array in the respective bank. A10 is sampled during a precharge command to determine whether all banks are to be precharged (A10 [HIGH]) or bank selected by BA0, BA1 (A10 [LOW]). The address inputs also provide the op-code during a LOAD MODE REGISTER (LMR) command. Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)1999 Micron Technology, Inc. All rights reserved. 128Mb: x4, x8, x16 SDRAM Pin/Ball Descriptions Table 4: 54-Pin TSOP 2, 4, 5, 7, 8, 10, 11, 13, 42, 44, 45, 47, 48, 50, 51, 53 2, 5, 8, 11, 44, 47, 50, 53 5, 11, 44, 50 Pin/Ball Descriptions (Continued) 54-Ball VFBGA 60-Ball FBGA A8, B9, B8, C9, C8, D9, D8, E9, E1, D2, D1, C2, C1, B2, B1, A2 - - DQ0- DQ15 A8, C7, D8, F7, F2, D1, C2, A1 C7, F7, F2, C2 B1, B8, D2, D7, E1, E8, G1, G2, G7, G8, H1, H8, J1, K1, K8, L7 L1 B7, C1, E7, F1 B2, C8, E2, F8 A7, R7 A2, H2, R2 DQ0-DQ7 x8: I/O Data input/output: Data bus for x8 (pins 2, 8, 47, and 53 are NCs for x4; balls A8, D8, D1, and A1 are NCs for x4). DQ0-DQ3 x4: I/O Data input/output: Data bus for x4. NC - - 40 E2 36 3, 9, 43, 49 G1 A7, B3, C7, D3 A3, B7, C3, D7 A9, E7, J9 A1, E3, J1 6, 12, 46, 52 1, 14, 27 28, 41, 54 PDF: 09005aef8091e66d/Source: 09005aef8091e625 128MSDRAM_2.fm - Rev. N 1/09 EN Symbol NC VDDQ VSSQ VDD VSS Type Description x16: I/O Data input/output: Data bus for x16 (pins 4, 7, 10, 13, 42, 45, 48, and 51 are NCs for x8; and 2, 4, 7, 8, 10, 13, 42, 45, 47, 48, 51, and 53 are NCs for x4). No connect: These pins should be left unconnected. - Address input (A12) for the 256Mb and 512Mb devices. Supply DQ power: Isolated DQ power on the die for improved noise immunity. Supply DQ ground: Isolated DQ ground on the die for improved noise immunity. Supply Power supply: +3.3 0.3V. Supply Ground. 14 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)1999 Micron Technology, Inc. All rights reserved. 128Mb: x4, x8, x16 SDRAM Functional Description Functional Description In general, the 128Mb SDRAMs (8 Meg x 4 x 4 banks, 4 Meg x 8 x 4 banks, and 2 Meg x 16 x 4 banks) are quad-bank DRAMs that operate at 3.3V and include a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Each of the x4's 33,554,432-bit banks is organized as 4,096 rows by 2,048 columns by 4 bits. Each of the x8's 33,554,432-bit banks is organized as 4,096 rows by 1,024 columns by 8 bits. Each of the x16's 33,554,432-bit banks is organized as 4,096 rows by 512 columns by 16 bits. Read and write accesses to the SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command, which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command are used to select the bank and row to be accessed (BA0 and BA1 select the bank, A0-A11 select the row). The address bits (x4: A0-A9, A11; x8: A0-A9; x16: A0-A8) registered coincident with the READ or WRITE command are used to select the starting column location for the burst access. Prior to normal operation, the SDRAM must be initialized. The following sections provide detailed information covering device initialization, register definition, command descriptions, and device operation. Initialization SDRAMs must be powered up and initialized in a predefined manner. Operational procedures other than those specified may result in undefined operation. After power is applied to VDD and VDDQ (simultaneously) and the clock is stable (stable clock is defined as a signal cycling within timing constraints specified for the clock pin), the SDRAM requires a 100s delay prior to issuing any command other than a COMMAND INHIBIT or NOP. Starting at some point during this 100s period and continuing at least through the end of this period, COMMAND INHIBIT or NOP commands must be applied. After the 100s delay has been satisfied with at least one COMMAND INHIBIT or NOP command having been applied, a PRECHARGE command should be applied. All banks must then be precharged, thereby placing the device in the all banks idle state. Once in the idle state, at least two AUTO REFRESH cycles must be performed. After the AUTO REFRESH cycles are complete, the SDRAM is ready for mode register programming. Because the mode register will power up in an unknown state, it must be loaded prior to applying any operational command. If desired, the two AUTO REFRESH commands can be issued after the LMR command. The recommended power-up sequence for SDRAMs: 1. Simultaneously apply power to VDD and VDDQ. 2. Assert and hold CKE at a LVTTL logic LOW since all inputs and outputs are LVTTLcompatible. 3. Provide stable CLOCK signal. Stable clock is defined as a signal cycling within timing constraints specified for the clock pin. 4. Wait at least 100s prior to issuing any command other than a COMMAND INHIBIT or NOP. 5. Starting at some point during this 100s period, bring CKE HIGH. Continuing at least through the end of this period, one or more COMMAND INHIBIT or NOP commands must be applied. 6. Perform a PRECHARGE ALL command. PDF: 09005aef8091e66d/Source: 09005aef8091e625 128MSDRAM_2.fm - Rev. N 1/09 EN 15 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)1999 Micron Technology, Inc. All rights reserved. 128Mb: x4, x8, x16 SDRAM Functional Description 7. Wait at least tRP time; during this time, NOPs or DESELECT commands must be given. All banks will complete their precharge, thereby placing the device in the all banks idle state. 8. Issue an AUTO REFRESH command. 9. Wait at least tRFC time, during which only NOPs or COMMAND INHIBIT commands are allowed. 10. Issue an AUTO REFRESH command. 11. Wait at least tRFC time, during which only NOPs or COMMAND INHIBIT commands are allowed. 12. The SDRAM is now ready for mode register programming. Because the mode register will power up in an unknown state, it should be loaded with desired bit values prior to applying any operational command. Using the LMR command, program the mode register. The mode register is programmed via the MODE REGISTER SET command with BA1 = 0, BA0 = 0 and retains the stored information until it is programmed again or the device loses power. Not programming the mode register upon initialization will result in default settings, which may not be desired. Outputs are guaranteed High-Z after the LMR command is issued. Outputs should be High-Z already before the LMR command is issued. 13. Wait at least tMRD time, during which only NOP or DESELECT commands are allowed. At this point, the DRAM is ready for any valid command. Note: If desired, more than two AUTO REFRESH commands can be issued in the sequence. After steps 9 and 10 are complete, repeat them until the desired number of AUTO REFRESH + tRFC loops is achieved. Register Definition Mode Register The mode register is used to define the specific mode of operation of the SDRAM. This definition includes the selection of a burst length (BL), a burst type, a CAS latency (CL), an operating mode, and a write burst mode, as shown in Figure 7 on page 18. The mode register is programmed via the LMR command and will retain the stored information until it is programmed again or the device loses power. Mode register bits M0-M2 specify the BL, M3 specifies the type of burst (sequential or interleaved), M4-M6 specify the CL, M7 and M8 specify the operating mode, M9 specifies the write burst mode, and M10 and M11 are reserved for future use. The mode register must be loaded when all banks are idle, and the controller must wait the specified time before initiating the subsequent operation. Violating either of these requirements will result in unspecified operation. Burst Length (BL) Read and write accesses to the SDRAM are burst oriented, with the BL being programmable, as shown in Figure 7 on page 18. BL determines the maximum number of column locations that can be accessed for a given READ or WRITE command. BL of 1, 2, 4, or 8 locations are available for both the sequential and the interleaved burst types, and a full-page burst is available for the sequential mode. The full-page burst is used in conjunction with the BURST TERMINATE command to generate arbitrary BLs. Reserved states cannot be used because unknown operation or incompatibility with future versions may result. PDF: 09005aef8091e66d/Source: 09005aef8091e625 128MSDRAM_2.fm - Rev. N 1/09 EN 16 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)1999 Micron Technology, Inc. All rights reserved. 128Mb: x4, x8, x16 SDRAM Functional Description When a READ or WRITE command is issued, a block of columns equal to the BL is effectively selected. All accesses for that burst take place within this block, meaning that the burst will wrap within the block if a boundary is reached. The block is uniquely selected by A1-A9, A11 (x4), A1-A9 (x8), or A1-A8 (x16) when BL = 2; by A2-A9, A11 (x4), A2-A9 (x8), or A2-A8 (x16) when BL = 4; and by A3-A9, A11 (x4), A3-A9 (x8), or A3-A8 (x16) when BL = 8. The remaining (least significant) address bit(s) is (are) used to select the starting location within the block. Full-page bursts wrap within the page if the boundary is reached. Burst Type Accesses within a given burst may be programmed either to be sequential or interleaved; this is referred to as the burst type and is selected via bit M3. The ordering of accesses within a burst is determined by the BL, the burst type, and the starting column address, as shown in Table 5 on page 19. PDF: 09005aef8091e66d/Source: 09005aef8091e625 128MSDRAM_2.fm - Rev. N 1/09 EN 17 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)1999 Micron Technology, Inc. All rights reserved. 128Mb: x4, x8, x16 SDRAM Functional Description Figure 7: Mode Register Definition A11 A10 11 9 10 Reserved A8 A9 8 A6 A7 7 WB Op Mode 6 A5 A4 5 A3 4 CAS Latency 3 BT Program A11, A10 = "0, 0" to ensure compatibility with future devices. A9 Write Burst Mode 0 Programmed Burst Length 1 Single Location Access A1 A2 1 2 Address Bus A0 0 Mode Register (Ax) Burst Length Burst Length A2 A1 A0 A3 = 0 A3 = 1 0 0 0 1 1 0 0 1 2 2 0 1 0 4 4 0 1 1 8 8 1 0 0 Reserved Reserved A8 A7 A6-A0 Operating Mode 1 0 1 Reserved Reserved 0 0 Defined Standard Operation 1 1 0 Reserved Reserved - - - All other states reserved 1 1 1 Full Page Reserved Burst Type 0 Sequential 1 Interleaved CAS Latency A6 A5 A4 PDF: 09005aef8091e66d/Source: 09005aef8091e625 128MSDRAM_2.fm - Rev. N 1/09 EN A3 0 0 0 Reserved 0 0 1 Reserved 0 1 0 2 0 1 1 3 1 0 0 Reserved 1 0 1 Reserved 1 1 0 Reserved 1 1 1 Reserved 18 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)1999 Micron Technology, Inc. All rights reserved. 128Mb: x4, x8, x16 SDRAM Functional Description Table 5: Burst Definition Burst Length Starting Column Address 2 4 8 Full page (y) Notes: A2 0 0 0 0 1 1 1 1 A1 0 0 1 1 A1 0 0 1 1 0 0 1 1 A0 0 1 A0 0 1 0 1 A0 0 1 0 1 0 1 0 1 n = A0-A11/9/8 (location 0-y) Order of Accesses Within a Burst Type = Sequential Type = Interleaved 0-1 1-0 0-1 1-0 0-1-2-3 1-2-3-0 2-3-0-1 3-0-1-2 0-1-2-3 1-0-3-2 2-3-0-1 3-2-1-0 0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-0 2-3-4-5-6-7-0-1 3-4-5-6-7-0-1-2 4-5-6-7-0-1-2-3 5-6-7-0-1-2-3-4 6-7-0-1-2-3-4-5 7-0-1-2-3-4-5-6 Cn, Cn + 1, Cn + 2, Cn + 3, Cn + 4..., ...Cn - 1, Cn 0-1-2-3-4-5-6-7 1-0-3-2-5-4-7-6 2-3-0-1-6-7-4-5 3-2-1-0-7-6-5-4 4-5-6-7-0-1-2-3 5-4-7-6-1-0-3-2 6-7-4-5-2-3-0-1 7-6-5-4-3-2-1-0 Not supported 1. For full-page accesses: y = 2,048 (x4), y = 1,024 (x8), and y = 512 (x16). 2. For BL = 2, A1-A9, A11 (x4), A1-A9 (x8), or A1-A8 (x16) select the block-of-two burst; A0 selects the starting column within the block. 3. For BL = 4, A2-A9, A11 (x4), A2-A9 (x8), or A2-A8 (x16) select the block-of-four burst; A0- A1 select the starting column within the block. 4. For BL = 8, A3-A9, A11 (x4), A3-A9 (x8), or A3-A8 (x16) select the block-of-eight burst; A0- A2 select the starting column within the block. 5. For a full-page burst, the full row is selected and A0-A9, A11 (x4), A0-A9 (x8), or A0-A8 (x16) select the starting column. 6. Whenever a boundary of the block is reached within a given sequence above, the following access wraps within the block. CAS Latency The CL is the delay, in clock cycles, between the registration of a READ command and the availability of the first piece of output data. The latency can be set to 2 or 3 clocks. If a READ command is registered at clock edge n and the latency is m clocks, the data will be available by clock edge n + m. The DQ will start driving as a result of the clock edge 1 cycle earlier (n + m - 1), and provided that the relevant access times are met, the data will be valid by clock edge n + m. For example, assuming that the clock cycle time is such that all relevant access times are met, if a read command is registered at T0 and the latency is programmed to 2 clocks, the DQ will start driving after T1 and the data will be valid by T2, as shown in Figure 8 on page 20. Table 6 on page 20 indicates the operating frequencies at which each CL setting can be used. Reserved states should not be used as unknown operation or incompatibility with future versions may result. PDF: 09005aef8091e66d/Source: 09005aef8091e625 128MSDRAM_2.fm - Rev. N 1/09 EN 19 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)1999 Micron Technology, Inc. All rights reserved. 128Mb: x4, x8, x16 SDRAM Functional Description Table 6: CAS Latency Allowable Operating Frequency (MHz) Figure 8: Speed CL = 2 CL = 3 -6A -7E -75 - 133 100 167 143 133 CAS Latency T0 T1 T2 T3 READ NOP NOP CLK COMMAND tLZ tOH DOUT DQ tAC CL = 2 T0 T1 T2 T3 T4 READ NOP NOP NOP CLK COMMAND tLZ tOH DOUT DQ tAC CL = 3 DON'T CARE UNDEFINED Operating Mode The normal operating mode is selected by setting M7 and M8 to 0; the other combinations of values for M7 and M8 are reserved for future use and/or test modes. The programmed BL applies to both read and write bursts. Test modes and reserved states should not be used because unknown operation or incompatibility with future versions may result. Write Burst Mode When M9 = 0, the BL programmed via M0-M2 applies both to read and write bursts; when M9 = 1, the programmed BL applies to read bursts, but write accesses are singlelocation (nonburst) accesses. PDF: 09005aef8091e66d/Source: 09005aef8091e625 128MSDRAM_2.fm - Rev. N 1/09 EN 20 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)1999 Micron Technology, Inc. All rights reserved. 128Mb: x4, x8, x16 SDRAM Commands Commands Table 7 provides a quick reference of available commands. This is followed by a written description of each command. Three additional truth tables appear following "Operations" on page 24; these tables provide current state/next state information. Table 7: Truth Table 1 - Commands and DQM Operation CKE is HIGH for all commands shown except SELF REFRESH Name (Function) CS# RAS# CAS# WE# DQM ADDR DQ Notes COMMAND INHIBIT (NOP) NO OPERATION (NOP) ACTIVE (Select bank and activate row) H L L X H L X H H X H H X X X X X X 1 READ (Select bank and column, and start READ burst) WRITE (Select bank and column, and start WRITE burst) BURST TERMINATE PRECHARGE (Deactivate row in bank or banks) AUTO refresh or self refresh (Enter self refresh mode) LMR L H L H L/H8 X 2 L H L L L/H8 Valid 2 L L L H L L H H L L L H X X X X X Bank/ row Bank/ col Bank/ col X Code X Active X X 3 4, 5 L L L L X X 6 - - - - - - - - L H Active High-Z 7 7 Write enable/output enable Write inhibit/output High-Z Notes: Opcode - - 1. A0-A11 provide row address, and BA0, BA1 determine which bank is made active. 2. A0-A9; A11 (x4); A0-A9 (x8); or A0-A8 (x16) provide column address; A10 HIGH enables the auto precharge feature (nonpersistent), while A10 LOW disables the auto precharge feature; BA0, BA1 determine which bank is being read from or written to. 3. A10 LOW: BA0, BA1 determine the bank being precharged. A10 HIGH: All banks precharged and BA0, BA1 are "Don't Care." 4. This command is AUTO REFRESH if CKE is HIGH and SELF REFRESH if CKE is LOW. 5. Internal refresh counter controls row addressing; all inputs and I/Os are "Don't Care" except for CKE. 6. A0-A11 define the op-code written to the mode register. 7. Activates or deactivates the DQ during WRITEs (0-clock delay) and READs (2-clock delay). COMMAND INHIBIT The COMMAND INHIBIT function prevents new commands from being executed by the SDRAM, regardless of whether the CLK signal is enabled. The SDRAM is effectively deselected. Operations already in progress are not affected. NO OPERATION (NOP) The NO OPERATION (NOP) command is used to perform a NOP to an SDRAM, which is selected (CS# is LOW). This prevents unwanted commands from being registered during idle or wait states. Operations already in progress are not affected. PDF: 09005aef8091e66d/Source: 09005aef8091e625 128MSDRAM_2.fm - Rev. N 1/09 EN 21 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)1999 Micron Technology, Inc. All rights reserved. 128Mb: x4, x8, x16 SDRAM Commands LOAD MODE REGISTER (LMR) The mode register is loaded via inputs A0-A11 (A12 should be driven LOW). See "Mode Register" heading in the "Register Definition" section on page 16. The LMR command can only be issued when all banks are idle, and a subsequent executable command cannot be issued until tMRD is met. ACTIVE The ACTIVE command is used to open (or activate) a row in a particular bank for a subsequent access. The value on the BA0, BA1 inputs selects the bank, and the address provided on inputs A0-A11 selects the row. This row remains active (or open) for accesses until a PRECHARGE command is issued to that bank. A PRECHARGE command must be issued before opening a different row in the same bank. READ The READ command is used to initiate a burst read access to an active row. The value on the BA0, BA1 inputs selects the bank, and the address provided on inputs A0-A9, A11 (x4), A0-A9 (x8), or A0-A8 (x16) selects the starting column location. The value on input A10 determines whether auto precharge is used. If auto precharge is selected, the row being accessed will be precharged at the end of the read burst; if auto precharge is not selected, the row will remain open for subsequent accesses. Read data appears on the DQs subject to the logic level on the DQM inputs 2 clocks earlier. If a given DQM signal was registered HIGH, the corresponding DQ will be High-Z 2 clocks later; if the DQM signal was registered LOW, the DQ will provide valid data. WRITE The WRITE command is used to initiate a burst write access to an active row. The value on the BA0, BA1 inputs selects the bank, and the address provided on inputs A0-A9, A11 (x4), A0-A9 (x8), or A0-A8 (x16) selects the starting column location. The value on input A10 determines whether auto precharge is used. If auto precharge is selected, the row being accessed will be precharged at the end of the write burst; if auto precharge is not selected, the row will remain open for subsequent accesses. Input data appearing on the DQ is written to the memory array subject to the DQM input logic level appearing coincident with the data. If a given DQM signal is registered LOW, the corresponding data will be written to memory; if the DQM signal is registered HIGH, the corresponding data inputs will be ignored, and a write will not be executed to that byte/column location. PRECHARGE The PRECHARGE command is used to deactivate the open row in a particular bank or the open row in all banks. The bank(s) will be available for a subsequent row access a specified time (tRP) after the PRECHARGE command is issued. Input A10 determines whether one or all banks are to be precharged, and in the case where only one bank is to be precharged, inputs BA0, BA1 select the bank. Otherwise BA0, BA1 are treated as "Don't Care." After a bank has been precharged, it is in the idle state and must be activated prior to any READ or WRITE commands being issued to that bank. Auto Precharge Auto precharge is a feature that performs the same individual-bank precharge function described above, without requiring an explicit command. This is accomplished by using A10 to enable auto precharge in conjunction with a specific READ or WRITE command. PDF: 09005aef8091e66d/Source: 09005aef8091e625 128MSDRAM_2.fm - Rev. N 1/09 EN 22 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)1999 Micron Technology, Inc. All rights reserved. 128Mb: x4, x8, x16 SDRAM Commands A precharge of the bank/row that is addressed with the READ or WRITE command is automatically performed upon completion of the READ or WRITE burst, except in the full-page burst mode, where auto precharge does not apply. Auto precharge is nonpersistent in that either it is enabled or disabled for each individual READ or WRITE command. Auto precharge ensures that the precharge is initiated at the earliest valid stage within a burst. The user must not issue another command to the same bank until the precharge time (tRP) is completed. This is determined as if an explicit PRECHARGE command was issued at the earliest possible time, as described for each burst type in the "Operations" section on page 24. BURST TERMINATE The BURST TERMINATE command is used either to truncate fixed-length or full-page bursts. The most recently registered READ or WRITE command prior to the BURST TERMINATE command will be truncated, as shown in the "Operations" section on page 24. The BURST TERMINATE command does not precharge the row; the row will remain open until a PRECHARGE command is issued. AUTO REFRESH AUTO REFRESH is used during normal operation of the SDRAM and is analogous to CAS#-BEFORE-RAS# (CBR) refresh in older DRAMs. This command is nonpersistent, so it must be issued each time a refresh is required. All active banks must be PRECHARGED prior to issuing an AUTO REFRESH command. The AUTO REFRESH command should not be issued until the minimum tRP has been met after the PRECHARGE command as shown in the operation section. The addressing is generated by the internal refresh controller. This makes the address bits "Don't Care" during an AUTO REFRESH command. Regardless of device width, the 128Mb SDRAM requires 4,096 AUTO REFRESH cycles every 64ms (commercial and industrial) or 16ms (automotive). Providing a distributed AUTO REFRESH command every 15.625s (commercial and industrial) or 3.906s (automotive) will meet the refresh requirement and ensure that each row is refreshed. Alternatively, 4,096 AUTO REFRESH commands can be issued in a burst at the minimum cycle rate (tRFC), once every 64ms (commercial and industrial) or 16ms (automotive). SELF REFRESH The SELF REFRESH command can be used to retain data in the SDRAM, even if the rest of the system is powered down. When in the self refresh mode, the SDRAM retains data without external clocking. The SELF REFRESH command is initiated like an AUTO REFRESH command except CKE is disabled (LOW). After the SELF REFRESH command is registered, all the inputs to the SDRAM become "Don't Care" with the exception of CKE, which must remain LOW. After self refresh mode is engaged, the SDRAM provides its own internal clocking, causing it to perform its own auto refresh cycles. The SDRAM must remain in self refresh mode for a minimum period equal to tRAS and may remain in self refresh mode for an indefinite period beyond that. PDF: 09005aef8091e66d/Source: 09005aef8091e625 128MSDRAM_2.fm - Rev. N 1/09 EN 23 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)1999 Micron Technology, Inc. All rights reserved. 128Mb: x4, x8, x16 SDRAM Operations The procedure for exiting self refresh requires a sequence of commands. First, CLK must be stable (stable clock is defined as a signal cycling within timing constraints specified for the clock pin) prior to CKE going back HIGH. After CKE is HIGH, the SDRAM must have NOP commands issued (a minimum of 2 clocks) for tXSR because this amount of time is required for the completion of any internal refresh in progress. Upon exiting the self refresh mode, AUTO REFRESH commands must be issued every 15.625s or less because both SELF REFRESH and AUTO REFRESH utilize the row refresh counter. Self refresh is not supported on automotive temperature (AT) devices. Operations Bank/row Activation Before any READ or WRITE commands can be issued to a bank within the SDRAM, a row in that bank must be "opened." This is accomplished via the ACTIVE command, which selects both the bank and the row to be activated (see Figure 9 on page 25). After opening a row (issuing an ACTIVE command), a READ or WRITE command may be issued to that row, subject to the tRCD specification. tRCD (MIN) should be divided by the clock period and rounded up to the next whole number to determine the earliest clock edge after the ACTIVE command on which a READ or WRITE command can be entered. For example, a tRCD specification of 20ns with a 125 MHz clock (8ns period) results in 2.5 clocks, rounded to 3. This is reflected in Figure 10 on page 25, which covers any case where 2 < tRCD (MIN)/tCK 3. (The same procedure is used to convert other specification limits from time units to clock cycles.) A subsequent ACTIVE command to a different row in the same bank can only be issued after the previous active row has been "closed" (precharged). The minimum time interval between successive ACTIVE commands to the same bank is defined by tRC. A subsequent ACTIVE command to another bank can be issued while the first bank is being accessed, which results in a reduction of total row-access overhead. The minimum time interval between successive ACTIVE commands to different banks is defined by t RRD. PDF: 09005aef8091e66d/Source: 09005aef8091e625 128MSDRAM_2.fm - Rev. N 1/09 EN 24 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)1999 Micron Technology, Inc. All rights reserved. 128Mb: x4, x8, x16 SDRAM Operations Figure 9: Activating a Specific Row in a Specific Bank CLK CKE HIGH CS# RAS# CAS# WE# ROW ADDRESS A0-A10, A11 BANK ADDRESS BA0, BA1 DON'T CARE Figure 10: Example: Meeting tRCD (MIN) When 2 < tRCD (MIN)/tCK 3 T0 T1 T2 NOP NOP T3 T4 CLK COMMAND ACTIVE READ or WRITE tRCD DON'T CARE Reads READ bursts are initiated with a READ command, as shown in Figure 11 on page 26. The starting column and bank addresses are provided with the READ command, and auto precharge either is enabled or disabled for that burst access. If auto precharge is enabled, the row being accessed is precharged at the completion of the burst. For the generic READ commands used in the following illustrations, auto precharge is disabled. During READ bursts, the valid data-out element from the starting column address will be available following the CL after the READ command. Each subsequent data-out element will be valid by the next positive clock edge. Figure 12 on page 26 shows general timing for each possible CL setting. Upon completion of a burst, assuming no other commands have been initiated, the DQ will go High-Z. A full-page burst will continue until terminated. (At the end of the page, it will wrap to column 0 and continue.) PDF: 09005aef8091e66d/Source: 09005aef8091e625 128MSDRAM_2.fm - Rev. N 1/09 EN 25 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)1999 Micron Technology, Inc. All rights reserved. 128Mb: x4, x8, x16 SDRAM Operations Figure 11: READ Command CLK CKE HIGH CS# RAS# CAS# WE# A0-A9, A11: x4 A0-A9: x8 A0-A8: x16 COLUMN ADDRESS A11: x8 A9, A11: x16 ENABLE AUTO PRECHARGE A10 DISABLE AUTO PRECHARGE BANK ADDRESS BA0, BA1 Figure 12: CAS Latency T0 T1 T2 T3 READ NOP NOP CLK COMMAND tLZ tOH DOUT DQ tAC CL = 2 T0 T1 T2 T3 T4 READ NOP NOP NOP CLK COMMAND tLZ tOH DOUT DQ tAC CL = 3 DON'T CARE PDF: 09005aef8091e66d/Source: 09005aef8091e625 128MSDRAM_2.fm - Rev. N 1/09 EN 26 UNDEFINED Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)1999 Micron Technology, Inc. All rights reserved. 128Mb: x4, x8, x16 SDRAM Operations Data from any READ burst may be truncated with a subsequent READ command, and data from a fixed-length READ burst may be immediately followed by data from a READ command. In either case, a continuous flow of data can be maintained. The first data element from the new burst either follows the last element of a completed burst or the last desired data element of a longer burst that is being truncated. The new READ command should be issued x cycles before the clock edge at which the last desired data element is valid, where x = CL - 1. This is shown in Figure 13 for L = 2 and CL = 3; data element n + 3 is either the last of a burst of four or the last desired of a longer burst. The 128Mb SDRAM uses a pipelined architecture and, therefore, does not require the 2n rule associated with a prefetch architecture. A READ command can be initiated on any clock cycle following a previous READ command. Full-speed random read accesses can be performed to the same bank, as shown in Figure 14 on page 28, or each subsequent READ may be performed to a different bank. Figure 13: Consecutive READ Bursts T0 T1 T2 T3 T4 T5 T6 CLK COMMAND READ ADDRESS BANK, COL n NOP NOP NOP NOP READ NOP X = 1 cycle BANK, COL b DOUT n+2 DOUT n+1 DOUT n DQ DOUT n+3 DOUT b CL = 2 T0 T1 T2 T3 T4 T5 T6 T7 CLK COMMAND READ ADDRESS BANK, COL n NOP NOP NOP NOP READ NOP NOP X = 2 cycles BANK, COL b DOUT n DQ DOUT n+1 DOUT n+2 DOUT n+3 DOUT b CL = 3 TRANSITIONING DATA Notes: PDF: 09005aef8091e66d/Source: 09005aef8091e625 128MSDRAM_2.fm - Rev. N 1/09 EN DON'T CARE 1. Each READ command may be to any bank. DQM is LOW. 27 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)1999 Micron Technology, Inc. All rights reserved. 128Mb: x4, x8, x16 SDRAM Operations Figure 14: Random READ Accesses T0 T1 T2 T3 T4 T5 CLK COMMAND READ READ READ READ ADDRESS BANK, COL n BANK, COL a BANK, COL x BANK, COL m DOUT n DQ NOP NOP DOUT x DOUT a DOUT m CL = 2 T0 T1 T2 T3 T4 T5 T6 CLK COMMAND READ READ READ READ ADDRESS BANK, COL n BANK, COL a BANK, COL x BANK, COL m DOUT n DQ NOP DOUT a NOP DOUT x NOP DOUT m CL = 3 TRANSITIONING DATA Notes: DON'T CARE 1. Each READ command may be to any bank. DQM is LOW. Data from any READ burst may be truncated with a subsequent WRITE command, and data from a fixed-length READ burst may be immediately followed by data from a WRITE command (subject to bus turnaround limitations). The WRITE burst may be initiated on the clock edge immediately following the last (or last desired) data element from the READ burst, provided that I/O contention can be avoided. In a given system design, there may be a possibility that the device driving the input data will go Low-Z before the SDRAM DQ go High-Z. In this case, at least a single-cycle delay should occur between the last read data and the WRITE command. The DQM input is used to avoid I/O contention, as shown in Figure 15 on page 29 and Figure 16 on page 29. The DQM signal must be asserted (HIGH) at least 2 clocks prior to the WRITE command (DQM latency is 2 clocks for output buffers) to suppress data-out from the READ. After the WRITE command is registered, the DQ will go High-Z (or remain High-Z), regardless of the state of the DQM signal, provided the DQM was active on the clock just prior to the WRITE command that truncated the READ command. If not, the second WRITE will be an invalid WRITE. For example, if DQM was LOW during T4 in Figure 16, then the WRITEs at T5 and T7 would be valid, while the WRITE at T6 would be invalid. PDF: 09005aef8091e66d/Source: 09005aef8091e625 128MSDRAM_2.fm - Rev. N 1/09 EN 28 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)1999 Micron Technology, Inc. All rights reserved. 128Mb: x4, x8, x16 SDRAM Operations The DQM signal must be de-asserted prior to the WRITE command (DQM latency is zero clocks for input buffers) to ensure that the written data is not masked. Figure 15 shows the case where the clock frequency allows for bus contention to be avoided without adding a NOP cycle, and Figure 16 shows the case where the additional NOP is needed. Figure 15: READ-to-WRITE T0 T1 T2 T3 T4 CLK DQM COMMAND READ ADDRESS BANK, COL n NOP NOP NOP WRITE BANK, COL b tCK tHZ DOUT n DQ DIN b tDS TRANSITIONING DATA Notes: Figure 16: DON'T CARE 1. CL = 3 is used for illustration. The READ command may be to any bank, and the WRITE command may be to any bank. If a burst of 1 is used, then DQM is not required. READ-to-WRITE with Extra Clock Cycle T0 T1 T2 T3 T4 T5 CLK DQM COMMAND READ ADDRESS BANK, COL n NOP NOP NOP NOP WRITE BANK, COL b tHZ DOUT n DQ DIN b tDS TRANSITIONING DATA Notes: DON'T CARE 1. CL = 3 is used for illustration. The READ command may be to any bank, and the WRITE command may be to any bank. A fixed-length READ burst may be followed by, or truncated with, a PRECHARGE command to the same bank (provided that auto precharge was not activated), and a fullpage burst may be truncated with a PRECHARGE command to the same bank. The PRECHARGE command should be issued x cycles before the clock edge at which the last PDF: 09005aef8091e66d/Source: 09005aef8091e625 128MSDRAM_2.fm - Rev. N 1/09 EN 29 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)1999 Micron Technology, Inc. All rights reserved. 128Mb: x4, x8, x16 SDRAM Operations desired data element is valid, where x = CL - 1. This is shown in Figure 17 for each possible CL; data element n + 3 is either the last of a burst of four or the last desired of a longer burst. Following the PRECHARGE command, a subsequent command to the same bank cannot be issued until tRP is met. Note that part of the row precharge time is hidden during the access of the last data element(s). In the case of a fixed-length burst being executed to completion, a PRECHARGE command issued at the optimum time (as described above) provides the same operation that would result from the same fixed-length burst with auto precharge. The disadvantage of the PRECHARGE command is that it requires that the command and address buses be available at the appropriate time to issue the command; the advantage of the PRECHARGE command is that it can be used to truncate fixed-length or full-page bursts. Full-page READ bursts can be truncated with the BURST TERMINATE command, and fixed-length READ bursts may be truncated with a BURST TERMINATE command, provided that auto precharge was not activated. The BURST TERMINATE command should be issued x cycles before the clock edge at which the last desired data element is valid, where x = CL - 1. This is shown in Figure 18 on page 31 for each possible CL; data element n + 3 is the last desired data element of a longer burst. Figure 17: READ-to-PRECHARGE T0 T1 T2 T3 T4 T5 T6 T7 CLK t RP COMMAND READ NOP NOP NOP PRECHARGE NOP NOP ACTIVE X = 1 cycle ADDRESS BANK (a or all) BANK a, COL n DOUT n+2 DOUT n+1 DOUT n DQ BANK a, ROW DOUT n+3 CL = 2 T0 T1 T2 T3 T4 T5 T6 T7 CLK t RP COMMAND READ ADDRESS BANK a, COL n NOP NOP NOP PRECHARGE NOP NOP ACTIVE X = 2 cycles BANK (a or all) DOUT n DQ DOUT n+1 BANK a, ROW DOUT n+2 DOUT n+3 CL = 3 TRANSITIONING DATA Notes: PDF: 09005aef8091e66d/Source: 09005aef8091e625 128MSDRAM_2.fm - Rev. N 1/09 EN DON'T CARE 1. DQM is LOW. 30 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)1999 Micron Technology, Inc. All rights reserved. 128Mb: x4, x8, x16 SDRAM Operations Figure 18: Terminating a READ Burst T0 T1 T2 T3 T4 T5 T6 CLK COMMAND READ ADDRESS BANK, COL n NOP NOP NOP BURST TERMINATE NOP NOP X = 1 cycle DOUT n+ 2 DOUT n+ 1 DOUT n DQ DOUT n+ 3 CL = 2 T0 T1 T2 T3 T4 T5 T6 T7 CLK COMMAND READ ADDRESS BANK, COL n NOP NOP NOP BURST TERMINATE NOP NOP NOP X = 2 cycles DOUT n DQ DOUT n+1 DOUT n+2 DOUT n+3 CL = 3 TRANSITIONING DATA Notes: DON'T CARE 1. DQM is LOW. WRITEs WRITE bursts are initiated with a WRITE command, as shown in Figure 19 on page 32. The starting column and bank addresses are provided with the WRITE command, and auto precharge either is enabled or disabled for that access. If auto precharge is enabled, the row being accessed is precharged at the completion of the burst. For the generic WRITE commands used in the following illustrations, auto precharge is disabled. During WRITE bursts, the first valid data-in element will be registered coincident with the WRITE command. Subsequent data elements will be registered on each successive positive clock edge. Upon completion of a fixed-length burst, assuming no other commands have been initiated, the DQ will remain High-Z and any additional input data will be ignored (see Figure 20 on page 32). A full-page burst will continue until terminated. (At the end of the page, it will wrap to column 0 and continue.) PDF: 09005aef8091e66d/Source: 09005aef8091e625 128MSDRAM_2.fm - Rev. N 1/09 EN 31 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)1999 Micron Technology, Inc. All rights reserved. 128Mb: x4, x8, x16 SDRAM Operations Figure 19: WRITE Command CLK CKE HIGH CS# RAS# CAS# WE# A0-A9, A11: x4 A0-A9: x8 A0-A8: x16 COLUMN ADDRESS A11: x8 A9, A11: x16 ENABLE AUTO PRECHARGE A10 DISABLE AUTO PRECHARGE BANK ADDRESS BA0, BA1 DON'T CARE Figure 20: WRITE Burst T0 T1 T2 T3 COMMAND WRITE NOP NOP NOP ADDRESS BANK, COL n CLK DQ DIN n DIN n+1 TRANSITIONING DATA Notes: DON'T CARE 1. BL = 2. DQM is LOW. Data for any WRITE burst may be truncated with a subsequent WRITE command, and data for a fixed-length WRITE burst may be immediately followed by data for a WRITE command. The new WRITE command can be issued on any clock following the previous WRITE command, and the data provided coincident with the new command applies to the new command. An example is shown in Figure 21 on page 33. Data n + 1 is either the last of a burst of two or the last desired element of a longer burst. The 128Mb SDRAM uses a pipelined architecture and, therefore, does not require the 2n rule associated with PDF: 09005aef8091e66d/Source: 09005aef8091e625 128MSDRAM_2.fm - Rev. N 1/09 EN 32 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)1999 Micron Technology, Inc. All rights reserved. 128Mb: x4, x8, x16 SDRAM Operations a prefetch architecture. A WRITE command can be initiated on any clock cycle following a previous WRITE command. Full-speed random write accesses within a page can be performed to the same bank, as shown in Figure 22 on page 33, or each subsequent WRITE may be performed to a different bank. Data for any WRITE burst may be truncated with a subsequent READ command, and data for a fixed-length WRITE burst may be immediately followed by a READ command. After the READ command is registered, the data inputs will be ignored, and writes will not be executed. An example is shown in Figure 23 on page 34. Data n + 1 is either the last of a burst of two or the last desired element of a longer burst. Figure 21: WRITE-to-WRITE T0 T1 T2 COMMAND WRITE NOP WRITE ADDRESS BANK, COL n CLK DIN n DQ BANK, COL b DIN n+1 TRANSITIONING DATA Notes: Figure 22: DIN b DON'T CARE 1. DQM is LOW. Each WRITE command may be to any bank. Random WRITE Cycles T0 T1 T2 T3 COMMAND WRITE WRITE WRITE WRITE ADDRESS BANK, COL n BANK, COL a BANK, COL x BANK, COL m DIN n DIN a DIN x DIN m CLK DQ TRANSITIONING DATA PDF: 09005aef8091e66d/Source: 09005aef8091e625 128MSDRAM_2.fm - Rev. N 1/09 EN 33 DON'T CARE Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)1999 Micron Technology, Inc. All rights reserved. 128Mb: x4, x8, x16 SDRAM Operations Figure 23: WRITE-to-READ T0 T1 T2 T3 T4 T5 COMMAND WRITE NOP READ NOP NOP NOP ADDRESS BANK, COL n DOUT b DOUT b+1 CLK DQ DIN n BANK, COL b DIN n+1 TRANSITIONING DATA DON'T CARE Data for a fixed-length WRITE burst may be followed by, or truncated with, a PRECHARGE command to the same bank (provided that auto precharge was not activated), and a full-page WRITE burst may be truncated with a PRECHARGE command to the same bank. The PRECHARGE command should be issued tWR after the clock edge at which the last desired input data element is registered. The auto precharge mode requires a tWR of at least 1 clock plus time (see note 24 on page 52), regardless of frequency. In addition, when truncating a WRITE burst, the DQM signal must be used to mask input data for the clock edge prior to, and the clock edge coincident with, the PRECHARGE command. An example is shown in Figure 24 on page 35. Data n + 1 is either the last of a burst of two or the last desired of a longer burst. Following the PRECHARGE command, a subsequent command to the same bank cannot be issued until tRP is met. In the case of a fixed-length burst being executed to completion, a PRECHARGE command issued at the optimum time (as described above) provides the same operation that would result from the same fixed-length burst with auto precharge. The disadvantage of the PRECHARGE command is that it requires that the command and address buses be available at the appropriate time to issue the command; the advantage of the PRECHARGE command is that it can be used to truncate fixed-length or full-page bursts. Fixed-length or full-page WRITE bursts can be truncated with the BURST TERMINATE command. When truncating a WRITE burst, the input data applied coincident with the BURST TERMINATE command will be ignored. The last data written (provided that DQM is LOW at that time) will be the input data applied 1 clock previous to the BURST TERMINATE command. This is shown in Figure 25 on page 35, where data n is the last desired data element of a longer burst. PDF: 09005aef8091e66d/Source: 09005aef8091e625 128MSDRAM_2.fm - Rev. N 1/09 EN 34 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)1999 Micron Technology, Inc. All rights reserved. 128Mb: x4, x8, x16 SDRAM Operations Figure 24: WRITE-to-PRECHARGE T0 T1 T2 T3 T4 T5 T6 NOP ACTIVE NOP CLK tWR @ tCLK 15ns DQM t RP COMMAND ADDRESS WRITE NOP NOP PRECHARGE BANK (a or all) BANK a, COL n BANK a, ROW t WR DQ DIN n DIN n+1 tWR = tCLK < 15ns DQM t RP COMMAND ADDRESS WRITE NOP NOP PRECHARGE NOP BANK (a or all) BANK a, COL n NOP ACTIVE BANK a, ROW t WR DQ DIN n DIN n+1 TRANSITIONING DATA Notes: Figure 25: DON'T CARE 1. DQM could remain LOW in this example if the WRITE burst is a fixed length of two. Terminating a WRITE Burst T0 T1 T2 COMMAND WRITE BURST TERMINATE ADDRESS BANK, COL n (ADDRESS) DIN n (DATA) CLK DQ TRANSITIONING DATA Notes: PDF: 09005aef8091e66d/Source: 09005aef8091e625 128MSDRAM_2.fm - Rev. N 1/09 EN NEXT COMMAND DON'T CARE 1. DQMs are LOW. 35 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)1999 Micron Technology, Inc. All rights reserved. 128Mb: x4, x8, x16 SDRAM Operations PRECHARGE The PRECHARGE command (see Figure 26) is used to deactivate the open row in a particular bank or the open row in all banks. The bank(s) will be available for a subsequent row access some specified time (tRP) after the PRECHARGE command is issued. Input A10 determines whether one or all banks are to be precharged, and in the case where only one bank is to be precharged, inputs BA0, BA1 select the bank. When all banks are to be precharged, inputs BA0, BA1 are treated as "Don't Care." After a bank has been precharged, it is in the idle state and must be activated prior to any READ or WRITE commands being issued to that bank. Figure 26: PRECHARGE Command CLK CKE HIGH CS# RAS# CAS# WE# A0-A9 All Banks A10 Bank Selected BA0, BA1 BANK ADDRESS VALID ADDRESS DON'T CARE Power-Down Power-down occurs if CKE is registered LOW coincident with a NOP or COMMAND INHIBIT when no accesses are in progress. If power-down occurs when all banks are idle, this mode is referred to as precharge power-down; if power-down occurs when there is a row active in any bank, this mode is referred to as active power-down. Entering power-down deactivates the input and output buffers, excluding CKE, for maximum power savings while in standby. The device may not remain in the power-down state longer than the refresh period (tREF or tREFAT ) since no REFRESH operations are performed in this mode. The power-down state is exited by registering a NOP or COMMAND INHIBIT and CKE HIGH at the desired clock edge (meeting tCKS). See Figure 27 on page 37. PDF: 09005aef8091e66d/Source: 09005aef8091e625 128MSDRAM_2.fm - Rev. N 1/09 EN 36 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)1999 Micron Technology, Inc. All rights reserved. 128Mb: x4, x8, x16 SDRAM Operations Figure 27: Power-Down (( )) (( )) CLK tCKS CKE > tCKS (( )) COMMAND (( )) (( )) NOP NOP tRCD tRAS All banks idle Input buffers gated off Enter power-down mode ACTIVE Exit power-down mode tRC DON'T CARE Clock Suspend The clock suspend mode occurs when a column access/burst is in progress and CKE is registered low. In the clock suspend mode, the internal clock is deactivated, "freezing" the synchronous logic. For each positive clock edge on which CKE is sampled LOW, the next internal positive clock edge is suspended. Any command or data present on the input pins at the time of a suspended internal clock edge is ignored; any data present on the DQ pins remains driven; and burst counters are not incremented, as long as the clock is suspended. (See examples in Figure 28 and Figure 29 on page 38.) Clock suspend mode is exited by registering CKE HIGH; the internal clock and related operation will resume on the subsequent positive clock edge. Figure 28: Clock Suspend During WRITE Burst T0 T1 NOP WRITE T2 T3 T4 T5 CLK CKE INTERNAL CLOCK COMMAND ADDRESS DIN NOP NOP DIN n+1 DIN n+2 BANK, COL n DIN n TRANSITIONING DATA PDF: 09005aef8091e66d/Source: 09005aef8091e625 128MSDRAM_2.fm - Rev. N 1/09 EN 37 DON'T CARE Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)1999 Micron Technology, Inc. All rights reserved. 128Mb: x4, x8, x16 SDRAM Operations Figure 29: Clock Suspend During READ Burst T0 T1 T2 T3 T4 T5 T6 CLK CKE INTERNAL CLOCK COMMAND READ ADDRESS BANK, COL n NOP NOP DOUT n DQ NOP NOP DOUT n+1 TRANSITIONING DATA Notes: DOUT n+2 NOP DOUT n+3 DON'T CARE 1. For this example, CL = 2, BL = 4 or greater, and DQM is LOW. BURST READ/SINGLE WRITE The burst read/single write mode is entered by programming the write burst mode bit (M9) in the mode register to a logic 1. In this mode, all WRITE commands result in the access of a single column location (burst of one), regardless of the programmed BL. READ commands access columns according to the programmed BL and sequence, just as in the normal mode of operation (M9 = 0). Concurrent Auto Precharge An access command (READ or WRITE) to another bank while an access command with auto precharge enabled is executing is not allowed by SDRAMs, unless the SDRAM supports concurrent auto precharge. Micron SDRAMs support concurrent auto precharge. Four cases where concurrent auto precharge occurs are defined below. READ with Auto Precharge * Interrupted by a READ (with or without auto precharge): A READ to bank m will interrupt a READ on bank n, CL later. The precharge to bank n will begin when the READ to bank m is registered (Figure 30 on page 39). * Interrupted by a WRITE (with or without auto precharge): A WRITE to bank m will interrupt a READ on bank n when registered. DQM should be used 2 clocks prior to the WRITE command to prevent bus contention. The precharge to bank n will begin when the WRITE to bank m is registered (Figure 31 on page 39). PDF: 09005aef8091e66d/Source: 09005aef8091e625 128MSDRAM_2.fm - Rev. N 1/09 EN 38 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)1999 Micron Technology, Inc. All rights reserved. 128Mb: x4, x8, x16 SDRAM Operations Figure 30: READ With Auto Precharge Interrupted by a READ T0 T1 T2 T3 T4 T5 T6 T7 CLK COMMAND BANK n NOP READ - AP BANK n Page Active Internal States READ - AP BANK m NOP READ with Burst of 4 NOP NOP NOP Idle Interrupt Burst, Precharge t RP - BANK n Page Active BANK m tRP - BANKm Precharge READ with Burst of 4 BANK n, COL a ADDRESS NOP BANK m, COL d DOUT a+1 DOUT a DQ DOUT d DOUT d+1 CL = 3 (BANK n) CL = 3 (BANK m) TRANSITIONING DATA Notes: Figure 31: DON'T CARE 1. DQM is LOW. READ With Auto Precharge Interrupted by a WRITE T0 T1 T2 T3 T4 T5 T6 T7 CLK COMMAND BANK n READ - AP BANK n NOP NOP NOP Page READ with Burst of 4 Active Internal States WRITE - AP BANK m NOP NOP Interrupt Burst, Precharge Idle tRP - BANK n Page Active BANK m ADDRESS NOP Write-Back WRITE with Burst of 4 BANK n, COL a t WR - BANK m BANK m, COL d DQM1 DOUT a DQ CL = 3 (BANK n) Notes: DIN d DIN d+1 TRANSITIONING DATA DIN d+2 DIN d+3 DON'T CARE 1. DQM is HIGH at T2 to prevent DOUT a + 1 from contending with DIN at T4. WRITE with Auto Precharge * Interrupted by a READ (with or without auto precharge): A READ to bank m will interrupt a WRITE on bank n when registered, with the data-out appearing CL later. The precharge to bank n will begin after tWR is met, where tWR begins when the READ to bank m is registered. The last valid WRITE to bank n will be data-in registered one clock prior to the READ to bank m (Figure 32 on page 40). PDF: 09005aef8091e66d/Source: 09005aef8091e625 128MSDRAM_2.fm - Rev. N 1/09 EN 39 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)1999 Micron Technology, Inc. All rights reserved. 128Mb: x4, x8, x16 SDRAM Operations * Interrupted by a WRITE (with or without auto precharge): A WRITE to bank m will interrupt a WRITE on bank n when registered. The precharge to bank n will begin after tWR is met, where tWR begins when the WRITE to bank m is registered. The last valid data WRITE to bank n will be data registered one clock prior to a WRITE to bank m (Figure 33). Figure 32: WRITE With Auto Precharge Interrupted by a READ T0 T1 T2 T3 T4 T5 T6 T7 CLK COMMAND BANK n NOP WRITE - AP BANK n Page Active Internal States READ - AP BANK m NOP WRITE with Burst of 4 Page Active ADDRESS BANK n, COL a NOP NOP Precharge tRP - BANK n - BANK n tRP - BANK m READ with Burst of 4 BANK m, COL d DOUT d+ 1 DOUT d DIN a+1 DIN a DQ NOP Interrupt Burst, Write-Back tWR BANK m NOP CL = 3 (BANK m) TRANSITIONING DATA Notes: Figure 33: DON'T CARE 1. DQM is LOW. WRITE With Auto Precharge Interrupted by a WRITE T0 T1 T2 T3 T4 T5 T6 T7 CLK COMMAND BANK n Internal States NOP WRITE - AP BANK n Page Active NOP NOP WRITE with Burst of 4 WRITE - AP BANK m NOP NOP Interrupt Burst, Write-Back tWR - BANK n NOP Precharge tRP - BANK n tWR BANK m Page Active ADDRESS BANK n, COL a DQ DIN a BANK m, COL d DIN a+1 DIN a+2 DIN d DIN d+1 TRANSITIONING DATA Notes: PDF: 09005aef8091e66d/Source: 09005aef8091e625 128MSDRAM_2.fm - Rev. N 1/09 EN - BANK m Write-Back WRITE with Burst of 4 DIN d+2 DIN d+3 DON'T CARE 1. DQM is LOW. 40 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)1999 Micron Technology, Inc. All rights reserved. 128Mb: x4, x8, x16 SDRAM Operations Table 8: Truth Table 2 - CKE Notes: 1-4 CKEn - 1 CKEn Current State Commandn Actionn Notes L L L H L Maintain power-down Maintain self refresh Maintain clock suspend Exit power-down Exit self refresh Exit clock suspend Power-down entry Self refresh entry Clock suspend entry H H X X X COMMAND INHIBIT or NOP COMMAND INHIBIT or NOPX X COMMAND INHIBIT or NOP AUTO REFRESH WRITE or NOP See Table 9 on page 42 5 6 7 H Power-down Self refresh Clock suspend Power-down Self refresh Clock suspend All banks idle All banks idle Reading or writing Notes: PDF: 09005aef8091e66d/Source: 09005aef8091e625 128MSDRAM_2.fm - Rev. N 1/09 EN 1. CKEn is the logic state of CKE at clock edge n; CKEn - 1 was the state of CKE at the previous clock edge. 2. Current state is the state of the SDRAM immediately prior to clock edge n. 3. COMMANDn is the command registered at clock edge n, and ACTIONn is a result of COMMANDn. 4. All states and sequences not shown are illegal or reserved. 5. Exiting power-down at clock edge n will put the device in the all banks idle state in time for clock edge n + 1 (provided that tCKS is met). 6. Exiting self refresh at clock edge n will put the device in the all banks idle state after tXSR is met. COMMAND INHIBIT or NOP commands should be issued on any clock edges occurring during the tXSR period. A minimum of two NOP commands must be provided during tXSR period. 7. After exiting clock suspend at clock edge n, the device will resume operation and recognize the next command at clock edge n + 1. 41 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)1999 Micron Technology, Inc. All rights reserved. 128Mb: x4, x8, x16 SDRAM Operations Table 9: Truth Table 3 - Current State Bank n, Command to Bank n Notes: 1-6; notes appear below and on next page Current State Any Idle Row active Read (auto precharge disabled) Write (Aauto precharge disabled) CS# RAS# CAS# WE# H L L L L L L L L L L L L L L L L X H L L L L H H L H H L H H H L H X H H L L H L L H L L H H L L H H X H H H L L H L L H L L L H L L L Notes: Command (Action) COMMAND INHIBIT (NOP/continue previous operation) NO OPERATION (NOP/continue previous operation) ACTIVE (Select and activate row) AUTO REFRESH LMR PRECHARGE READ (Select column and start READ burst) WRITE (Select column and start WRITE burst) PRECHARGE (Deactivate row in bank or banks) READ (Select column and start new READ burst) WRITE (Select column and start WRITE burst) PRECHARGE (Truncate READ burst, start precharge) BURST TERMINATE READ (Select column and start READ burst) WRITE (Select column and start new WRITE burst) PRECHARGE (Truncate WRITE burst, start precharge) BURST TERMINATE Notes 7 7 11 10 10 8 10 10 8 9 10 10 8 9 1. This table applies when CKEn - 1 was HIGH and CKEn is HIGH (see Table 8 on page 41) and after tXSR has been met (if the previous state was self refresh). 2. This table is bank-specific, except where noted; that is, the current state is for a specific bank, and the commands shown are those allowed to be issued to that bank when in that state. Exceptions are covered in the notes below. 3. Current state definitions: The bank has been precharged, and tRP has been met. A row in the bank has been activated, and tRCD has been met. No data bursts/accesses and no register accesses are in progress. Read: A READ burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated. Write: A WRITE burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated. 4. The following states must not be interrupted by a command issued to the same bank. COMMAND INHIBIT or NOP commands or allowable commands to the other bank should be issued on any clock edge occurring during these states. Allowable commands to the other bank are determined by its current state and Truth Table 3 and according to Truth Table 4. Idle: Row active: Precharging: Starts with registration of a PRECHARGE command and ends when is met. After tRP is met, the bank will be in the idle state. Starts with registration of an ACTIVE command and ends when tRCD is met. After tRCD is met, the bank will be in the row active state. Starts with registration of a READ command with auto precharge enabled and ends when tRP has been met. After tRP is met, the bank will be in the idle state. Starts with registration of a WRITE command with auto precharge enabled and ends when tRP has been met. After tRP is met, the bank will be in the idle state. tRP Row activating: Read w/auto precharge enabled: Write w/auto precharge enabled: PDF: 09005aef8091e66d/Source: 09005aef8091e625 128MSDRAM_2.fm - Rev. N 1/09 EN 42 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)1999 Micron Technology, Inc. All rights reserved. 128Mb: x4, x8, x16 SDRAM Operations 5. The following states must not be interrupted by any executable command; COMMAND INHIBIT or NOP commands must be applied on each positive clock edge during these states. Refreshing: 6. 7. 8. 9. 10. 11. PDF: 09005aef8091e66d/Source: 09005aef8091e625 128MSDRAM_2.fm - Rev. N 1/09 EN Starts with registration of an AUTO REFRESH command and ends when tRC is met. After tRC is met, the SDRAM will be in the all banks idle state. Starts with registration of a LMR command and ends when tMRD Accessing mode has been met. After tMRD is met, the SDRAM will be in the all banks register: idle state. Precharging all: Starts with registration of a PRECHARGE ALL command and ends when tRP is met. After tRP is met, all banks will be in the idle state. All states and sequences not shown are illegal or reserved. Not bank-specific; requires that all banks are idle. May or may not be bank-specific; if all banks are to be precharged, all must be in a valid state for precharging. Not bank-specific; BURST TERMINATE affects the most recent READ or WRITE burst, regardless of bank. READs or WRITEs listed in the Command (Action) column include READs or WRITEs with auto precharge enabled and READs or WRITEs with auto precharge disabled. Does not affect the state of the bank and acts as a NOP to that bank. 43 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)1999 Micron Technology, Inc. All rights reserved. 128Mb: x4, x8, x16 SDRAM Operations Table 10: Truth Table 4 - Current State Bank n, Command to Bank m Notes: 1-6; notes appear below and on next page Current State Any Idle Row activating, active, or precharging Read (auto precharge disabled) Write (auto precharge disabled) Read (with auto precharge) Write (with auto precharge) CS# RAS# CAS# WE# H L X L L L L L L L L L L L L L L L L L L L L X H X L H H L L H H L L H H L L H H L L H H L X H X H L L H H L L H H L L H H L L H H L L H X H X H H L L H H L L H H L L H H L L H H L L Notes: Command (Action) COMMAND INHIBIT (NOP/continue previous operation) NO OPERATION (NOP/continue previous operation) Any command otherwise allowed to bank m ACTIVE (Select and activate row) READ (Select column and start READ burst) WRITE (Select column and start WRITE burst) PRECHARGE ACTIVE (Select and activate row) READ (Select column and start new READ burst) WRITE (Select column and start WRITE burst) PRECHARGE ACTIVE (Select and activate row) READ (Select column and start READ burst) WRITE (Select column and start new WRITE burst) PRECHARGE ACTIVE (Select and activate row) READ (Select column and start new READ burst) WRITE (Select column and start WRITE burst) PRECHARGE ACTIVE (Select and activate row) READ (Select column and start READ burst) WRITE (Select column and start new WRITE burst) PRECHARGE Notes 7 7 7, 10 7, 11 9 7, 12 7, 13 9 7, 8, 14 7, 8, 15 9 7, 8, 16 7, 8, 17 9 1. This table applies when CKEn - 1 was HIGH and CKEn is HIGH (see Table 8 on page 41) and after tXSR has been met (if the previous state was self refresh). 2. This table describes alternate bank operation, except where noted; that is, the current state is for bank n, and the commands shown are those allowed to be issued to bank m (assuming that bank m is in such a state that the given command is allowable). Exceptions are covered in the notes below. 3. Current state definitions: The bank has been precharged, and tRP has been met. A row in the bank has been activated, and tRCD has been met. No data bursts/accesses and no register accesses are in progress. Read: A READ burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated. Write: A WRITE burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated. Starts with registration of a READ command with auto precharge Read w/auto precharge enabled: enabled, and ends when tRP has been met. After tRP is met, the bank will be in the idle state. Write w/auto Starts with registration of a WRITE command with auto precharge precharge enabled: enabled, and ends when tRP has been met. After tRP is met, the bank will be in the idle state. 4. AUTO REFRESH, SELF REFRESH, and LMR commands may only be issued when all banks are idle. Idle: Row active: PDF: 09005aef8091e66d/Source: 09005aef8091e625 128MSDRAM_2.fm - Rev. N 1/09 EN 44 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)1999 Micron Technology, Inc. All rights reserved. 128Mb: x4, x8, x16 SDRAM Operations 5. A BURST TERMINATE command cannot be issued to another bank; it applies to the bank represented by the current state only. 6. All states and sequences not shown are illegal or reserved. 7. READs or WRITEs to bank m listed in the Command (Action) column include READs or WRITEs with auto precharge enabled and READs or WRITEs with auto precharge disabled. 8. Concurrent auto precharge: Bank n will initiate the auto precharge command when its burst has been interrupted by bank m's burst. 9. Burst in bank n continues as initiated. 10. For a READ without auto precharge interrupted by a READ (with or without auto precharge), the READ to bank m will interrupt the READ on bank n, CL later (Figure 13 on page 27). 11. For a READ without auto precharge interrupted by a WRITE (with or without auto precharge), the WRITE to bank m will interrupt the READ on bank n when registered (Figure 15 on page 29 and Figure 16 on page 29). DQM should be used 1 clock prior to the WRITE command to prevent bus contention. 12. For a WRITE without auto precharge interrupted by a READ (with or without auto precharge), the READ to bank m will interrupt the WRITE on bank n when registered (Figure 23 on page 34), with the data-out appearing CL later. The last valid WRITE to bank n will be data-in registered 1 clock prior to the READ to bank m. 13. For a WRITE without auto precharge interrupted by a WRITE (with or without auto precharge), the WRITE to bank m will interrupt the WRITE on bank n when registered (Figure 21 on page 33). The last valid WRITE to bank n will be data-in registered 1 clock prior to the READ to bank m. 14. For a READ with auto precharge interrupted by a READ (with or without auto precharge), the READ to bank m will interrupt the READ on bank n, CL later. The precharge to bank n will begin when the READ to bank m is registered (Figure 30 on page 39). 15. For a READ with auto precharge interrupted by a WRITE (with or without auto precharge), the WRITE to bank m will interrupt the READ on bank n when registered. DQM should be used 2 clocks prior to the WRITE command to prevent bus contention. The precharge to bank n will begin when the WRITE to bank m is registered (Figure 31 on page 39). 16. For a WRITE with auto precharge interrupted by a READ (with or without auto precharge), the READ to bank m will interrupt the WRITE on bank n when registered, with the data-out appearing CL later. The precharge to bank n will begin after tWR is met, where tWR begins when the READ to bank m is registered. The last valid WRITE to bank n will be data-in registered one clock prior to the READ to bank m (Figure 32 on page 40). 17. For a WRITE with auto precharge interrupted by a WRITE (with or without auto precharge), the WRITE to bank m will interrupt the WRITE on bank n when registered. The precharge to bank n will begin after tWR is met, where tWR begins when the WRITE to bank m is registered. The last valid WRITE to bank n will be data registered 1 clock prior to the WRITE to bank m (Figure 33 on page 40). PDF: 09005aef8091e66d/Source: 09005aef8091e625 128MSDRAM_2.fm - Rev. N 1/09 EN 45 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)1999 Micron Technology, Inc. All rights reserved. 128Mb: x4, x8, x16 SDRAM Electrical Specifications Electrical Specifications Stresses greater than those listed in Table 11 may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Table 11: Absolute Maximum Ratings Parameter Voltage on VDD/VDDQ supply relative to VSS Voltage on inputs, NC or I/O pins relative to VSS Operating temperature TA (commercial) TA (industrial) TA (automotive) Storage temperature (plastic) Power dissipation Min Max Rating -1 -1 +4.6 +4.6 V V C 0 -40 -40 -55 +70 +85 +105 +150 1 C W Temperature and Thermal Impedance It is imperative that the SDRAM device's temperature specifications, shown in Table 12 on page 47, be maintained to ensure the junction temperature is in the proper operating range to meet data sheet specifications. An important step in maintaining the proper junction temperature is using the device's thermal impedances correctly. The thermal impedances are listed in Table 13 on page 47 for the applicable die revision and packages being made available. These thermal impedance values vary according to the density, package, and particular design used for each device. Incorrectly using thermal impedances can produce significant errors. Read Micron technical note TN-00-08, "Thermal Applications" prior to using the thermal impedances listed in Table 13. To ensure the compatibility of current and future designs, contact Micron Applications Engineering to confirm thermal impedance values. The SDRAM device's safe junction temperature range can be maintained when the TC specification is not exceeded. In applications where the device's ambient temperature is too high, use of forced air and/or heat sinks may be required to satisfy the case temperature specifications. PDF: 09005aef8091e66d/Source: 09005aef8091e625 128MSDRAM_2.fm - Rev. N 1/09 EN 46 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)1999 Micron Technology, Inc. All rights reserved. 128Mb: x4, x8, x16 SDRAM Electrical Specifications Table 12: Temperature Limits Parameter Symbol Table 13: 0 -40 -40 80 90 105 0 -40 -40 85 95 110 0 -40 -40 - 70 85 105 260 TJ TA TPEAK Units Notes C 1, 2, 3, 4 C 3 C 3, 5 C 1. MAX operating case temperature, TC is measured in the center of the package on the top side of the device, as shown in Figure 34, Figure 35, and Figure 36 on page 48. 2. Device functionality is not guaranteed if the device exceeds maximum TC during operation. 3. All temperature specifications must be satisfied 4. The case temperature should be measured by gluing a thermocouple to the top center of the component. This should be done with a 1mm bead of conductive epoxy, as defined by the JEDEC EIA/JESD51 standards. Care should be taken to ensure the thermocouple bead is touching the case. 5. Operating ambient temperature surrounding the package. Thermal Impedance Simulated Values Die Revision G Max TC Operating case temperature: Commercial Industrial Automotive Junction temperature: Commercial Industrial Automotive Ambient temperature: Commercial Industrial Automotive Peak reflow temperature Notes: Min Package Substrate JA (C/W) Airflow = 0m/s 54-pin TSOP 2-layer 4-layer 2-layer 4-layer 2-layer 4-layer 86.2 58.9 72.1 54.5 70.9 54.6 54-ball VFBGA 60-ball FBGA Notes: PDF: 09005aef8091e66d/Source: 09005aef8091e625 128MSDRAM_2.fm - Rev. N 1/09 EN JA (C/W) Airflow = 1m/s JA (C/W) Airflow = 2m/s JB (C/W) JC (C/W) 67.8 50.7 57.3 46.6 56.8 47.3 62 47.6 50.6 42.8 50.3 43.5 46.9 41.5 36 35.5 36.3 36.3 11.3 4.1 1.9 1. For designs expected to last beyond the die revision listed, contact Micron Applications Engineering to confirm thermal impedance values. 2. Thermal resistance data is sampled from multiple lots, and the values should be viewed as typical. 3. These are estimates; actual results may vary. 47 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)1999 Micron Technology, Inc. All rights reserved. 128Mb: x4, x8, x16 SDRAM Electrical Specifications Figure 34: Example Temperature Test Point Location, 54-Pin TSOP: Top View 22.22mm 11.11mm Test point 10.16mm 5.08mm Figure 35: Example Temperature Test Point Location, 54-Ball VFBGA: Top View 8.00mm 4.00mm Test point 8.00mm 4.00mm Figure 36: Example Temperature Test Point Location, 60-Ball FBGA: Top View 8.00mm 4.00mm Test point 16.00mm 8.00mm PDF: 09005aef8091e66d/Source: 09005aef8091e625 128MSDRAM_2.fm - Rev. N 1/09 EN 48 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)1999 Micron Technology, Inc. All rights reserved. 128Mb: x4, x8, x16 SDRAM Electrical Specifications Table 14: DC Electrical Characteristics and Operating Conditions Notes: 1, 5, 6; notes appear on page 51; VDD/VDDQ = +3.3 0.3V Parameter/Condition Supply voltage Input high voltage: Logic 1; All inputs Input low voltage: Logic 0; All inputs Input leakage current: Any input 0V VIN VDD (All other pins not under test = 0V) Output leakage current: DQ are disabled; 0V VOUT VDDQ Output levels: Output high voltage (IOUT = -4mA) Output low voltage (IOUT = 4mA) Table 15: Symbol Min Max Units Notes VDD/VDDQ VIH VIL II 3 2 -0.3 -5 3.6 VDD + 0.3 0.8 5 V V V A 22 22 IOZ -5 5 A VOH VOL 2.4 - - 0.4 V V IDD Specifications and Conditions Notes: 1, 5, 6, 11, 13; notes appear on page 51; VDD/VDDQ = +3.3 0.3V Max Parameter/Condition Operating current: Active mode; Burst = 2; READ or WRITE; tRC = tRC (MIN) Standby current: Power-down mode; All banks idle; CKE = LOW Standby current: Active mode; CKE = HIGH; CS# = HIGH; All banks active after tRCD met; No accesses in progress Operating current: Burst mode; Page burst; READ or WRITE; All banks active tRFC = tRFC (MIN) Auto refresh current: tRFC = 15.625s CKE = HIGH; CS# = HIGH tRFC = 3.906s(AT) Self refresh current: Standard CKE 0.2V Low power (L) Table 16: Symbol -6A -7E -75 Units Notes IDD1 170 160 150 mA IDD2 2 2 2 mA 3, 18, 19, 32 32 IDD3 50 50 50 mA 3, 12, 19, 32 IDD4 165 165 150 mA IDD5 IDD6 IDD6 IDD7 IDD7 330 3 6 2 - 330 3 6 2 1 310 3 6 2 1 mA mA mA mA mA 3, 18, 19, 32 3, 12, 18, 19, 32, 33 4 Capacitance Note: 2; notes appear on page 51 Parameter - TSOP "TG" Package Input capacitance: CLK Input capacitance: All other input-only pins Input/output capacitance: DQ Parameter - FBGA "FB" Input capacitance: CLK Input capacitance: All other input-only pins PDF: 09005aef8091e66d/Source: 09005aef8091e625 128MSDRAM_2.fm - Rev. N 1/09 EN 49 Symbol Min Max Units Notes CI1 CI2 CIO 2.5 2.5 4.0 3.5 3.8 6.0 pF pF pF 29 30 31 CI1 CI2 1.5 1.5 3.5 3.8 pF pF 34 35 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)1999 Micron Technology, Inc. All rights reserved. 128Mb: x4, x8, x16 SDRAM Electrical Specifications Table 17: Electrical Characteristics and Recommended AC Operating Conditions Notes: 5, 6, 8, 9, 11; notes appear on page 51 AC Characteristics -6A Parameter Symbol Access time from CLK (positive edge) Address hold time Address setup time CLK high-level width CLK low-level width Clock cycle time CL = 3 CL = 2 CL = 3 CL = 2 CKE hold time CKE setup time CS#, RAS#, CAS#, WE#, DQM hold time CS#, RAS#, CAS#, WE#, DQM setup time Data-in hold time Data-in setup time Data-out High-Z time CL = 3 CL = 2 Data-out Low-Z time Data-out hold time (load) Data-out hold time (no load) ACTIVE-to-PRECHARGE command ACTIVE-to-ACTIVE command period ACTIVE-to-READ or WRITE delay Refresh period (4,096 rows) Refresh period - Automotive (4,096 rows) AUTO REFRESH period PRECHARGE command period ACTIVE bank a to ACTIVE bank b command Transition time WRITE recovery time Exit SELF REFRESH to ACTIVE command Table 18: -7E Min Max AC(3) t AC(2) t AH t AS tCH t CL tCK(3) tCK(2) tCKH tCKS tCMH tCMS tDH tDS tHZ(3) tHZ(2) tLZ tOH tOHN tRAS tRC tRCD tREF tREF AT - - 0.8 1.5 2.5 2.5 6 - 0.8 1.5 0.8 1.5 0.8 1.5 - - 1 3 1.8 42 60 18 - - 5.4 - - - - - - - - - - - - - 5.4 - - - - 120,000 - - 64 16 tRFC 60 18 12 0.3 1 CLK + 7ns 12 67 t tRP tRRD tT tWR tXSR Min -75 Max Min Max Units Notes - - 0.8 1.5 2.5 2.5 7.5 10 0.8 1.5 0.8 1.5 0.8 1.5 - - 1 3 1.8 44 66 20 - - 5.4 6 - - - - - - - - - - - - 5.4 6 - - - 120,000 - - 64 16 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms ms 27 1 3 1.8 37 60 15 - - 5.4 5.4 - - - - - - - - - - - - 5.4 5.4 - - - 120,000 - - 64 16 - - - 66 15 14 - - - 66 20 15 - - - ns ns ns 1.2 - 0.3 1 CLK + 7ns 14 67 1.2 - 0.3 1 CLK + 7.5ns 15 75 1.2 - ns - 7 24 - - ns ns 25 20 0.8 1.5 2.5 2.5 7 7.5 0.8 1.5 0.8 1.5 0.8 1.5 - - - - 23 23 10 10 28 AC Functional Characteristics Notes: 5, 6, 7, 8, 9, 11; notes appear on page 51 Parameter Symbol tCCD READ/WRITE command to READ/WRITE command CKE to clock disable or power-down entry mode CKE to clock enable or power-down exit setup mode DQM to input data delay PDF: 09005aef8091e66d/Source: 09005aef8091e625 128MSDRAM_2.fm - Rev. N 1/09 EN tCKED t PED tDQD 50 -6A 1 1 1 0 -7E 1 1 1 0 -75 Units Notes 1 1 1 0 tCK 17 14 14 17 tCK t CK tCK Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)1999 Micron Technology, Inc. All rights reserved. 128Mb: x4, x8, x16 SDRAM Notes Table 18: AC Functional Characteristics Notes: 5, 6, 7, 8, 9, 11; notes appear on page 51 Parameter Symbol DQM to data mask during WRITEs DQM to data High-Z during READs WRITE command to input data delay Data-in to ACTIVE command Data-in to PRECHARGE command Last data-in to burst STOP command Last data-in to new READ/WRITE command Last data-in to PRECHARGE command LMR command to ACTIVE or REFRESH command Data-out to High-Z from PRECHARGE command t DQM DQZ t DWD t DAL tDPL t BDL t CDL t RDL t MRD t ROH(3) tROH(2) t CL = 3 CL = 2 -6A 0 2 0 5 2 1 1 2 2 3 - -7E 0 2 0 4 2 1 1 2 2 3 2 -75 0 2 0 5 2 1 1 2 2 3 2 Units t CK CK t CK t CK tCK t CK t CK t CK t CK t CK tCK t Notes 17 17 17 15, 21 16, 21 17 17 16, 21 26 17 17 Notes 1. All voltages referenced to VSS. 2. This parameter is sampled. VDD, VDDQ = +3.3V; f = 1 MHz, TA = 25C; pin under test biased at 1.4V. 3. IDD is dependent on output loading and cycle rates. Specified values are obtained with minimum cycle time and the outputs open. 4. Enables on-chip refresh and address counters. 5. The minimum specifications are used only to indicate cycle time at which proper operation over the full temperature range (0C TA +70C (commercial), -40C TA +85C (industrial), and -40C TA +105C (automotive) ) is ensured. 6. An initial pause of 100s is required after power-up, followed by two AUTO REFRESH commands, before proper device operation is ensured. (VDD and VDDQ must be powered up simultaneously. VSS and VSSQ must be at same potential.) The two AUTO REFRESH command wake-ups should be repeated any time the tREF refresh requirement is exceeded. 7. AC characteristics assume tT = 1ns. 8. In addition to meeting the transition rate specification, the clock and CKE must transit between VIH and VIL (or between VIL and VIH) in a monotonic manner. 9. Outputs measured at 1.5V with equivalent load: Q 50pF 10. tHZ defines the time at which the output achieves the open circuit condition; it is not a reference to VOH or VOL. The last valid data element will meet tOH before going High-Z. 11. AC timing and IDD tests have VIL = 0V and VIH = 3V, with timing referenced to 1.5V crossover point. If the input transition time is longer than 1 ns, then the timing is referenced at VIL (MAX) and VIH (MIN) and no longer at the 1.5V crossover point. CLK should always be 1.5V referenced to crossover. Refer to Micron technical note TN-48-09 for more details. PDF: 09005aef8091e66d/Source: 09005aef8091e625 128MSDRAM_2.fm - Rev. N 1/09 EN 51 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)1999 Micron Technology, Inc. All rights reserved. 128Mb: x4, x8, x16 SDRAM Notes 12. Other input signals are allowed to transition no more than once every 2 clocks and are otherwise at valid VIH or VIL levels. 13. IDD specifications are tested after the device is properly initialized. 14. Timing actually specified by tCKS; clock(s) specified as a reference only at minimum cycle rate. 15. Timing actually specified by tWR plus tRP; clock(s) specified as a reference only at minimum cycle rate. 16. Timing actually specified by tWR. 17. Required clocks are specified by JEDEC functionality and are not dependent on any timing parameter. 18. The IDD current will increase or decrease proportionally according to the amount of frequency alteration for the test condition. 19. Address transitions average one transition every 2 clocks. 20. CLK must be toggled a minimum of two times during this period. 21. Based on tCK = 7.5ns for -75/-7E, and tCK = 6ns for -6A. 22. VIH overshoot: VIH (MAX) = VDDQ + 2V for a pulse width 3ns, and the pulse width cannot be greater than one-third of the cycle rate. VIL undershoot: VIL (MIN) = -2V for a pulse width 3ns. 23. The clock frequency must remain constant (stable clock is defined as a signal cycling within timing constraints specified for the clock pin) during access or precharge states (READ, WRITE, including tWR, and PRECHARGE commands). CKE may be used to reduce the data rate. 24. Auto precharge mode only. The precharge timing budget (tRP) begins 6ns for -6A, 7ns for -7E, and 7.5ns for -75 after the first clock delay, after the last WRITE is executed. 25. Precharge mode only. 26. JEDEC and PC100 specify 3 clocks. 27. tAC for -75/-7E at CL = 3 with no load is 4.6ns and is guaranteed by design. 28. Parameter guaranteed by design. 29. PC100 specifies a maximum of 4pF. 30. PC100 specifies a maximum of 5pF. 31. PC100 specifies a maximum of 6.5pF. 32. For -75, CL = 3 and tCK = 7.5ns; for -7E, CL = 2 and tCK = 7.5ns, and CL = 3 and tCK = 6ns. 33. CKE is HIGH during refresh command period tRFC (MIN) else CKE is LOW. The IDD6 limit is actually a nominal value and does not result in a fail value. 34. PC133 specifies a minimum of 2.5pF. 35. PC133 specifies a minimum of 2.5pF. 36. PC133 specifies a minimum of 3.0pF. PDF: 09005aef8091e66d/Source: 09005aef8091e625 128MSDRAM_2.fm - Rev. N 1/09 EN 52 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)1999 Micron Technology, Inc. All rights reserved. 128Mb: x4, x8, x16 SDRAM Timing Diagrams Timing Diagrams Figure 37: Initialize and Load Mode Register T0 CLK (( )) CKE (( )) (( )) COMMAND (( )) (( )) tCK T1 tCKH tCKS Tn + 1 (( )) (( )) tCH tCMS tCMH (( )) NOP NOP (( )) AUTO REFRESH AUTO REFRESH (( )) NOP NOP (( )) (( )) (( )) (( )) (( )) (( )) (( )) A0-A9, A11 (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) A10 (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) BA0, BA1 (( )) (( )) DQ (( )) ALL BANKS SINGLE BANK ALL BANKS High-Z T = 100s MIN tRP Power-up: VDD and CLK stable Tp + 2 Tp + 3 (( )) (( )) (( )) DQM / DQML, DQMH Tp + 1 tCMS tCMH (( )) PRECHARGE (( )) NOP (( )) (( )) (( )) (( )) (( )) tCMS tCMH To + 1 tCL (( )) (( )) Precharge all banks tRFC tRFC AUTO REFRESH AUTO REFRESH LOAD MODE REGISTER tAS NOP tAH ROW CODE tAS ACTIVE tAH ROW CODE BANK tMRD Program Mode Register 2, 3, 4 DON'T CARE Notes: PDF: 09005aef8091e66d/Source: 09005aef8091e625 128MSDRAM_2.fm - Rev. N 1/09 EN 1. 2. 3. 4. If CS# is HIGH at clock HIGH time, all commands applied are NOP. The mode register may be loaded prior to the AUTO REFRESH cycles if desired. JEDEC and PC100 specify 3 clocks. Outputs are guaranteed High-Z after command is issued. 53 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)1999 Micron Technology, Inc. All rights reserved. 128Mb: x4, x8, x16 SDRAM Timing Diagrams Figure 38: Power-Down Mode T0 T1 tCK CLK T2 (( )) (( )) tCL tCKS tCH CKE tCKS PRECHARGE Tn + 2 tCKS (( )) tCKH tCMS tCMH COMMAND Tn + 1 NOP (( )) (( )) NOP NOP ACTIVE DQM / DQML, DQMH (( )) (( )) A0-A9, A11 (( )) (( )) ROW (( )) (( )) ROW (( )) (( )) BANK ALL BANKS A10 SINGLE BANK tAS BA0, BA1 tAH BANK(S) High-Z (( )) DQ Two clock cycles Input buffers gated off while in power-down mode Precharge all active banks All banks idle, enter power-down mode All banks idle Exit power-down mode DON'T CARE Notes: PDF: 09005aef8091e66d/Source: 09005aef8091e625 128MSDRAM_2.fm - Rev. N 1/09 EN 1. Violating refresh requirements during power-down may result in a loss of data. 54 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)1999 Micron Technology, Inc. All rights reserved. 128Mb: x4, x8, x16 SDRAM Timing Diagrams Figure 39: Clock Suspend Mode T0 T1 T2 tCK CLK T3 T4 T5 T6 T7 T8 NOP WRITE T9 tCL tCH tCKS tCKH CKE tCKS tCKH tCMS tCMH COMMAND READ NOP NOP NOP NOP NOP tCMS tCMH DQM / DQML, DQMH A0-A9, A11 tAS tAH COLUMN m 2 tAS tAH tAS tAH COLUMN e 2 A10 BA0, BA1 BANK BANK tAC tOH tAC DQ tLZ DOUT m tHZ DOUT m + 1 tDS tDH DIN e DIN e + 1 DON'T CARE UNDEFINED Notes: PDF: 09005aef8091e66d/Source: 09005aef8091e625 128MSDRAM_2.fm - Rev. N 1/09 EN 1. For this example, BL = 2, CL = 3, and auto precharge is disabled. 2. x16: A9 and A11 = "Don't Care." x8: A11 = "Don't Care." 55 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)1999 Micron Technology, Inc. All rights reserved. 128Mb: x4, x8, x16 SDRAM Timing Diagrams Figure 40: Auto Refresh Mode T0 CLK T1 tCK T2 (( )) (( )) tCH tCKS tCKH tCMS tCMH PRECHARGE NOP AUTO REFRESH NOP A0-A9, A11 ALL BANKS A10 SINGLE BANK tAS DQ (( )) ( ( NOP )) To + 1 (( )) AUTO REFRESH NOP (( )) (( )) DQM / DQML, DQMH BA0, BA1 (( )) (( )) (( )) CKE COMMAND Tn + 1 tCL (( )) ( ( NOP )) ACTIVE (( )) (( )) (( )) (( )) (( )) (( )) ROW (( )) (( )) (( )) (( )) ROW tAH BANK(S) High-Z tRP tRFC1 Precharge all active banks Notes: PDF: 09005aef8091e66d/Source: 09005aef8091e625 128MSDRAM_2.fm - Rev. N 1/09 EN (( )) (( )) (( )) (( )) (( )) (( )) BANK tRFC1 DON'T CARE 1. Each AUTO REFRESH command performs a refresh cycle. Back-to-back commands are not required. 56 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)1999 Micron Technology, Inc. All rights reserved. 128Mb: x4, x8, x16 SDRAM Timing Diagrams Figure 41: Self Refresh Mode T0 CLK T1 tCK tCL tCH T2 tCKS tRAS min1 CKE COMMAND tCKS tCKH tCMS tCMH NOP A0-A9, A11 ALL BANKS A10 SINGLE BANK BA0, BA1 DQ AUTO REFRESH (( )) (( )) To + 1 To + 2 (( )) (( )) (( )) PRECHARGE tAS Tn + 1 (( )) (( )) (( )) (( )) (( ) ) or COMMAND NOP ( ( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) INHIBIT AUTO REFRESH tAH BANK(S) High-Z tRP Precharge all active banks tXSR Enter self refresh mode Exit self refresh mode (Restart refresh time base) CLK stable prior to exiting self refresh mode Notes: PDF: 09005aef8091e66d/Source: 09005aef8091e625 128MSDRAM_2.fm - Rev. N 1/09 EN 1. 2. 3. DON'T CARE No maximum time limit for self refresh. tRAS MAX applies to non-self refresh mode. requires minimum of 2 clocks regardless of frequency or timing. Self refresh mode not supported on automotive temperature (AT) devices. tXSR 57 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)1999 Micron Technology, Inc. All rights reserved. 128Mb: x4, x8, x16 SDRAM Timing Diagrams Figure 42: READ - Without Auto Precharge T0 T1 tCK CLK T2 T3 T4 T5 NOP NOP T6 T7 T8 NOP ACTIVE tCL tCH tCKS tCKH CKE tCMS tCMH COMMAND ACTIVE NOP READ NOP PRECHARGE tCMS tCMH DQM / DQML, DQMH tAS A0-A9, A11 tAS COLUMN m2 ROW tAH ALL BANKS ROW A10 tAS BA0, BA1 tAH ROW ROW tAH BANK DISABLE AUTO PRECHARGE SINGLE BANKS BANK BANK(S) tAC tOH tAC DQ tLZ tRCD DOUT m tAC tOH DOUT m+1 BANK tAC tOH tOH DOUT m+2 DOUT m+3 tHZ tRP CAS Latency tRAS tRC DON'T CARE UNDEFINED Notes: PDF: 09005aef8091e66d/Source: 09005aef8091e625 128MSDRAM_2.fm - Rev. N 1/09 EN 1. For this example, BL = 4, CL = 2, and the READ burst is followed by a "manual" PRECHARGE. 2. x16: A9 and A11 = "Don't Care." x8: A11 = "Don't Care." 58 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)1999 Micron Technology, Inc. All rights reserved. 128Mb: x4, x8, x16 SDRAM Timing Diagrams Figure 43: READ - With Auto Precharge T0 T1 tCK CLK tCKS T2 T3 T4 T5 NOP NOP T6 T7 T8 NOP ACTIVE tCL tCH tCKH CKE tCMS tCMH COMMAND ACTIVE NOP READ tCMS NOP NOP tCMH DQM / DQML, DQMH tAS A0-A9, A11 tAH ROW ENABLE AUTO PRECHARGE ROW tAS BA0, BA1 COLUMN m 2 ROW tAS A10 tAH ROW tAH BANK BANK BANK tAC tOH tAC DQ DOUT m tLZ tRCD tAC tOH DOUT m + 1 tAC tOH DOUT m + 2 tOH DOUT m + 3 tHZ tRP CAS Latency tRAS tRC DON'T CARE UNDEFINED Notes: PDF: 09005aef8091e66d/Source: 09005aef8091e625 128MSDRAM_2.fm - Rev. N 1/09 EN 1. For this example, BL = 4, and CL = 2. 2. x16: A9 and A11 = "Don't Care." x8: A11 = "Don't Care." 59 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)1999 Micron Technology, Inc. All rights reserved. 128Mb: x4, x8, x16 SDRAM Timing Diagrams Figure 44: Single READ - Without Auto Precharge T0 T1 tCK CLK T2 T3 T4 T5 NOP 3 NOP 3 T6 T7 T8 tCL tCH tCKS tCKH CKE tCMS tCMH COMMAND ACTIVE NOP READ PRECHARGE NOP ACTIVE NOP tCMS tCMH DQM / DQML, DQMH tAS A0-A9, A11 tAS COLUMN m2 ROW tAH ALL BANKS ROW A10 tAS BA0, BA1 tAH ROW ROW DISABLE AUTO PRECHARGE tAH BANK SINGLE BANKS BANK BANK(S) tOH tAC DQ tLZ tRCD BANK DOUT m tHZ tRP CAS Latency tRAS tRC DON'T CARE UNDEFINED Notes: PDF: 09005aef8091e66d/Source: 09005aef8091e625 128MSDRAM_2.fm - Rev. N 1/09 EN 1. For this example, BL = 1, CL = 2, and the READ burst is followed by a "manual" PRECHARGE. 2. x16: A9 and A11 = "Don't Care." x8: A11 = "Don't Care." 3. PRECHARGE command not allowed or tRAS would be violated. 60 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)1999 Micron Technology, Inc. All rights reserved. 128Mb: x4, x8, x16 SDRAM Timing Diagrams Figure 45: Single READ - With Auto Precharge T0 T1 tCK CLK tCKS T2 T3 T4 T5 T6 T7 T8 tCL tCH tCKH CKE tCMS tCMH COMMAND ACTIVE NOP NOP2 NOP2 READ tCMS NOP NOP ACTIVE NOP tCMH DQM / DQML, DQMU tAS A0-A9, A11 tAH ROW ENABLE AUTO PRECHARGE ROW tAS BA0, BA1 COLUMN m3 ROW tAS A10 tAH ROW tAH BANK BANK BANK tAC t OH DOUT m DQ tRCD CAS Latency tHZ tRP tRAS tRC DON'T CARE UNDEFINED Notes: PDF: 09005aef8091e66d/Source: 09005aef8091e625 128MSDRAM_2.fm - Rev. N 1/09 EN 1. For this example, BL = 1, and CL = 2. 2. x16: A9 and A11 = "Don't Care." x8: A11 = "Don't Care." 3. READ command not allowed or tRAS would be violated. 61 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)1999 Micron Technology, Inc. All rights reserved. 128Mb: x4, x8, x16 SDRAM Timing Diagrams Figure 46: Alternating Bank Read Accesses T0 T1 tCK CLK T2 T3 T4 T5 NOP ACTIVE T6 T7 T8 READ NOP ACTIVE tCL tCH tCKS tCKH CKE tCMS tCMH COMMAND ACTIVE NOP READ tCMS NOP tCMH DQM / DQML, DQMH tAS A0-A9, A11 tAS A10 COLUMN m 2 tAH COLUMN b 2 ROW ENABLE AUTO PRECHARGE ROW ENABLE AUTO PRECHARGE ROW tAS BA0, BA1 tAH ROW ROW ROW tAH BANK 0 BANK 0 BANK 3 tAC tOH tAC DQ DOUT m tLZ tRCD - BANK 0 BANK 3 tAC tOH DOUT m + 1 BANK 0 tAC tOH DOUT m + 2 tAC tOH DOUT m + 3 tRP - BANK 0 CAS Latency - BANK 0 tAC tOH DOUT b tRCD - BANK 0 tRAS - BANK 0 tRC - BANK 0 tRCD - BANK 3 tRRD CAS Latency - BANK 3 DON'T CARE UNDEFINED Notes: PDF: 09005aef8091e66d/Source: 09005aef8091e625 128MSDRAM_2.fm - Rev. N 1/09 EN 1. For this example, BL = 4, and CL = 2. 2. x16: A9 and A11 = "Don't Care." x8: A11 = "Don't Care." 62 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)1999 Micron Technology, Inc. All rights reserved. 128Mb: x4, x8, x16 SDRAM Timing Diagrams Figure 47: READ - Full-Page Burst T0 T1 T2 tCL CLK T3 T4 T5 T6 (( )) (( )) tCK tCH tCKS tCMH ACTIVE NOP READ tCMS NOP NOP NOP NOP tCMH tAS tAH tAH NOP BURST TERM NOP NOP (( )) (( )) ROW tAS (( )) (( )) (( )) (( )) COLUMN m 2 ROW tAS BA0, BA1 Tn + 4 (( )) (( )) DQM / DQML, DQMH A10 Tn + 3 (( )) (( )) tCMS A0-A9, A11 Tn + 2 tCKH CKE COMMAND Tn + 1 tAH BANK (( )) (( )) BANK tAC tAC DQ tOH DOUT m DOUT m+1 tLZ tRCD CAS Latency tAC tOH tAC ( ( tOH ) ) DOUT m+2 (( )) (( )) tAC tOH tOH DOUT m-1 DOUT m DOUT m+1 512 (x16) locations within same row 1,024 (x8) locations within same row 2,048 (x4) locations within same row Full page completed Full-page burst does not self-terminate. 3 Can use BURST TERMINATE command. Notes: PDF: 09005aef8091e66d/Source: 09005aef8091e625 128MSDRAM_2.fm - Rev. N 1/09 EN tAC tOH tHZ DON'T CARE UNDEFINED 1. For this example, CL = 2. 2. x16: A9 and A11 = "Don't Care." x8: A11 = "Don't Care." 3. Page left open; no tRP. 63 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)1999 Micron Technology, Inc. All rights reserved. 128Mb: x4, x8, x16 SDRAM Timing Diagrams Figure 48: READ - DQM Operation T0 T1 tCK CLK tCKS tCKH tCMS tCMH T2 T3 T4 T5 NOP NOP T6 T7 T8 NOP NOP NOP tCL tCH CKE COMMAND ACTIVE NOP READ tCMS NOP tCMH DQM / DQML, DQMH tAS A0-A9, A11 tAS A10 COLUMN m 2 tAH ENABLE AUTO PRECHARGE ROW tAS BA0, BA1 tAH ROW DISABLE AUTO PRECHARGE tAH BANK BANK tAC DQ tOH DOUT m tLZ tRCD tAC tHZ tAC tOH DOUT m + 2 tLZ tOH DOUT m + 3 tHZ CAS Latency DON'T CARE UNDEFINED Notes: PDF: 09005aef8091e66d/Source: 09005aef8091e625 128MSDRAM_2.fm - Rev. N 1/09 EN 1. For this example, BL = 4, and CL = 2. 2. x16: A9 and A11 = "Don't Care." x8: A11 = "Don't Care." 64 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)1999 Micron Technology, Inc. All rights reserved. 128Mb: x4, x8, x16 SDRAM Timing Diagrams Figure 49: WRITE - Without Auto Precharge T0 tCK CLK T1 T2 tCL T3 T4 T5 T6 T7 T8 T9 NOP NOP NOP NOP PRECHARGE NOP ACTIVE tCH tCKS tCKH tCMS tCMH CKE COMMAND ACTIVE NOP WRITE tCMS tCMH DQM / DQML, DQMH tAS A0-A9, A11 tAS A10 COLUMN m 3 ROW tAH ALL BANKS ROW tAS BA0, BA1 tAH ROW ROW tAH DISABLE AUTO PRECHARGE SINGLE BANK BANK BANK BANK tDS tDH DIN m DQ tDS tDH DIN m + 1 tDS tDH DIN m + 2 tDS tDH DIN m + 3 t WR 2 tRCD tRAS BANK tRP tRC DON'T CARE Notes: PDF: 09005aef8091e66d/Source: 09005aef8091e625 128MSDRAM_2.fm - Rev. N 1/09 EN 1. For this example, BL = 4, and the WRITE burst is followed by a "manual" PRECHARGE. 2. 15ns is required between <DIN m + 3> and the PRECHARGE command, regardless of frequency. 3. x16: A9 and A11 = "Don't Care." x8: A11 = "Don't Care." 65 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)1999 Micron Technology, Inc. All rights reserved. 128Mb: x4, x8, x16 SDRAM Timing Diagrams Figure 50: WRITE - With Auto Precharge T0 tCK CLK tCKS tCKH tCMS tCMH T1 T2 tCL T3 T4 T5 T6 T7 T8 T9 NOP NOP NOP NOP NOP NOP ACTIVE tCH CKE COMMAND ACTIVE NOP WRITE tCMS tCMH DQM / DQML, DQMH tAS A0-A9, A11 tAH ROW ENABLE AUTO PRECHARGE ROW tAS BA0, BA1 COLUMN m 2 ROW tAS A10 tAH ROW tAH BANK BANK tDS tDH DIN m DQ BANK tDS tDH DIN m + 1 tDS tDH DIN m + 2 tRCD tRAS tDS tDH DIN m + 3 tWR tRP tRC DON'T CARE Notes: PDF: 09005aef8091e66d/Source: 09005aef8091e625 128MSDRAM_2.fm - Rev. N 1/09 EN 1. For this example, BL = 4. 2. x16: A9 and A11 = "Don't Care." x8: A11 = "Don't Care." 66 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)1999 Micron Technology, Inc. All rights reserved. 128Mb: x4, x8, x16 SDRAM Timing Diagrams Figure 51: Single WRITE - Without Auto Precharge T0 tCK CLK T1 T2 tCL T3 T4 NOP2 NOP2 T5 T6 T7 T8 ACTIVE NOP tCH tCKS tCKH tCMS tCMH CKE COMMAND ACTIVE NOP WRITE PRECHARGE NOP tCMS tCMH DQM / DQML, DQMU tAS A0-A9, A11 tAH ALL BANKS ROW tAS BA0, BA1 COLUMN m 3 ROW tAS A10 tAH ROW tAH DISABLE AUTO PRECHARGE SINGLE BANK BANK BANK BANK tDS BANK tDH DIN m DQ tRCD tRAS tRP t WR 4 tRC DON'T CARE Notes: PDF: 09005aef8091e66d/Source: 09005aef8091e625 128MSDRAM_2.fm - Rev. N 1/09 EN 1. For this example, BL = 1, and the WRITE burst is followed by a "manual" PRECHARGE. 2. 15ns is required between <DIN m> and the PRECHARGE command, regardless of frequency. 3. x16: A9 and A11 = "Don't Care." x8: A11 = "Don't Care." 67 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)1999 Micron Technology, Inc. All rights reserved. 128Mb: x4, x8, x16 SDRAM Timing Diagrams Figure 52: Single WRITE - With Auto Precharge T0 tCK CLK tCKS tCKH tCMS tCMH T1 tCL T2 T3 T4 T5 T6 T7 NOP3 WRITE NOP NOP NOP T8 T9 tCH CKE COMMAND NOP3 ACTIVE NOP3 tCMS ACTIVE NOP tCMH DQM / DQML, DQMH tAS A0-A9, A11 tAH ROW ENABLE AUTO PRECHARGE ROW tAS BA0, BA1 COLUMN m 2 ROW tAS A10 tAH ROW tAH BANK BANK tDS BANK tDH DIN m DQ tRCD tRAS tWR tRP tRC DON'T CARE Notes: PDF: 09005aef8091e66d/Source: 09005aef8091e625 128MSDRAM_2.fm - Rev. N 1/09 EN 1. For this example, BL = 1. 2. x16: A9 and A11 = "Don't Care." x8: A11 = "Don't Care." 3. Write command not allowed or tRAS would be violated. 68 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)1999 Micron Technology, Inc. All rights reserved. 128Mb: x4, x8, x16 SDRAM Timing Diagrams Figure 53: Alternating Bank Write Accesses T0 tCK CLK T1 T2 tCL T3 T4 T5 T6 T7 T8 T9 NOP NOP ACTIVE tCH tCKS tCKH tCMS tCMH CKE COMMAND ACTIVE NOP WRITE tCMS NOP ACTIVE NOP WRITE tCMH DQM / DQML, DQMH tAS A0-A9, A11 tAH COLUMN b 2 ROW ENABLE AUTO PRECHARGE ROW ENABLE AUTO PRECHARGE ROW tAS BA0, BA1 COLUMN m 2 ROW tAS A10 tAH ROW ROW tAH BANK 0 BANK 0 tDS tDH DIN m DQ BANK 1 tDS tDH DIN m + 1 tDS BANK 1 tDH tDS DIN m + 2 tDH DIN m + 3 tDS tDH DIN b tWR - BANK 0 tRCD - BANK 0 BANK 0 tDS tDH DIN b + 1 tDS tDH DIN b + 2 tRP - BANK 0 tDS tDH DIN b + 3 tRCD - BANK 0 tRAS - BANK 0 tRC - BANK 0 tRCD - BANK 1 tRRD tWR - BANK 1 DON'T CARE Notes: PDF: 09005aef8091e66d/Source: 09005aef8091e625 128MSDRAM_2.fm - Rev. N 1/09 EN 1. For this example, BL = 4. 2. x16: A9 and A11 = "Don't Care." x8: A11 = "Don't Care." 69 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)1999 Micron Technology, Inc. All rights reserved. 128Mb: x4, x8, x16 SDRAM Timing Diagrams Figure 54: WRITE - Full-Page Burst T0 T1 T2 tCL CLK T3 T4 T5 (( )) (( )) tCK tCH tCKS tCKH COMMAND tCMH ACTIVE NOP WRITE NOP NOP NOP tCMS tCMH tAS A10 (( )) (( )) NOP BURST TERM NOP (( )) (( )) COLUMN m 1 tAH (( )) (( )) ROW tAS BA0, BA1 tAH ROW tAS Tn + 3 (( )) (( )) DQM / DQML, DQMH A0-A9, A11 Tn + 2 (( )) (( )) CKE tCMS Tn + 1 tAH BANK (( )) (( )) BANK tDS tDH DIN m DQ tDS tDH DIN m + 1 tRCD tDS tDH DIN m + 2 tDS tDH DIN m + 3 (( )) (( )) tDS DIN m - 1 512 (x16) locations within same row 1,024 (x8) locations within same row 2,048 (x4) locations within same row Full page completed Notes: PDF: 09005aef8091e66d/Source: 09005aef8091e625 128MSDRAM_2.fm - Rev. N 1/09 EN tDH Full-page burst does not self-terminate. Can use BURST TERMINATE command to stop.2, 3 DON'T CARE 1. x16: A9 and A11 = "Don't Care." x8: A11 = "Don't Care." 2. tWR must be satisfied prior to PRECHARGE command. 3. Page left open; no tRP. 70 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)1999 Micron Technology, Inc. All rights reserved. 128Mb: x4, x8, x16 SDRAM Timing Diagrams Figure 55: WRITE - DQM Operation T0 T1 tCK CLK T2 T3 T4 T5 NOP NOP NOP T6 T7 NOP NOP tCL tCH tCKS tCKH tCMS tCMH CKE COMMAND ACTIVE NOP WRITE tCMS tCMH DQM / DQML, DQMH tAS A0-A9, A11 tAS A10 COLUMN m 2 tAH ENABLE AUTO PRECHARGE ROW tAS BA0, BA1 tAH ROW tAH DISABLE AUTO PRECHARGE BANK BANK tDS tDH tDS DIN m DQ tDH DIN m + 2 tDS tDH DIN m + 3 tRCD DON'T CARE Notes: PDF: 09005aef8091e66d/Source: 09005aef8091e625 128MSDRAM_2.fm - Rev. N 1/09 EN 1. For this example, BL = 4. 2. x16: A9 and A11 = "Don't Care." x8: A11 = "Don't Care." 71 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)1999 Micron Technology, Inc. All rights reserved. 128Mb: x4, x8, x16 SDRAM Package Dimensions Package Dimensions Figure 56: 54-Pin Plastic TSOP (400 mil) 0.10 1.2 MAX 0.375 0.075 TYP PIN #1 ID 0.80 TYP (FOR REFERENCE ONLY) 22.22 .08 2X R 0.75 2X R 1.00 2X 0.71 PLATED LEAD FINISH: 90% Sn, 10% Pb OR 100%Sn PLASTIC PACKAGE MATERIAL: EPOXY NOVOLAC PACKAGE WIDTH AND LENGTH DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.25 PER SIDE. 2X 0.10 2.80 GAGE PLANE 10.16 0.08 0.25 +0.10 0.10 -0.05 11.76 0.20 SEE DETAIL A +0.03 0.15 -0.02 0.50 0.10 0.80 DETAIL A Notes: PDF: 09005aef8091e66d/Source: 09005aef8091e625 128MSDRAM_2.fm - Rev. N 1/09 EN 1. All dimensions in millimeters. 2. Package width and length do not include mold protrusion; allowable mold protrusion is 0.25mm per side. 3. "2X" means the notch is present in two locations (both ends of the device). 72 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)1999 Micron Technology, Inc. All rights reserved. 128Mb: x4, x8, x16 SDRAM Package Dimensions Figure 57: 60-Ball FBGA "FB/BB" Package (x8 device), 8mm x 16mm 0.155 0.013 0.850 0.05 0.10 A SEATING PLANE 2.40 0.05 CTR 60X O 0.45 DIMENSIONS APPLY TO SOLDER BALLS POST REFLOW. PREREFLOW DIAMETER IS 0.42 ON A 0.33 NSMD BALL PAD. SOLDER BALL MATERIAL: 62% Sn, 36% Pb, 2% Ag OR 96.5% Sn. 3% Ag, 0.5% Cu A SUBSTRATE: PLASTIC LAMINATE 8.00 0.10 5.60 0.80 TYP BALL #1 ID ENCAPSULATION MATERIAL: EPOXY NOVOLAC BALL #1 ID BALL A1 BALL A8 0.80 TYP 8.00 0.05 16.00 0.10 CL 11.20 5.60 2.80 1.20 MAX 4.00 0.05 Notes: PDF: 09005aef8091e66d/Source: 09005aef8091e625 128MSDRAM_2.fm - Rev. N 1/09 EN 1. All dimensions in millimeters. 2. Recommended pad size for PCB is 0.33mm 0.025mm. 3. Topside part marking decoder can be found at http://www.micron.com/decoder. 73 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)1999 Micron Technology, Inc. All rights reserved. 128Mb: x4, x8, x16 SDRAM Package Dimensions Figure 58: 54-Ball VFBGA "F4/B4" Package (x16 device), 8mm x 8mm 0.65 0.05 SEATING PLANE SOLDER BALL MATERIAL: 62% Sn, 36% Pb, 2% Ag OR 96.5% Sn, 3% Ag, 0.5% Cu SOLDER MASK DEFINED BALL PADS: O0.40 SUBSTRATE MATERIAL: PLASTIC LAMINATE MOLD COMPOUND: EPOXY NOVOLAC C 0.10 C 54X O0.45 0.05 SOLDER BALL DIAMETER REFERS TO POST REFLOW CONDITION. THE PREREFLOW DIAMETER IS 0.42. 6.40 0.80 TYP BALL A1 ID BALL A1 ID BALL A1 4.00 0.05 BALL A9 6.40 CL 8.00 0.10 3.20 0.80 TYP CL 3.20 4.00 0.05 1.00 MAX 8.00 0.10 Notes: 1. All dimensions in millimeters. 2. Recommended pad size for PCB is 0.40mm SMD. 3. Topside part marking decoder can be found at http://www.micron.com/decoder. (R) 8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900 prodmktg@micron.com www.micron.com Customer Comment Line: 800-932-4992 Micron, the M logo, and the Micron logo are trademarks of Micron Technology, Inc. All other trademarks are the property of their respective owners. This data sheet contains minimum and maximum limits specified over the complete power supply and temperature range set forth herein. Although considered final, these specifications are subject to change, as further product development and data characterization sometimes occur. PDF: 09005aef8091e66d/Source: 09005aef8091e625 128MSDRAM_2.fm - Rev. N 1/09 EN 74 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)1999 Micron Technology, Inc. All rights reserved.