FLX... =_ =z SET GHNOLOG Y TE AUGUST 16, 1997 VERSION 1.0 1. GENERAL DESCRIPTION PCI 9052 provides a compact high performance PCI bus target (slave) interface for adapter boards. PCI 9052 is designed to connect a wide variety of local bus designs to the PCI bus and allow relatively slow local bus designs to achieve 132 MB/sec burst transfers on the PCI bus. PCI 9052 can be programmed to connect directly to multiplexed or nonmultiplexed 8, 16, or 32 bit local bus. 8- and 16-bit modes enable easy conversion of ISA designs to PCI. (Refer to Figure 1-1.) PCI 9052 contains a read and write FIFO to speed match 32-bit wide, 33 MHz PCI bus to a local bus, which may be narrower or slower. Up to five Local Address Spaces and up to four chip selects are supported. 1.1 MAJOR FEATURES PCI Specification 2.1 compliant. PC! 9052 is compliant with PCI Specification 2.1, supporting low cost slave adapters. The chip allows simple conversion of ISA adapters to PCI. Direct slave (Target) data transfer mode. PCI 9052 supports burst memory-mapped and = |l/O-mapped accesses from the PCI bus to local bus. Read and write FIFOs enable high-performance bursting on the local and PCI buses. PCI bus is always bursting; however, the local bus can be set to bursting or continuous single cycle. Interrupt generator. PC] 9052 can generate a PCI interrupt from two local bus interrupt inputs. Clock. PCI 9052 local bus interface runs from a local TTL clock and generates necessary internal clocks. This clock runs asynchronously to the PCI clock, allowing the local bus to run at an independent rate from PCI clock. Buffered PCI bus clock (BCLKo) may be connected to the local bus clock (LCLK). Programmable local bus configurations. PCI 9052 supports 8, 16, or 32 bit local buses, which may be multiplexed or nonmultiplexed. PCI 9052 has four byte enables (LBE[3:0]#), 26 address lines (LA[27:2]), and 32, 16, or 8 bit data lines (LAD[31:0]). PCI 9052 PCI BUS TARGET CHIP WITH GLUELESS ISA INTERFACE LOGIC FOR LOW COST ADAPTERS Read Ahead Mode. PCI 9052 supports read ahead mode, where prefetched data can be read from the PCI 9052 internal FIFO instead of the local side. Address must be subsequent to previous address and 32-bit aligned (next address = current address + 4). Bus drivers. All control, address, and data signals generated by PCI 9052 directly drive the PCI and local bus, without external drivers. Serial EEPROM interface. PCI 9052 contains a serial EEPROM interface, used to load _ configuration information. This is useful for loading information unique to a particular adapter (Such as Network ID, Vendor ID, and chip selects). Note: Serial EEPROM is required to switch PCI 9052 into ISA interface mode. Four local chip selects. PCI 9052 provides up to four local chip selects. Base address and range of each chip select are independently programmable from the serial EEPROM or host. Five Local Address Spaces. Base address and range of each Local Address Space are independently programmable from the serial EEPROM or host. Big/Little Endian byte swapping. PCI 9052 supports Big and Little Endian byte ordering. PCI 9052 also supports Big Endian byte lane mode to redirect the current word/byte lane during 16 or 8 bit local bus operation. Read/write strobe delay and write cycle hold. Read and Write (RD# and WR#) signals can be delayed from the beginning of cycle for legacy interfaces (such as ISA bus). Local bus wait states. In addition to LRDYi# (local ready input) handshake signal for variable wait state generations, PCI 9052 has an internal wait state(s) generator (R/W address to data, R/W data-to-data, and R/W data-to-address). Programmable prefetch counter. The local bus prefetch counter can be programmed for 0 (no prefetch), 4, 8, 16, or continuous (prefetch counter turned off) Prefetch mode. The prefetched data can be used as cached data if a consecutive address is used (must be longword (Lword) aligned). PLX Technology, Inc., 1997 Page 1 Version 1.0SECTION 1 PCI 9052 Delayed Read mode. PCI 9052 supports PCI Specification 2.1 Delayed Read with e PCI Read with Write Flush Mode e PCI Read No Flush Mode e PCI Read No Write Mode e PCI Write Mode PCI Read/Write request time out Timer. PCI 9052 has a programmable PCI Target Retry Delay Timer, which, when expired, generates a RETRY to the PCI bus. ISA mode Interface Logic on-board. PCI 9052 supports single cycle reads/writes for 8-, 16-bit memory Zao GENERAL DESCRIPTION and I/O mapped accesses from the PCI bus to ISA bus. Space 0 and Space 1 are used in conjunction with memory and I/O mapped accesses. Refer to Section 4, ISA Interface Mode, on how to use PCI 9052 in ISA mode. PCI LOCK mechanism. PCI 9052 supports PCI target LOCK sequences. A PCI master can obtain exclusive access to PCI 9052 device by locking to PCI 9052. PCI bus transfers up to 132 MB/sec. Low power CMOS in 160 pin plastic QFP package. ZN AD[31:0 LAD[31:0 C/BE[3:0]# , | \ LA[27:2 <<__PAR_ LBE[3:0]# FRAME# _, LINTi4 . LINTi2 __IRDY# c LCLK Q) _stop# 2 _____LHOLD | DseEL_ || _____LHOLDA VO | <_DEVSEL# @ LRESET# , | w Controller O PERR# __| | ____BCLKO | 3 OQ} , senn# | | CS[1:0]# a 2 _ USEROWAITO# , | % USER1/LLOCK# CLK ~__USER2Z/CS2# _, 9 RST# / ___USER3/CS3# a INTA ADS# Memory *~ Lock# BLAST# NU RD# __RD lg PCI WR# <__EESK <___LRDYi# Serial ___ EFEDO_, 9052 <<___BIERM# EEPROM | FED __ ALE, ,__EECS MODE MEMWR# MEMRD# lIOWR# IORD# SBHE# ISAA[1:0] > LA[23:2] a LAD[15:0] ns BALE CHRDY NOWS# Figure 1-1. PCI 9052 Signal Interfaces PLX Technology, Inc., 1997 Page 2 Version 1.0SECTION 2 PCI 9052 BUS OPERATION 2. BUS OPERATION 2.1 PCI BUS CYCLES PCI 9052 is PCI Specification 2.1 compliant. 2.1.1 PCI Target Command Codes As a target, PCI 9052 allows access to PCI 9052 internal registers and the local bus, using commands listed in Table 2-1. Table 2-1. Target Command Codes /O Read (2h) I/O Write (3h) Memory Read (6h) Memory Write (7h) Memory Read Multiple (Ch) Memory Read Line (Eh) Memory Write and Invalidate (Fh) Configuration Read (Ah) Configuration Write (Bh) All read or write accesses to PCI 9052 can be byte, word, or Lword accesses. All memory commands are aliased to basic memory commands. All I/O accesses to PCI 9052 are decoded to a Lword boundary. Byte enables are used to determine which bytes are read from or written to. An I/O access with illegal byte enable combinations is terminated with a Target Abort. 2.2 LOCAL BUS CYCLES 2.2.1 Local Bus Slave Not supported. No Direct Master capability. Internal registers are not readable/writable from the local side. The internal registers are accessible from the Host CPU on PCI bus or from serial EEPROM. 2.2.2 Local Bus Master PCI 9052 is master of the local bus. 2.2.2.1 Ready/Wait-State Control If LRDYi# input is disabled, external LRDYi# input has no effect on wait states for a local access. Wait-state counter internally generates wait states between address-to-data, data-to-data, and data-to-address cycles. The wait-state counter is initialized with its configuration register value at the start of each data access. With LRDYi# input enabled, PCI 9052 will not monitor the LRDYi# signal until the wait-state counter reaches 0. The LRDYi# input then controls the number of additional wait states. (Refer to Figure 2-1 and Figure 2-2.) The BIERM# input is not sampled until wait-state counter is 0. PLX Technology, Inc., 1997 Version 1.0SECTION 2 PCI 9052 BUS OPERATION Ons 250ns 500ns I I I | | I | LEK A.D PDD DDD DDS ADS# | YE BLAST# \ Of / LA[27:2] LAD[31:0] WAITO# / \ / WR# \ { \ / LW/R# LRDYi# L/ Lf > rite Strobe Delay Example=1 nwAb Example=2 > Data Transferred <> Write Cycle Hold Example=3 NXDA Example=2 Figure 2-1. PCI 9052 Single Cycle Write Note: Ons I ot LCLK \S\J 100ns I ot 200ns I I ot ot PN SINS NS NSINSINS NS 300ns 400 ADS# BLAST# LS LA[27:2] ADDR LAD[31:0] WAITO# RD# LW/R# \ LRDYi# Reid Strobe Delay Ex: ample= 1 <> NRAD Example-2 Data Transferred > <> NXDA Example=2 Figure 2-2. PCI 9052 Single Cycle Read NWDD is only relevant in a burst cycle, where it determines the wait state between successive data cycles. Note: NADD is only relevant in a burst cycle, where it determines the wait state between successive data cycles. PLX Technology, Inc., 1997 Page 4 Version 1.0SECTION 2 PCI 9052 BUS OPERATION 2.2.2.2 Burst Mode and Continuous Burst Mode (Bterm Burst Terminate Mode) 2.2.2.2.1_ Burst Mode If bursting is enabled and Bterm input not enabled, PCI 9052 bursts as follows: Starts on any boundary and continues up to an address boundary, as described in Table 2-2. After transferring the data at the boundary, PCI 9052 generates a new address cycle (ADS#). Table 2-2. Burst Mode Boundaries 32 Four Lwords or up to a quad Lword boundary (LA3, LA2 = 11) 16 Four words or up to a quad word boundary (LA2, LA1 = 11) 8 Four bytes or up to a quad byte boundary (LA1, LAO = 11) 2.2.2.2.2 Continuous Burst Mode (Bterm Burst Terminate Mode) Bterm mode enables PCI 9052 to perform long bursts to devices that can accept longer than four Lword bursts. PCI 9052 generates one address cycle, then continues to burst data. If a device requires a new address cycle after a certain address boundary, it can assert BTERM# input to cause PCI 9052 to generate a new address cycle. BTERM# input is a ready input that acknowledges the current data transfer and requests that a new address cycle be generated (ADS#), which is the address for next data transfer. Enable Bterm mode and PCI 9052 asserts BLAST# only if FIFOs become FULL or EMPTY, or a transfer is complete. Partial Lwords Accesses. Lword accesses (in which not all byte enables are asserted) break into single address and data cycles. Table 2-3. Partial Lword Accesses Single Cycle (Default) Single Cycle Burst ModeFour Lwords at a time =/-A[olo -~70O/;7-+/]o Continuous Burst ModeBurst until Bterm input is asserted (refer to above descriptions) 2.2.2.3 Recovery States In Nonmultiplexed mode, PCI 9052 uses NXDA (data-to- address wait states) value in the bus region descriptor register to determine how many recovery states to insert between last data transfer and next address cycle. This value can be programmed between zero and three clock cycles. In Multiplexed mode, PCI 9052 inserts a minimum of one recovery state between last data transfer and next address cycle. Add recovery states by programming values greater than one into NXDA bits of the bus region descriptor register. 2.2.2.4 Direct Slave Write Access to 8- and 16-Bit Bus For direct slave writes/reads, only bytes specified by a PCI bus master are written/read. Access to an 8- or 16- bit bus results in the PCI bus Lword being broken into multiple local bus transfers. For each transfer, byte enables are encoded to provide local address bits LA[1:0]. Do not use direct PCI access to an 8-bit bus with nonadjacent byte enables in a PCI Lword. Nonadjacent byte enables cause an_ incorrect LA[1:0] address sequence when bursting to memory. Therefore, for each Lword written to an 8-bit bus, PCI 9052 does not write data after the first gap. Direct PCI accesses to an 8-bit bus with nonadjacent byte enables are not terminated with a Target Abort. Therefore, for nonadjacent bytes (illegal byte enables), the PCI master must perform single cycles. PLX Technology, Inc., 1997 Page 5 Version 1.0SECTION 2 PCI 9052 BUS OPERATION 2.2.2.5 Local Bus Little/Big Endian PCI bus is a Little Endian bus, where data is Lword aligned to lowermost byte lane. Byte 0 (address 0) appears in AD[7:0], Byte 1 appears in AD[15:8], Byte 2 appears in AD[23:16], and Byte 3 appears in AD[81:24]. PCI 9052 local bus can be programmed to operate in Big or Little Endian mode. In Big Endian mode, PCI 9052 transposes data byte lanes. Transfer data as follows: 32 Bit Local Bus. Data is Lword aligned to the uppermost byte lane. Byte lanes and burst orders are listed in Table 2-4 and illustrated in Figure 2-3. Table 2-4. Upper Byte Lane Transfer First transfer Byte 0 appears on Local Data [31:24] Byte 1 appears on Local Data [23:16] 16 Bit Local Bus. For a 16 bit local bus, PCI 9052 can be programmed to use the upper or lower word lane. Byte lanes and burst order are listed in Table 2-5 and Table 2-6 and illustrated in Figure 2-4. Table 2-5. Upper Word Lane Transfer First transfer Byte 0 appears on Local Data [31:24], Byte 1 appears on Local Data [23:16] Second transfer Byte 2 appears on Local Data [31:24], Byte 3 appears on Local Data [23:16] Table 2-6. Lower Word Lane Transfer First transfer Byte 0 appears on Local Data [15:8], Byte 1 appears on Local Data [7:0] Second transfer Byte 2 appears on Local Data [15:8], Byte 3 appears on Local Data [7:0] Little Endian Byte 2 appears on Local Data [15:8] 31 0 Byte 3 appears on Local Data [7:0] BYTE 3 BYTE 2 BYTE 1 BYTEO 31 Little Endian 0 First aK BYTES | BYTE2 | BYTE1 BYTE 0 Second Cycle BYTEO | BYTE1 31 16 15 0 BYTE 0 BYTE 1 Big Endian 31 16 31 15 0 0 Big Endian BYTE 0 BYTE 1 BYTE 2 BYTE 3 Figure 2-4. Big/Little Endian16 Bit Local Bus Big Endian Figure 2-3. Big/Little Endian32 Bit Local Bus PLX Technology, Inc., 1997 Page 6 Version 1.0SECTION 2 PCI 9052 BUS OPERATION 8 Bit Local Bus. For an 8 bit local bus, PCI 9052 can be programmed to use the upper or lower byte lane. Byte lanes and burst order are listed in Table 2-7 and Table 2-8 and illustrated in Figure 2-5. Table 2-7. Upper Byte Lane Transfer First transfer Byte 0 appears on Local Data [31:24] Second transfer Byte 1 appears on Local Data [31:24] Third transfer Byte 2 appears on Local Data [31:24] Fourth transfer Byte 3 appears on Local Data [31:24] Table 2-8. Lower Byte Lane Transfer First transfer Byte 0 appears on Local Data [7:0] Second transfer Byte 1 appears on Local Data [7:0] Third transfer Byte 2 appears on Local Data [7:0] Fourth transfer Byte 3 appears on Local Data [7:0] 31 Little Endian 0 BYTE3 BYTE 2 BYTE 1 BYTE O First Cycle BYTEO Second Cycle BYTEO | 7 0 Third Cycle 31 24 BYTEO |7 0 31 24 BYTEO (7 0 Fourth Cycle Big Endian Figure 2-5. Big/Little Endian8 Bit Local Bus For each of the following transfer types, PCI 9052 local bus can be independently programmed to operate in Little Endian or Big Endian mode: e Direct Slave PCI access to Local Address Space 0 e Direct Slave PCI access to Local Address Space 1 e Direct Slave PCI access to Local Address Space 2 e Direct Slave PCI access to Local Address Space 3 e Direct Slave PCI access to Expansion ROM Space 2.2.2.6 Chip Select x Base Registers PCI 9052 includes the ability to provide Chip Select control signals to four devices on the local bus side of PCI 9052. This eliminates the need to add address decoding circuitry on the adapter card. Without this feature, the user must add address decoding logic for each Chip Select required. This circuitry would then have to monitor the address bus and generate a chip select signal(s). There are four Chip Select x Base registers. These registers control the four chip select pins on PCI 9052, respectively. For example, Chip Select 0 Base Address Register controls CSO# (pin 130), Chip Select 1 Base Address Register controls CS1# (pin 131), and so forth. The Chip Select x Base registers serve three purposes: 1. To enable or disable chip select functions within PCI 9052. If enabled, the Chip Select signal is active if the address on the address line falls within the address specified by the range and base address. If disabled, the Chip Select signal is not active. 2. To set range or length of addresses at which the Chip Select signal(s) are active. 3. To set base address at which the range starts. To program the Chip Select x Base registers, there are three rules that must be followed: 1. Range must be a power of 2. 2. Base address must be a multiple of the range 3. Multiple Chip Select x Base registers, if used, are programmed to not overlap one another. The 28 bit Chip Select x Base register is programmed as listed in Table 2-9. Table 2-9. Chip Select x Base Register Signal Programming MSB=27 LSB=0 XXXX XXXX | XXXKX | XXXKX | XXKXKX | XXXX | XXXY Where the Y bit (bit 0) enables or disables the chip select signal. X bits are used to determine the length and base address of where the CS# pin is asserted. To program the base and length, the X bits are set as follows: Length or range of the device is equal to the first bit set above the Y bit. Determined by setting bit in the register equal to the exponent in the exponential representation of the range. Bit is counted up, starting at the Y bit, where the Y bit is counted as 1. PLX Technology, Inc., 1997 Version 1.0SECTION 2 PCI 9052 BUS OPERATION Base address is determined by the bit or bits set above the range bit. Multiple of the range. Number uses all of the bits in register above the bit set to determine the range. Base Address RangeAddress at which CS# is asserted The ONO ON [| FFFFFFFh Figure 2-6. Chip Select Base Address and Range 2.2.2.6.1 Procedure The following procedure describes how to use the Chip Select x Base registers. 1. Determine the range in hex. Convert this number to a power of two. Range must be a power of two (for example, 2', 2, 2, 2", and so forth.) 2. Set bit in the Chip Select x Base register to determine the range. Use exponent of the range to set bit in the Chip Select x Base register. In a binary representation of the Chip Select x Base register, count left, starting at the Y bit, where Y is one. Only one bit may be set. 3. Determine base address. It is recommended to use hex numbers for the base address. Base address must be a multiple of the range. 4. Determine base address multiplier. Divide range into the base address in hex: (base address)/(range)=(base address multiplier) Convert base address multiplier to binary. Example: Suppose a 16K SRAM device must be attached to the local bus and a chip select must be provided. The base address will be 24000h. The memory map is as follows: 24000h 27FFFh Latent FFFFFFFh 1. Determine the range in hex and convert the number to a power of 2 (for example, 16K is equivalent to 4000h, or 2* bits). 2. Set the bit in the Chip Select x Base register to determine the range. Set the 14" bit to 1. MSB=27 LSB=0 0000 0000 0000 0010 0000 0000 0000 3. Determine the base address (for example, 24000h). Determine the base address multiplier. Divide the range into the base address in hex (for example, 24000h/4000h=9h). 5. Convert the base address multiplier to binary (for example, 1001b). 6. Set the base address multiplier bits directly above the range bit in the Chip Select x Base register. Base Address Range MSB=27 LSB=0 0000 0000 0010 0110 0000 0000 0000 A complete example of setting the Chip Select x Base register with a range of 4000h and a base address of 24000h, and enabled is as follows: Set base address multiplier bits directly above the MSB=27 LSB=0 range bit in the Chip Select x Base register. 0000 coco | o010 | 0110 | 0000 | o000 | 0001 PLX Technology, Inc., 1997 Page 8 Version 1.0SECTION 3 PCI 9052 FUNCTIONAL DESCRIPTION 3. FUNCTIONAL DESCRIPTION 3.1 PCI 9052 INITIALIZATION During power up, PCI RST# signal resets default values of PCI 9052 internal registers. In return, PCI 9052 outputs local reset signal (LRESET#) and checks for existence of the serial EEPROM. If a serial EEPROM is installed, and the first 16-bit word is not FFFF, PCI 9052 loads the internal registers from the serial EEPROM. Otherwise, default values are used. PCI 9052 configuration registers can be written only by the optional serial EEPROM or PCI host processor. During the serial EEPROM initialization, PC] 9052 response to PCI target accesses is RETRYs. 3.2 RESET 3.2.1 PCI Bus Input RST# PCI bus RST# input causes all PCI bus outputs to float, resets entire PCI 9052, and asserts local reset output LRESET#. 3.2.2 Software Reset A host on the PCI bus can set the software reset bit in Miscellaneous Control Register (CNTRL; 50h) to reset PCI 9052 and assert LRESET# output. Contents of the PCI and local configuration registers are not reset. When the software reset bit is set, PCI] 9052 responds only to configuration registers accesses, and not to local bus accesses. PCI 9052 remains in this reset condition until the PCI host clears the software reset bit. 3.2.3 Local Bus Output LRESET# LRESET# is asserted when PCI bus RST# input is asserted (4 to 10 ns delay) or bit 30 (software reset bit) in Miscellaneous Control Register (CNTRL; 50h) is set to 1. 3.3 SERIAL EEPROM After reset, PC] 9052 attempts to read serial EEPROM to determine its presence. An active low start bit indicates serial EEPROM is present. (Refer to manufacturers data sheet for particular serial EEPROM being used.) If the first word in serial EEPROM is not FFFF, then PCI 9052 assumes the device is not blank, and continues reading. Serial EEPROM first stores the most significant bit of each 32-bit word. (The first bit in serial EEPROM is bit 15 of the Device ID.) 25 32-bit words are sequentially stored in the serial EEPROM (such as National NM93CS46 or compatible). Note: 2K bit devices, such as 93CS56, are not compatible. A host on the PCI bus can read or program serial EEPROM. Bits [29:24] of Miscellaneous Control Register (CNTRL: 50h) control PCI 9052 pins, enabling reading or writing of serial EEPROM bits. (Refer to manufacturers data sheet for particular serial EEPROM being used.) To reload serial EEPROM data into PCI 9052 Internal registers, write 1 to bit 29 of register (CNTRL; 50h). To read/write to the serial EEPROM: 1. Enable serial EEPROM CSJ[3:0]# by writing 1 to bit 25 of the register (CNTRL; 50h). 2. Generate serial EEPROM clock by writing 0 and then 1. Data is read or written during the zero-to-one transition (refer to bit 24). Send the command code to serial EEPROM. If serial EEPROM is present, a 0 value is returned as a Start bit after the command code. Read or write data. Write 0 to bit 25 to end serial EEPROM access (serial EEPROM CS[3:0}# pin will go low). Serial EEPROM load sequence, listed in Table 3-1, uses the following abbreviations: MSW = Most Significant Word Bits [31:16] LSW = Least Significant Word Bits [15:0] Note: PCI 9052 does not support serial EEPROMS that do not support sequential read and write (such as 93C 46). PLX Technology, Inc., 1997 Page 9 Version 1.0SECTION 3 PCI 9052 FUNCTIONAL DESCRIPTION 3.3.1 Serial EEPROM Load Sequence Table 3-1. Serial EEPROM Load Sequence Note: Serial EEPROM value shown is the register value used on a demo board. 0 PCI 02 9050 Device ID. 2 PCI 00 10B5 Vendor ID. 4 PCI OA 0680 Class Code. 6 PCI 08 000x Class code (revision is not loadable). 8 PCI 2E 9050 Subsystem ID. A PCI 2C 10B5 Subsystem Vendor ID. c PCI 3E XXXX (Maximum Latency and Minimum Grant are not loadable.) E PCI 3C O1xx Interrupt Pin (Interrupt Line Routing is not loadable). 10 LOCAL 02 OFFE MSW of Range for PCI to Local Address Space 0. 12 LOCAL 00 0000 LSW of Range for PCI to Local Address Space 0. 14 LOCAL 06 OFFE MSW of Range for PCI to Local Address Space 1. 16 LOCAL 04 0000 LSW of Range for PCI to Local Address Space 1. 18 LOCAL 0A OFFF MSW of Range for PCI to Local Address Space 2. 1A LOCAL 08 0000 LSW of Range for PCI to Local Address Space 2. 1c LOCAL OE OFFC MSW of Range for PCI to Local Address Space 3. 1E LOCAL 0C 0000 LSW of Range for PCI to Local Address Space 3. 20 LOCAL 12 0000 MSW of Range for PCI to Local Expansion ROM. 22 LOCAL 10 0000 LSW of Range for PCI to Local Expansion ROM. 24 LOCAL 16 0000 MSW of Local Base Address (Remap) for PCI to Local Address Space 0. 26 LOCAL 14 0001 LSW of Local Base Address (Remap) for PCI to Local Address Space 0. 28 LOCAL 1A 0002 MSW of Local Base Address (Remap) for PCI to Local Address Space 1. 2A LOCAL 18 0001 LSW of Local Base Address (Remap) for PCI to Local Address Space 1. 2c LOCAL 1E 0004 MSW of Local Base Address (Remap) for PCI to Local Address Space 2. 2E LOCAL 1C 0001 LSW of Local Base Address (Remap) for PCI to Local Address Space 2. 30 LOCAL 22 0008 MSW of Local Base Address (Remap) for PCI to Local Address Space 3. 32 LOCAL 20 0001 LSW of Local Base Address (Remap) for PCI to Local Address Space 3. 34 LOCAL 26 0010 MSW of Local Base Address (Remap) for PCI to Local Expansion ROM. 36 LOCAL 24 0000 LSW of Local Base Address (Remap) for PCI to Local Expansion ROM. PLX Technology, Inc., 1997 Page 10 Version 1.0SECTION 3 PCI 9052 FUNCTIONAL DESCRIPTION Table 3-1. Serial EEPROM Load Sequence (continued) 38 LOCAL 2A 0080 MSW of Bus Region Descriptors for Local Address Space 0. 3A LOCAL 28 0026 LSW of Bus Region Descriptors for Local Address Space 0. 3C LOCAL 2E 0080 MSW of Bus Region Descriptors for Local Address Space 1. 3E LOCAL 2C 003F LSW of Bus Region Descriptors for Local Address Space 1. 40 LOCAL 32 0040 MSW of Bus Region Descriptors for Local Address Space 2. 42 LOCAL 30 0037 LSW of Bus Region Descriptors for Local Address Space 2. 44 LOCAL 36 5421 MSW of Bus Region Descriptors for Local Address Space 3. 46 LOCAL 34 38E9 LSW of Bus Region Descriptors for Local Address Space 3. 48 LOCAL 3A 0000 MSW of Bus Region Descriptors for Expansion ROM Space. 4A LOCAL 38 0000 LSW of Bus Region Descriptors for Expansion ROM Space. 4c LOCAL 3E 0004 MSW of Chip Select (CS) 0 Base and Range Register. 4E LOCAL 3C 0001 LSW of Chip Select (CS) 0 Base and Range Register. 50 LOCAL 42 OO0A MSW of Chip Select (CS) 1 Base and Range Register. 52 LOCAL 40 0001 LSW of Chip Select (CS) 1 Base and Range Register. 54 LOCAL 46 0000 MSW of Chip Select (CS) 2 Base and Range Register. 56 LOCAL 44 0000 LSW of Chip Select (CS) 2 Base and Range Register. 58 LOCAL 4A 0004 MSW of Chip Select (CS) 3 Base and Range Register. 5A LOCAL 48 8001 LSW of Chip Select (CS) 3 Base and Range Register. 5C LOCAL 4E 0000 MSW of Interrupt Control/Status Register. 5E LOCAL 4C 0000 LSW of Interrupt Control/Status Register. 60 LOCAL 52 0005 MSW of serial EEPROM Control and Miscellaneous Control Register. 62 LOCAL 50 4291 LSW of serial EEPROM Control and Miscellaneous Control Register. Vendor ID and Subsystem Device ID are at offset 2Ch of 3.4 INTERNAL REGISTER ACCESS the PCI configuration Registers. Device ID and Vendor PCI 9052 chip provides several internal registers, allowing maximum flexibility in bus interface design and performance. Register types are as follows: e PCl registers (accessible from the PCI bus and serial EEPROM) Local configuration registers (accessible from the PCI bus and serial EEPROM) Note: Local Configuration Base Address Register access can be limited to memory mapped or W/O mapped. Access can also be disabled by way of bits [13:12] of the register at (CNTRL; 50h). 3.4.1 Internal Registers Device and Vendor ID. There are two sets of device and vendor IDs. Device and Vendor ID are located at offset 0 of the PCI Configuration Registers. Subsystem ID identify the particular device, and manufacturer of device. Subsystem Vendor ID and Subsystem ID provide a way to distinguish between vendors of the PCI interface chip and manufacturer of add-in board using the PCI chip. Status Register. Contains information of PCI bus- related events. Command Register. Controls the ability of a device to respond to PCI accesses. It controls whether the device responds to I/O space or memory space accesses. Class Code Register. Identifies the general function of the device. Refer to the PCI Specification for further details. Revision ID Register. Value read from this register represents current silicon revision of PCI 9052. PLX Technology, Inc., 1997 Page 11 Version 1.0SECTION 3 PCI 9052 FUNCTIONAL DESCRIPTION Header Type. Defines the format of device configuration header and whether the device is single-function or multifunction. Cache Line Size. Defines system cache line size in units of 32-bit words. PCI Base Address Register for Memory Accesses to Local Configuration Registers. System BIOS uses this register to assign a segment of the PCI address space for memory accesses to PCI 9052 Local Configuration Registers. PCI address range occupied by these configuration registers fixes at 128 bytes. During initialization, host writes FFFFFFFF to this register, then reads back FFFFFF/0, determining the required memory space of 128 bytes. Host then writes the base address to bits [31:7]. PCI Base Address Register for I/O Accesses to Local Configuration Registers. System BIOS uses. this register to assign a segment of the PCI address space for YO accesses to PCI 9052 Local Configuration Registers. PCI address range occupied by these configuration registers fixes at 128 bytes. During initialization, host writes FFFFFFFF to this register, then reads back FFFFFF/1, determining a required 128 bytes of I/O space. Host then writes the base address to bits [31:7]. PCI Base Address Regisiter for Accesses to Local Address Space 0 (also true for Space 1, 2, and 3). System BIOS uses this register to assign a segment of the PCI address space for accesses to Local Address Space 0. PCI address range occupied by this space is determined by Local Address Space 0 Range Register. During initialization, host writes FFFFFFFF to this register, then reads back a value determined by the range. Host then writes the base address to the upper bits of this register. PCI Expansion ROM Base Address Register. System BIOS uses this register to assign a segment of the PCI address space for accesses to the Expansion ROM. PCI address range occupied by this space is determined by Expansion ROM Range Register. During initialization, host writes FFFFFFFF to this register, then reads back a value determined by the range. Host then writes the base address to upper bits of this register. Address decoding for expansion ROM can be enabled through the serial EEPROM by writing 1 to (EROMRR; 10h), bit 0. PCI Interrupt Line Register. Identifies where the interrupt line of the device connects on_ interrupt controller(s) of system. PCI Interrupt Pin Register. Specifies the interrupt request pin (if any) to be used. 3.4.2 PCI Bus Access to Internal Registers PCI 9052 configuration registers are accessed from the PCI bus by way of a configuration type 0 cycle. PCI 9052 local configuration registers are accessed by one of the following: Amemory cycle, with the PCI bus address matching the base address specified in PCI Base Address Register for Memory Accesses to Local Configuration Registers (PCIBARO; 10h) e Anl/O cycle, with the PCI bus address matching the base address specified in PC] Base Address Register for I/O Accesses to Local Configuration Registers (PCIBAR1; 14h) All PCI read or write accesses to PCI 9052 registers can be byte, word, or Lword accesses. Memory accesses to PCI 9052 registers can be burst or non-burst. PCI 9052 responds with a PCI Disconnect for all I/O accesses to PCI 9052 registers. 3.5 DIRECT DATA TRANSFER MODES PCI host processor can directly access devices on the local bus for reads and writes. Configuration registers within PCI 9052 control decoding and remapping of these accesses to Local Address Space. Read and write FIFOs enable high-performance bursting on local and PCI buses. 3.5.1 Direct Slave Operation (PCI Master to Local Bus Access) PCI 9052 supports memory mapped burst transfer accesses and I/O mapped single transfer accesses to the local bus from PCI bus. PCI Base Address registers are provided to determine adapter location in PCI memory and I/O space. In addition, local mapping registers are provided to allow address translation from the PCI address space to Local Address Space. PCI 9052 disconnects after one transfer for all Direct Slave I/O accesses. For single cycle Direct Slave reads, PCI 9052 reads a single local bus Lword. For Direct Slave memory accesses, burst read pre-fetching is enabled or disabled through Local Address Space Bus Region Descriptor Registers. If read prefetching is disabled, PCI 9052 disconnects after one read transfer. If prefetching is enabled, read prefetch size can be programmed through Local Address Space Bus Region Descriptor Registers. PLX Technology, Inc., 1997 Version 1.0SECTION 3 PCI 9052 PCI 9052 can be programmed though the Miscellaneous Control Register (CNTRL; 50h) to perform delayed reads, as specified in PCI Specification v2.1. 3.5.1.1 PCI 2.1 Mode PCI 9052 can be programmed through the Local Arbitration and PCI Mode Register to perform delayed reads, as specified in PCI specification v2.1. PCI Bus Local Bus PCI Read request Cc Spec v2.1 mode set in PCI 9052 tells Internal Registers host to retry read cycle later PCI 9052 requests read data from PCI Bus is free to Data-is stored Local Bus perform other in. 16 Lword cycles during Internal FIFO. Local memory this time returns requested data to PCI 9052 PCI host returns to c> fetch read data again PCI 9052 returns prefetched data Read data is now immediately ready for host Figure 3-1. PCI Specification v2.1 Delayed Reads In addition to delayed read, PCI 9052 supports the following in PCI specification v2.1 features. No write while read is pending (RETRY for reads) Write and flush pending read PCI 9052 also supports Read Ahead mode (refer to Figure 3-2), where prefetched data can be read from the PCI 9052 internal FIFO instead of from the local side. The address must be subsequent to the previous address and must be 32-bit aligned (next address = current address + 4). FUNCTIONAL DESCRIPTION PCI Bus Local Bus PCI 9052 Read Ahead mode PCI 9052 prefetches data from Local Bus is set via device internal register => PCI read request Read data PCI master read Prefetched data returns with is stored:in Sequential Address internal FIFO PCI 9052 prefetches more data if FIFO PCI 9052 returns space is available 7 prefetched data > immediately fram Read data internal FIFO ~ without reading again from local side PCI 9052 prefetches more data from local memory Figure 3-2. PCI 9052 Read Ahead Mode PCI 9052 can be programmed to keep the PCI bus by generating a wait state(s), de-asserting TRDY#, if write FIFO becomes full. (Refer to Figure 3-3 and Figure 3-4.) Master Slave Master Slave ZN FRAME#, C/BE#, Z~ AD (addr) IRDY#, AD (data) | DEVSEL#, TRDY# na 2 a a 5 PCl 3 o 3 9052 = LA, ADS#, LW/R#. WR# LD, BLAST#, : LRDYi# VY VY Figure 3-3. Direct Slave Write For direct slave writes, the PCI (Master) writes data to the local bus (slave). PLX Technology, Inc., 1997 Version 1.0SECTION 3 PCI 9052 FUNCTIONAL DESCRIPTION Master Slave Master Slave e LBE1# Address bit 1= (LA1) Zn FRAME#, C/BE#, ZN e LBEO# Byte Low Enable (BLE#) = LAD[7:0] AD (addr) = 8-bit bus. LBE[1:0]# are encoded to provide LA[1:0]: IRDY# e LBE3# Unused DEVSEL# Q S e LBE2# Unused a a 5 PCI B e LBE1# Address bit 1 = (LA1) a oO 9052 = LBEO# Address bit 0 = (LAO) LA, ADS#, LW/R#, WR#, BLAST# TRDY#, AD (data) oa Each PCI to Local Address space is defined as part of the reset initialization: WV VY Figure 3-4. Direct Slave Read For direct slave reads, the PCI (Master) reads data from the local bus (Slave). PCI 9052 supports on-the-fly Endian conversion for Space 0, Space 1, and expansion ROM space. The local bus can be Big/Little Endian by the programmable internal register configuration. Note: PCI bus is always Little Endian. 3.5.1.2 PCI to Local Address Mapping Five Local Address Spaces (local spaces 0-3 and expansion ROM) are accessible from the PCI bus. A set of four registers defines each space, defining the local bus characteristics: e PCI Base Address e Local Range e Local Base Address (Remap) e Local Bus Region Descriptor Byte Enables (LBE[3:0]#, pins 46-49) are encoded based upon configured bus width: 32-bit bus. Four byte enables indicate which of the four bytes are active during a data cycle: e LBE3# Byte Enable 3 = LAD[31:24] e LBE2# Byte Enable 2 = LAD[23:16] e LBE1# Byte Enable 1 = LAD[15:8] e LBEO# Byte Enable 0 = LAD[7:0] 16-bit bus. LBE[3,1:0]# are encoded to provide BHE#, LA1, and BLE#: e LBE3# Byte High Enable (BHE#) = LAD[15:8] e LBE2# Unused Local bus initialization software. Range specifies which PCI address bits to use to decode a PCI access to local bus space. Each of the bits correspond to an address bit, with bit 31 corresponding to address bit 31. Write 1 to all bits to be included in the decoding. Write 0 to all bits to be ignored. Remap PCI address into a local address. Bits in this register remap (replace) the PCI address bits used in decoding into the local address bits. Local Bus Region Descriptor specifies the local bus characteristics, such as bus width, bursting, prefetching, and number of wait states. PCI Initialization Software. PCI host bus-initialization software determines the required address space by writing a value of all ones (1) to a PCI Base Address register and then reading back the value. PCI 9052 returns zeros (0) in don't care address bits, specifying the required address space. PCI software then maps Local Address space into the PCI Address space by programming PCI Base Address register. Example: A 1 MB Local Address Space 02300000h through 023FFFFFh is accessible from the PCI bus at PCI addresses 78900000h through 789FFFFFh. 1. From serial EEPROM sets the Range and Local Base address registers as follows: e Range = FFFOQOOOOh (1 MB, decode the upper 12 PCI address bits) e Local Base Address (remap) = 023XXXXxXh (Local Base Address for PCI to local accesses) 2. PCI Initialization software writes all ones (1) to the PCI Base Address, then reads back the value. PCI 9052 returns a value FFFOOOOOh. PCI software then writes to PCI Base Address register: e PCI Base Address = 789XXXXXh (PCI Base Address for access to Local Address space) PLX Technology, Inc., 1997 Version 1.0SECTION 3 PCI 9052 For PCI accesses to the local bus, PCI 9052 has a 16 Lword (64 byte) write FIFO and an eight Lword (32 byte) read FIFO. FIFO enables the local bus to operate independently of the PCI bus. PCI 9052 can be programmed to return a RETRY response or to throttle TRDY# for PCI bus transactions attempting to write to PCI 9052 local bus when write FIFO is full. For PCI read transactions from PCI 9052 local bus, PCI 9052 holds off TRDY# while gathering the local bus Lword to be returned. For read accesses mapped to the PCI memory space, PCI 9052 prefetches up to four Lwords from the local bus. Unused read data is flushed from FIFO. For read accesses mapped to the PCI I/O FUNCTIONAL DESCRIPTION space, PCI 9052 does not prefetch read data. It breaks each read of the burst cycle into a single address/data cycle on the local bus. The period of time that PCI 9052 holds off TRDY# is programmed in the Miscellaneous Control Register (CNTRL; 50h). PCI 9052 issues a RETRY to the PCI bus master when programmed time period expires. This happens when PCI 9052 cannot get the data from the local bus and return TRDY# within the programmed time period. PCI Bus Serial Master EEPROM 1 _---- Initialize Local 2 Configuration Registers Initialize PCI =, | Range for PCI to Local Address Space 0, 1, 2, and 3 <_ g Base Address Local Base Address (Remap) for PCI to Local Address Space 0, 1,2, and3 ~ | Bus Region Descriptors for PCI to Local Accesses < | Range for PCI to Local Expansion ROM < | Local Base Address (Remap) for PCI to Local Expansion ROM | | Bus Region Descriptors for PCI to Local Accesses <_ Local Bus ne Hardware Characteristics Lad PCI Base Address to Local Address Space 0, 1, 2, or 3 | >| PCI Base Address to Local Expansion ROM | 3 4 PCI Bus ------- . eocscccn- Local Bus Access _> Fl FOs <___> Access 64 Byte Deep Write 32 Byte Deep Read PCI Address / Space PCI Base ___ Address Local Memory Local Base Address Figure 3-5. PCI Master Direct Access of Local Bus oN PLX Technology, Inc., 1997 Page 15 Version 1.0SECTION 3 PCI 9052 FUNCTIONAL DESCRIPTION 3.5.1.3 Direct Slave Lock PCI 9052 supports direct PCI to local bus exclusive accesses (locked atomic operations). A PCI locked operation to local bus results in the entire address space 0-3 and expansion ROM space being locked until PCI bus master releases the spaces. PCI 9052 asserts LLOCKo# during the first clock of an atomic operation (address cycle) and negates it a minimum of one clock following the last bus access for atomic operation. LLOCKo# is negated after PCI 9052 detects PCI FRAME#, with PC| LOCK# negated at the same time. (Refer to Section 9, Timing Diagrams.) Miscellaneous Control Register (CNTRL; 50h) enables locked operations. It is the responsibility of external arbitration logic to monitor LLOCKo# pin and enforce the meaning for an atomic operation. For example, if a local master initiates a locked operation, the local arbiter may choose to not grant use of the local bus to other masters until locked operation is complete. 3.5.1.4 Arbitration When the PCI bus detects a new transfer request, PCI 9052 takes control of the local bus. Another device can gain control of the local bus by asserting LHOLD. If PCI 9052 has no cycles to run, it asserts LHOLDA, transferring control to the external master. If PCI 9052 needs the local bus before the external master has finished, LHOLDA is negated (preempt condition). The arbiter waits for LHOLD to be negated before taking control of the bus. 3.6 PCI INTERRUPTS (INTA#) You can generate a PCI interrupt (INTA#) with local interrupt inputs LINTi1 and LINTi2, and the software interrupt (CNTRL register bit 30). Through PCI 9052 Interrupt Control/Status Register, individual sources of an interrupt can be enabled or disabled. Interrupt Control/Status Register also provides interrupt status for each source of the interrupt. PCI 9052 PCI bus interrupt is an asynchronous level output. Clear an interrupt by disabling an interrupt enable bit of a source or by clearing the cause of an interrupt. 3.7 LOCAL INTERRUPT (LINTI[2:1]) PCI 9052 provides two local interrupts (LINTi[2:1]). The local interrupts can be used to generate PCI interrupt. LINTi[2:1] supports edge or level trigger, programmable through register (INTCSR; 4Ch). 3.8 PCI SERR# (PCI NMI) PCI 9052 generates a SERR# pulse if parity checking is enabled in the PCI Command Register and an address parity error is detected. Through the PCI Command Register, SERR# output is enabled. PLX Technology, Inc., 1997 Page 16 Version 1.0SECTION 4 PCI 9052 4. ISA INTERFACE MODE 4.1 ARCHITECTURE A major architectural feature of PCI 9052 is the inclusion of a glueless ISA logic interface. This provides for a smooth ISA to PCI conversion. It supports 8- and 16-bit wide ISA devices that can be memory or I/O mapped. Read Ahead mode can be used to improve read data throughput. PCI 9052 performs only single cycles once ISA interface mode is enabled. Note: Serial EEPROM is required to enable ISA Interface mode. 4.2 CONFIGURATION METHODS Use one of the following methods to configure PCI 9052 for ISA interface mode. Table 4-1. Serial EEPROM Load Sequence PCI 02 Device ID. PCI 00 Vendor ID. PCI OA Class Code. PCI 2E Subsystem ID. PCI 2C Subsystem Vendor ID. 0 2 4 6 8 A c E afafiufif/ifif.i OQ} rPlaloal;Al[ myo PCI 08 Class code (revision is not loadable). ISA INTERFACE MODE Preprogram serial EEPROM method Using the pre-programmer, program the serial EEPROM. Refer to Table 4-1 for appropriate values. Note: LRESET# pin is always an active high signal for ISA mode. Ensure PC! 9052 mode-pin is set to 0. On-the-fly method From the PCI bus, program the serial EEPROM through PCI 9052 using the same values as indicated in the preprogramming method. Notes: LRESET# pin changes its polarity from active low to active high in ISA mode. Ensure PCI 9052 mode pin is set to 0. While in ISA mode, Local Space 2, 3, and Expansion ROM can be configured to operate in Non-multiplexed mode. PCI 3E (Maximum Latency and Minimum Grant are not loadable.) PCI 3C Interrupt Pin (Interrupt Line Routing is not loadable). LOCAL 02 MSW of Range for PCI to Local Address Space 0. LOCAL 00 LSW of Range for PCI to Local Address Space 0. Bit 0 must be 0 for memory mapped. LOCAL 06 MSW of Range for PCI to Local Address Space 1. LOCAL 04 _ LSW of Range for PCI to Local Address Space 1. Bit O must be 1 for I/O mapped. LOCAL 0A _ MSW of Range for PCI to Local Address Space 2. LOCAL 08 XXXX LSW of Range for PCI to Local Address Space 2. LOCAL OE XXXX MSW of Range for PCI to Local Address Space 3. 1E LOCAL 0C XXXX LSW of Range for PCI to Local Address Space 3. Notes: Serial EEPROM value shown is the register value used on a demo board. Serial EEPROM value of X represents dont care. PLX Technology, Inc., 1997 Version 1.0SECTION 4 PCI 9052 ISA INTERFACE MODE Table 4-1. Serial EEPROM Load Sequence (continued) 20 LOCAL 12 XXXX MSW of Range for PCI to Local Expansion ROM. 22 LOCAL 10 XXXX LSW of Range for PCI to Local Expansion ROM. 24 LOCAL 16 _ MSW of Local Base Address (Remap) for PCI to Local Address Space 0. 26 LOCAL 14 _ LSW of Local Base Address (Remap) for PCI to Local Address Space 0. 28 LOCAL 1A _ MSW of Local Base Address (Remap) for PCI to Local Address Space 1. 2A LOCAL 18 _ LSW of Local Base Address (Remap) for PCI to Local Address Space 1. 2c LOCAL 1E XXXX MSW of Local Base Address (Remap) for PCI to Local Address Space 2. 2E LOCAL 1C XXXX LSW of Local Base Address (Remap) for PCI to Local Address Space 2. 30 LOCAL 22 XXXX MSW of Local Base Address (Remap) for PCI to Local Address Space 3. 32 LOCAL 20 XXXX LSW of Local Base Address (Remap) for PCI to Local Address Space 3. 34 LOCAL 26 XXXX MSW of Local Base Address (Remap) for PCI to Local Expansion ROM. 36 LOCAL 24 XXXX LSW of Local Base Address (Remap) for PCI to Local Expansion ROM. 38 LOCAL 2A _ MSW of Bus Region Descriptors for Local Address Space 0. Refer to Table 4-2. 3A LOCAL 28 _ LSW of Bus Region Descriptors for Local Address Space 0. Refer to Table 4-2. 3C LOCAL 2E _ MSW of Bus Region Descriptors for Local Address Space 1. Refer to Table 4-2. 3E LOCAL 2C _ LSW of Bus Region Descriptors for Local Address Space 1. Refer to Table 4-2. 40 LOCAL 32 XXXX MSW of Bus Region Descriptors for Local Address Space 2. 42 LOCAL 30 XXXX LSW of Bus Region Descriptors for Local Address Space 2. 44 LOCAL 36 XXXX MSW of Bus Region Descriptors for Local Address Space 3. 46 LOCAL 34 XXXX LSW of Bus Region Descriptors for Local Address Space 3. 48 LOCAL 3A XXXX MSW of Bus Region Descriptors for Expansion ROM Space. 4A LOCAL 38 XXXX LSW of Bus Region Descriptors for Expansion ROM Space. 4c LOCAL 3E _ MSW of Chip Select (CS) 0 Base and Range Register. Base address must match Local Space 0 remap address. 4E LOCAL 3C _ LSW of Chip Select (CS) 0 Base and Range Register. Base address must match Local Space 0 remap address. 50 LOCAL 42 _ MSW of Chip Select (CS) 1 Base and Range Register. Base address must match Local Space 1 remap address. 52 LOCAL 40 _ LSW of Chip Select (CS) 1 Base and Range Register. Base address must match Local Space 1 remap address. 54 LOCAL 46 XXXX MSW of Chip Select (CS) 2 Base and Range Register. 56 LOCAL 44 XXXX LSW of Chip Select (CS) 2 Base and Range Register. 58 LOCAL 4A XXXX MSW of Chip Select (CS) 3 Base and Range Register. 5A LOCAL 48 XXXX LSW of Chip Select (CS) 3 Base and Range Register. 5C LOCAL 4E _ MSW of Interrupt Control/Status Register. Refer to Table 4-3. SE LOCAL 4C _ LSW of Interrupt Control/Status Register. Refer to Table 4-3. 60 LOCAL 52 _ MSW of Serial EEPROM Control and Miscellaneous Control Register. Refer to Table 4-4. 62 LOCAL 50 _ LSW of Serial EEPROM Control and Miscellaneous Control Register. Refer to Table 4-4. Notes: Serial EEPROM value shown is the register value used on a demo board. Serial EEPROM value of X represents dont care. PLX Technology, Inc., 1997 Page 18 Version 1.0SECTION 4 PCI 9052 ISA INTERFACE MODE 4.3 CONFIGURATION NOTES Be aware of the following when configuring for ISA interface mode: PCI 9052 pin defaults have not changed for regular Direct Slave accesses. When NC is indicated, this represents a true No Connect. To access ISA interface pins, refer to PCI 9052 Data Sheet Pin Out (C/SA Mode) diagram (refer to Section 8.3, PCI 9052 Pin Out). Space 0 is assigned to memory accesses for ISA interface. Space 1 interface. is assigned to I/O accesses for ISA ISA accesses are active whenever a local address of Space 0 is in the range of CSO#, and a local address of Space 1 is in the range CS1#. Standard Slave cycles could be accessed using Space 2, Space 3, and serial EEPROM. 4.4 CONFIGURING LOCAL REGISTERS FOR ISA MODE Be aware of the following when configuring local registers for ISA interface mode: Serial EEPROM presence must be detected on board for PCI 9052 to operate in ISA interface mode. MODE pin must be set to 0, non-multiplexed bus. LASORR and LAS1RR registers must be set. Refer to Table 5-26 and Table 5-27. Note: Bit 0 should be set to 0 in LASORR and to 1 in LAS1RAR registers to indicate memory mapping for Space 0, and I/O mapping for Space 1 on the PCI Bus. LASOBA and LAS1BA registers should be set. Refer to Table 5-31 and Table 5-32. LASOBRD and LAS1BRD registers should be set as listed in Table 4-2. CSOBASE and CS1BASE must be set accordingly to the local address of Space O and Space 1. Otherwise, the ISA interface is never acknowledged. Refer to Table 5-41 and Table 5-42. Set INTCSR registers as listed in Table 4-3. Set CNTRL register as listed in Table 4-4. PLX Technology, Inc., 1997 Page 19 Version 1.0SECTION 4 PCI 9052 ISA INTERFACE MODE Table 4-2. LASOBRD and LAS1BRD Register Settings 0 Burst is disabled on local bus. 0 1 Ready is enabled. Internal to PCI 9052. 1 2 BTERM# feature is not used. x 4:3 Prefetch on local bus is disabled. XX 5 Prefetch is disabled. 0 10:6 Refer to the (LASOBRD; 28h) Local Address Space 0 Bus Region _ Descriptor Register, Table 5-36, and the (_LAS2BRD; 30h) Local Address Space 2 Bus Region Descriptor Register, Table 5-38. 12:11 No Data-to-Data Wait States. 00 19:13 Refer to registers 28h and 30h. _ 21:20 No Data-to-Data Wait States. _ 23:22 h2 is prohibited from use. 0/1 25:24 Refer to the (LASOBRD; 28h) Local Address Space 0 Bus Region _ Descriptor Register, Table 5-36, and the (_LAS2BRD; 30h) Local Address Space 2 Bus Region Descriptor Register, Table 5-38. 27:26 Read strobe is not used. XX 29:28 Write strobe is not used. XX 31:30 Write strobe feature is not used. XX Table 4-3. INTCSR Register Settings 9:0 Refer to the (INTCSR; 4Ch) Interrupt Control/Status Register, Table _ 5-45. 12 ISA_MODE feature enabled. Must be 1. 1 Table 4-4. CNTRL Register Settings Pin 138 is programmed to USER I/O. Pin 138 is programmed to be an output. USER I/O feature is disabled with ISA_MODE bit. Pin 139 is programmed to USER I/O. Pin 139 is programmed to be an output. USER I/O feature is disabled with ISA_MODE bit. Refer to the (CNTRL; 50h) User I/O, PCI Target Response, Serial EEPROM, Initialization Control Register, Table 5-46. Notes: Serial EEPROM value of xX represents dont care. PLX Technology, Inc., 1997 Page 20 Version 1.0SECTION 5 PCI 9052 REGISTERS 5. REGISTERS 5.1 REGISTER ADDRESS MAPPING Table 5-1. PCI Configuration Registers Y N Y[31:8] N Device ID Vendor ID Status Command Class Code Revision ID BIST Header Type PCI Latency Timer Cache Line Size 2 PCI Base Address 0 for Memory Mapped Configuration Registers PCI Base Address 1 for I/O Mapped Configuration Registers PCI Base Address 2 for Local Address Space 0 PCI Base Address 3 for Local Address Space 1 PCI Base Address 4 for Local Address Space 2 PCI Base Address 5 for Local Address Space 3 Cardbus CIS Pointer (Not Supported) Subsystem ID Subsystem Vendor ID PCI Base Address for Local Expansion ROM Reserved z|<|z|z|<|<|<||<|<|N]z|/<|z ZiZ2)/<~)/2)/2)/2;/2;/2/2 Zz Zz Reserved Max_Lat Min_Gnt Interrupt Pin Interrupt Line Y[7:0] Y[15:8] PLX Technology, Inc., 1997 Page 21 Version 1.0SECTION 5 PCI 9052 REGISTERS 5.1.1 Local Configuration Registers Table 5-2. Local Configuration Registers Local Address Space 0 Range Local Address Space 1Range Local Address Space 2 Range Local Address Space 3 Range Local Expansion ROM Range Local Address Space 0 Local Base Address (Remap) Local Address Space 1 Local Base Address (Remap) Local Address Space 2 Local Base Address (Remap) Local Address Space 3 Local Base Address (Remap) Expansion ROM Local Base Address (Remap) Local Address Space 0 Bus Region Descriptors Local Address Space 1 Bus Region Descriptors Local Address Space 2 Bus Region Descriptors Local Address Space 3 Bus Region Descriptors Expansion ROM Bus Region Descriptors Chip Select 0 Base Address Chip Select 1 Base Address Chip Select 2 Base Address Chip Select 3 Base Address Interrupt Control/Status Serial EEPROM Control, PCI Slave Response, User I/O Control, Init Control Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y PLX Technology, Inc., 1997 Page 22 Version 1.0SECTION 5 PCI 9052 REGISTERS 5.2 PCI CONFIGURATION REGISTERS All registers may be written to or read from byte, word, or Lword accesses. 5.2.1 (PCIIDR; 00h) PCI Configuration ID Register Table 5-3. (PCIIDR; 00h) PCI Configuration ID Register Description 15:0 | Vendor ID. Identifies manufacturer of the device. Defaults to PCI SIG issued Vendor ID Yes Serial 10B5h of PLX if no serial EEPROM is present. EEPROM 31:16 | Device ID. Identifies particular device. Defaults to PLX part number for the PCI interface Yes Serial 9050 chip if no serial EEPROM is present. EEPROM 5.2.2 (PCICR; 04h) PCI Command Register Table 5-4. (PCICR; 04h) PCI Command Register Description 0 \/O Space. Value of 1 allows device to respond to I/O space accesses. Value of 0 Yes Yes 0 disables device from responding to I/O space accesses. 1 Memory Space. Value of 1 allows device to respond to memory space accesses. Value Yes Yes 0 of 0 disables device from responding to memory space accesses. 2 Master Enable. Value of 1 allows device to function as a bus master. Value of 0 Yes No 0 disables device from generating bus master accesses. 3 Special Cycle. Not Supported. Yes No 0 4 Memory Write/Invalidate. Not Supported. Yes No 0 5 VGA Palette Snoop. Not Supported. Yes No 0 6 Parity Error Response. Value of 0 indicates a parity error is ignored and operation Yes Yes 0 continues. Value of 1 indicates parity checking is enabled. 7 Wait Cycle Control. Controls whether the device does address/data stepping. Value of 0 Yes No 0 indicates device never does stepping. Value of 1 indicates device always does stepping. Note: Hardcoded to 0. SERR# Enable. Value of 1 enables SERR# driver. Value of 0 disables SERR# driver. Yes Yes Fast Back-to-Back Enable. Indicates what type of fast back-to-back transfers a Master Yes No 0 can perform on the bus. Value of 1 indicates fast back-to-back transfers can occur to any agent on the bus. Value of 0 indicates fast back-to-back transfers can only occur to the same agent as the previous cycle. 15:10 | Reserved. Yes No 0 PLX Technology, Inc., 1997 Page 23 Version 1.0SECTION 5 PCI 9052 REGISTERS 5.2.3 (PCISR; 06h) PCI Status Register Table 5-5. (PCISR; 06h) PCI Status Register Description 6:0 Reserved. Yes No 0 7 Fast Back-to-Back Capable. Value of 1 indicates adapter can accept fast back-to-back Yes No th transactions. Value of 0 indicates adapter cannot accept fast back-to-back transactions. 8 Master Data Parity Error Detected. Not Supported. Yes No 0 10:9 DEVSEL Timing. Indicates timing for DEVSEL# assertion. Value of 01 is medium. Yes No 01 11 Target Abort. Value of 1 indicates PCI 9052 has signaled a target abort. Writing a Yes Yes 0 value of 1 clears bit (0). 12 Received Target Abort. Value of 1 indicates PCI 9052 has received a target abort Yes No 0 signal. Not Supported. 13 Received Master Abort. Value of 1 indicates PCI 9052 has received a master abort Yes No 0 signal. Not supported 14 Signaled System Error. Value of 1 indicates PCI 9052 has reported a system error on Yes Yes 0 SERR# signal. Writing a value of 1 clears error status bit (0). 15 Detected Parity Error. Value of 1 indicates PCI 9052 has detected a PCI bus parity Yes Yes 0 error, even if parity error handling is disabled (Parity Error Response bit in the Command Register is clear). To cause a bit to be set, one of these two conditions must exist: 1) PCI 9052 detected a parity error during a PCI address phase; or, 2) PCI 9052 detected a data parity error when it was the target of a write. Writing a value of 1 clears bit (0). 5.2.4 (PCIREV; 08h) PCI Revision ID Register Table 5-6. (PCIREV; 08h) PCI Revision ID Register Description Revision ID. The silicon revision of PCI 9052. Current Revision Note: Hardcoded to 9050. 5.2.5 (PCICCR; 09-OBh) PCI Class Code Register Table 5-7. (PCICCR; 09-OBh) PCI Class Code Register Description 7:0 Specific Register Level Programming Interface (00h). No interface defined. Yes Serial 00 EEPROM 15:8 Subclass Encoding (80h). Other bridge device. Yes Serial 80h EEPROM 23:16 Base Class Encoding. Other bridge Device. Yes Serial 06h EEPROM PLX Technology, Inc., 1997 Page 24 Version 1.0SECTION 5 PCI 9052 REGISTERS 5.2.6 (PCICLSR; 0Ch) PCI Cache Line Size Register Table 5-8. (PCICLSR; O0Ch) PCI Cache Line Size Register Description 7:0 System Cache Line Size (in units of 32-bit words). Can be written and read; however, Yes Yes 0 the value has no effect on operation of chip. 5.2.7 (PCILTR; ODh) PCI Latency Timer Register Table 5-9. (PCILTR; ODh) PCI Latency Timer Register Description 7:0 PCI Latency Timer. Not Supported. Yes No 0 5.2.8 (PCIHTR; OEh) PCI Header Type Register Table 5-10. (PCIHTR; OEh) PCI Header Type Register Description 6:0 Configuration Layout Type. Specifies layout of bits 10h through 3Fh in configuration Yes No 0 space. Only one encoding 0 is defined. All other encodings are reserved. 7 Header Type. Value of 1 indicates multiple functions. Value of 0 indicates a single Yes No 0 function. 5.2.9 (PCIBISTR; OFh) PCI Built-In Self Test (BIST) Register Table 5-11. (PCIBISTR; OFh) PCI Built-In Self Test (BIST) Register Description Built-In Self Test. Value of 0 indicates device has passed its test. Not Supported. Yes No 0 PLX Technology, Inc., 1997 Page 25 Version 1.0SECTION 5 PCI 9052 REGISTERS 5.2.10 (PCIBARO; 10h) PCI Base Address Register for Memory Accesses to Local Configuration Registers Table 5-12. (PCIBARO; 10h) PCI Base Address Register for Memory Accesses to Local Configuration Registers Description 0 Memory Space Indicator. Value of 0 indicates register maps into Memory space. Yes No 0 Value of 1 indicates register maps into I/O space. Note: Hardcoded to 0. 2:1 Location of register: Yes No 0 00 = Locate anywhere in 32 bit memory address space 01 = Locate below 1 MB memory address space 10 = Locate anywhere in 64 bit memory address space 11 = Reserved Note: Hardcoded to 0. 3 Prefetchable. Value of 1 indicates no side effect on reads. Yes No 0 Note: Hardcoded to 0. 6:4 Memory Base Address. Memory base address for access to local configuration Yes No 0 registers (default 128 bytes). Note: Hardcoded to 0. 31:7 Memory Base Address. Memory base address for access to local configuration Yes Yes 0 registers Note: PCIBARO can be enabled or disabled using bits [13:12] in CNTRL register. 5.2.11 (PCIBAR1; 14h) PCI Base Address Register for I/O Accesses to Local Configuration Registers Table 5-13. (PCIBAR1; 14h) PCI Base Address Address Register for I/O Accesses to Local Configuration Registers Description 0 Memory Space Indicator. Value of 0 indicates register maps into Memory space. Yes No th Value of 1 indicates register maps into I/O space. Note: Hardcoded to 1. 1 Reserved. Yes No 6:2 \/O Base Address. Base address for I/O access to local configuration registers Yes No (default 128 bytes). Note: Hardcoded to 0. 31:7 \/O Base Address. Base address for I/O access to local configuration registers. Yes Yes 0 Note: PCIBAR1 can be enabled or disabled using bits [13:12] in CNTRL register. PLX Technology, Inc., 1997 Page 26 Version 1.0SECTION 5 PCI 9052 REGISTERS 5.2.12 (PCIBAR2; 18h) PCI Base Address Register for Memory Access to Local Address Space 0 Table 5-14. (PCIBAR2; 18h) PCI Base Address Register for Memory Access to Local Address Space 0 Description 0 Memory Space Indicator. Value of 0 indicates register maps into Memory space. Yes No 0 Value of 1 indicates register maps into I/O space. (Specified in LASORR register.) 2:1 Location of Register (if Memory space): Yes Mem: No 0 00 = Locate anywhere in 32 bit memory address space 01 = Locate below 1 MB memory address space 10 = Locate anywhere in 64 bit memory address space 11 = Reserved (Specified in LASORR register.) If /O space, bit 1 is always 0, and bit 2 is included in base address. VO: bit 1 no, bit 2 yes 3 Prefetchable (if Memory space). Value of 1 indicates no side effects on reads. This Yes Mem: No 0 bit reflects the value of bit 3 in LASORR register, only provides status to the system, and has no effect on operation of PCI 9052. Associated Bus Region Descriptor VO: Yes Register (LASOBRD) controls prefetching features of this address space. (Specified in LASORR register.) If /O space, bit 3 is included in the base address. 31:4 Base Address. Base address for accesses to Local Address Space. Yes Yes 0 Note: PCIBAR2 can be enabled or disabled by setting or clearing bit 0 in LASOBA register. 5.2.13 (PCIBAR3; 1Ch) PCI Base Address Register for Memory Access to Local Address Space 1 Table 5-15. (PCIBAR3; 1Ch) PCI Base Address Register for Memory Access to Local Address Space 1 Description 0 Memory Space Indicator. Value of 0 indicates register maps into Memory space. Yes No 0 Value of 1 indicates register maps into I/O space. (Specified in LAS1RR register.) 2:1 Location of Register (if Memory space): Yes Mem: No 0 00 = Locate anywhere in 32 bit memory address space 01 = Locate below 1 MB memory address space 10 = Locate anywhere in 64 bit memory address space 11 = Reserved (Specified in LAS1RR register.) If /O space, bit 1 is always 0, and bit 2 is included in the base address. VO: bit 1 no, bit 2 yes 3 Prefetchable (if Memory space). Value of 1 indicates no side effects on reads. This Yes Mem: No 0 bit reflects the value of bit 3 in LAS1RR register, only provides status to the system, and has no effect on operation of PCI 9052. Associated Bus Region Descriptor VO: Yes Register (LAS1OBRD) controls prefetching features of this address space. (Specified in LAS1RR register.) If /O space, bit 3 is included in the base address. 31:4 Base Address. Base address for accesses to the Local Address Space. Yes Yes 0 Note: PCIBAR3 can be enabled or disabled by setting or clearing bit 0 in LAS1BA register. PLX Technology, Inc., 1997 Page 27 Version 1.0SECTION 5 PCI 9052 REGISTERS 5.2.14 (PCIBAR4; 20h) PCI Base Address Register for Memory Access to Local Address Space 2 Table 5-16. (PCIBAR4; 20h) PCI Base Address Register for Memory Access to Local Address Space 2 Description 0 Memory Space Indicator. Value of 0 indicates register maps into Memory space. Yes No 0 Value of 1 indicates register maps into I/O space. (Specified in LAS2RR register.) 2:1 Location of Register (if Memory space): Yes Mem: No 0 00 = Locate anywhere in 32 bit memory address space 01 = Locate below 1 MB memory address space 10 = Locate anywhere in 64 bit memory address space 11 = Reserved (Specified in LAS2RR register.) If /O space, bit 1 is always 0, and bit 2 is included in the base address. VO: bit 1 no, bit 2 yes 3 Prefetchable (if Memory space). Value of 1 indicates there are no side effects on Yes Mem: No 0 reads. This bit reflects the value of bit 3 in LAS2RR register, only provides status to the system, and has no effect on operation of PCI 9052. Associated Bus Region /O: Yes Descriptor Register (LAS2BRD) controls prefetching features of this address space. (Specified in LAS2RR register.) If /O space, bit 3 is included in the base address. 31:4 Base Address. Base address for accesses to Local Address Space. Yes Yes 0 Note: PCIBAR4 can be enabled or disabled by setting or clearing bit 0 in LAS2BA register. 5.2.15 (PCIBAR5; 24h) PCI Base Address Register for Memory Access to Local Address Space 3 Table 5-17. (PCIBAR5; 24h) PCI Base Address Register for Memory Access to Local Address Space 3 Description 0 Memory Space Indicator. Value of 0 indicates register maps into Memory space. Yes No 0 Value of 1 indicates register maps into I/O space. (Specified in LAS3RR register.) 2:1 Location of Register (if Memory space): Yes Mem: No 0 00 = Locate anywhere in 32 bit memory address space 01 = Locate below 1 MB memory address space 10 = Locate anywhere in 64 bit memory address space 11 = Reserved (Specified in LAS3RR register.) If /O space, bit 1 is always 0, and bit 2 is included in the base address. VO: bit 1 no, bit 2 yes 3 Prefetchable (if Memory space). Value of 1 indicates there are no side effects on Yes Mem: No 0 reads. This bit reflects the value of bit 3 in LAS3RR register, only provides status to the system, and has no effect on operation of PCI 9052. Associated Bus Region VO: Yes Descriptor Register (_LAS3RR) controls prefetching features of this address space. (Specified in LAS3RR register.) If /O space, bit 3 is included in the base address. 31:4 Base Address. Base address for accesses to Local Address Space. Yes Yes 0 Note: PCIBARS5 can be enabled or disabled by setting or clearing bit 0 in LAS3BA register. PLX Technology, Inc., 1997 Page 28 Version 1.0SECTION 5 PCI 9052 REGISTERS 5.2.16 (PCICIS; 28h) PCI Cardbus CIS Pointer Register Table 5-18. (PCICIS; 28h) PCI Cardbus CIS Pointer Register Description 31:0 Cardbus Information Structure Pointer for PCMCIA. Not Supported. Yes No 0 5.2.17 (PCISVID; 2Ch) PCI Subsystem Vendor ID Register Table 5-19. (PCISVID; 2Ch) PCI Subsystem Vendor ID Register Description 15:0 Subsystem Vendor ID. (Unique add-in board Vendor ID.) Yes Serial 0 EEPROM 5.2.18 (PCISID; 2Eh) PCI Subsystem ID Register Table 5-20. (PCISID; 2Eh) PCI Subsystem ID Register Description 15:0 Subsystem ID. (Unique add-in board Device ID.) Yes Serial 0 EEPROM 5.2.19 (PCIERBAR; 30h) PCI Expansion ROM Base Address Register Table 5-21. (PCIERBAR; 30h) PCI Expansion ROM Base Address Regisiter Description 0 Address Decode Enable. Value of 1 indicates the device accepts accesses to Yes Yes 0 expansion ROM address. Value of 0 indicates the device does not accept accesses to expansion ROM space. 10:1 Reserved. Yes No 31:11 Expansion ROM Base Address (upper 21 bits). Yes Yes 5.2.20 (PCIILR; 3Ch) PCI Interrupt Line Register Table 5-22. (PCIILR; 3Ch) PCI Interrupt Line Register Description 7:0 Interrupt Line Routing Value. Indicates to which system interrupt controller(s) input Yes Yes 0 the interrupt line of device is connected. PLX Technology, Inc., 1997 Page 29 Version 1.0SECTION 5 PCI 9052 REGISTERS 5.2.21 (PCIIPR; 3Dh) PCI Interrupt Pin Register Table 5-23. (PCIIPR; 3Dh) PCI Interrupt Pin Register Description Interrupt Pin Register. Indicates interrupt pin device uses. The following values are decoded: 0 = No Interrupt Pin 1 = INTA# 2 = INTB# 3 = INTC# 4 = INTD# Note: PCI 9052 supports only one PCI interrupt (INTA#). 5.2.22 (PCIMGR; 3Eh) PCI Min_Gnt Register Table 5-24. (PCIMGR; 3Eh) PCI Min_Gnt Register Description Min_Gnt. Specifies needed length of Burst period for the device, assuming a clock rate of 33 MHz. Value is a multiple of 1/4 ys increments. Not Supported. 5.2.23 (PCIMLR; 3Fh) PCI Max_Lat Register Table 5-25. (PCIMLR; 3Fh) PCI Max_Lat Register Description Max_Lat. Specifies how often the device must gain access to PCI bus. Value is a multiple of 1/4 us increments. Not Supported. PLX Technology, Inc., 1997 Page 30 Version 1.0SECTION 5 PCI 9052 REGISTERS 5.3 LOCAL CONFIGURATION REGISTERS 5.3.1 (LASORR; 00h) Local Address Space 0 Range Register Table 5-26. (LASORR; 00h) Local Address Space 0 Range Register Description 0 Memory Space Indicator. Value of 0 indicates Local Address Space 0 maps into Yes Yes 0 PCI memory space. Value of 1 indicates Local Address Space 0 maps into PCI I/O space. 2:1 If mapped into Memory space, encoding is as follows: Yes Yes 0 2/i Meaning 00 Locate anywhere in 32 bit PCI address space 01 Locate below 1 MB in PCI address space 10 Locate anywhere in 64 bit PCI address space 11 Reserved If mapped into I/O space, bit 1 must be a value of 0. Bit 2 is included with bits [27:3] to indicate decoding range. 3 If mapped into Memory space, value of 1 indicates that reads are prefetchable (Bit Yes Yes 0 has no effect on operation of PCI 9052, but is for system status.) If mapped into I/O space, bit is included with bits [27:2] to indicate decoding range. 27:4 Specifies PCI address bits used to decode PCI access to Local Bus Space 0. Yes Yes FFOOoO Each bit corresponds to an address bit. Bit 27 corresponds to Address bit 27. Value of 1 indicates the bits should be included in decode. Write a value of 0 to all others (used in conjunction with PCI Configuration Register 18h). Default is 1 MB. 31:28 Unused. (PCI address bits [31:28] are always included in decoding.) Yes No 0 5.3.2 (LAS1RR; 04h) Local Address Space 1 Range Register Table 5-27. (LAS1RR; 04h) Local Address Space 1 Range Register Description 0 Memory Space Indicator. Value of 0 indicates Local Address Space 1 maps into Yes Yes 0 PCI memory space. Value of 1 indicates Local Address Space 1 maps into PCI I/O space. 2:1 If mapped into Memory space, encoding is as follows: Yes Yes 0 2/i Meaning 00 Locate anywhere in 32 bit PCI address space 01 Locate below 1 MB in PCI address space 10 Locate anywhere in 64 bit PCI address space 11 Reserved If mapped into I/O space, bit 1 must be a value of 0. Bit 2 is included with bits [27:3] to indicate decoding range. 3 If mapped into Memory space, value of 1 indicates that reads are prefetchable. Yes Yes 0 If mapped into I/O space, bit is included with bits [27:2] to indicate decoding range. 27:4 Specifies PCI address bits used to decode PCI access to Local Bus Space 1. Yes Yes 0 Each bit corresponds to an address bit. Bit 27 corresponds to Address bit 27. Value of 1 indicates the bits should be included in decode. Write a value of 0 to all others (used in conjunction with PCI Configuration register 1Ch). 31:28 Unused. (PCI address bits [31:28] are always included in decoding.) Yes No 0 PLX Technology, Inc., 1997 Page 31 Version 1.0SECTION 5 PCI 9052 5.3.3 (LAS2RR; 08h) Local Address Space 2 Range Register Table 5-28. (LAS2RR; 08h) Local Address Space 2 Range Register Description 0 Memory Space Indicator. Value of 0 indicates Local Address Space 2 maps into Yes Yes PCI memory space. Value of 1 indicates Local Address Space 2 maps into PCI I/O space. 2:1 If mapped into Memory space, encoding is as follows: Yes Yes 2/1 Meaning 00 Locate anywhere in 32 bit PCI address space 01 Locate below 1 MB in PCI address space 10 Locate anywhere in 64 bit PCI address space 11 Reserved If mapped into I/O space, bit 1 must be a value of 0. Bit 2 is included with bits [27:3] to indicate decoding range. 3 If mapped into Memory space, value of 1 indicates that reads are prefetchable. Yes Yes If mapped into I/O space, bit is included with bits [27:2] to indicate decoding range. 27:4 Specifies PCI address bits used to decode PCI access to Local Bus Space 2. Yes Yes Each bit corresponds to an address bit. Bit 27 corresponds to Address bit 27. Value of 1 indicates the bits should be included in decode. Write a value of 0 to all others (used in conjunction with Configuration register 20h). 31:28 Unused. (PCI address bits [31:28] are always included in decoding.) Yes No 5.3.4 (LAS3RR; OCh) Local Address Space 3 Range Register Table 5-29. (LAS3RR; 0Ch) Local Address Space 3 Range Register Description 0 Memory Space Indicator. Value of 0 indicates to Local Address Space 3 maps into Yes Yes PCI memory space. Value of 1 indicates Local Address Space 3 maps into PCI I/O space. 2:1 If mapped into Memory space, encoding is as follows: Yes Yes 2/1 Meaning 00 Locate anywhere in 32 bit PCI address space 01 Locate below 1 MB in PCI address space 10 Locate anywhere in 64 bit PCI address space 11 Reserved If mapped into I/O space, bit 1 must be a value of 0. Bit 2 is included with bits [27:3] to indicate decoding range. 3 If mapped into Memory space, value of 1 indicates that reads are prefetchable. Yes Yes If mapped into I/O space, bit is included with bits [27:2] to indicate decoding range. 27:4 Specifies PCI address bits used to decode PCI access to Local Bus Space 3. Yes Yes Each bit corresponds to an address bit. Bit 27 corresponds to Address bit 27. Value of 1 indicates the bits should be included in decode. Write a value of 0 to all others (used in conjunction with PCI Configuration register 24h). 31:28 Unused. (PCI address bits [31:28] are always included in decoding.) Yes No PLX Technology, Inc., 1997 Page 32 REGISTERSSECTION 5 PCI 9052 5.3.5 (EROMRR; 10h) Expansion ROM Range Register Table 5-30. (EROMRR; 10h) Expansion ROM Range Register Description REGISTERS 0 Address Decode Enable. Bit 0 can only be enabled from serial EEPROM. No Serial 0 To disable, refer to (PCIERBAR; 30h [0]; Table 5-21). EEPROM Only 10:1 Unused. Yes No 0 27:11 Specifies PCI address bits used to decode PCI to local bus expansion ROM. Each Yes Yes 11111111111100000 bit corresponds to an Address bit. Value of 1 indicates the bits should be included in decode. Write a value of 0 to all others (used in conjunction with PCI Configuration register 30h). Default is 64 KB. 31:28 Unused. (PCI address bits [31:28] are always included in decoding.) Yes Yes 1111 5.3.6 (LASOBA; 14h) Local Address Space 0 Local Base Address (Remap) Register Table 5-31. (LASOBA; 14h) Local Address Space 0 Local Base Address (Remap) Regisiter Description 0 Space 0 Enable. Value of 1 enables decode of PCI addresses for Direct Slave Yes Yes 1 access to Local Space 0. Value of 0 disables decode. 1 Unused. Yes Yes 3:2 If Local Space 0 is mapped into Memory space, bits are not used. Yes Yes If mapped into I/O space, bits are included with bits [27:4] for remapping. 27:4 Remap of PCI Address to Local Address Space 0 into a Local Address Space. The Yes Yes 0 bits in this register remap (replace) PCI Address bits used in decode as the Local Address bits. 31:28 Unused. (Local address bits [31:28] do not exist in PCI 9052.) Yes No 0 5.3.7 (LAS1BA; 18h) Local Address Space 1 Local Base Address (Remap) Register Table 5-32. (LAS1BA; 18h) Local Address Space 1 Local Base Address (Remap) Register Description 0 Space 1 Enable. Value of 1 enables decode of PCI addresses for Direct Slave Yes Yes 0 access to Local Space 1. Value of 0 disables decode. 1 Unused. Yes Yes 3:2 If to Local Space 1 is mapped into Memory space, bits are not used. Yes Yes If mapped into I/O space, bits are included with bits [27:4] for remapping. 27:4 Remap of PCI Address to Local Address Space 1 into a Local Address Space. The Yes Yes 0 bits in this register remap (replace) PCI Address bits used in decode as the Local Address bits. 31:28 Unused. (Local address bits [31:28] do not exist in PCI 9052.) Yes No 0 PLX Technology, Inc., 1997 Page 33 Version 1.0SECTION 5 PCI 9052 REGISTERS 5.3.8 (LAS2BA; 1Ch) Local Address Space 2 Local Base Address (Remap) Register Table 5-33. (LAS2BA; 1Ch) Local Address Space 2 Local Base Address (Remap) Register Description 0 Space 2 Enable. Value of 1 enables decode of PCI addresses for Direct Slave Yes Yes 0 access to Local Space 2. Value of 0 disables decode. 1 Unused. Yes Yes 3:2 If Local Space 2 is mapped into Memory space, bits are not used. Yes Yes If mapped into I/O space, bits are included with bits [27:4] for remapping. 27:4 Remap of PCI Address to Local Address Space 2 into a Local Address Space. The Yes Yes 0 bits in this register remap (replace) PCI Address bits used in decode as the Local Address bits. 31:28 Unused. (Local address bits [31:28] do not exist in PCI 9052.) Yes No 0 5.3.9 (LAS3BA; 20h) Local Address Space 3 Local Base Address (Remap) Register Table 5-34. (LAS3BA; 20h) Local Address Space 3 Local Base Address (Remap) Regisiter Description 0 Space 3 Enable. Value of 1 enables decode of PCI addresses for Direct Slave Yes Yes 0 access to Local Space 3. Value of 0 disables decode. 1 Unused. Yes Yes 3:2 If Local Space 3 is mapped into Memory space, bits are not used. Yes Yes If mapped into I/O space, bits are included with bits [27:4] for remapping. 27:4 Remap of PCI Address to Local Address Space 3 into a Local Address Space. The Yes Yes 0 bits in this register remap (replace) PCI Address bits used in decode as the Local Address bits. 31:28 Unused. (Local address bits [31:28] do not exist in PCI 9052.) Yes No 0 5.3.10 (EROMBA; 24h) Expansion ROM Local Base Address (Remap) Register Table 5-35. (EROMBA; 24h) Expansion ROM Local Base Address (Remap) Register Description 10:0 Unused. Yes No 0 27:11 Remap of PCI Expansion ROM space into a Local Address Space. The bits in this Yes Yes 00000001000000000 register remap (replace) PCI address bits used in decode as the local address bits. Default base is 1 MB (above default Local Address Space 0). 31:28 Unused. (Local address bits [31:28] do not exist in PCI 9052.) Yes No 0 PLX Technology, Inc., 1997 Page 34 Version 1.0SECTION 5 PCI 9052 REGISTERS 5.3.11 (LASOBRD; 28h) Local Address Space 0 Bus Region Descriptor Register Table 5-36. (_.ASOBRD; 28h) Local Address Space 0 Bus Region Descriptor Register Description 0 Burst Enable. Value of 1 indicates bursting is enabled. Value of 0 indicates Yes Yes 0 bursting is disabled. Bursting only occurs if Prefetch Count is not equal to 00. 1 Ready Input Enable. Value of 1 indicates READY input enabled. Value of 0 Yes Yes 0 indicates disabled. 2 Bterm Input Enable. Value of 1 indicates Bterm Input is enabled. Value of 0 Yes Yes 0 indicates Bterm Input is disabled. Burst length limited to four Lwords. 4:3 Prefetch Count. Number of Lwords to prefetch during memory read cycle. Only Yes Yes 0 used if bit 5 is high (prefetch count enabled). 00 = Do not prefetch. Only read bytes specified by C/BE lines. 01 = Prefetch four Lwords if bit 5 is set. 10 = Prefetch eight Lwords if bit 5 is set. 11 = Prefetch 16 Lwords if bit 5 is set. 5 Prefetch Count Enable. Value of 1 prefetches up to the number of Lwords Yes Yes 0 specified in prefetch count. Value of 0 ignores the count and prefetching continues until terminated by the PCI bus. 10:6 NRAD Wait States. Number of Read Address-to-Data wait states (0-31). Yes Yes 0 12:11 NRDD Wait States. Number of Read Data-to-Data wait states (0-3). Yes Yes 0 14:13 NXDA Wait States. Number of Read/Write Data-to-Address wait states (0-3). Yes Yes 0 19:15 NWAD Wait States. Number of Write Address-to-Data wait states (0-31). Yes Yes 0 21:20 NWDD Wait States. Number of Write Data-to-Data wait states (0-3). Yes Yes 0 23:22 Bus Width. Yes Yes 10 00 = 8 bit 01 = 16 bit 10 = 32 bit 11 = Reserved 24 Byte Ordering. Value of 1 indicates Big Endian. Value of 0 indicates Little Endian. Yes Yes 25 Big Endian Byte Lane Mode. Value of 1 indicates that in Big Endian mode byte Yes Yes lanes, [31:16] be used for 16 bit local bus, and byte lane [31:24] for an 8 bit local bus. Value of 0 indicates that in Big Endian mode byte lanes, [15:0] be used for 16 bit local bus, and byte lane [7:0] for an 8 bit local bus. 27:26 Read Strobe Delay. Number of clocks from beginning of cycle until RD strobe is Yes Yes 0 asserted (0-3). This value must be < NRAD for RD to be asserted. 29:28 Write Strobe Delay. Number of clocks from beginning of cycle until WR strobe is Yes Yes 0 asserted (0-3). This value must be < NWAD for WR to be asserted. 31:30 Write Cycle Hold. Number of clocks from WR negation until end of cycle. (0-3). Yes Yes 0 PLX Technology, Inc., 1997 Page 35 Version 1.0SECTION 5 PCI 9052 REGISTERS 5.3.12 (LAS1BRD; 2Ch) Local Address Space 1 Bus Region Descriptor Register Table 5-37. (LAS1BRD; 2Ch) Local Address Space 1 Bus Region Descriptor Register Description 0 Burst Enable. Value of 1 indicates bursting is enabled. Value of 0 indicates Yes Yes 0 bursting is disabled. Bursting only occurs if the Prefetch Count is not equal to 00. 1 Ready Input Enable. Value of 1 indicates enabled. Value of 0 indicates disabled. Yes Yes 2 Bterm Input Enable. Value of 1 indicates Bterm Input is enabled. Value of 0 Yes Yes indicates Bterm Input is disabled. Burst length limited to four Lwords. 4:3 Prefetch Count. Number of Lwords to prefetch during memory read cycle. Yes Yes 0 Only used if bit 5 is high (prefetch count enabled). 00 = Do not prefetch. Only read bytes specified by C/BE lines. 01 = Prefetch four Lwords if bit 5 is set. 10 = Prefetch eight Lwords if bit 5 is set. 11 = Prefetch 16 Lwords if bit 5 is set. 5 Prefetch Count Enable. Value of 1 prefetches up to the number of Lwords Yes Yes 0 specified in prefetch count. Value of 0 ignores the count and prefetching continues until terminated by PCI bus. 10:6 NRAD Wait States. Number of Read Address-to-Data wait states (0-31). Yes Yes 0 12:11 NRDD Wait States. Number of Read Data-to-Data wait states (0-3). Yes Yes 0 14:13 NXDA Wait States. Number of Read/Write Data-to-Address wait states (0-3). Yes Yes 0 19:15 NWAD Wait States. Number of Write Address-to-Data wait states (0-31). Yes Yes 0 21:20 NWDD Wait States. Number of Write Data-to-Data wait states (0-3). Yes Yes 0 23:22 Bus Width. Yes Yes 10 00 = 8 bit 01 = 16 bit 10 = 32 bit 11 = Reserved 24 Byte Ordering. Value of 1 indicates Big Endian. Value of 0 indicates Little Endian. Yes Yes 25 Big Endian Byte Lane Mode. Value of 1 indicates that in Big Endian mode byte Yes Yes lanes, [31:16] be used for 16 bit local bus, and byte lane [31:24] for an 8 bit local bus. Value of 0 indicates that in Big Endian mode byte lanes, [15:0] be used for 16 bit local bus, and byte lane [7:0] for an 8 bit local bus. 27:26 Read Strobe Delay. Number of clocks from beginning of cycle until RD strobe is Yes Yes 0 asserted (0-3). This value must be < NRAD for RD to be asserted. 29:28 Write Strobe Delay. Number of clocks from beginning of cycle until WR strobe is Yes Yes 0 asserted (0-3). This value must be < NWAD for WR to be asserted. 31:30 Write Cycle Hold. Number of clocks from WR negation until end of cycle (0-3). Yes Yes 0 PLX Technology, Inc., 1997 Page 36 Version 1.0SECTION 5 PCI 9052 REGISTERS 5.3.13 (LAS2BRD; 30h) Local Address Space 2 Bus Region Descriptor Register Table 5-38. (_AS2BRD; 30h) Local Address Space 2 Bus Region Descriptor Register Description 0 Burst Enable. Value of 1 indicates bursting is enabled. Value of 0 indicates Yes Yes 0 bursting is disabled. Bursting only occurs if Prefetch Count is not equal to 00. 1 Ready Input Enable. Value of 1 indicates enabled. Value of 0 indicates disabled. Yes Yes 2 Bterm Input Enable. Value of 1 indicates Bterm Input is enabled. Value of 0 Yes Yes indicates Bterm Input is disabled. Burst length limited to four Lwords. 4:3 Prefetch Count. Number of Lwords to prefetch during memory read cycle. Yes Yes 0 Only used if bit 5 is high (prefetch count enabled). 00 = Do not prefetch. Only read bytes specified by C/BE lines. 01 = Prefetch four Lwords if bit 5 is set. 10 = Prefetch eight Lwords if bit 5 is set. 11 = Prefetch 16 Lwords if bit 5 is set. 5 Prefetch Count Enable. Value of 1 prefetches up to the number of Lwords Yes Yes 0 specified in prefetch count. Value of 0 ignores the count and prefetching continues until terminated by PCI bus. 10:6 NRAD Wait States. Number of Read Address-to-Data wait states (0-31). Yes Yes 0 12:11 NRDD Wait States. Number of Read Data-to-Data wait states (0-3). Yes Yes 0 14:13 NXDA Wait States. Number of Read/Write Data-to-Address wait states (0-3). Yes Yes 0 19:15 NWAD Wait States. Number of Write Address-to-Data wait states (0-31). Yes Yes 0 21:20 NWDD Wait States. Number of Write Data-to-Data wait states (0-3). Yes Yes 0 23:22 Bus Width. Yes Yes 10 00 = 8 bit 01 = 16 bit 10 = 32 bit 11 = Reserved 24 Byte Ordering. Yes Yes 0 1 = Big Endian 0 = Little Endian 25 Big Endian Byte Lane Mode. Value of 1 indicates that in Big Endian mode byte Yes Yes 0 lanes, [31:16] be used for a 16 bit local bus, and byte lane [31:24] for an 8 bit local bus. Value of 0 indicates that in Big Endian mode byte lanes, [15:0] be used for 16 bit local bus, and byte lane [7:0] for an 8 bit local bus. 27:26 Read Strobe Delay. Number of clocks from beginning of cycle until RD strobe is Yes Yes 0 asserted (0-3). This value must be < NRAD for RD to be asserted. 29:28 Write Strobe Delay. Number of clocks from beginning of cycle until WR strobe is Yes Yes 0 asserted (0-3). This value must be < NWAD for WR to be asserted. 31:30 Write Cycle Hold. Number of clocks from WR negation until end of cycle (0-3). Yes Yes 0 PLX Technology, Inc., 1997 Page 37 Version 1.0SECTION 5 PCI 9052 REGISTERS 5.3.14 (LAS3BRD; 34h) Local Address Space 3 Bus Region Descriptor Register Table 5-39. (_AS3BRD; 34h) Local Address Space 3 Bus Region Descriptor Register Description 0 Burst Enable. Value of 1 indicates bursting is enabled. Value of 0 indicates Yes Yes 0 bursting is disabled. Bursting only occurs if Prefetch Count is not equal to 00. 1 Ready Input Enable. Value of 1 indicates enabled. Value of 0 indicates disabled. Yes Yes 2 Bterm Input Enable. Value of 1 indicates Bterm Input is enabled. Value of 0 Yes Yes indicates Bterm Input is disabled. Burst length limited to four Lwords. 4:3 Prefetch Count. Number of Lwords to prefetch during memory read cycle. Only Yes Yes 0 used if bit 5 is high (prefetch count enabled). 00 = Do not prefetch. Only read bytes specified by C/BE lines. 01 = Prefetch four Lwords if bit 5 is set. 10 = Prefetch eight Lwords if bit 5 is set. 11 = Prefetch 16 Lwords if bit 5 is set. 5 Prefetch Count Enable. Value of 1 prefetches up to the number of Lwords Yes Yes 0 specified in prefetch count. Value of 0 ignores the count and prefetching continues until terminated by PCI bus. 10:6 NRAD Wait States. Number of Read Address-to-Data wait states (0-31). Yes Yes 0 12:11 NRDD Wait States. Number of Read Data-to-Data wait states (0-3). Yes Yes 0 14:13 NXDA Wait States. Number of Read/Write Data-to-Address wait states (0-3). Yes Yes 0 19:15 NWAD Wait States. Number of Write Address-to-Data wait states (0-31). Yes Yes 0 21:20 NWDD Wait States. Number of Write Data-to-Data wait states (0-3). Yes Yes 0 23:22 Bus Width. Yes Yes 10 00 = 8 bit 01 = 16 bit 10 = 32 bit 11 = Reserved 24 Byte Ordering. Value of 1 indicates Big Endian. Value of 0 indicates Little Endian. Yes Yes 25 Big Endian Byte Lane Mode. Value of 1 indicates that in Big Endian mode byte Yes Yes lanes, [31:16] be used for 16 bit local bus, and byte lane [31:24] for an 8 bit local bus. Value of 0 indicates that in Big Endian mode byte lanes, [15:0] be used for 16 bit local bus, and byte lane [7:0] for an 8 bit local bus. 27:26 Read Strobe Delay. Number of clocks from beginning of cycle until RD strobe is Yes Yes 0 asserted (0-3). This value must be < NRAD for RD to be asserted. 29:28 Write Strobe Delay. Number of clocks from beginning of cycle until WR strobe is Yes Yes 0 asserted (0-3). This value must be < NWAD for WR to be asserted. 31:30 Write Cycle Hold. Number of clocks from WR negation until end of cycle (0-3). Yes Yes 0 PLX Technology, Inc., 1997 Page 38 Version 1.0SECTION 5 PCI 9052 REGISTERS 5.3.15 (EROMBRD; 38h) Expansion ROM Bus Region Descriptor Register Table 5-40. (EROMBRD; 38h) Expansion ROM Bus Region Descriptor Register Description 0 Burst Enable. Value of 1 indicates bursting is enabled. Value of 0 indicates Yes Yes 0 bursting is disabled. Bursting only occurs if Prefetch Count is not equal to 00. 1 Ready Input Enable. Value of 1 indicates enabled. Value of 0 indicates disabled. Yes Yes 2 Bterm Input Enable. Value of 1 indicates Bterm Input is enabled. Value of 0 Yes Yes indicates Bterm Input is disabled. Burst length limited to four Lwords. 4:3 Prefetch Count. Number of Lwords to prefetch during memory read cycle. Only Yes Yes 0 used if bit 5 is high (prefetch count enabled). 00 = Do not prefetch. Only read bytes specified by C/BE lines. 01 = Prefetch four Lwords if bit 5 is set. 10 = Prefetch eight Lwords if bit 5 is set. 11 = Prefetch 16 Lwords if bit 5 is set. 5 Prefetch Count Enable. Value of 1 prefetches up to the number of Lwords Yes Yes 0 specified in prefetch count. Value of 0 ignores the count and prefetching continues until terminated by PCI bus. 10:6 NRAD Wait States. Number of Read Address-to-Data wait states (0-31). Yes Yes 0 12:11 NRDD Wait States. Number of Read Data-to-Data wait states (0-3). Yes Yes 0 14:13 NXDA Wait States. Number of Read/Write Data-to-Address wait states (0-3). Yes Yes 0 19:15 NWAD Wait States. Number of Write Address-to-Data wait states (0-31). Yes Yes 0 21:20 NWDD Wait States. Number of Write Data-to-Data wait states (0-3). Yes Yes 0 23:22 Bus Width. Yes Yes 0 00 = 8 bit 01 = 16 bit 10 = 32 bit 11 = Reserved 24 Byte Ordering. Value of 1 indicates Big Endian. Value of 0 indicates Little Endian. Yes Yes 25 Big Endian Byte Lane Mode. Value of 1 indicates that in Big Endian mode byte Yes Yes lanes, [31:16] be used for 16 bit local bus, and byte lane [31:24] for an 8 bit local bus. Value of 0 indicates that in Big Endian mode byte lanes, [15:0] be used for 16 bit local bus, and byte lane [7:0] for an 8 bit local bus 27:26 Read Strobe Delay. Number of clocks from beginning of cycle until RD strobe is Yes Yes 0 asserted (0-3). This value must be < NRAD for RD to be asserted. 29:28 Write Strobe Delay. Number of clocks from beginning of cycle until WR strobe is Yes Yes 0 asserted (0-3). This value must be < NWAD for WR to be asserted. 31:30 Write Cycle Hold. Number of clocks from WR negation until end of cycle (0-3). Yes Yes 0 PLX Technology, Inc., 1997 Page 39 Version 1.0SECTION 5 PCI 9052 REGISTERS 5.3.16 (CSOBASE; 3Ch) Chip Select 0 Base Address Register Table 5-41. (CSOBASE; 3Ch) Chip Select 0 Base Address Register Description 0 Chip Select 0 Enable. Value of 1 indicates enabled. Value of 0 indicates disabled. Yes Yes 27:1 Local Base Address of Chip Select 0. Write zeroes in the least significant bits to Yes Yes define the range for Chip Select 0. Starting from bit 1 and scanning toward bit 27, the first 1 found defines size. The remaining most significant bits, excluding the first 1 found, define base address. 31:28 Unused. Yes No 0 5.3.17 (CS1BASE; 40h) Chip Select 1 Base Address Register Table 5-42. (CS1BASE; 40h) Chip Select 1 Base Address Register Description 0 Chip Select 1 Enable. Value of 1 indicates enabled. Value of 0 indicates disabled. Yes Yes 27:1 Local Base Address of Chip Select 1. Write zeroes in the least significant bits to Yes Yes define the range for Chip Select 1. Starting from bit 1 and scanning toward bit 27, the first 1 found defines size. The remaining most significant bits, excluding the first 1 found, define base address. 31:28 Unused. Yes No 0 5.3.18 (CS2BASE; 44h) Chip Select 2 Base Address Register Table 5-43. (CS2BASE; 44h) Chip Select 2 Base Address Register Description 0 Chip Select 2 Enable. Value of 1 indicates enabled. Value of 0 indicates disabled. Yes Yes 27:1 Local Base Address of Chip Select 2. Write zeroes in the least significant bits to Yes Yes define the range for Chip Select 2. Starting from bit 1 and scanning toward bit 27, the first 1 found defines size. The remaining most significant bits, excluding the first 1 found, define the base address. 31:28 Unused. Yes No 0 5.3.19 (CS3BASE; 48h) Chip Select 3 Base Address Register Table 5-44. (CS3BASE; 48h) Chip Select 3 Base Address Register Description 0 Chip Select 3 Enable. Value of 1 indicates enabled. Value of 0 indicates disabled. Yes Yes 27:1 Local Base Address of Chip Select 3. Write zeroes in the least significant bits to Yes Yes define the range for Chip Select 3. Starting from bit 1 and scanning toward bit 27, the first 1 found defines size. The remaining most significant bits, excluding the first 1 found, define base address. 31:28 Unused. Yes No 0 PLX Technology, Inc., 1997 Page 40 Version 1.0SECTION 5 PCI 9052 REGISTERS 5.3.20 (INTCSR; 4Ch) Interrupt Control/Status Register Table 5-45. (INTCSR; 4Ch) Interrupt Control/Status Register Description 0 Local Interrupt 1 Enable. Value of 1 indicates enabled. Value of 0 indicates Yes Yes disabled. 1 Local Interrupt 1 Polarity. Value of 1 indicates Active high. Value of 0 indicates Yes Yes Active low. 2 Local Interrupt 1 Status. Value of 1 indicates Interrupt active. Value of 0 indicates Yes No Interrupt not active. 3 Local Interrupt 2 Enable. Value of 1 indicates enabled. Value of 0 indicates Yes Yes disabled. 4 Local Interrupt 2 Polarity. Value of 1 indicates Active high. Value of 0 indicates Yes Yes Active low. 5 Local Interrupt 2 Status. Value of 1 indicates Interrupt active. Value of 0 indicates Yes No Interrupt not active. PCI Interrupt Enable. Value of 1 enables PCI interrupt. Yes Yes Software Interrupt. Value of 1 generates interrupt. Yes Yes Local Interrupt 1 Select Enable. Value of 1 indicates enabled edge triggerable Yes Yes interrupt. Value of 0 indicates enabled level triggerable interrupt. Note: Operates only in high polarity mode. 9 Local Interrupt 2 Select Enable. Value of 2 indicates enabled edge triggerable Yes Yes interrupt. Value of 0 indicates enabled level triggerable interrupt. Note: Operates only in high polarity mode. 10 Local Edge Triggerable Interrupt Clear Bit. Writing 1 to this bit clears Interrupt_1. Yes Yes 11 Local Edge Triggerable Interrupt Clear Bit. Writing 2 to this bit clears Interrupt_2. Yes Yes 12 ISA Interface Mode Enable. Writing 1 enables ISA Interface mode. Writing 0 Yes Serial disables ISA Interface mode. EEPROM only 31:13 Unused. Yes No 5.3.21 (CNTRL; 50h) User I/O, PCI Target Response, Serial EEPROM, Initialization Control Register Table 5-46. (CNTRL; 50h) User I/O, PCI Target Response, Serial EEPROM, Initialization Control Register Description User I/O 0 or WAITO# Pin Select. Selects the function of USERO/WAITO# pin. Value of 1 indicates pin is WAITO#. Value of 0 indicates pin is USERO. Yes Yes User I/O 0 Direction. Value of 0 indicates Input. Value of 1 indicates Output. Always an output if WAITO# function is selected. Yes Yes User I/O 0 Data. If programmed as output, writing a value of 1 causes corresponding pin to go high. If programmed as input, reading provides state of corresponding pin. Yes Yes User I/O 1 or LLOCKo# Pin Select. Selects the function of USER1/LLOCKo# pin. Value of 1 indicates pin is LLOCKo#. Value of 0 indicates pin is USER1. Yes Yes User I/O 1 Direction. Value of 0 indicates Input. Value of 1 indicates Output. Always an output if LLOCK function is selected. Yes Yes User I/O 1 Data. If programmed as output, writing a value of 1 causes corresponding pin to go high. If programmed as input, reading provides state of corresponding pin. Yes Yes PLX Technology, Inc., 1997 Page 41 Version 1.0SECTION 5 PCI 9052 REGISTERS Table 5-46. (CNTRL; 50h) User I/O, PCI Target Response, Serial EEPROM, Initialization Control Register Description (continued) User I/O 2 or CS2# Pin Select. Selects the function of USER2/CS2# pin. Value of 1 indicates pin is CS2#. Value of 0 indicates pin is USER2. Yes Yes User I/O 2 Direction. Value of 0 indicates Input. Value of 1 indicates Output. Always an output if CS2 function is selected. Yes Yes User I/O 2 Data. If programmed as output, writing a value of 1 causes corresponding pin to go high. If programmed as input, reading provides state of corresponding pin. Yes Yes User I/O 3 or CS3# Pin Select. Selects the function of USER3/CS3# pin. Value of 1 indicates pin is CS3#. Value of 0 indicates pin is USERS. Yes Yes 10 User I/O 3 Direction. Value of 0 indicates Input. Value of 1 indicates Output. Always an output if CS3 function is selected. Yes Yes 11 User I/O 3 Data. If programmed as output, writing a value of 1 causes corresponding pin to go high. If programmed as input, reading provides state of corresponding pin. Yes Yes 13:12 PCI Configuration Base Address Register (PCIBAR) Enables. 00 = PCIBARO (Memory) and PCIBAR1 (I/O) enabled. 01 = PCIBARO (Memory) only. 10 = PCIBAR1 (I/O) only. 11 = PCIBARO (Memory) and PCIBAR?1 (I/O) enabled. Yes Yes 00 14 PCI Read Mode. Value of 1 immediately disconnects for a read. Prefetch the data into direct slave read FIFO. Returns data when PCI read cycle is reapplied (PCI specification v2.1 compatible). Value of O negates TRDY# until read data is available. Yes Yes 15 PCI Read with Write Flush Mode. Value of 1 flushes pending read cycle if write cycle is detected. Value of 0 does not affect pending reads when a write cycle occurs (PCI specification v2.1 compatible). Yes Yes 16 PCI Read No Flush Mode. Value of 1 does not flush the read FIFO if PCI read cycle completes (Read Ahead mode). Value of 0 flushes read FIFO if PCI read cycle completes. Yes Yes 17 PCI Read No Write Mode. Value of 1 forces retry on writes if read is pending. Value of 0 allows a write to occur while a read is pending. Yes Yes 18 PCI Write Mode. Value of 1 disconnects if write FIFO becomes full. Value of 0 negates TRDY# until space is available in direct slave write FIFO. Yes Yes 22:19 PCI Target Retry Delay Clocks. Number of PCI clocks (multiplied by 8) after the beginning of a direct slave cycle until a retry is issued. Only valid for read cycles if bit 14 is low. Only valid for write cycles if bit 17 is low. Yes Yes 23 Direct Slave Lock Enable. Value of 1 enables PCI direct slave locked sequences. Value of 0 disables direct slave locked sequences. Yes Yes 24 Serial EEPROM Clock for Local or PCI Bus Reads or Writes to serial EEPROM. Toggling this bit generates a serial EEPROM clock. (Refer to manufacturer's data sheet for particular serial EEPROM being used.) Yes Yes 25 Serial EEPROM Chip Select. For local or PCI bus reads or writes to serial EEPROM, setting this bit to 1 provides serial EEPROM chip select. Yes Yes 26 Write Bit to serial EEPROM. For writes, this output bit is the input to serial EEPROM. Clocked into the serial EEPROM by serial EEPROM clock. Yes Yes 27 Read serial EEPROM Data Bit. For reads, this input bit is the output of serial EEPROM. Clocked out of the serial EEPROM by serial EEPROM clock. Yes No 28 Serial EEPROM Valid. Value of 1 indicates a valid serial EEPROM is present. Yes No 29 Reload Configuration Registers. When set to 0, writing a value of 1 causes PCI 9052 to reload local configuration registers from serial EEPROM. Yes Yes 30 PCI Adapter Software Reset. Value of 1 resets PCI 9052 and issues a reset to the local bus. Contents of PCI and local configuration registers will not be reset. Yes Yes 31 Mask Revision. Yes No PLX Technology, Inc., 1997 Page 42 Version 1.0SECTION 6 PCI 9052 6. PIN DESCRIPTION 6.1 PIN SUMMARY Table 6-2 through Table 6-5 describe PCI 9052 pins: Power and ground pin descriptions Serial EEPROM interface pin descriptions PCI system bus interface pin descriptions Local bus support pin descriptions Table 6-6 through Table 6-8 describe local bus data transfer pins: Mode independent Non-Multiplexed mode Multiplexed mode Table 6-9 and Table 6-10 describe ISA-related pins. Unspecified pins are no connects (NC). The BTERM#, LRDYi#, and NOWS# pins have an 80k ohm internal pull-up resistor on the local. The TEST pin has a 50k ohm internal pull-down resistor on the local side. PIN DESCRIPTION For a visual view of the chip pin layout, refer to Section 8.3, PCI 9052 Pin Out. Table 6-1 lists abbreviations used in this section to represent the various pin types. Table 6-1. Pin Type Abbreviations Input and output pin Input pin only Output pin only Tri-state pin Open collector pin Totem pole pin Sustained tri-state pin, driven high for one CLK before float PLX Technology, Inc., 1997 Page 43 Version 1.0SECTION 6 PCI 9052 Table 6-2. Power and Ground Pin Description (23 pins) PIN DESCRIPTION TEST Test 1 99 Test pin. Pull high for test. Pull low for normal operation. When TEST is pulled high, all outputs except RD# (pin 126) are placed in tri-state. RD# provides a NAND-TREE output when TEST is pulled high. NG Spare N/A 45, 67 Unused. VDD Power 10 I 1, 10, Power supply pins (5 V). see 81 Liberal .01 WF to .1 pF decoupling capacitors should be 103, 121, placed near PCI 9052. 146 VSs Ground 10 9, 26, Ground pins. 40, 51, 65, 80, 104, 120, 147, 160 Table 6-3. Serial EEPROM Interface Pin Description (4 pins) EECS Serial EEPROM Chip Select 1 Oo 142 Serial EEPROM Chip Select. TP 6mA EEDO Serial EEPROM Data Out 1 I 143 Serial EEPROM Read Data. EEDI Serial EEPROM Data In 1 Oo 145 Serial EEPROM Write Data. TP 6mA EESK Serial EEPROM Serial Data 1 Oo 144 Serial EEPROM Clock. Clock TP 6mA PLX Technology, Inc., 1997 Page 44 Version 1.0SECTION 6 PCI 9052 PIN DESCRIPTION Table 6-4. PCI System Bus Interface Pin Description (49 pins) AD[31:0] Address and Data 32 VO 150-157, 2-8, | Multiplexed on the same PCI pins. A bus transaction TS 11, 23-25, consists of an address phase, followed by one or more 6mA 28-32, 34-39, | data phases. PC] 9052 supports both read and write 42-43 bursts. C/BE[3:0}# | Bus Command 4 158, 12, Multiplexed on the same PCI pins. During the address and Byte Enables 22, 33 phase of a transaction, defines bus command. During data phase, used as Byte Enables. For additional information, refer to PCI Specification v2.1. CLK Clock 1 149 Provides timing for all transactions on PCI and is an input to every PCI device. PCI operates up to 33 MHz. DEVSEL# | Device Select 1 oO 16 When actively driven, indicates the driving device has STS decoded its address as the target of current access. 6mA FRAME# Cycle Frame 1 I 13 Driven by the current master to indicate beginning and duration of an access. Asserted to indicate a bus transaction is beginning. While asserted, data transfers continue. When negated, the transaction is in the final data phase. IDSEL Initialization Device Select 1 159 Chip select used during configuration read and write transactions. INTA# Interrupt A 1 Oo 44 Requests an interrupt. oc 6mA IRDY# Initiator Ready 1 I 14 Indicates the ability of initiating agent (bus master) to complete current data phase of transaction. LOCK# Lock 1 18 Indicates an atomic operation that may require multiple transactions to complete. PAR Parity 1 VO 21 Indicates even parity across AD[31:0] and C/BE[3:0]#. TS Parity generation is required by all PCI agents. PAR is 6mA stable and valid one clock after address phase. For data phases, PAR is stable and valid one clock after IRDY# is asserted on a write transaction or TRDY# is asserted on a read transaction. Once PAR is valid, it remains valid until one clock after completion of current data phase. PERR# Parity Error 1 oO 19 Indicates only the reporting of data parity errors during STS all PCI transactions, except during a Special Cycle. 6mA RST# Reset 1 I 148 Brings PCl-specific registers, sequencers, and signals to aconsistent state. SERR# Systems Error 1 oO 20 For reporting address parity errors, data parity errors on oc Special Cycle command, or any other system error 6mA where the result will be catastrophic. STOP# Stop 1 oO 17 Indicates the current target is requesting the master to STS stop current transaction. 6mA TRDY# Target Ready 1 oO 15 Indicates the ability of target agent (selected device) to STS complete the current data phase of transaction. 6mA PLX Technology, Inc., 1997 Page 45 Version 1.0SECTION 6 PCI 9052 PIN DESCRIPTION Table 6-5. Local Bus Support Pin Descriptions (14 Pins) MODE Bus Mode 1 68 Selects bus operation mode of PCI 9052. 1 = Multiplexed Bus mode 0 = Non-Multiplexed mode LINTi4 Local Interrupt 7 In 1 137 When asserted, causes a PCI interrupt. Polarity is determined by INTCSR configuration register. LINTi2 Local Interrupt 2 In 1 136 When asserted, causes a PCI interrupt. Polarity is determined by INTCSR configuration register. LCLK Local Bus Clock 1 135 Local clock up to 40 MHz, and may be asynchronous to PCI clock. LHOLD Hold Request 1 134 Asserted by a local bus master to request use of local bus. LHOLDA Hold Acknowledge 1 oO 133 Asserted by PCI 9052 to grant control of local bus to a TP local bus master. When PCI 9052 needs the local bus, it 6mA signals a preempt by negating LHOLDA. LRESET# Local Reset Out 1 Oo 132 Local bus reset output, asserted when PCI 9052 is reset, TP and used to reset devices on local bus. 6 MA BCLKO BCLK Out 1 oO 63 Indicates a buffered version of the PCI clock for optional TP use by local bus. 24mA CS[1:0]# Chip Selects 2 oO 131, 130 General purpose chip selects. The base and range of TS each may be programmed in configuration registers. 6mA USERO/WAITO# User I/O 0 or WAIT Out 1 VO 138 Can be programmed to be a configurable User I/O pin, TS USERO, or local bus WAIT out pin. WAITO# is asserted 6mA when wait states are caused by the internal wait-state generator. Serves as an output to provide ready-out status. USER1/LLOCKo# | User I/O 1 or LLOCK 1 VO 139 Can be programmed to be a configurable User I/O pin, Out TS USER1, or local bus LLOCK out pin, LLOCKo#. 6mA LLOCKo# indicates an atomic operation that may require multiple transactions to complete and can be used by the local bus to lock resources. USER2/CS2# User I/O 2 or CS2 Out 1 0 140 Can be programmed to be a configurable User I/O pin, TS USER}, or as Chip Select 2 output pin, CS2#. 6mA USER3/CS3# User I/O 3 or CS3 Out 1 0 141 Can be programmed to be a configurable User I/O pin, TS USER3, or as Chip Select 3 output pin, CS3#. 6mA PLX Technology, Inc., 1997 Page 46 Version 1.0SECTION 6 PCI 9052 PIN DESCRIPTION Table 6-6. Local Bus Data Transfer Pins Description (Mode Independent) (7 pins) ADS# Address Strobe 1 oO 123 Indicates valid address and start of a new bus access. TS Asserted for the first clock of a bus access. 12mA ALE Address Latch Enable 1 oO 64 Asserted during the address phase and negated before TS data phase. 6mA LW/R Write/Read 1 oO 127 Asserted high for writes and low for reads. TS 6mA BLAST# Burst Last 1 oO 124 Signal driven by the current local bus master to indicate TS last transfer in a bus access. 6mA RD# Read Strobe 1 oO 126 General purpose read strobe. The timing is controlled TS by current Bus Region Descriptor Register. 12mA WR# Write Strobe 1 oO 125 General purpose write strobe. The timing is controlled TS by current Bus Region Descriptor Register. 12mA LRDYi# Local Ready In 1 I 128 Local ready input indicates read data is on the local bus, or that write data is accepted. Used in conjunction with the programmable wait-state generator. PLX Technology, Inc., 1997 Page 47 Version 1.0SECTION 6 PCI 9052 PIN DESCRIPTION Table 6-7. Local Bus Data Transfer Pins Description (Non-Multiplexed Mode) (63 pins) BTERM# Burst Terminate 1 129 If disabled through PCI 9052 configuration registers, PCI 9052 bursts up to four transactions, Lword transfer depends upon bus width and type. If enabled, PCI 9052 continues to burst until Bterm input is asserted. Ready input which breaks up a burst cycle and causes another address cycle to occur. Also used in conjunction with the wait state generator. LA[27:2] Address Bus 26 oO 122, Carries the upper 26 bits of 28 bit physical address bus. TS 119-105, Increments during bursts to indicate successive data 6mA 102-100, cycles. 98-92 LAD[31 :0] Data Bus 32 0 52-62, Carries 32, 16, or 8 bit data quantities, depending TS 69-79, on bus width configuration. 6mA 82-91 8 bit = LAD[7:0] 16 bit = LAD[15:0] 32 bit = LAD[31:0] LBE[3:0]# Byte Enables 4 Oo 46-49 Byte enables are encoded based on configured bus TS width: 12mA 32-Bit Bus Four byte enables indicate which of the four bytes are active during a data cycle. * LBE3# Byte Enable 3 = LAD[31:24] * LBE2# Byte Enable 2 = LAD[23:16] * LBE1# Byte Enable 1 = LAD[15:8] * LBEO# Byte Enable 0 = LAD[7:0] 16-Bit Bus LBE[3,1:0]# are encoded to provide BHE#, LA1, and BLE#. e LBE3# Byte High Enable (BHE#) = LAD[15:8] e LBE2# Unused e LBE1# Address bit 1 (LA1) e LBEO# Byte Low Enable (BLE#) = LAD[7:0] 8-Bit Bus LBE[1:0]# are encoded to provide LA[1:0]. e LBE3# Unused e LBE2# Unused e LBE1# Address bit 1 (LA1) e LBEO# Address bit 0 (LAO) PLX Technology, Inc., 1997 Page 48 Version 1.0SECTION 6 PCI 9052 PIN DESCRIPTION Table 6-8. Local Bus Data Transfer Pins Description (Multiplexed Mode) (63 pins) BTERM# Burst Terminate 1 129 If disabled through PCI 9052 configuration registers, PCI 9052 will burst up to four transactions, Lword transfer depends upon the bus width and type. If enabled, PCI 9052 continues to burst until BTERM# input is asserted. BTERM# is a ready input that breaks up a burst cycle and causes another address cycle to occur. Also used in conjunction with the wait state generator. LA[27:2] Address Bus 26 Oo 122, Carries the upper 26 bits of 28 bit physical address bus. TS 119-105, During bursts LA[27:2] increments to indicate 6mA 102-100, successive data cycles. 98-92 LAD[31:0] Address/Data Bus 32 VO 52-62, During the address phase, bus carries the upper TS 69-79, 26 bits of 28 bit physical address bus. During the data 6mA 82-91 phase, bus carries 32, 16, or 8 bit data quantities, depending on bus width configuration. 8 bit = LAD[7:0] 16 bit = LAD[15:0] 32 bit = LAD[31:0] LBE[3:0]# Byte Enables 4 oO 46-49 Byte enables are encoded based upon configured bus TS width: 12mA 32-Bit Bus Four byte enables indicate which of the four bytes are active during a data cycle. * LBE3# Byte Enable 3 = LAD[31:24] * LBE2# Byte Enable 2 = LAD[23:16] * LBE1# Byte Enable 1 = LAD[15:8] * LBEO# Byte Enable 0 = LAD[7:0] 16-Bit Bus LBE[3,1:0]# are encoded to provide BHE#, LA1, and BLE#. e LBE3# Byte High Enable (BHE#) = LAD[15:8] e LBE2# Unused e LBE1# Address bit 1 (LA1) e LBEO# Byte Low Enable (BLE#) = LAD[7:0] 8-Bit Bus LBE[1:0]# are encoded to provide LA[1:0]. e LBE3# Unused e LBE2# Unused e LBE1# Address bit 1 (LA1) e LBEO# Address bit 0 (LAO) PLX Technology, Inc., 1997 Page 49 Version 1.0SECTION 6 PCI 9052 PIN DESCRIPTION Table 6-9. ISA Local Bus Data Transfer Pins Description (Non-multiplexed Mode) MEMWR# ; Memory Write 1 oO 131 Command given to a memory slave to latch data TS from the ISA data bus. 6mA MEMRD# Memory Read 1 oO 130 Command given to a memory slave to drive the TS data onto ISA data bus. 6mA IOWR# I/O Write 1 oO 139 Command given to an ISA I/O slave device to latch TS data from the ISA data bus. 6mA IORD# I/O Read 1 oO 138 Command given to an ISA I/O slave device to drive TS data onto the ISA data bus. 6mA SBHE# System Byte High Enable 1 Oo 46 When asserted, indicates that a byte is being TS transferred on the upper byte [15:8] of data bus. 12 mA ISAA[1:0] ISA Address Bus 2 oO 48, 49 ISAA[1:0] are the ISA bus address phase bits. Bits TS [1:0] should be used in conjunction with LA[23:2]. 12mA For 16 bit ISA bus, ISAAO is used as LBE# signal. For 8 bit ISA bus, ISAAO is used as address bit. BALE Bus Address Latch Enable 1 oO 64 Asserted to indicate that the address and SBHE# TS signal lines are valid. 6mA CHRDY Channel Ready 1 I 45 Input from the slave device to indicate that additional time (wait states) is required to complete cycle. Signal goes low when the slave device requires wait states. NOWS# No Wait States 1 67 Input from the slave device to indicate that current cycle can be shortened after the slave has decoded address and command signals. A 16-bit ISA memory or I/O cycle can be reduced by 2 CLKs. An 8-bit memory or I/O cycle can be reduced by 3 CLKs. CHRDY has precedence over NOWS#. LA[23:2] Address Bus 22 oO 116-105, Address bus carries the upper 22 bits of 28 bit TS 102-100, physical address bus. 6mA 98-92 LAD[15:0] Data Bus 16 VO 74-79, Data bus phase. Bus carries 16 bit data quantities TS 82-91 when configured to be 16-bit wide. 6mA LAD[7:0] Data Bus 8 VO 84-91 Data bus phase. Bus carries 8 bit data quantities TS when configured to be 8-bit wide. 6mA PLX Technology, Inc., 1997 Page 50 Version 1.0SECTION 6 PCI 9052 PIN DESCRIPTION Table 6-10. Generic Local Bus Support Pin Descriptions When ISA_MODE Enabled (Non-Multiplexed Mode) MODE Bus Mode 1 68 Select bus operation mode of PCI 9052: 1 = Multiplexed bus 0 = Non-multiplexed bus LINTI4 Local Interrupt 1 1 137 Level Triggered: When asserted causes a PCl interrupt. Polarity is determined by INTCSR configuration register. Edged Triggered: Only for Positive polarity. When asserted causes a PCI interrupt. To clear, refer to INTCSR configuration register (Table 5-45). LINTI2 Local Interrupt 2 1 136 Level Triggered: When asserted causes a PCl interrupt. Polarity is determined by INTCSR configuration register. Edged Triggered: Only for Positive polarity. When asserted causes a PCI interrupt. To clear, refer to INTCSR configuration register (Table 5-45). LCLK Local Bus Clock 1 135 Local clock for ISA 8 MHz, and may be asynchronous to the PCI clock. LHOLD Hold Request 1 134 A local bus master asserts LHOLD to request use of the Local Bus. LHOLDA Hold Acknowledge 1 oO 133 PCI 9052 asserts LHOLDA to grant control of the local TP bus to a local bus master. When the PCI needs local 6mA bus, it can signal a preempt by negating. LRESET Local Reset Out 1 Oo 132 Local Reset Out. When ISA_MODE bit is enabled, the TP signal is active high. It is asserted when PCI 9052 chip 6mA is reset, and used to reset devices on the local bus. Note: LRESET is inverted if ISA mode is enabled. BCLKO BCLK Out 1 oO 63 This is a buffered version of the PCI clock for optional TP use by local bus. 24mA USER2/CS2# User I/O 2 or CS2 Out 1 0 140 This pin can be programmed to be a configurable User TS I/O pin, or as the Chip Select 2 pin. 6mA USER3/CS3# User I/O 3 or CS3 Out 1 0 141 This pin can be programmed to be a configurable User TS I/O pin, or as the Chip Select 3 pin. 6mA PLX Technology, Inc., 1997 Page 51 Version 1.0SECTION 7 PCI 9052 ELECTRICAL AND TIMING SPECIFICATIONS 7. ELECTRICAL AND TIMING SPECIFICATIONS Table 7-1. Absolute Maximum Ratings -65 C to +150 C Storage temperature Ambient temperature with power applied -55 C to +125 C Supply voltage to ground 0.5 V to +7.0V Input voltage (VIN) VSS -0.5 V VDD +0.5 V Output voltage (VOUT) VSS -0.5 V VDD +0.5 V Table 7-2. Operating Ranges Min = VSS Max = VDD 0 C to +70 C 115 C Maximum Table 7-3. Capacitance (sample tested only) VIN=2.0V f= 1 MHz VOUT = 2.0 V f= 1 MHz COUT Output 10 pF Table 7-4. Electrical Characteristics Tested over Operating Range VDD = Min, VIN = VIH or VIL IOH = -4.0 mA IOL per Tables Input High Level _ _ Output High Voltage Output Low Voltage Input Low Level _ _ Input Leakage Current Tri-State Output Leakage Current VSS < VIN < VDD, VDD = Max VSS < VIN < VDD, VDD = Max Power Supply Current VDD = 5.25 V, PCLK = LCLK = 33 MHz PLX Technology, Inc., 1997 Page 52 Version 1.0SECTION 7 PCI 9052 ELECTRICAL AND TIMING SPECIFICATIONS Table 7-5. AC Electrical Characteristics (Local Outputs) Measured over Operating Range LHOLDA ADS# BLAST# LBE[3:0}# LW/R# LAD[31:0] LA[27:2] LRESET# RD# WR# BCLKo 2 7 WAITO# 9.6 LLOCKo# 8 USER[3:0] 5* CS[3:0]# 11 Note: Values followed with an asterisk (*) are referenced from the PCI side. Local fe NN Clock Inputs C Valid > Figure 7-1. PCI 9052 Local Output Delay PLX Technology, Inc., 1997 Page 53 Version 1.0SECTION 7 PCI 9052 ELECTRICAL AND TIMING SPECIFICATIONS Local Bus Input Setup and Hold Times: e Hold time = 2 ns min e Setup time = 8 ns min Local fo NS Clock I VALID ! (Max) | + T > | VALID | I (Min) | Outputs Valid Figure 7-2. PCI 9052 Local Input Setup and Hold Waveform Table 7-6. Clock Frequencies Local Clock Input 0 40 MHz PCI Clock Input 0 33 MHz PLX Technology, Inc., 1997 Page 54 Version 1.0SECTION 8 PCI 9052 PACKAGE, SIGNAL, AND PIN OUT SPECS 8. PACKAGE, SIGNAL, AND PIN OUT SPECS 8.1 PACKAGE MECHANICAL DIMENSIONS For 160-pin PQFP . 31.2+ 0.4 P 28 + 0.1 OLA ANT AN ANAANAATHANAOATAT af \ 0 = How R = Index = : LO- Sa pin J UT TTT OTTTTTT S ' 0.65 +e 03+ 0.1 | y+ Max 0.8 + 0.2 SIT | S \ SUITE, NEw 0-10 Dimensions in millimeters J A 1.6 <t_ Figure 8-1. Package Mechanical Dimensions PLX Technology, Inc., 1997 Page 55 Version 1.0SECTION 8 PCI 9052 PACKAGE, SIGNAL, AND PIN OUT SPECS 8.2 TYPICAL BUS TARGET INTERFACE ADAPTER za Cc J ISA C/ISA i~ ADJ[31:0 ___LADS1:0] __, LAD[31:0] LAD[31:0] LAD[31:0] C/BE[3:0]# LA[27:2 LA[27:2 PAR LBE[S:0]# LBE[S:0]# ISAA[1:O/LBEY LBE[S:0]#/ISAA[{ 0] __FRAME# , LINTi1 LINTi1 __LNTi1 __LINTit __IRDY# , 3 LINTi2 LINTi2 __LINTI2 _LINTi2 _IRDY# LCLK LCLK __LClK __lclK n _STOP# _ 2 LHOLD LHOLD _LHOLD > ps , || LHOLDA, _LHOLDA __LHOLDA y 0 a o Controller _ DEVSEL# 9 ___LRESET# , ___LRESET# , _LRESET , _LRESET , O _PERR# i] ___ BCLKO. BCLKO ___BCLKO_ a. _SERR# 5 cSio]# , CS1:# USEROWAITO#, 4 USEROMWAITO#, USERI/LLOCK#, 4 USER1/LLOCK#, 4 NOWS# = =4 NOWS# 8 DRAM CLK _USER2/CS2# , 4 USER2/CS2# , 4USER2/CS2#, USER2/CS2#, RST# _USER3/CS3#_, 4 USER3/CS3# , 4USER3/(CS34% USER3/CS3#, a oa __INTA# ADS# p ADS# p ADS# , | & an __LocK# , ___ BLAST# 5 __BLAST# __piast#_, | 8 DRAM PCI Whe We wee | NU 9052 |__qDe ,_Ap# , ___RD# __swr# _EESK <__ LRDYi# __LRDYi# _LRDVi# Serial | _EEDO , ___BTERM# __BIERM# __BIERM# EEPROM | _ED! ALE > ALE > BALE, ALE/BALE , ECS MODE gS MODEC=SS SC MODEC=E, XS MODE MEMWR# MEMWR# MEMRD# MEMRD# _, lOWR# lOWR# lORD# lORD# SBHE# SBHE# Figure 8-2. Typical Bus Target Interface Adapter (C, J, ISA, and C/ISA Modes) Page 56 Version 1.0 PLX Technology, Inc., 1997SECTION 8 PCI 9052 8.3 PCI 9052 PIN OUT PACKAGE, SIGNAL, AND PIN OUT SPECS Refer to Section 6, Pin Description, for a complete description of each pin. Cc ISA TEST TEST bE a w E LADO LAD1 LAD3 LAD4 LADS LAD6 LAD7 LADS LAD9 VDD LAD2 LADS LAD7 LADi VDD VDD VDD VDD VSS vss VSS La27 NC NC LADIO LAD10 LADIO ADS# ADS# NC Lap Labi Lap BLAST# BLAST# NC LADI2 LaD12 LADI2 wre wre NC LADI3 LAD13 LADI3 RD# RD# NC LADI4 LaD14 LADI4 Lwin Lwin NC LADI5 LAD15 LADI5 LADVi# LADVi# NC NC LaDi6 LADI6 BTERM# BTERM# NC NC LAD17 LADI7 cso# cso# MEMRD# NC LaDi8 LADI8 csi# csi# MEMWR# NC LAaDi9 LADI9 LRESET# LRESET# LRESET NC LaD20 LAD20 LHOLDA LHOLDA NC MODE MODE MODE LHOLD LHOLD NC Nows# NC NC LOLK LOLK LOLK VDD VDD VDD UNT2 UNT2 LINT2 VSS vss VSS UNTiI UNTiI LINTi BALE ALE ALE USEROWAITO# USEROWAITO# IORD# BCLKo BCLKo BCLKo USERI/LLOCKo# USER1/LLOCKo# IOWR# NC Lap21 LAD21 USER2/CS2# USER2/CS2# USER2/CS2# NC Lap22 LAD22 USER3/CS3# USER3/CS3# USER3/CS3# NC LaD23 LAD23 EECS EECS EECS NC Lap24 LAD24 EEDO EEDO EEDO NC LaD25 LAD25 EESK EESK EESK NC LaD26 LAD26 EEDI EEDI EEDI NC LaD27 LAD27 VDD VDD VDD NC Lap28 LAD28 VSS VSS vss NC LaD29 LAD29 RST# RST# RST# NC LAD30 LAD30 cK cK CLK NC LaDs1 LADS1 AD31 AD31 AD31 VSS vss VSS AD3O AD3O AD30 VDD VDD VDD AD29 AD29 AD29 ISAAO/LBE# LBEO# LBEO# AD28 AD28 AD28 ISAAI LBE1 LBE1# AD27 AD27 AD27 NC LBEQ# LBE2# AD26 AD26 AD26 SBHE# LBES# LBES# AD25 AD25 AD25 CHRDY NC NC AD24 AD24 AD24 INTAE INTA# INTAE C/BES# C/BES# C/BES# ADO ADO ADO IDSEL IDSEL IDSEL ADI ADI ADI VSS VSS vss VDD VDD VDD * * geeeGrsee 3 BEBE eee EE CEeeeee Se Oe STE FT OH OBES eee eS eee ee G AeA aees * * aeeteesee = SSSR SSS GR aR SGC aSSEECHE SE CSREES SSESR Bag Rg Be Oo OO OO EC FAH EGE ORE USO eee Ae SA Ae aaa eh oedsses * % ase ty _ S CENA R SEE Hg CH Sr BeOS EE UOT lHQaM ES gone n zane BAOaAooo Seas ee eae AGEs Pagaggaagaggsgggagag Pattetceqeqq> > fous ravnrtandodaeetcseseaetctcqeecodctaqcaeqacaS Figure 8-3. PCI 9052 Pin Out (C, J, and ISA Modes) Note: LRESET is inverted if ISA mode is enabled. PLX Technology, Inc., 1997 Page 57 Version 1.0SECTION 8 PCI 9052 PACKAGE, SIGNAL, AND PIN OUT SPECS QRRORARSRASSSELSLEILNM yar SohonaownynnS SARBAAREBBO 0999999999999 E99 8999999559559599559558 QQSE SPF OAESSSSSSSSRSSPESSSSHRSSSSSSSERRE voD 421 80 | VSS Lazy 422 79) LADIO ADS# 123 78.) LAD11 BLAST# 124 77 | LADI2 WR 125 76 | LADI3 RD# 128 75 | LADI4 LW/R# 127 74) LADI5 LRDYi# 428 73 | LADIG BTERM# 129 72) LADIT MEMAD# 480. 74:| LADI8 MEMWR# 481 70:| LADI9 LRESET 182 69 | LAD20 LHOLDA 133 68; MODE LHOLD 184 67) NOWS# LCLK 135 66 | VOD LINTI2 136 65 | VSS LINTH 187 64) ALE/BALE lORD# 138 63 | BCLKo lOwRs# 199 PCI 9052 62) LAD2t USERZ/CS2# | 140 61} LAD22 USER3/CS3# | 141 60 | LAD23 EECS 442 50) LAD24 FEDO 143 C/ISA Mode 58 | LAD25 EESK 144 57) LADZ6 EEDI 145 56 | LAD27 VoD +46 5:| LAD2B vss 147 84) LAD29 RST# 148 53) LAD3O CLK 149 52| LADS AD31 160 51 | vss AD30 181 50 | VDD AD29 162 49 | LBEO#/ISAAO AD28 153 48 | LBEI#/ISAAL ADe7 184 47 | LBEO# AD26 165 46 | LBE3#/SBHE# AD25 158 45 | CHRDY AD24 157 44 | INTA# C/BES# 158 43:| ADO IDSEL 159. 42] ADI vss 160 41| VDD OE EI OB OO OO RI O08 OR OED O08 OS: SPN RU OI OO) a orm oe sm NEESER ORE INES ONESEMESINE 00 @0O OOOP OO . * if a % aRNESSEE ya Snes eee Set Toren ak Saad pansaay Bee ee bbOB eo ER REP OHH EZ ES oSeSS SRR SSS8BSSSS -tietcddcadaaer se ec OuFran oanaOQdtad dese acacae ec tcodtcadaacaatS Figure 8-4. PCI 9052 Pin Out (C/ISA Mode) Note: LRESET is inverted if ISA mode is enabled. PLX Technology, Inc., 1997 Page 58 Version 1.0SECTION 9 PCI 9052 TIMING DIAGRAMS 9. TIMING DIAGRAMS PCI 9052 operates in three modes, selected through mode pins, corresponding to three bus typesC, J, ISA. Timing Diagrams are provided for the three operating modes. For some functions, a timing diagram may only be provided for one mode of operation. Although a different mode is used, the timing diagram can be used to determine functionality. 9.1 LIST OF TIMING DIAGRAMS PClI/Local PCI 9052 Initialization Timing Diagram 9-1. Initialization from Serial EEPROM Timing Diagram 9-2. Local Bus Arbitration Timing Diagram 9-3. Local LINTi1# Input Asserting PCI Output INTA# Timing Diagram 9-4. PCI RST# Asserting Local Output LRESET# Timing Diagram 9-5. USER I/O Pin 0 Is an Input Timing Diagram 9-6. USER I/O Pin 0 Is an Output Timing Diagram 9-7. Chip Select 0 PCl/Local Direct Slave Single Timing Diagram 9-8. Direct Slave Single Write (32 Bit Local Bus) Timing Diagram 9-9. Direct Slave Single Read without Wait States (32 Bit Local Bus) Timing Diagram 9-10. Direct Slave Single Read with Wait States (32 Bit Local Bus) PCli/Local Direct Slave Non-Burst Timing Diagram 9-11. Direct Slave Non-Burst Write with Wait States (32 Bit Local Bus) Timing Diagram 9-12. Direct Slave Non-Burst Write (8 Bit Local Bus) Timing Diagram 9-13. Direct Slave Non-Burst Read with BTERM# Enabled (32 Bit Local Bus) Timing Diagram 9-14. Direct Slave Non-Burst Read with Unaligned PCI Address (32 Bit Local Bus) Timing Diagram 9-15. Direct Slave Non-Burst Read with Prefetch (16 Bit Local Bus) Timing Diagram 9-16. Direct Slave Non-Burst Read with Prefetch (8 Bit Local Bus) PCl/Local Direct Slave Burst Timing Diagram 9-17. Direct Slave Burst Write with Delayed Local Bus (32 Bit Local Bus) Timing Diagram 9-18. Direct Slave Burst Write with BTERM# Enabled (32 Bit Local Bus) Timing Diagram 9-19. Direct Slave Burst Write with BTERM# Disabled and Wait States (32 Bit Local Bus) Timing Diagram 9-20. Direct Slave Burst Write with BTERM# Enabled (32 Bit Local Bus) Timing Diagram 9-21. Direct Slave Burst Write (16 Bit Local Bus) Timing Diagram 9-22. Direct Slave Burst Write with BTERM# Enabled (8 Bit Local Bus) Timing Diagram 9-23. Direct Slave Burst Read with Prefetch of Four Lwords (32 Bit Local Bus) Timing Diagram 9-24. Direct Slave Burst Read with Prefetch of Eight Lwords (16 Bit Local Bus) Timing Diagram 9-25. Direct Slave Burst Read with Prefetch of Four Lwords (8 Bit Local Bus) PCI/Local Miscellaneous Functionality Timing Diagram 9-26. Direct Slave Write PCI Spec v2.1 Timing Diagram 9-27. Direct Slave Read PCI Spec v2.1 Timing Diagram 9-28. Direct Slave Read with Read Ahead Mode Enabled Timing Diagram 9-29. Read Ahead Mode Timing Diagram 9-30. PCI Lock Mode PLX Technology, Inc., 1997 Page 59 Version 1.0SECTION 9 PCI 9052 TIMING DIAGRAMS PCl/Local Big Endian Mode and Multiplexed Local Bus (J Mode) Timing Diagram 9-31. Timing Diagram 9-32. Timing Diagram 9-33. Timing Diagram 9-34. ( ) . Direct Slave Burst Read and Multiplexed Local Bus (32 Bit Local Bus, J Mode) ( ) Timing Diagram 9-35 Timing Diagram 9-36. ISA Timing Diagram 9-37. Timing Diagram 9-38. Timing Diagram 9-39 Timing Diagram 9-40 Timing Diagram 9-41. Timing Diagram 9-42. Timing Diagram 9-43. Timing Diagram 9-44. Timing Diagram 9-45. Timing Diagram 9-46. Timing Diagram 9-47. Direct Slave Single Write to 32 Bit Local Bus Big Endian and Multiplexed Local Bus (J Mode) Direct Slave Single Read from 32 Bit Local Bus Big Endian and Multiplexed Local Bus (J Mode) Direct Slave Burst Write and Multiplexed Local Bus (32 Bit Local Bus, J Mode) Direct Slave Burst Write and Multiplexed Local Bus (16 Bit Local Bus, J Mode Direct Slave Burst Read and Multiplexed Local Bus (16 Bit Local Bus, J Mode 8 Bit Memory Read/Write Standard ISA Cycle (6 LCLK Shown) 8 Bit Memory Read/Write Extended ISA Cycle (7 LCLK Shown) . 8 Bit Memory Read/Write Compressed ISA Cycle (3 LCLK Shown) . 8 Bit VO Read/Write Standard ISA Cycle (6 LCLK Shown) 8 Bit /O Read/Write Extended ISA Cycle (7 LCLK Shown) 8 Bit /O Read/Write Compressed ISA Cycle (3 LCLK Shown) 16 Bit Memory Read/Write Standard ISA Cycle (8 LCLK Shown) 16 Bit Memory Read/Write Extended ISA Cycle (4 LCLK Shown) 16 Bit Memory Read/Write Compressed ISA Cycle (2 LCLK Shown) 16 Bit /O Read/Write Standard ISA Cycle (3 LCLK Shown) 16 Bit I/O Read/Write Extended ISA Cycle (4 LCLK Shown) PLX Technology, Inc. , 1997 Page 60 Version 1.0SECTION 9 PCI 9052 TIMING DIAGRAMS 9.2 PCI/LOCAL TIMING DIAGRAMS 9.2.1 PCI 9052 Initialization Ous 5us 10us 15us 20us 25us bo | J | bo | J | bo | J | bo | J | EESK LJ LIU LU UU UU UU UU LRESETo# | EECS | EEDI o/i[ijfojojojojojojo EEDO { 0 |D15]D14] D13| D12] D114] Dio] De] Ds] D7| De] D5] D4] D3] D2] D1 | Do START BIT 0 INDICATES SERIAL EEPROM PRESENT ----| BITS [31:16] CFG REGISTER 0 HEX INTERNALLY PULLED UP EESK JUUUUUUU UU U2 EEDO [015/014] p13] D19.D11| Dio] Dg | Ds | D7 | D | D5| D4] D3] D2] D1 | De | D15| D14]D13] D12] D11] Did D9 | Ds] D7] D] D5 | D4] D3 BITS [15:0] CFG REGISTER 0 HEX BITS [31:16] OF CFG REGISTER 8 HEX CONTINUES EESK(continues) EECS EEDO _ [p15|p14| D13|D12/D11]D10| Dg | Ds] D7| D | D5] D4] D3] D2] D1] Do LAST WORD EESK, EEDO, EECS FROM CFG REGISTERS AFTER COMPLETION OF READ CONTINUES Timing Diagram 9-1. Initialization from Serial EEPROM PLX Technology, Inc., 1997 Page 61 Version 1.0SECTION 9 PCI 9052 TIMING DIAGRAMS Ons 250ns 500ns | | | | | | | | | | LOLK VS \S VS NS NS NS NS NS NI NS NS NSN NS NI NS NI NI NY NS NG LHOLD / \ / Should not be re-asserted until LHOLDA goes low LHOLDA / LOCAL BUS [Pc 9052 Drives the Local Bus Local Bus Master Drives the Bus PCI 9052 Drives the Local Bus Timing Diagram 9-2. Local Bus Arbitration FRAME# \ / BIT[2]=1 INDICATES LINTit IS.ACTIVE AD[31:0] { ADDR X x X Data} C/BE[3:0]# { cmp X BYTE, ENABLES }_________1 IRDY# \ f/. | DEVSEL# a TRDY# \ Sf] INTA# \ RESPONSE ON THE PCI SIDE LcK_/ \/S\S VS VS VS VS VS VS NS NS NS NS WS LINTi1, LINTi2 \ LINTH1, LINTI2 ARE ACTIVE LOW LINTi1, LINTi2 / LINTH, LINTi2 ARE ACTIVE HIGH Timing Diagram 9-3. Local LINTi1# Input Asserting PCI Output INTA# PLX Technology, Inc., 1997 Page 62 Version 1.0SECTION 9 PCI 9052 TIMING DIAGRAMS RST# \ Asynchronous LOK __/ \__S \ SSNS TTT LRESET# \ Asynchronous to LCLK Timing Diagram 9-4. PCI RST# Asserting Local Output LRESET# FRAME# ~\_/ \/ \/ LW USERO IS INPUT DATA DATA AD[31:0] AX_X_ XOX XAX DD) (AX _X BITI2]=) (AX_X BIT21=9 CMD CMD CMD CMD C/BE[3:0]# IRDY# ~ \ [ \ [-.-\ /. a DEVSEL# ~ \___/ \__/ \__S _/ TRDY# \/ / / / LHOLD LHOLDA ADS# BLAST# LA[27:2] LAD[31:0] LRDYi# USER[3:0] \ USER I/O [3:0] PIN IS AN INPUT / Timing Diagram 9-5. USER I/O Pin 0 Is an Input PLX Technology, Inc., 1997 Page 63 Version 1.0SECTION 9 PCI 9052 TIMING DIAGRAMS Ons 250ns 500ns 750ns 1000ns 1250ns rotot tt Et tot tT rot ET UE UE UU FRAME# ~\_/ \/ \/ \/ USERO SET AS OUTPUT DATA DATA AD[31:0] ~aX_D__) (AX Dd) (AX BITISI=0_} (AX _BITIS]=1_) CMD CMD CMD CMD C/BE[3:0]}# {_X___BE__ (X- BE) (xX BE) ( X BE.) IRDY# \ / \ / \ / \ / DEVSEL# \___/ \ / \ / TRDY# \/ \/ \/ \/ LHOLD LHOLDA ADS# BLAST# LA[27:2] LAD[31:0] LRDYi# USER[3:0] \_USER V/O [3:0] PIN IS AN OUTPU// Timing Diagram 9-6. USER I/O Pin 0 Is an Output PLX Technology, Inc., 1997 Page 64 Version 1.0SECTION 9 PCI 9052 TIMING DIAGRAMS FRAME# __\. / AD[31:0] {_anpr X DO X_or X_o2 X 03) C/BE[3:0}# t{_cwo X BE ) IRDY# \ / DEVSEL# \ / TRDY# \ / LcK {VL SVS VS VSI NS NS NS NS NS NS VS NS NS NS NS LHOLD LHOLDA ADS# \___/ V___ BLAST# ee \ LA[27:2] { ADDR XK +4 X 48 XK +12 X LAD[31:0] { po X di. X D2 X D3 } LRDYi# \ [iY CS[3:0]# \ [ LBE[3:0]# { LBE }_ WR# \ RD# LW/R# \ CSO0# Base Address is in the range of Space 0 CSO# is asserted same for the other chip selects Timing Diagram 9-7. Chip Select 0 PLX Technology, Inc., 1997 Page 65 Version 1.0SECTION 9 PCI 9052 TIMING DIAGRAMS 9.2.2 Direct Slave Single Ons 100ns 200ns AD[31:0] {__abpr_ X DATA ) C/BE[3:0]}# __cup_ X BE } IRDY# ... (CS DEVSEL# \ / TRDY# \ PERR# STOP# tCK_/\/SVSVSYSNYS YSIS VS VS NI AVY LHOLD LHOLDA ADS# Lf BLAST# Lf. LA[27:2] { ADDR X Ava. } LAD[31:0] {_ DATA_}_ LBE[3:0}# LBE LRDYi# Lf USERO/WAITO# RD# WR# YL ft LW/R# Single write, 32 bit local bus, without wait states Space 0 is mapped to I/O Address-to-data = zero wait state Data-to-data = zero wait state Read strobe = zero wait state Timing Diagram 9-8. Direct Slave Single Write (32 Bit Local Bus) PLX Technology, Inc., 1997 Page 66 Version 1.0SECTION 9 PCI 9052 TIMING DIAGRAMS CLK VS VS VSI VSI NS NS NS NS NS NS NS NS NS NI NS NS FRAME# AD[31:0] C/BE[3:0}# IRDY# DEVSEL# TRDY# PERR# STOP# LOK f\S\S\S\VS\VSINVI VSS NS NSN NI NS NS NI NS Ons ; | tod 100ns 400ns es es ee OO | UY _{{_cmp X BE Oe [ NN _ \__/ LHOLD LHOLDA ADS# \_/ BLAST# \__/ LA[27:2] { ADDR 7 LAD[31:0] {DATA } LBE[3:0}# LBE LRDYi# \___/ USERO/WAITO# RD# L_/ WR# LW/R# LV / Single read, 32 bit local bus, without wait states Space 0 is mapped to I/O Address-to-data = zero wait states Data-to-data = zero wait states Read strobe = zero wait states Timing Diagram 9-9. Direct Slave Single Read without Wait States (32 Bit Local Bus) PLX Technology, Inc., 1997 Page 67 Version 1.0SECTION 9 PCI 9052 TIMING DIAGRAMS CLK VS VS VSI VSI NS NS NS NS NS NS NS NS NS NI NS NS FRAME# AD[31:0] C/BE[3:0}# IRDY# DEVSEL# TRDY# PERR# STOP# LOK f\S\S\S\VS\VSINVI VSS NS NSN NI NS NS NI NS Ons ; | tod 100ns Pr | | otto 400ns ee ee ee | "_/ _{{_cmp X Oe ~N BE LHOLD LHOLDA ADS# \_/ ALE /\ BLAST# Ve fT LA[27:2] { ADDR X +4 LAD[31:0] oe LBE[3:0]# { LBE LRDYi# L/S USERO/WAITO# RD# a WR# LW/R# \ [| Single read, 32 bit local bus, with wait states Space 0 is mapped to I/O Address-to-data = zero wait states Data-to-data = zero wait states Read strobe = zero wait states Timing Diagram 9-10. Direct Slave Single Read with Wait States (32 Bit Local Bus) PLX Technology, Inc., 1997 Page 68 Version 1.0SECTION 9 PCI 9052 TIMING DIAGRAMS 9.2.3 Direct Slave Non-Burst Ons 250ns 500ns 750ns 1000ns 1250ns | FRAME# \ / ADDR AD[31:0] {__X__Do_Xp7}zXb3 CMD C/BE[3:0}# ~_X.8e_) IRDY# _\__ DEVSEL# \____/ TRDY# \. / PERR# STOP# LHOLD LHOLDA ADS# \/ \/ \/ \/ ALE il fl I ADDRESS-TO-DATA WAIT STATE BLAST# \ IN NN LA[27:2] ___{ ADDR xX +4 X +8 X +6 \ LAD[31:0]) _ DO YH Di HX D2 \ D3 \ LBE[3:0}# ____+{ LBE yy LRDYi# \/ \/ \/ \/ WAITO# ~ <CSCSC:~:~COCCC NN eeeSSFti<C;7~ Rh hh UU PY!!hlUl UL S!t!tltUC ELrtttCisY RD# WRITE STROBE WAIT STATE WR# \ I NN LW/R# Non-burst write of four Lwords 32 bit local bus, BTERM+# is disabled Address-to-data = five wait states Data-to-data = one wait state Write strobe = three wait states Write cycle hold = two wait states Timing Diagram 9-11. Direct Slave Non-Burst Write with Wait States (32 Bit Local Bus) PLX Technology, Inc., 1997 Page 69 Version 1.0SECTION 9 PCI 9052 TIMING DIAGRAMS Ons 250ns 500ns 750ns 1000ns FRAME# = \ / ADDR ADI31 0) ope[so# X=) IRDY# \ / DEVSEL# \ / TRDY# \ / PERR# STOP# LHOLD LHOLDA ADS# LS LS L/S L/ LS / LS J BLAST# \ JS \ Sy \ [ \_Ss \_S VS VTS LA[27:2] __{ ADDR X 7 LAD[31:0] { - - - HH -H H. 1H LBE[3:0}# _{{ c Xo x E X FOX c X po. Xx E X] LRDYi# LS L/S LS / / _/ LS BTERM# RD# WR# LW/R# / WAITO# \S L/S \S S/S LS LS \S Non-burst write of five Lwords 8 bit local bus Address-to-data = one wait state Data-to-data = zero wait states Two wait states = WR# non-asserted Write hold cycle = one wait state Timing Diagram 9-12. Direct Slave Non-Burst Write (8 Bit Local Bus) PLX Technology, Inc., 1997 Page 70 Version 1.0SECTION 9 PCI 9052 TIMING DIAGRAMS Ons 250ns 500ns 750ns | | | | | | | | | | | | | | | CLK WA. PAD AAA DD APDAD DD PDPDPDPDD DDD PDD DDD DIS FRAME# \ fT apis1:0) _) { a ( Di X D2 C/BE[3:0]# ry BE IRDY# \ f. DEVSEL# \ f TRDY# \_/ \_/ \_/ \_/ LHOLD J LHOLDA [| 3 DATA-TO-ADDRESS WAIT STATES ADS# \_S/ \_/ \_/ \_/ \_S ALE /\ /\ /\ /\ /\ BLAST# \_/ \ | \_/ LS LS LA[27:2] _(_anpr_X vA 8 x e x 710 x LAD[31:0] (00) (7) ) (03) (05) LRDYi# \_/ \_/ \_/ LS \_/ LBE[3:0} _____-/ (BE }_ BTERM# RD# \_/ \_/ \_S/ \_/ \S/ WR# LWR# [1 Direct slave read from Space 1 Burst disabled, BTERM# enabled Local bus: Little Endian, 32 bit Data-to-address = three wait states Write strobe = zero wait states Write cycle hold = zero wait states Timing Diagram 9-13. Direct Slave Non-Burst Read with BTERM# Enabled (32 Bit Local Bus) PLX Technology, Inc., 1997 Page 71 Version 1.0SECTION 9 PCI 9052 TIMING DIAGRAMS Ons 250ns 500ns AD[381:0] {ADDR} {DATA} C/BE[3:0]# { cmpX CBE[3:0}# }_ IRDY# <C~SY f. | DEVSEL# =S=sS<OY {| TRDY# \__/ PERR# STOP# ONLY ONE LWORD TRANSFERRED LEK A.A PA DDD PPP PPP PL PPP PPS LHOLD LHOLDA ADS# \_/ \_/ BLAST# \_/ \_/ LA[27:2] { ADDR X av X ADDRESS-TO-DATA DO[15:0] Do[31:16] LAD[31:0] =, {>} LBE[3:0]# { LBE x LBE X Lee | .______ LRDYi# \_/ \__/ WAITO# \ / \ / BTERM# RD# \ { \ / WR# LWR#t - / 16 bit local bus Address-to-data = two wait states Data-to-data = zero wait states Read strobe = zero wait states Timing Diagram 9-14. Direct Slave Non-Burst Read with Unaligned PCI Address (32 Bit Local Bus) PLX Technology, Inc., 1997 Page 72 Version 1.0SECTION 9 PCI 9052 TIMING DIAGRAMS Ons 250ns 500ns 750ns 1000ns I I I I I I I I I I I I I I I I I I CLK AD) PAD PDDPPPPPPPPPPPPPPPPPPPPPPPPLP PP PP ITI FRAME# ~\ ADDR AD[31:0] _} CMD C/BE[3:0]# {_X BE X BE X BE X BE IRDY# \ DEVSEL# \ TRDY# \/ \/ \/ PERR# | Do x D1 x b2 3 on CULUS STOP# LOLK A)\ {DADA DDD DADA DDD DDN LHOLD LHOLDA ADS# VS VS NS NSA NS NS NS NS ALE f] f i] i I] I I] I] BLAST# LSJ NS NS NS NS NS NS NS LA[27:2]). @______{ ADDR X At4 X A+8 x A+C } ADDRESS|TO-DATA WAIT STATE [15:0] DO[S1:16] D1[15:0] - D1[st:16] D215:0] 28116] - Ds[15:0] _ Dafst-16] LAD[31:0] ()_)_)_ C )_)>_> LBE[3:0]# { [a X%- 6 X- 4 X 6 XK 4 XX 6 KX 4 KX 6 X LRDY i# VJ NS NS NSA NS NS NSA NS LW/R# \ WAITO# tS NS NS NS NSF NS NS NS BTERM# READ STROBE WAIT STATE RD# VJ NS NS NSA NS NS NS NS WR# Address-to-data = one wait state Non-burst read of four Lwords Prefetch four Lwords 16 bit local bus Data-to-data = one wait state Read strobe = one wait state Timing Diagram 9-15. Direct Slave Non-Burst Read with Prefetch (16 Bit Local Bus) PLX Technology, Inc., 1997 Page 73 Version 1.0SECTION 9 PCI 9052 TIMING DIAGRAMS Ons 495ns 990ns 1485ns | | | | | | | | | | | | | | | om MUTT TUAAIT VARI QUQTAVOOQNQOWHOQOQHVOQK TOOHQOQTVOGQHQOWHVOQOQIVOWH OOOOH GORI VON QOyHVOWOnTVOQTOVOD VGOnITOWnQOyTVOWE FRAME# / D4 DO X Di 4 D2 XY D3 X} BE \_________ B- Oo a AD[31:0] 0 oO = Oo C/BE[3:0}# IRDY# Jia DEVSEL# TRDY# \/ V/ V/ V/ \/ PERR# STOP# LCLK | LHOLD | LHOLDA | ADS# | ALE | BLAST# | LA[27:2] | LAD[31:0] | LBE[3:0]# . LRDYi# | BTERM# WR# RD# | LWIR# WAITO# | Timing Diagram 9-16. Direct Slave Non-Burst Read with Prefetch (8 Bit Local Bus) PLX Technology, Inc., 1997 Page 74 Version 1.0SECTION 9 PCI 9052 TIMING DIAGRAMS 9.2.4 Direct Slave Burst Ons 250ns 500ns AD[31:0] 4apprX_ bo X bi KX D2-X D3 X v4 } C/BE[3:0]}# +_cmpX BE } IRDY# \ [ DEVSEL# \ [ TRDY# \ / LOLK Sf \S\S\S VS NS NS NI NSN NTN NS NI NS NI NS NS NS NS NG LHOLD _/ \ LHOLDA .___/ ~~ ~-DELAYEDLOCALBUS._+\ ADS# \_/ BLAST# ee LA[27:2] { ADDR XK +4 X 48. X 4c X +10 }J LAD[S1:0] LBE[3:0]# { LBE }_ LRDYi# \ / RD# WR# \ / LW/R# / Timing Diagram 9-17. Direct Slave Burst Write with Delayed Local Bus (32 Bit Local Bus) PLX Technology, Inc., 1997 Page 75 Version 1.0SECTION 9 PCI 9052 TIMING DIAGRAMS Ons 250ns 500ns | | | | | | | | | | | | Cl VAT AT AT AT AT AC AC ATAU AC ATAU Rene Rene ne Renee nene nent FRAME# \ / AD[31:0] (ADD _Do:X D1 X D2X D3X D4 X Ds X_DsX D7 X DsX D9XD10XD11 C/BE[3:10}# BE ) IRDY# \ DEVSEL# \ TRDY# \ ~S ~S LOLK S\SV\SV\S VSN VDD VP VDD VPI PI POI VPI VPP SN NG LHOLD LHOLDA ADS# \_/ ALE /\ BLAST# LS LA[27:2] LD[31:0] LRDYi# \ [| LBE[3:0}# { LBE RD# WR# \ [| LW/R# For Space 2 (same for Space 0, 1, and 3, and expansion ROM) Local bus: Little Endian, 32 bit Burst enabled (burst write of 12 Lwords), BTERM# enabled Timing Diagram 9-18. Direct Slave Burst Write with BTERM# Enabled (32 Bit Local Bus) PLX Technology, Inc., 1997 Page 76 Version 1.0SECTION 9 PCI 9052 TIMING DIAGRAMS Ons 250ns 500ns 750ns | | | | | | | | | | | | | | | OLAV AV AVAVAUAVAVAVAVAVAUAUAUAUAUAUAVAVAVAVAVAVAVAVAUAUAUAVAVAVAVAT FRAME# ~ \ / ADDR AD[31:0] (__XDoX'D1X b2X DsXD4XD5X D6 XK D7X DX D9XD 10X01 C/BE[3:0]# ry BE IRDY# ~~-\ DEVSEL# ~~~ TRDY# \ Nae s oN ON LOLK JS\/.\/\P\/\ PPL PL PPI PP PPP LPPPLPPPPPPIIVISING LHOLD / LHOLDA / | 2 DATA-TO-ADDRESS WAIT STATES ADS# YS \/ \_/ ALE /\ /\ /\ BLAST# \ J \_/ \/ LA(27:2] Ho KKK _120___KaaXeziXi2d LD[31:0] DOK DIX De D3 (BeXD5\D8XD7) (aX DaXD10No11) LRDYi# Nf RD# WR# VN PNY LW/R# LBE[3:0]# { LBE X -tBE X LBE X _LBE xX LBE }_ For Space 2 (same for Space 0, 1, and 3, and expansion ROM) Local bus: Little Endian, 32 bit Burst enabled (burst write of four Lwords), BTERM# disabled Data-to-address = two wait states Timing Diagram 9-19. Direct Slave Burst Write with BTERM# Disabled and Wait States (32 Bit Local Bus) PLX Technology, Inc., 1997 Page 77 Version 1.0SECTION 9 PCI 9052 TIMING DIAGRAMS FRAME# ~~ / AD[31:0] (_ anor X_bo X_bi X_p2 Xs X_ps } C/BE[3:0}# t{_cmoX BE } IRDY# t<iCS~~.. \ / DEVSEL#~ = COst<iS~~OC(N / TRDY# ~~ / LcK _/\S\S\VS VS VSINVSI NSIS NS NS NS NS NS NS NSN LHOLD LHOLDA ADS# YK / ALE /\ BLAST# \ / LA[27:2] { ADDR X +4. XK 48 X sc KX +10 X LAD[31:0] { po X bi. X be xX v3 xX D4 } LBE[3:0]# { LBE }+ LRDYi# \ / | LW/R# RD# WR# \ [| BTERM# Local bus: Little Endian, 32 bit Burst enabled (burst write of five Lwords), BTERM# enabled Address-to-data = zero wait states Data-to-data = zero wait states Write strobe = zero wait states Write cycle hold = zero wait states Timing Diagram 9-20. Direct Slave Burst Write with BTERM# Enabled (32 Bit Local Bus) PLX Technology, Inc., 1997 Page 78 Version 1.0SECTION 9 PCI 9052 TIMING DIAGRAMS CLK VDD. DPPPLPPPPPPPPPPLPPPPPPPLPPPLPPPPPPLTITIVIN Ons | | | | | | | | | | | | 1000ns | FRAME# = \ A ADDR AD[31:0] {__X__Do__ XD1XD%X 3 CMD C/BE[3:0]# {_X BE ) IRDY# \ / DEVSEL# \ / TRDY# t<iiC slr PERR# STOP# LOLK /\/\/)\P/\PPPPPLPPPPPP PIP PPPPPPIPPPIPIDP LIVI LHOLD LHOLDA ADS# LS BLAST# \S | LA[27:2] _________{ ADDR x +4 X +8 \ +0 \ LAD[31:0] { Doi5:0) XX Do[si:i6] KX Di[15:0] Di[3i:16].X D2[15:0] X D2[31:16] X D3[15:0] XK D3[31:16] } LBE[3:0]}4# +++ 4. X. 6 X-4 KX 6 KX 4 KX 6 KX 4 XX 6} LRDYi# \IJO NS ONS NS NS NS NS NTS WAITO# \ /\ {\ [\_/ \_/ \ [ / \ / RD# WR# \ / | LW/R# Burst enabled (burst write of four Lwords) Address-to-data = four wait states Data-to-data = two wait states Write strobe = one wait state Write cycle hold = zero wait states Timing Diagram 9-21. Direct Slave Burst Write (16 Bit Local Bus) PLX Technology, Inc., 1997 Page 79 Version 1.0SECTION 9 PCI 9052 TIMING DIAGRAMS CLK V/V/V P/V. PPV PPP \ PPP PPI PL PIF FRAME# AD[31:0] C/BE[3:0]# __X BYTE ENABLE ) IRDY# DEVSEL# TRDY# PERR# STOP# LOLK /\/\/\/\ JP/JP /\ PIPPI PPI PIPPI LHOLD LHOLDA ADS# ALE BLAST# LA[27:2] LAD[31:0] LBE[3:0}# LRDYi# USERO/WAITO# BTERM# RD# WR# LW/R# Ons 250ns 500ns | | | | | | | | | 750ns | | | ~\S ADDR (__X__b0 oi 2X6) CMD oN UM Y a ee LS LS /\ /\ an ADDR 4 A+4 X \S | xX] A+8 xX A+G \ C XOXEXFXCKX D KEKFEXRCKOXEXEKCKOXKEXE ) / Burst enabled (burst write of four Lwords), BTERM# enabled Timing Diagram 9-22. Direct Slave Burst Write with BTERM# Enabled (8 Bit Local Bus) PLX Technology, Inc., 1997 Page 80 Version 1.0SECTION 9 PCI 9052 TIMING DIAGRAMS CLK FRAME# AD[31:0] C/BE[3:0]# IRDY# DEVSEL# TRDY# PERR# STOP# LCLK LHOLD LHOLDA ADS# ALE BLAST# LA[27:2] LAD[31:0] LBE[3:0}# LRDYi# USERO/WAITO# BTERM# RD# WR# LW/R# Ons 100ns 200ns 300ns 400ns 500ns Pt to tot TE EE Eo or te EE dE a { appr) Do + cmd X BE | { ADDR X +4 X 48 XK 4c X x } DO D3 LBE \ oot Local burst Address-to-data = zero wait states Data-to-data = zero wait states Read strobe = zero wait states Timing Diagram 9-23. Direct Slave Burst Read with Prefetch of Four Lwords (32 Bit Local Bus) PLX Technology, Inc., 1997 Page 81 Version 1.0SECTION 9 PCI 9052 TIMING DIAGRAMS Ons 250ns 500ns 750ns | | | | | | | | | | | | | | CLK V/V/V V/V/V PP PIPPI PI PII PI. PI PIPING FRAME# ~ \ /...... 4 ADDR AD[31:0] {_) {oppo X bei X pre X pps X op4 XK Ps C/BE[3:0]# x BE IRDY# ~~ OS, / DEVSEL# \ [| TRDY# LSVLSVS NS NVI NS NST PERR# STOP# LOLK /\/\/\/\/ VII VPI PP PI PI PI PUI III IYI WPI PILI LHOLD LHOLDA ADS# \_/ ALE /\ BLAST# \_/ LA[27:2] __{ ADDR X X X X X X X X ADDRE$S-TO-DATA WAIT STATE LAD[31:0] LBE[3:0}# __{{_ [4X6 X4X6X4X6X 4X6 XOX 4X6 X4X EX 4 XK 6X 4 )-_ LRDYi# \ {4 LWIRt 7 t~<isTCCSNY /.. 4 WAITO# \_/ READ STROBE WAIT STATE RD# \ [Oo WR# Burst read seven Lwords Address-to-data = one wait state Data-to-data = zero wait states Read strobe = three wait states Timing Diagram 9-24. Direct Slave Burst Read with Prefetch of Eight Lwords (16 Bit Local Bus) PLX Technology, Inc., 1997 Page 82 Version 1.0SECTION 9 PCI 9052 TIMING DIAGRAMS FRAME# AD[31:0] C/BE[3:0}# IRDY# DEVSEL# TRDY# PERR# STOP# LCLK LHOLD LHOLDA ADS# BLAST# LA[27:2] LAD[31:0] LBE[3:0]# LRDYi# WAITO# BTERM# RD# WR# LW/R# Ons | | > 4 oO aD 0 Qo = o 500ns ee 1250ns ao DO x D1 x Je BE Direct slave Burst read four Lwords 8 bit local bus Address-to-data = one wait state Data-to-data = one wait state Read strobe = zero wait states Timing Diagram 9-25. Direct Slave Burst Read with Prefetch of Four Lwords (8 Bit Local Bus) PLX Technology, Inc., 1997 Page 83 Version 1.0SECTION 9 PCI 9052 TIMING DIAGRAMS 9.2.5 Miscellaneous Functionality Ons 250ns 500ns 750ns 1000ns 1250ns bP | tT to tE ETE Eo Eo tro Ee Ee Ee EE FRAME# ~~ \ / AD[31:0] C/BE[3:0]# ry BE } IRDY# / DEVSEL \ / TRDY# ~~ \ / PERR# STOP# \ DROP BUS MODE LHOLD / \ LHOLDA / DELAYED LOCAL BUS \ ADS# \/ ALE I] BLAST# \/ | LA[27:2] LAD[31:0] LBE[3:0]# { LBE }- LRDYi# \ _ LW/R# RD# WR# \ [| Timing Diagram 9-26. Direct Slave Write PCI Spec v2.1 PLX Technology, Inc., 1997 Page 84 Version 1.0SECTION 9 PCI 9052 TIMING DIAGRAMS Ons 250ns 500ns 750ns 1 | | | | | | | | | | | | | | | | CLK PD). /)PD DPD PPD PLPPPLPL PPD PLPPPLPLPPPPPPIN FRAME# ~\ / \_/ \ / \_/ ADDR ADDR ADDR ADDR AD[31:0] {_} {_) ( Do D1D2X 3X D4X D5XD6XD7X\D8) (~ Xbo) CMD CMD CMD CMD C/BE[3:0]}# {_X__Be (_} {xX BE (__XBEX_] IRDY# ~\ / \ / \_/ DEVSEL# ~. \ / \/ \ / \/ TRDY# \ / \_/ PERR# RETRY RETRY STOP# ~.\ [ \_/ DELAYED READ ENTRIES WRITE IS NOT ALLOWED DURING READS DATA WRITE RETRIES AND DELAYED READ COMPLETES LOLK D\/)\/).\ PD /PL PLD PLD PPPPPPLPL PP PP PLP PPLIPILI LHOLD LHOLDA ADS# \_/ ALE /\ fT BLAST# \_/ LA[27:2] LAD[31:0] { boX D1 XDeXD3X D4 YX DsX D4 NX D7 ds KX Da XD10X011XDI2XDI1sX014 X15) LBE[3:0]4 __{ LBE } LRDY# ~~ |... \ / WR# RD# = = =tstiCSC;~O;;;;~;..CO:C~SN / LWIR# 7 = t<iaiC / Disconnect immediately for a read Does not effect pending reads when write cycle occurs Does not flush the read FIFO if PCI ready cycle completes Force Retry on write if read pending Negate TRDY# until space is available in the direct slave write FIFO Timing Diagram 9-27. Direct Slave Read PCI Spec v2.1 PLX Technology, Inc., 1997 Page 85 Version 1.0SECTION 9 PCI 9052 TIMING DIAGRAMS CLK FRAME# AD[31:0] C/BE[3:0}# IRDY# DEVSEL# TRDY# PERR# STOP# LOK /\/)\/\D)\/D\PL\ PD PDDPDJLPPLIPIPYIPLIPPIPIPLPISPUIIY LHOLD LHOLDA ADS# ALE BLAST# LA[27:2] LAD[31:0] LRDYi# RD# LW/R# USERO/WAITO# BTERM# LBE[3:0}# Ons 250ns 500ns 750ns | | | | | | | | | | | | | | | | WAVAVAVAVAVAVAVAVAVAVAVAVAVACAVAUAVAVAVAVAVAVAUAVAVACAUAVACAVAVAL | ADDR CMD BE a | a 3) | | READS PREFETCHED DATA IN FIFO LS /\ \_/ FAB 08 KAKA KAA ok biXeX 03 XOX D5 D6XD7) CN NY \ / | LBE ee Direct slave read for Space 0 (same for Space 1, 2, and 3, and expansion ROM) Prefetch eight Lwords 32 bit local bus Timing Diagram 9-28. Direct Slave Read with Read Ahead Mode Enabled PLX Technology, Inc., 1997 Page 86 Version 1.0SECTION 9 PCI 9052 TIMING DIAGRAMS Ons 250ns 500ns 750ns 1000ns 1250ns 1500ns Pt tt tt dt tt tt te tt tet tt te de tb te te ct Pc a dd CLK VWWVYW)IVVY/VJVJJVVI/IYIVIVIVVIYIVVIWWVVVVV9 FRAME# 7\/ \ {FT {,_ ADDR Do ADDR +4 = D1D2 D3D4 ADDR+8 D5 D6 D7 D8 AD[31:0] } C1) ()-000.Q2777>9)- ->]-]-]--{ + 000-_ CMD CMD C/BE[3:0]# ~X BE) (X_ BE__) (xX BE) IRDY# \ NT [FT f DEVSEL# ~\ / \ / Lf TRDY# \/ \ / a LOLK AMVWWVVAVVJYVVYYYYV VV VV VWI ADS# \/ \/ \/ BLAST# \/ \/ 44484410 LA[27:2] ( ADDRX KX XXX XK) XXXX X XX] DO D1 D2 D3D4 D5D6D7 D8 bs LAD[31:0]) XXQ00 0X) OOOO XX] LBE[3:0]# -{+ LBE - LRDYi# \ / \ / RD# \ / \ / WR# LW/R# \ Timing Diagram 9-29. Read Ahead Mode PLX Technology, Inc., 1997 Page 87 Version 1.0SECTION 9 PCI 9052 TIMING DIAGRAMS FRAME# Vf Vf \fo VP ADDR | | | | | ADDRE | | | | ADDR2 | |) | ADDR OO AD[31:0] ) () C) {)}-{} OOO OM C/BE[3:0]# (XBE_) (Xi BE (X BE IRDYE ~ AQ fo Qf Nf NP DEVSEL# ~ \ fo Nf Nf Nf TRDY# \fo \ fo STOP# ~. \f....... Vf LOCK# oo YN ADS# VU BLAST# V/ LA[27:2] (appa _) LAD[31:0] () LBE[3:0}# (1Be_) LRDYi# \ / WD# \__/ RD# LW/R# \/ Timing Diagram 9-30. PCI Lock Mode PLX Technology, Inc., 1997 Page 88 Version 1.0SECTION 9 PCI 9052 TIMING DIAGRAMS 9.2.6 Big Endian Mode and Multiplexed Local Bus (J Mode) fans 00s /'80rs Po0ns brtttdl tier t ttt ttt tbat AD[31:0] +___appr_X 12345678 ) C/BE[3:0}# _{__cmp__X BE } IRDY# \ / DEVSEL# \ / TRDY# \ / PERR# STOP# LCLK_f{ \_f \ S/S SVS VS VS VS LS NS NV LHOLD LHOLDA ADS# \__sfo BLAST# \ Sf 87654321 LA[27:2] { ADDR X }_ LBE[3:0}# LBE LRDYi# \ fd USERO/WAITO# RD# WR# \ fd LW/R# / Timing Diagram 9-31. Direct Slave Single Write to 32 Bit Local Bus Big Endian and Multiplexed Local Bus (J Mode) PLX Technology, Inc., 1997 Page 89 Version 1.0SECTION 9 PCI 9052 TIMING DIAGRAMS CLK VS VS VSI VSI NS NS NS NS NS NS NS NS NS NI NS NS FRAME# AD[31:0] C/BE[3:0}# IRDY# DEVSEL# TRDY# PERR# STOP# LOK f\S\S\S\VS\VSINVI VSS NS NSN NI NS NS NI NS LHOLD LHOLDA ADS# BLAST# LA[27:2] LBE[3:0}# LRDYi# USERO/WAITO# RD# WR# LW/R# Ons ; | tod 100ns 200ns 300ns 400ns 1 | | to tod "_/ 12345678 _{{_cmp X Oe NN BE LS LS 87654321 { ADDR x ; { LBE } L/S L/S LW Space 0 is mapped to I/O Address-to-data = zero wait states Data-to-data = zero wait states Read strobe = zero wait states Timing Diagram 9-32. Direct Slave Single Read from 32 Bit Local Bus Big Endian and Multiplexed Local Bus (J Mode) PLX Technology, Inc., 1997 Page 90 Version 1.0SECTION 9 PCI 9052 TIMING DIAGRAMS FRAME# SSS / AD[31:0] _abbrX_ bo X Di X b2 X v3 XK v4 } C/BE[3:0]}# _cmp X BE } IRDY# \ DEVSEL# \ TRDY# \ Ss ONS OOS LcK _/\S\S\S\S VS NS NS NS NVI NS NSN NS NS NS NY LHOLD LHOLDA ADS# LS ALE I\ BLAST# \/ | LA[27:2] { ADDR X po. xX pi X ve. X os KX v4. X LBE[3:0]# { LBE }+ LRDYi# \ [| LW/R# RD# WR# \ [| BTERM# Do D1 D2 D3 D4 PCI 12345678 AABBCCDD 87654321 EEFFGGHH 12345678 Local bus 87654321 DDCCBBAA 12345678 HHGGFFEE 87654321 Burst enabled (burst write of five Lwords), BTERM# enabled Local bus: Big Endian, 32 bit Address-to-data = zero wait states Write strobe = zero wait states Write cycle hold = zero wait states Timing Diagram 9-33. Direct Slave Burst Write and Multiplexed Local Bus (32 Bit Local Bus, J Mode) PLX Technology, Inc., 1997 Page 91 Version 1.0SECTION 9 PCI 9052 TIMING DIAGRAMS FRAME# AD [31:0] CMD C/BE[3:0}4# X=) IRDY# \ / DEVSEL# \ / TRDY# \ / LcK _/\S\S\S\S VS NS NS NS NVI NS NSN NS NS NS NY LHOLD LHOLDA ADS# \ / ALE /\ BLAST# \ f.- | LA[27:2] { ADDR _X_Dlo XDLi xX bie. X ois X LBE[3:0]# { 4 X 6 X 4.X 6 X LRDYi# \ / LW/R# RD# WR# \ / BTERM# PCI 12548678 AABBCCDD DLO DLt DL2 DL3 Local bus 78XXXX56 34XXXX12 DDXXXXCG _BBXXXXAA Burst enabled (burst write of four Lwords), BTERM# enabled Local bus: Big Endian, 16 bit Address-to-data = zero wait states Write strobe = zero wait states Write cycle hold = zero wait states Timing Diagram 9-34. Direct Slave Burst Write and Multiplexed Local Bus (16 Bit Local Bus, J Mode) PLX Technology, Inc., 1997 Page 92 Version 1.0SECTION 9 PCI 9052 TIMING DIAGRAMS Ons 100ns 200ns 300ns 400ns 500ns a ee | CK VIVIAN VP DS OP SD DNS FRAME# ~~ \ a AD[31:0] {ADDA) C/BE[3:0]# {_cmoX BE IRDY# \ DEVSEL#~ ...~.~SA\ TRDY# \ / PERR# STOP# LCLK LHOLD LHOLDA ADS# ALE BLAST# ae [ LA[27:2] { ADDR X Do X Di X De X be} LBE[3:0]# { LBE } LRDYi# \ / USERO/WAITO# BTERM# RD# \ / WR# LW/R# \ / Do D1 D2 D3 PCI 12345678 AABBCCDD 87654321 EEFFGGHH Local 87654321 DDCCBBAA 12345678 HHGGFFEE Prefetch four Lwords Local burst Address-to-data = zero wait states Data-to-data = zero wait states Read strobe = zero wait states Timing Diagram 9-35. Direct Slave Burst Read and Multiplexed Local Bus (32 Bit Local Bus, J Mode) PLX Technology, Inc., 1997 Page 93 Version 1.0SECTION 9 PCI 9052 TIMING DIAGRAMS Ons 250ns 500ns | | | | | | | | | | | | CUK NS NS NS NS VIDIO VPI PI VPI PL IP LV I PTT FRAME# _\ a ADDR AD[31:0] 4__} po Xi XY] C/BE[3:0]# x BE IRDY# \ f_ DEVSEL ~~ \ [| TRDY# LS \S | PERR# STOP# LOLK J \/S\S\S\S NISSAN VI VDI VD OVI VD OVI VI VDI VDI VPI OS LHOLD LHOLDA ADS# \__/ ALE /\ BLAST# \_/ LA[27:2] (~appr_XboX D1 X_b2 LBE[3:0]}# LRDYi# \ / LWR# ON RD# \ / WR# Do D1 OD DL le DLs Local 78XXXX56 34XXXX12 DDXXXXCC BBXXXXAA Burst enabled (burst read of four words) Address-to-data = one wait state Data-to-data = zero wait states Read strobe = three wait states Timing Diagram 9-36. Direct Slave Burst Read and Multiplexed Local Bus (16 Bit Local Bus, J Mode) PLX Technology, Inc., 1997 Page 94 Version 1.0SECTION 9 PCI 9052 TIMING DIAGRAMS 9.3 ISA TIMING DIAGRAMS Ons 1000ns 1250ns 1 | tod . Prot tt tot til LCLK BALE LA[23:2] ISAA[1:0], SBHE# MEMRD#/MEMWR# IORD#/IOWR# NOWS# CHRDY LAD[15:0] (Read) LAD[15:0] (Write) Timing Diagram 9-37. 8 Bit Memory Read/Write Standard ISA Cycle (6 LCLK Shown) 1000ns 1250ns I tot od 1 | tod LCLK BALE LA[23:2] ISAA[1:0], SBHE# MEMRD#/MEMWR# lIORD#/IOWR# NOWS# CHRDY LAD[15:0] (Read) LAD[15:0] (Write) Timing Diagram 9-38. 8 Bit Memory Read/Write Extended ISA Cycle (7 LCLK Shown) PLX Technology, Inc., 1997 Page 95 Version 1.0SECTION 9 PCI 9052 TIMING DIAGRAMS Ons 250ns 500ns 750ns 1000ns 1250ns | | | | | 1 | | Potol LOLK 7\_, I-\N J VSI VV (\_ ~\ININI NS BALE /\ LA[23:2] ISAA[1:0], SBHE# MEMRD#/MEMWR# IORD#/IOWR# NOWS# CHRDY LAD[15:0] (Read) LAD[15:0] (Write) Timing Diagram 9-39. 8 Bit Memory Read/Write Compressed ISA Cycle (3 LCLK Shown) LCLK BALE LA[23:2] ISAA[1:0], SBHE# MEMRD#/MEMWR# IORD#/IOWR# NOWS# CHRDY LAD[15:0] (Read) LAD[15:0] (Write) Timing Diagram 9-40. 8 Bit I/O Read/Write Standard ISA Cycle (6 LCLK Shown) PLX Technology, Inc., 1997 Page 96 Version 1.0SECTION 9 PCI 9052 TIMING DIAGRAMS 1000ns 1250ns 1 | tod 1 | tod LCLK BALE LA[23:2] ISAA[1:0], SBHE# MEMRD#/ MEMWR# lIORD#/IOWR# NOWS# CHRDY LAD[15:0] (Read) LAD[15:0] (Write) Timing Diagram 9-41. 8 Bit I/O Read/Write Extended ISA Cycle (7 LCLK Shown) 1000ns en LCLK BALE LA[23:2] ISAA[1:0], SBHE# MEMRD#/MEMWR# lIORD#/IOWR# NOWS# CHRDY LAD[15:0] (Read) LAD[15:0] (Write) Timing Diagram 9-42. 8 Bit l/O Read/Write Compressed ISA Cycle (3 LCLK Shown) PLX Technology, Inc., 1997 Page 97 Version 1.0SECTION 9 LCLK BALE LA[23:2] ISAA[1:0], SBHE# MEMRD#/MEMWR# IORD#/IOWR# NOWS# CHRDY LAD[15:0] (Read) LAD[15:0] (Write) PCI 9052 1000ns | | Timing Diagram 9-43. 16 Bit Memory Read/Write Standard ISA Cycle (3 LCLK Shown) TIMING DIAGRAMS 1250ns | LCLK BALE LA[23:2] ISAA[1:0], SBHE# MEMRD#/MEMWR# IORD#/IOWR# NOWS# CHRDY LAD[15:0] (Read) LAD[15:0] (Write) | | [\_f Ny _ 250ns Timing Diagram 9-44. 16 Bit Memory Read/Write Extended ISA Cycle (4 LCLK Shown) PLX Technology, Inc., 1997 Page 98 Version 1.0SECTION 9 PCI 9052 TIMING DIAGRAMS 1000ns 1250ns oe 1 i tod LCLK BALE LA[23:2] ISAA[1:0], SBHE# MEMRD#/MEMWR# IORD#/IOWR# NOWS# CHRDY LAD[15:0] (Read) LAD[15:0] (Write) Timing Diagram 9-45. 16 Bit Memory Read/Write Compressed ISA Cycle (2 LCLK Shown) 1000ns 1250ns I tot od 1 | tod LCLK BALE LA[23:2] ISAA[1:0], SBHE# MEMRD#/MEMWR# lIORD#/IOWR# NOWS# CHRDY LAD[15:0] (Read) LAD[15:0] (Write) Timing Diagram 9-46. 16 Bit I/O Read/Write Standard ISA Cycle (3 LCLK Shown) PLX Technology, Inc., 1997 Page 99 Version 1.0SECTION 9 PCI 9052 TIMING DIAGRAMS Ons 250ns 500ns 750ns 1000ns 1250ns | | 1 | | | | 1 I | | LCLK BALE LA[23:2] ISAA[1:0], SBHE# MEMRD#/MEMWR# lIORD#/IOWR# NOWS# CHRDY LAD[15:0] (Read) LAD[15:0] (Write) Timing Diagram 9-47. 16 Bit |/O Read/Write Extended ISA Cycle (4 LCLK Shown) PLX Technology, Inc., 1997 Page 100 Version 1.0