General Description
The MAX15039 high-efficiency switching regulator
delivers up to 6A load current at output voltages from
0.6V to 90% of VIN. The IC operates from 2.9V to 5.5V,
making it ideal for on-board point-of-load and postregu-
lation applications. Total output error is less than ±1%
over load, line, and temperature ranges.
The MAX15039 features fixed-frequency PWM mode
operation with a switching frequency range of 500kHz
to 2MHz set by an external resistor. The MAX15039
provides the option of operating in a skip mode to
improve light-load efficiency. High-frequency operation
allows for an all-ceramic capacitor design. The high
operating frequency also allows for small-size external
components.
The low-resistance on-chip nMOS switches ensure high
efficiency at heavy loads while minimizing critical induc-
tances, making the layout a much simpler task with
respect to discrete solutions. Following a simple layout
and footprint ensures first-pass success in new designs.
The MAX15039 comes with a high bandwidth (28MHz)
voltage-error amplifier. The voltage-mode control archi-
tecture and the voltage-error amplifier permit a type III
compensation scheme to be utilized to achieve maxi-
mum loop bandwidth, up to 20% of the switching fre-
quency. High loop bandwidth provides fast transient
response, resulting in less required output capacitance
and allowing for all-ceramic-capacitor designs.
The MAX15039 provides two three-state logic inputs to
select one of nine preset output voltages. The preset
output voltages allow customers to achieve ±1% out-
put-voltage accuracy without using expensive 0.1%
resistors. In addition, the output voltage can be set to
any customer value by either using two external resis-
tors at the feedback with a 0.6V internal reference or
applying an external reference voltage to the REFIN
input. The MAX15039 offers programmable soft-start
time using one capacitor to reduce input inrush current.
Applications
Server Power Supplies
POLs
ASIC/CPU/DSP Core and I/O Voltages
DDR Power Supplies
Base-Station Power Supplies
Telecom and Networking Power Supplies
RAID Control Power Supplies
Features
♦Internal 26mΩRDS(ON) High-Side and 20mΩ
RDS(ON) Low-Side MOSFETs
♦Continuous 6A Output Current Over Temperature
♦±1% Output Accuracy Over Load, Line, and
Temperature
♦Operates from 2.9V to 5.5V VIN Supply
♦Adjustable Output from 0.6V to (0.9 x VIN)
♦Soft-Start Reduces Inrush Supply Current
♦500kHz to 2MHz Adjustable Switching Frequency
♦Compatible with Ceramic, Polymer, and
Electrolytic Output Capacitors
♦Nine Preset and Adjustable Output Voltages
0.6V, 0.7V, 0.8V, 1.0V, 1.2V, 1.5V, 1.8V, 2.0V,
2.5V, and Adjustable
♦Monotonic Startup for Safe-Start Into Prebiased
Outputs
♦Selectable Forced PWM or Skip Mode for Light
Load Efficiency
♦Overcurrent and Overtemperature Protection
♦Output Current Sink/Source Capable with Cycle-
by-Cycle Protection
♦Open-Drain, Power-Good Output
♦Lead-Free, 4mm x 4mm, 24-Pin Thin QFN Package
MAX15039
6A, 2MHz Step-Down Regulator
with Integrated Switches
________________________________________________________________
Maxim Integrated Products
1
OUTPUT
1.8V, 6A
INPUT
2.9V TO 5.5V
BST
LX
OUT
IN
EN
VDD
CTL2
CTL1
PGND
FB
VDD
COMP
PWRGD
FREQ
REFIN
SS
GND
MODE
MAX15039
Typical Operating Circuit
Ordering Information
19-4321; Rev 3; 12/10
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
PART TEMP RANGE PIN-PACKAGE
MAX15039ETG+ -40°C to +85°C 24 Thin QFN-EP*
+
Denotes a lead(Pb)-free/RoHS-compliant package.
*
EP = Exposed pad.
Pin Configuration appears at end of data sheet.
EVALUATION KIT
AVAILABLE
MAX15039
6A, 2MHz Step-Down Regulator
with Integrated Switches
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
(VIN = VEN = 5V, CVDD = 2.2µF, TA= TJ= -40°C to +85°C, typical values are at TA= +25°C, circuit of Figure 1, unless otherwise
noted.) (Note 3)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
IN, PWRGD to GND..................................................-0.3V to +6V
VDD to GND..................-0.3V to the lower of +4V or (VIN + 0.3V)
COMP, FB, MODE, REFIN, CTL1, CTL2, SS,
FREQ to GND ..........................................-0.3V to (VDD + 0.3V)
OUT, EN to GND ......................................................-0.3V to +6V
BST to LX..................................................................-0.3V to +6V
BST to GND ............................................................-0.3V to +12V
PGND to GND .......................................................-0.3V to +0.3V
LX to PGND ..................-0.3V to the lower of +6V or (VIN + 0.3V)
LX to PGND ..........-1V to the lower of +6V or (VIN + 1V) for 50ns
ILX(RMS) (Note 1) ......................................................................6A
VDD Output Short-Circuit Duration .............................Continuous
Converter Output Short-Circuit Duration ....................Continuous
Continuous Power Dissipation (TA= +70°C)
24-Pin TQFN (derate 27.8mW/°C above +70°C) ........2222mW
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Soldering Temperature (reflow) .......................................+260°C
Note 2: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-
layer board. For detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial.
Note 1: LX has internal clamp diodes to PGND and IN. Applications that forward bias these diodes should take care not to exceed
the IC’s package power dissipation limits.
PARAMETER CONDITIONS MIN TYP MAX UNITS
IN
IN Voltage Range 2.9 5.5 V
VIN = 3.3V 4.9 8
IN Supply Current fS = 1MHz, no load VIN = 5V 5.2 8.5 mA
VIN = 5V, VEN = 0V 10 20
Total Shutdown Current from IN VIN = VDD = 3.3V, VEN = 0V 45 µA
3.3V LDO (VDD)
VDD rising 2.6 2.8
VDD falling 2.35 2.55 V
VDD Undervoltage Lockout
Threshold LX starts/stops switching
Minimum glitch-width
rejection 10 µs
VDD Output Voltage VIN = 5V, IVDD = 0 to 10mA 3.1 3.3 3.5 V
VDD Dropout VIN = 2.9V, IVDD = 10mA 0.08 V
VDD Current Limit VIN = 5V, VDD = 0V 25 40 mA
BST
BST Supply Current VBST = VIN = 5V, VLX = 0 or 5V, VEN = 0V 0.025 µA
PWM COMPARATOR
PWM Comparator Propagation
Delay 10mV overdrive 20 ns
PWM Peak-to-Peak Ramp
Amplitude 1V
PWM Valley Amplitude 0.8 V
PACKAGE THERMAL CHARACTERISTICS (Note 2)
TQFN
Junction-to-Ambient Thermal Resistance (θJA) ............36°C/W
Junction-to-Case Resistance (θJC).................................6°C/W
MAX15039
6A, 2MHz Step-Down Regulator
with Integrated Switches
_______________________________________________________________________________________ 3
ELECTRICAL CHARACTERISTICS (continued)
(VIN = VEN = 5V, CVDD = 2.2μF, TA= TJ= -40°C to +85°C, typical values are at TA= +25°C, circuit of Figure 1, unless otherwise
noted.) (Note 3)
PARAMETER CONDITIONS MIN TYP MAX UNITS
ERROR AMPLIFIER
COMP Clamp Voltage, High VIN = 2.9V to 5V, VFB = 0.5V, VREFIN = 0.6V 2 V
COMP Clamp Voltage, Low VIN = 2.9V to 5V, VFB = 0.7V, VREFIN = 0.6V 0.7 V
COMP Slew Rate VFB step from 0.5V to 0.7V in 10ns 1.6 V/μs
COMP Shutdown Resistance From COMP to GND, VIN = 3.3V, VCOMP = 100mV,
VEN = VSS = 0V 6Ω
Internally Preset Output Voltage
Accuracy VREFIN = VSS, MODE = GND -1 +1 %
FB Set-Point Value CTL1 = CTL2 = GND, MODE = GND 0.594 0.6 0.606 V
FB to OUT Resistor All VID settings except CTL1 = CTL2 = GND 5.5 8 10.5 kΩ
Open-Loop Voltage Gain 115 dB
Error-Amplifier Unity-Gain
Bandwidth 28 MHz
Error-Amplifier and REFIN
Common-Mode Input Range VDD = 2.9V to 3.5V 0 VDD - 2 V
VFB = 0.7V, sinking 1
Error-Amplifier Maximum Output
Current
VCOMP = 1V,
VREFIN = 0.6V VFB = 0.5V, sourcing -1 mA
FB Input Bias Current CTL1 = CTL2 = GND -125 nA
CTL_
VCTL_ = 0V -7.2
CTL_ Input Bias Current VCTL_ = VDD 7.2 μA
Low, falling 0.8
Open VDD/2
CTL_ Input Threshold
High, rising VDD -
0.8
V
Hysteresis All VID transitions 50 mV
REFIN
REFIN Input Bias Current VREFIN = 0.6V -185 nA
REFIN Offset Voltage VREFIN = 0.9V, FB shorted to COMP -4.5 +4.5 mV
LX (All Pins Combined)
VIN = VBST - VLX = 3.3V 35
LX On-Resistance, High Side ILX = -2A VIN = VBST - VLX = 5V 26 45 mΩ
VIN = 3.3V 25
LX On-Resistance, Low Side ILX = 2A VIN = 5V 20 35 mΩ
High-side sourcing 9 11
Low-side sinking 11LX Current-Limit Threshold
Zero-crossing current threshold, MODE = VDD 0.2
A
VLX = 0V -0.01
LX Leakage Current VIN = 5V, VEN = 0V VLX = 5V -0.01 μA
MAX15039
6A, 2MHz Step-Down Regulator
with Integrated Switches
4 _______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(VIN = VEN = 5V, CVDD = 2.2μF, TA= TJ= -40°C to +85°C, typical values are at TA= +25°C, circuit of Figure 1, unless otherwise
noted.) (Note 3)
PARAMETER CONDITIONS MIN TYP MAX UNITS
RFREQ = 49.9kΩ0.9 1 1.1
LX Switching Frequency VIN = 2.9V to 5.5V RFREQ = 23.6kΩ1.8 2 2.2 MHz
Switching Frequency Range 500 2000 kHz
LX Minimum Off-Time 78 ns
LX Maximum Duty Cycle RFREQ = 49.9kΩ92 95 %
LX Minimum Duty Cycle RFREQ = 49.9kΩ515%
Average Short-Circuit IN Supply
Current OUT connected to GND, VIN = 5V 0.35 A
RMS LX Output Current 6A
ENABLE
EN Input Logic-Low Threshold EN falling 0.9 V
EN Input Logic-High Threshold EN rising 1.5 V
EN Input Current VEN = 0 or 5V, VIN = 5V 0.01 μA
MODE
Logic-low, falling 26
Logic VDD/2 or open, rising 50MODE Input-Logic Threshold
Logic-high, rising 74
%VDD
MODE Input-Logic Hysteresis MODE falling 5 %VDD
MODE = GND -5
MODE Input Bias Current MODE = VDD 5μA
SS
SS Current VSS = 0.45V, VREFIN = 0.6V, sourcing 6.7 8 9.3 μA
THERMAL SHUTDOWN
Thermal-Shutdown Threshold Rising 165 °C
Thermal-Shutdown Hysteresis 25 °C
POWER GOOD (PWRGD)
VFB falling, VREFIN = 0.6V 88 90 92
Power-Good Threshold Voltage VFB rising, VREFIN = 0.6V 92.5
%
VREFIN
Power-Good Edge Deglitch VFB rising or falling 48 Clock
cycles
PWRGD Output-Voltage Low IPWRGD = 4mA 0.03 0.1 V
PWRGD Leakage Current VIN = VPWRGD = 5V, VFB = 0.7V, VREFIN = 0.6V 0.01 μA
HICCUP OVERCURRENT LIMIT
Current-Limit Startup Blanking 112 Clock
cycles
Autoretry Restart Time 896 Clock
cycles
MAX15039
6A, 2MHz Step-Down Regulator
with Integrated Switches
_______________________________________________________________________________________
5
EFFICIENCY
vs. OUTPUT CURRENT
MAX15039 toc01
OUTPUT CURRENT (A)
EFFICIENCY (%)
1.0
50
60
70
80
90
100
40
0.1 10.0
VOUT = 2.5V
VOUT = 1.8V
VOUT = 1.2V
PWM
SKIP
EFFICIENCY
vs. OUTPUT CURRENT
MAX15039 toc02
OUTPUT CURRENT (A)
EFFICIENCY (%)
1.0
50
60
70
80
90
100
40
0.1 10.0
VOUT = 2.5V
VOUT = 1.8V
VOUT = 1.2V
VIN = 3.3V
PWM
SKIP
FREQUENCY
vs. INPUT VOLTAGE
MAX15039 toc03
INPUT VOLTAGE (V)
FREQUENCY (MHz)
5.04.53.0 3.5 4.0
1.85
1.90
1.95
2.00
2.05
2.10
2.15
2.20
1.80
2.5 5.5
TA = +85°C
TA = +25°C
TA = -40°C
RFREQ = 23.2kΩ
FREQUENCY
vs. INPUT VOLTAGE
MAX15039 toc04
INPUT VOLTAGE (V)
FREQUENCY (MHz)
5.04.53.0 3.5 4.0
0.85
0.90
0.95
1.00
1.05
1.10
1.15
1.20
0.80
2.5 5.5
TA = +85°C
TA = +25°C
TA = -40°C
RFREQ = 49.9kΩ
LOAD REGULATION
MAX15039 toc05a
LOAD CURRENT (A)
OUTPUT-VOLTAGE CHANGE (%)
56
4123
-0.45
-0.40
-0.35
-0.30
-0.25
-0.20
-0.15
-0.10
-0.05
0
-0.50
07
VOUT = 1.2V
VOUT = 1.8V
VOUT = 2.5V
LINE REGULATION (LOAD = 6A)
MAX15039 toc05b
INPUT VOLTAGE (V)
OUTPUT-VOLTAGE CHANGE (%)
5.04.54.03.53.0
-0.10
-0.08
-0.06
-0.04
-0.02
0
-0.12
2.5 5.5
VOUT = 1.2V
VOUT = 1.8V
Typical Operating Characteristics
(Typical values are VIN = VEN = 5V, VOUT = 1.8V, RFREQ = 49.9kΩ, IOUT = 6A, TA= +25°C, circuit of Figure 1, unless otherwise noted.)
ELECTRICAL CHARACTERISTICS (continued)
(VIN = VEN = 5V, CVDD = 2.2μF, TA= TJ= -40°C to +85°C, typical values are at TA= +25°C, circuit of Figure 1, unless otherwise
noted.) (Note 3)
PARAMETER CONDITIONS MIN TYP MAX UNITS
FB Hiccup Threshold VFB falling 70 %
VREFIN
Hiccup Threshold Blanking Time VFB falling 28 μs
Note 3: Specifications are 100% production tested at TA= +25°C. Limits over the operating temperature range are guaranteed by design.
MAX15039
6A, 2MHz Step-Down Regulator
with Integrated Switches
6 _______________________________________________________________________________________
Typical Operating Characteristics (continued)
(Typical values are VIN = VEN = 5V, VOUT = 1.8V, RFREQ = 49.9kΩ, IOUT = 6A, TA= +25°C, circuit of Figure 1, unless otherwise noted.)
LOAD TRANSIENT
MAX15039 toc06
40μs/div
VOUT
AC-COUPLED
100mV/div
2A
IOUT
0A
SWITCHING WAVEFORMS
(FORCED PWM, 2A LOAD)
MAX15039 toc07
400ns/div
AC-COUPLED
50mV/div
VOUT
ILX
VLX
2A/div
0A
5V/div
SWITCHING WAVEFORMS
(SKIP MODE, NO LOAD)
MAX15039 toc08
2μs/div
AC-COUPLED
100mV/div
VOUT
ILX
VLX
1A/div
0A
0V
5V/div
SOFT-START WAVEFORM
(RLOAD = 0.5Ω)
MAX15039 toc09
400μs/div
VEN
5V/div
0V
VOUT
1V/div
SHUTDOWN WAVEFORM
(RLOAD = 0.5Ω)
MAX15039 toc10
10μs/div
VEN
5V/div
0V
VOUT
1V/div
INPUT SHUTDOWN CURRENT
vs. INPUT VOLTAGE
MAX15039 toc11
INPUT VOLTAGE (V)
INPUT SHUTDOWN CURRENT (μA)
5.04.54.03.53.0
6
7
8
9
10
11
12
5
2.5 5.5
VEN = 0V
MAXIMUM OUTPUT CURRENT
vs. OUTPUT VOLTAGE
MAX15039 toc12
OUTPUT VOLTAGE (V)
MAXIMUM OUTPUT CURRENT (A)
2.01.51.0
3
4
5
6
7
8
9
10
2
0.5 2.5
MAX15039
6A, 2MHz Step-Down Regulator
with Integrated Switches
_______________________________________________________________________________________
7
Typical Operating Characteristics (continued)
(Typical values are VIN = VEN = 5V, VOUT = 1.8V, RFREQ = 49.9kΩ, IOUT = 6A, TA= +25°C, circuit of Figure 1, unless otherwise noted.)
HICCUP CURRENT LIMIT
MAX15039 toc13
400μs/div
1V/div
5A/div
1A/div
0V
0A
0A
VOUT
IOUT
IIN
RMS INPUT CURRENT DURING
SHORT CIRCUIT vs. INPUT VOLTAGE
MAX15039 toc14
INPUT VOLTAGE (V)
RMS INPUT CURRENT (A)
5.04.54.03.53.0
0.1
0.3
0.2
0.5
0.4
0.7
0.6
0.8
0
2.5 5.5
VOUT = 0V
EXPOSED PAD TEMPERATURE
vs. AMBIENT TEMPERATURE
MAX15039 toc15
AMBIENT TEMPERATURE (°C)
EXPOSED PAD TEMPERATURE (°C)
80604020
10
20
30
40
50
60
70
80
90
100
0
0100
MEASURED ON A MAX15039EVKIT
6A LOAD
FEEDBACK VOLTAGE
vs. TEMPERATURE
MAX15039 toc16
TEMPERATURE (°C)
FEEDBACK VOLTAGE (V)
6035-15 10
0.57
0.58
0.59
0.60
0.62
0.61
0.63
0.64
0.56
-40 85
SOFT-START WITH REFIN
MAX15039 toc17
200μs/div
1A/div
0.5V/div
2V/div
0A
1V/div
0V
0V
0V
IIN
VPWRGD
VREFIN
VOUT
STARTING INTO PREBIASED OUTPUT
(MODE = VDD, VOUT = 2.5V, 2A LOAD)
MAX15039 toc18
200μs/div
5V/div
1V/div
5V/div
0V
2A
0A
0V
0V
VEN
VPWRGD
VOUT
IOUT
STARTING INTO PREBIASED OUTPUT
(MODE = VDD/2, VOUT = 2.5V, 2A LOAD)
MAX15039 toc19
200μs/div
5V/div
1V/div
5V/div
0V
2A
0A
0V
0V
VEN
VPWRGD
VOUT
IOUT
MAX15039
6A, 2MHz Step-Down Regulator
with Integrated Switches
8 _______________________________________________________________________________________
Typical Operating Characteristics (continued)
(Typical values are VIN = VEN = 5V, VOUT = 1.8V, RFREQ = 49.9kΩ, IOUT = 6A, TA= +25°C, circuit of Figure 1, unless otherwise noted.)
STARTING INTO PREBIASED OUTPUT
(MODE = VDD, VOUT = 2.5V, NO LOAD)
MAX15039 toc20
200μs/div
VEN
2V/div
VOUT
1V/div
VPWRGD
2V/div
0V
0V
0V
STARTING INTO PREBIASED OUTPUT
(MODE = VDD/2, VOUT = 2.5V, NO LOAD)
MAX15039 toc21
200μs/div
VEN
2V/div
VOUT
1V/div
VPWRGD
2V/div
0V
0V
0V
STARTING INTO PREBIASED OUTPUT
ABOVE NOMINAL SET POINT (VOUT = 1.5V)
MAX15039 toc22
1ms/div
VEN
2V/div
VOUT
1V/div
VPWRGD
2V/div
0V
0V
0V
VMODE = VDD,
NO LOAD
STARTING INTO PREBIASED OUTPUT
ABOVE NOMINAL SET POINT (VOUT = 1.5V)
MAX15039 toc23
1ms/div
VEN
2V/div
VOUT
1V/div
VPWRGD
2V/div
0V
0V
0V
VOUT = 1.5V,
VMODE = VDD/2,
NO LOAD
TRANSITION FROM SKIP MODE
TO FORCED PWM MODE
MAX15039 toc24
2ms/div
VMODE
5V/div
VLX
5V/div
VOUT
0.5V/div
0V
NO LOAD
TRANSITION FROM FORCED
PWM MODE TO SKIP MODE
MAX15039 toc25
4ms/div
VMODE
5V/div
VLX
5V/div
VOUT
0.5V/div
0V
NO LOAD
MAX15039
6A, 2MHz Step-Down Regulator
with Integrated Switches
_______________________________________________________________________________________ 9
Pin Description
PIN NAME FUNCTION
1 MODE Functional Mode Selection Input. See the MODE Selection section for more information.
2V
DD 3.3V LDO Output. Supply input for the internal analog core. Connect a low-ESR, ceramic capacitor with a
minimum value of 2.2μF from VDD to GND.
3 CTL1
4 CTL2
Preset Output-Voltage Selection Inputs. CTL1 and CTL2 set the output voltage to one of nine preset
voltages. See Table 1 and the Programming the Output Voltage (CTL1, CTL2) section for preset voltages.
5 REFIN
External Reference Input. Connect REFIN to SS to use the internal 0.6V reference. Connecting REFIN to an
external voltage forces FB to regulate to the voltage applied to REFIN. REFIN is internally pulled to GND
when the IC is in shutdown/hiccup mode.
6SS
Soft-Start Input. Connect a capacitor from SS to GND to set the startup time. Use a capacitor with a 1nF
minimum value. See the Soft-Start and REFIN section for details on setting the soft-start time.
7 GND Analog Ground Connection. Connect GND and PGND together at one point near the input bypass capacitor
return terminal.
8 COMP Voltage Error-Amplifier Output. Connect the necessary compensation network from COMP to FB and OUT.
COMP is internally pulled to GND when the IC is in shutdown/hiccup mode.
9FB
Feedback Input. Connect FB to the center tap of an external resistive divider from the output to GND to set
the output voltage from 0.6V to 90% of VIN. Connect FB through an RC network to the output when using
CTL1 and CTL2 to select any of nine preset voltages.
10 OUT Output-Voltage Sense. Connect to the converter output. Leave OUT unconnected when an external resistive
divider is used.
11 FREQ Oscillator Frequency Select. Connect a precision resistor from FREQ to GND to select the switching
frequency. See the Frequency Select (FREQ) section.
12 PWRGD
Open-Drain, Power-Good Output. PWRGD is high impedance when VFB rises above 92.5% (typ) of VREFIN
and VREFIN is above 0.54V. PWRGD is internally pulled low when VFB falls below 90% (typ) of VREFIN or
VREFIN is below 0.54V. PWRGD is internally pulled low when the IC is in shutdown mode, VDD is below the
internal UVLO threshold, or the IC is in thermal shutdown.
13 BST High-Side MOSFET Driver Supply. Internally connected to IN through a pMOS switch. Bypass BST to LX with
a 0.1μF capacitor.
14, 15,
16 LX Inductor Connection. All LX pins are internally shorted together. Connect all LX pins to the switched side of
the inductor. LX is high impedance when the IC is in shutdown mode.
17–20 PGND Power Ground. Connect all PGND pins externally to the power ground plane. Connect all PGND pins
together near the IC.
21, 22,
23 IN Input Power Supply. Input supply range is from 2.9V to 5.5V. Bypass IN to PGND with a 22μF ceramic
capacitor.
24 EN Enable Input. Logic input to enable/disable the MAX15039.
—EP
Exposed Pad. Solder EP to a large contiguous copper plane connected to PGND to optimize thermal
performance. Do not use EP as a ground connection for the device.
MAX15039
6A, 2MHz Step-Down Regulator
with Integrated Switches
10 ______________________________________________________________________________________
Block Diagram
CONTROL
LOGIC
IN
LX
PGND
MODE
IN
BST
THERMAL
SHUTDOWN
SOFT-START
VOLTAGE
REFERENCE
BIAS
GENERATOR
OSCILLATOR
1VP-P
SHUTDOWN
CONTROL
UVLO
CIRCUITRY
3.3V LDO
VDD
SHDN
FB
0.9 x VREFIN
SS
FB
COMP
GND
PWRGD
FREQ
ERROR
AMPLIFIER PWM
COMPARATOR
CURRENT-LIMIT
COMPARATOR
CURRENT-LIMIT
COMPARATOR
BST SWITCH
COMP CLAMPS
EN
REFIN
VID
VOLTAGE-
CONTROL
CIRCUITRY
OUT
CTL2
CTL1
8kΩ
MAX15039
MAX15039
C10
0.1μF
C6
22μFOUTPUT
1.8V, 6A
INPUT
2.9V TO 5.5V
C7
0.1μF
C5
2.2μF
BST
LX
OUT
IN
VDD
CTL2
CTL1
PGND
FB
C1
33pF
C2
1500pF
VDD
R1
20kΩ
R2
2.67kΩ
COMP
L1
0.47μH
C3
560pF
C4
0.022μF
R4
49.9kΩ
C8
22μF
C9
0.01μF
R3
158Ω
PWRGD
EN
FREQ
REFIN
SS
GND
MODE
MAX15039
2.2Ω
C15
1000pF
OPTIONAL
Figure 1. Typical Application Circuit: 1MHz, All-Ceramic-Capacitor Design with VIN = 2.9V to 5.5V and VOUT = 1.8V
Detailed Description
The MAX15039 high-efficiency, voltage-mode switching
regulator delivers up to 6A of output current. The
MAX15039 provides output voltages from 0.6V to 0.9 x
VIN from 2.9V to 5.5V input supplies, making it ideal for
on-board point-of-load applications. The output-voltage
accuracy is better than ±1% over load, line, and tem-
perature.
The MAX15039 features a wide switching frequency
range, allowing the user to achieve all-ceramic-capaci-
tor designs and fast transient responses (see Figure 1).
The high operating frequency minimizes the size of
external components. The MAX15039 is available in a
small (4mm x 4mm), lead-free, 24-pin thin QFN pack-
age. The REFIN function makes the MAX15039 an ideal
candidate for DDR and tracking power supplies. Using
internal low-RDS(ON) (20mΩfor the low-side n-channel
MOSFET and 26mΩfor the high-side n-channel
MOSFET) maintains high efficiency at both heavy-load
and high-switching frequencies.
The MAX15039 employs voltage-mode control architec-
ture with a high bandwidth (28MHz) error amplifier. The
voltage-mode control architecture allows up to 2MHz
switching frequency, reducing board area. The op amp
voltage-error amplifier works with type III compensation
to fully utilize the bandwidth of the high-frequency
switching to obtain fast transient response. Adjustable
soft-start time provides flexibilities to minimize input
startup inrush current. An open-drain, power-good
(PWRGD) output goes high when VFB reaches 92.5% of
VREFIN and VREFIN is greater than 0.54V.
The MAX15039 provides an option for three modes of
operation: regular PWM, PWM mode with monotonic
startup into prebiased output, or skip mode with monot-
onic startup into prebiased output.
6A, 2MHz Step-Down Regulator
with Integrated Switches
______________________________________________________________________________________ 11
Controller Function
The controller logic block is the central processor that
determines the duty cycle of the high-side MOSFET
under different line, load, and temperature conditions.
Under normal operation, where the current-limit and
temperature protection are not triggered, the controller
logic block takes the output from the PWM comparator
and generates the driver signals for both high-side and
low-side MOSFETs. The break-before-make logic and
the timing for charging the bootstrap capacitors are
calculated by the controller logic block. The error signal
from the voltage-error amplifier is compared with the
ramp signal generated by the oscillator at the PWM
comparator and, thus, the required PWM signal is pro-
duced. The high-side switch is turned on at the begin-
ning of the oscillator cycle and turns off when the ramp
voltage exceeds the VCOMP signal or the current-limit
threshold is exceeded. The low-side switch is then
turned on for the remainder of the oscillator cycle.
Current Limit
The internal, high-side MOSFET has a typical 11A peak
current-limit threshold. When current flowing out of LX
exceeds this limit, the high-side MOSFET turns off and
the synchronous rectifier turns on. The synchronous
rectifier remains on until the inductor current falls below
the low-side current limit. This lowers the duty cycle
and causes the output voltage to droop until the current
limit is no longer exceeded. The MAX15039 uses a hic-
cup mode to prevent overheating during short-circuit
output conditions.
During current limit, if VFB drops below 70% of VREFIN
and stays below this level for 12μs or more, the
MAX15039 enters hiccup mode. The high-side
MOSFET and the synchronous rectifier are turned off
and both COMP and REFIN are internally pulled low. If
REFIN and SS are connected together, both are pulled
low. The part remains in this state for 896 clock cycles
and then attempts to restart for 112 clock cycles. If the
fault causing current limit has cleared, the part resumes
normal operation. Otherwise, the part reenters hiccup
mode again.
Soft-Start and REFIN
The MAX15039 utilizes an adjustable soft-start function
to limit inrush current during startup. An 8μA (typ) cur-
rent source charges an external capacitor connected to
SS. The soft-start time is adjusted by the value of the
external capacitor from SS to GND. The required
capacitance value is determined as:
where tSS is the required soft-start time in seconds. The
MAX15039 also features an external reference input
(REFIN). The IC regulates FB to the voltage applied to
REFIN. The internal soft-start is not available when
using an external reference. A method of soft-start
when using an external reference is shown in Figure 2.
Connect REFIN to SS to use the internal 0.6V reference.
Use a capacitor of 1nF minimum value at SS.
Undervoltage Lockout (UVLO)
The UVLO circuitry inhibits switching when VDD is below
2.55V (typ). Once VDD rises above 2.6V (typ), UVLO
clears and the soft-start function activates. A 50mV hys-
teresis is built in for glitch immunity.
BST
The gate-drive voltage for the high-side, n-channel
switch is generated by a flying-capacitor boost circuit.
The capacitor between BST and LX is charged from the
VIN supply while the low-side MOSFET is on. When the
low-side MOSFET is switched off, the voltage of the
capacitor is stacked above LX to provide the necessary
turn-on voltage for the high-side internal MOSFET.
Frequency Select (FREQ)
The switching frequency is resistor programmable from
500kHz to 2MHz. Set the switching frequency of the IC
with a resistor (RFREQ) connected from FREQ to GND.
RFREQ is calculated as:
where fSis the desired switching frequency in Hertz.
Rk
sf s
FREQ S
=×−
50
095
1005
Ω
.(.)
μμ
CAt
V
SS
=×8
06
μ
.
C
R2
R1
REFIN
MAX15039
Figure 2. Typical Soft-Start Implementation with External
Reference
MAX15039
6A, 2MHz Step-Down Regulator
with Integrated Switches
12 ______________________________________________________________________________________
MAX15039
Power-Good Output (PWRGD)
PWRGD is an open-drain output that goes high imped-
ance when VFB is above 0.925 x VREFIN and VREFIN is
above 0.54V for at least 48 clock cycles. PWRGD pulls
low when VFB is below 90% of VREFIN or VREFIN is
below 0.54V for at least 48 clock cycles. PWRGD is low
when the IC is in shutdown mode, VDD is below the
internal UVLO threshold, or the IC is in thermal shut-
down mode.
Programming the Output Voltage
(CTL1, CTL2)
As shown in Table 1, the output voltage is pin program-
mable by the logic states of CTL1 and CTL2. CTL1 and
CTL2 are trilevel inputs: VDD, unconnected, and GND.
An 8.06kΩresistor must be connected between OUT
and FB when CTL1 and CTL2 are connected to GND.
The logic states of CTL1 and CTL2 should be pro-
grammed only before power-up. Once the part is
enabled, CTL1 and CTL2 should not be changed. If the
output voltage needs to be reprogrammed, cycle
power or EN and reprogram before enabling. The out-
put voltage can be programmed continuously from
0.6V to 90% of VIN by using a resistor-divider network
from VOUT to FB to GND as shown in Figure 3a. CTL1
and CTL2 must be connected to GND.
Shutdown Mode
Drive EN to GND to shut down the IC and reduce quies-
cent current to 10μA (typ). During shutdown, the LX is
high impedance. Drive EN high to enable the MAX15039.
Thermal Protection
Thermal-overload protection limits total power dissipation
in the device. When the junction temperature exceeds
TJ= +165°C, a thermal sensor forces the device into
shutdown, allowing the die to cool. The thermal sensor
turns the device on again after the junction temperature
cools by 20°C, causing a pulsed output during continu-
ous overload conditions. The soft-start sequence begins
after recovery from a thermal-shutdown condition.
Applications Information
IN and VDD Decoupling
To decrease the noise effects due to the high switching
frequency and maximize the output accuracy of
the MAX15039, decouple IN with a 22μF capacitor from
IN to PGND. Also, decouple VDD with a 2.2μF low-ESR
ceramic capacitor from VDD to GND. Place these
capacitors as close as possible to the IC.
6A, 2MHz Step-Down Regulator
with Integrated Switches
______________________________________________________________________________________ 13
MAX15039
L
COUT
EXTERNAL RESISTIVE DIVIDER
INTERNAL PRESET VOLTAGES
VOUT
R3
R4
R1
COMP
FB
OUT
CTL1
CTL2
LX
C1
C3
R2
C3
R2
C2
MAX15039
L
a)
b)
COUT
VOUT
R3
8kΩ
R1
COMP
OUT
FB
CTL1
VOLTAGE
SELECT CTL2
LX
C1
C2
Figure 3. Type III Compensation Network
CTL1 CTL2 VOUT (V)
VOUT WHEN
USING
EXTERNAL
REFIN
(V)
GND GND
0.6* or
0.6 < VOUT ≤
0.9 x VIN**
VREFIN* or
VREFIN < VOUT ≤
0.9 x VIN**
VDD VDD 0.7 VREFIN x (7/6)
GND Unconnected 0.8 VREFIN x (4/3)
GND VDD 1.0 VREFIN x (5/3)
Unconnected GND 1.2 VREFIN x 2
Unconnected Unconnected 1.5 VREFIN x 2.5
Unconnected VDD 1.8 VREFIN x 3
VDD GND 2.0 VREFIN x (10/3)
VDD Unconnected 2.5 VREFIN x (25/6)
Table 1. CTL1 and CTL2 Output Voltage
Selection
*
Install an 8.06k
Ω
resistor at R3 and do not install a resistor at R4.
**
Install R3 and R4 following the equation in the
Compensation
Design
section (see Figure 3a)
.
MAX15039
6A, 2MHz Step-Down Regulator
with Integrated Switches
14 ______________________________________________________________________________________
Inductor Selection
Choose an inductor with the following equation:
where LIR is the ratio of the inductor ripple current to full
load current at the minimum duty cycle. Choose LIR
between 20% to 40% for best performance and stability.
Use an inductor with the lowest possible DC resistance
that fits in the allotted dimensions. Powdered iron ferrite
core types are often the best choice for performance.
With any core material, the core must be large enough
not to saturate at the current limit of the MAX15039.
Output-Capacitor Selection
The key selection parameters for the output capacitor are
capacitance, ESR, ESL, and voltage-rating requirements.
These affect the overall stability, output ripple voltage,
and transient response of the DC-DC converter. The out-
put ripple occurs due to variations in the charge stored
in the output capacitor, the voltage drop due to the
capacitor’s ESR, and the voltage drop due to the
capacitor’s ESL. Estimate the output-voltage ripple due
to the output capacitance, ESR, and ESL:
where the output ripple due to output capacitance,
ESR, and ESL is:
or:
or whichever is larger.
The peak-to-peak inductor current (IP-P) is:
Use these equations for initial output-capacitor selec-
tion. Determine final values by testing a prototype or an
evaluation circuit. A smaller ripple current results in less
output-voltage ripple. Since the inductor ripple current
is a factor of the inductor value, the output-voltage rip-
ple decreases with larger inductance. Use ceramic
capacitors for low ESR and low ESL at the switching
frequency of the converter. The ripple voltage due to
ESL is negligible when using ceramic capacitors.
Load-transient response depends on the selected out-
put capacitance. During a load transient, the output
instantly changes by ESR x ΔILOAD. Before the con-
troller can respond, the output deviates further,
depending on the inductor and output capacitor val-
ues. After a short time, the controller responds by regu-
lating the output voltage back to its predetermined
value. The controller response time depends on the
closed-loop bandwidth. A higher bandwidth yields a
faster response time, preventing the output from deviat-
ing further from its regulating value. See the
Compen-
sation Design
section for more details.
Input-Capacitor Selection
The input capacitor reduces the current peaks drawn
from the input power supply and reduces switching
noise in the IC. The total input capacitance must be
equal or greater than the value given by the following
equation to keep the input-ripple voltage within specifi-
cation and minimize the high-frequency ripple current
being fed back to the input source:
where VIN-RIPPLE is the maximum allowed input ripple
voltage across the input capacitors and is recommend-
ed to be less than 2% of the minimum input voltage. D
is the duty cycle (VOUT/VIN) and TSis the switching
period (1/fS).
The impedance of the input capacitor at the switching
frequency should be less than that of the input source so
high-frequency switching currents do not pass through
the input source, but are instead shunted through the
input capacitor. The input capacitor must meet the ripple
current requirement imposed by the switching currents.
The RMS input ripple current is given by:
where IRIPPLE is the input RMS ripple current.
II VVV
V
RIPPLE LOAD OUT IN OUT
IN
=× ×−()
CDxT xI
V
IN MIN SOUT
IN RIPPLE
_=
-
IVV
fL xV
V
PP IN OUT
S
OUT
IN
−=×
−
VI
RIPPLE ESL P
()
=−PP
OFF
tx ESL
VI
tx ESL
RIPPLE ESL PP
ON
()
=−
VIxE
RIPPLE ESR P P()
=−SSR
VI
xC xf
RIPPLE C PP
OUT S
()
=−
8
VV V V
RIPPLE RIPPLE C RIPPLE ESR RIPPLE ESL
=+ +
() ( ) ( ))
LVVV
fV LIRI
OUT IN OUT
SIN OUTMAX
=×
×××
−()
()
MAX15039
Compensation Design
The power transfer function consists of one double pole
and one zero. The double pole is introduced by the
inductor L and the output capacitor CO. The ESR of the
output capacitor determines the zero. The double pole
and zero frequencies are given as follows:
where RLis equal to the sum of the output inductor’s DCR
(DC resistance) and the internal switch resistance,
RDS(ON). A typical value for RDS(ON) is 20mΩ(low-side
MOSFET) and 26mΩ(high-side MOSFET). ROis the output
load resistance, which is equal to the rated output voltage
divided by the rated output current. ESR is the total equiv-
alent series resistance of the output capacitor. If there is
more than one output capacitor of the same type in paral-
lel, the value of the ESR in the above equation is equal to
that of the ESR of a single output capacitor divided by the
total number of output capacitors.
The high switching frequency range of the MAX15039
allows the use of ceramic output capacitors. Since the
ESR of ceramic capacitors is typically very low, the fre-
quency of the associated transfer function zero is higher
than the unity-gain crossover frequency, fC, and the zero
cannot be used to compensate for the double pole creat-
ed by the output filtering inductor and capacitor. The dou-
ble pole produces a gain drop of 40dB/decade and a
phase shift of 180°. The compensation network error
amplifier must compensate for this gain drop and phase
shift to achieve a stable high-bandwidth closed-loop sys-
tem. Therefore, use type III compensation as shown in
Figures 3 and 4. Type III compensation possesses three
poles and two zeros with the first pole, fP1_EA, located at
zero frequency (DC). Locations of other poles and zeros
of the type III compensation are given by:
The above equations are based on the assumptions
that C1 >> C2 and R3 >> R2 are true in most applica-
tions. Placements of these poles and zeros are deter-
mined by the frequencies of the double pole and ESR
zero of the power transfer function. It is also a function
of the desired close-loop bandwidth. The following sec-
tion outlines the step-by-step design procedure to cal-
culate the required compensation components for the
MAX15039. When the output voltage of the MAX15039
is programmed to a preset voltage, R3 is internal to the
IC and R4 does not exist (Figure 3b).
When externally programming the MAX15039 (Figure
3a), the output voltage is determined by:
or:
if using an external VREFIN, and VOUT > VREFIN.
For a 0.6V output, or for VOUT = VREFIN, connect an
8.06kΩresistor from FB to VOUT. The zero-cross fre-
quency of the close-loop, fC, should be between 10%
and 20% of the switching frequency, fS. A higher zero-
cross frequency results in faster transient response.
Once fCis chosen, C1 is calculated from the following
equation:
where VP-P is the ramp peak-to-peak voltage (1V typ).
Due to the underdamped nature of the output LC dou-
ble pole, set the two zero frequencies of the type III
compensation less than the LC double-pole frequency
to provide adequate phase boost. Set the two zero fre-
quencies to 80% of the LC double-pole frequency.
Hence:
CxR xL x C x R ESR
RR
OO
LO
31
08 3
=+
+.
()
RxC xL x C x R ESR
RR
OO
LO
11
08 1
=+
+.
()
C
xV
V
xxRx R
Rf
IN
PP
L
OC
1
1 5625
231
=
+×
−
.
()π
()
()
RVR
VV
REFIN
OUT REFIN
43
=×
−
RR
Vfor V V
OUT OUT
406 3
06 06=×>
−
.
(.)
(.))
1
223
2π
=××
fRC
PEA_
fPEA3
1
_=2212π× ×RC
fRC
ZEA2
1
233
_=××π
fRC
ZEA1
1
211
_=××π
fx ESR x C
Z ESR O
_=1
2π
ff
xLxC x R ESR
RR
PLC P LC
OO
OL
12
1
2
__
==
+
+
⎛
⎝
⎜
⎞
⎠
⎟
π
6A, 2MHz Step-Down Regulator
with Integrated Switches
______________________________________________________________________________________ 15
Set the third compensation pole at 1/2 of the switching
frequency. Calculate C2 as follows:
The above equations provide application compensation
when the zero-cross frequency is significantly higher than
the double-pole frequency. When the zero-cross frequen-
cy is near the double-pole frequency, the actual zero-
cross frequency is higher than the calculated frequency.
In this case, lowering the value of R1 reduces the zero-
cross frequency. Also, set the third pole of the type III
compensation close to the switching frequency if the
zero-cross frequency is above 200kHz to boost the phase
margin. The recommended range for R3 is 2kΩto 10kΩ.
Note that the loop compensation remains unchanged if
only R4’s resistance is altered to set different outputs.
MODE Selection
The MAX15039 features a mode selection input
(MODE) that users can select a functional mode for the
device (see Table 2).
Forced-PWM Mode
Connect MODE to GND to select forced-PWM mode. In
forced-PWM mode, the MAX15039 operates at a con-
stant switching frequency (set by the resistor at FREQ
terminal) with no pulse skipping. PWM operation starts
after a brief settling time when EN goes high. The low-
side switch turns on first, charging the bootstrap
capacitor to provide the gate-drive voltage for the high-
side switch. The low-side switch turns off either at the
end of the clock period or once the low-side switch
sinks 1.35A current (typ), whichever occurs first. If the
low-side switch is turned off before the end of the clock
period, the high-side switch is turned on for the remain-
ing part of the time interval until the inductor current
reaches 0.9A, or the end of clock cycle is encountered.
Starting from the first PWM activity, the sink current
threshold is increased through an internal 4-step DAC
to reach the current limit of 11A after 128 clock periods.
This is done to help a smooth recovery of the regulated
voltage even in case of accidental prebiased output in
spite of the initial forced-PWM mode selection.
Soft-Starting Into a Prebiased Output
Mode (Monotonic Startup)
When MODE is left unconnected or biased to VDD/2, the
MAX15039 soft-starts into a prebiased output without dis-
charging the output capacitor. This type of operation is
also termed monotonic startup. See the Starting Into
Prebiased Output waveforms in the
Typical Operating
Characteristics
section for an example.
In monotonic startup mode, both low-side and high-
side switches remain off to avoid discharging the prebi-
ased output. PWM operation starts when the FB voltage
crosses the SS voltage. As in forced-PWM mode, the
PWM activity starts with the low-side switch turning on
first to build the bootstrap capacitor charge.
CRf
S
21
1
=××π
RC x ESR
C
O
23
=
DOUBLE POLE
GAIN (dB)
SECOND
POLE
FIRST AND SECOND ZEROS
POWER-STAGE
TRANSFER
FUNCTION
COMPENSATION
TRANSFER
FUNCTION
OPEN-LOOP
GAIN
THIRD
POLE
Figure 4. Type III Compensation Illustration
MAX15039
6A, 2MHz Step-Down Regulator
with Integrated Switches
16 ______________________________________________________________________________________
MODE CONNECTION OPERATION MODE
GND Forced PWM
Unconnected or
VDD/2
Forced PWM. Soft-start up into a
prebiased output (monotonic startup).
VDD Skip Mode. Soft-start into a prebiased
output (monotonic startup).
Table 2. Mode Selection
MAX15039
The MAX15039 is also able to start into prebiased with
the output above the nominal set point without abruptly
discharging the output, thanks to the sink current con-
trol of the low-side switch through a 4-step DAC in 128
clock cycles. Monotonic startup mode automatically
switches to forced-PWM mode 4096 clock cycles delay
after the voltage at FB increases above 92.5% of
VREFIN. The additional delay prevents an early transi-
tion from monotonic startup to forced-PWM mode dur-
ing soft-start when a prolonged time constant external
REFIN voltage is applied.
The maximum allowed soft-start time is 2ms when an
external reference is applied at REFIN in the case of
starting up into prebiased output.
Skip Mode
Connect MODE to VDD to select skip mode. In skip
mode, the MAX15039 switches only as necessary to
maintain the output at light loads (not capable of sinking
current from the output), but still operates with fixed-fre-
quency (set by the resistor at FREQ terminal) PWM at
medium and heavy loads. This maximizes light-load effi-
ciency and reduces the input quiescent current.
In case of prolonged high-side idle activity (beyond
eight clock cycles), the low-side switch is turned on
briefly to rebuild the charge lost in the bootstrap capac-
itor before the next on-cycle of the high-side switch.
In skip mode, the low-side switch is turned off when the
inductor current decreases to 0.2A (typ) to ensure no
reverse current flowing from the output capacitor and
the best conversion efficiency/minimum supply current.
The high-side switch minimum on-time is controlled to
guarantee that 0.9A current is reached to avoid high
frequency bursts at no load conditions and that might
cause a rapid increase of the supply current caused by
additional switching losses.
Even if skip mode is selected at the device turn-on, the
monotonic startup mode is internally selected during
soft-start. The transition to skip mode is automatically
achieved 4096 clock cycles after the voltage at FB
increases above 92.5% of VREFIN.
Changing from skip mode to forced-PWM mode and
vice-versa can be done at any time. The output capaci-
tor should be large enough to limit the output-voltage
overshoot/undershoot due to the settling times to reach
different duty-cycle set points corresponding to forced-
PWM mode and skip mode at light loads.
PCB Layout Considerations and
Thermal Performance
Careful PCB layout is critical to achieve clean and sta-
ble operation. It is highly recommended to duplicate the
MAX15039 EV kit layout for optimum performance. If devi-
ation is necessary, follow these guidelines for good PCB
layout:
1) Connect input and output capacitors to the power
ground plane; connect all other capacitors to the sig-
nal ground plane.
2) Place capacitors on VDD, IN, and SS as close as pos-
sible to the IC and its corresponding pin using direct
traces. Keep power ground plane (connected to
PGND) and signal ground plane (connected to GND)
separate.
3) Keep the high-current paths as short and wide as
possible. Keep the path of switching current short
and minimize the loop area formed by LX, the out-
put capacitors, and the input capacitors.
4) Connect IN, LX, and PGND separately to a large
copper area to help cool the IC to further improve
efficiency and long-term reliability.
5) Ensure all feedback connections are short and
direct. Place the feedback resistors and compensa-
tion components as close as possible to the IC.
6) Route high-speed switching nodes, such as LX,
away from sensitive analog areas (FB, COMP).
6A, 2MHz Step-Down Regulator
with Integrated Switches
______________________________________________________________________________________ 17
MAX15039
6A, 2MHz Step-Down Regulator
with Integrated Switches
18 ______________________________________________________________________________________
Chip Information
PROCESS: BiCMOS
THIN QFN
MAX15039
19
20
EP
21
22
12 3456
18 17 16 15 14 13
23
24
12
11
10
9
8
7
PGND
IN
PGND
IN
EN
MODE
VDD
CTL1
CTL2
REFIN
SS
PGND
PGND
LX
LX
BST
IN
PWRGD
OUT
FREQ
FB
GND
COMP
LX
TOP VIEW
+
Pin Configuration
Package Information
For the latest package outline information and land patterns
(footprints), go to www.maxim-ic.com/packages. Note that a
“+”, “#”, or “-” in the package code indicates RoHS status only.
Package drawings may show a different suffix character, but
the drawing pertains to the package regardless of RoHS status.
PACKAGE
TYPE
PACKAGE
CODE
OUTLINE
NO.
LAND
PATTERN NO.
24 TQFN-EP T2444-4 21-0139 90-0022
MAX15039
6A, 2MHz Step-Down Regulator
with Integrated Switches
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________
19
© 2010 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.
Revision History
REVISION
NUMBER
REVISION
DATE DESCRIPTION PAGES
CHANGED
0 10/08 Initial release —
1 12/09 Updated the Typical Operating Characteristics.5
2 5/10 Updated the Electrical Characteristics, Table 1, and the Compensation
Design section. 3, 13, 15
3 12/10 Corrected error in C1 equation 15
