MM74HCT74 — Dual D-Type Flip-Flop with Preset and Clear
©1984 Fairchild Semiconductor Corporation www.fairchildsemi.com
MM74HCT74 Rev. 1.4.0
March 2008
MM74HCT74
Dual D-Type Flip-Flop with Preset and Clear
Features
■
Typical propagation delay: 20ns
■
Low quiescent current: 40µA maximum (74HCT Series)
■
Low input current: 1µA maximum
■
Fanout of 10 LS-TTL loads
■
Meta-stable hardened
General Description
The MM74HCT74 utilizes advanced silicon-gate CMOS
technology to achieve operation speeds similar to the
equivalent LS-TTL part. It possesses the high noise
immunity and low power consumption of standard
CMOS integrated circuits, along with the ability to drive
10 LS-TTL loads.
This flip-flop has independent data, preset, clear, and
clock inputs and Q and Q outputs. The logic level
present at the data input is transferred to the output
during the positive-going transition of the clock pulse.
Preset and clear are independent of the clock and
accomplished by a low level at the appropriate input.
The 74HCT logic family is functionally and pin-out
compatible with the standard 74LS logic family. All inputs
are protected from damage due to static discharge by
internal diode clamps to V
CC
and ground.
MM74HCT devices are intended to interface between
TTL and NMOS components and standard CMOS
devices. These parts are also plug-in replacements for
LS-TTL devices and can be used to reduce power
consumption in existing designs.
Ordering Information
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.
All packages are lead free per JEDEC: J-STD-020B standard.
Order Number
Package
Number Package Description
MM74HCT74M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
MM74HCT74SJ M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
MM74HCT74MTC MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
MM74HCT74N N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
©1984 Fairchild Semiconductor Corporation www.fairchildsemi.com
MM74HCT74 Rev. 1.4.0 2
MM74HCT74 — Dual D-Type Flip-Flop with Preset and Clear
Connection Diagram
Pin Assignments for DIP, SOIC, SOP and TSSOP
Truth Table
Q0
=
the level of Q before the indicated input conditions
were established.
Note:
1. This configuration is nonstable; that is, it will not persist
when preset and clear inputs return to their inactive
(HIGH) level.
Logic Diagram
Inputs Outputs
PR CLR CLK D Q Q
LHXXHL
HLXXLH
LLXXH
(1)
H
(1)
HH
↑
HHL
HH
↑
LLH
HHLXQ0 Q0
©1984 Fairchild Semiconductor Corporation www.fairchildsemi.com
MM74HCT74 Rev. 1.4.0 3
MM74HCT74 — Dual D-Type Flip-Flop with Preset and Clear
Absolute Maximum Ratings
(2)
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Notes:
2. Unless otherwise specified all voltages are referenced to ground.
3. Power Dissipation temperature derating — plastic “N” package: –12 mW/°C from 65°C to 85°C.
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to absolute maximum ratings.
Symbol Parameter Rating
V
CC
Supply Voltage –0.5 to +7.0V
V
IN
DC Input Voltage –1.5 to V
CC
+1.5V
V
OUT
DC Output Voltage –0.5 to V
CC
+0.5V
I
IK
, I
OK
Clamp Diode Current ±20mA
I
OUT
DC Output Current, per pin ±25mA
I
CC
DC V
CC
or GND Current, per pin ±50mA
T
STG
Storage Temperature Range –65°C to +150°C
P
D
Power Dissipation
Note 3
S.O. Package only
600mW
500mW
T
L
Lead Temperature (Soldering 10 seconds) 260°C
Symbol Parameter Min. Max. Units
V
CC
Supply Voltage 4.5 5.5 V
V
IN
, V
OUT
DC Input or Output Voltage 0 V
CC
V
T
A
Operating Temperature Range –40 +85 °C
t
r
, t
f
Input Rise or Fall Times 500 ns
©1984 Fairchild Semiconductor Corporation www.fairchildsemi.com
MM74HCT74 Rev. 1.4.0 4
MM74HCT74 — Dual D-Type Flip-Flop with Preset and Clear
DC Electrical Characteristics
V
CC
=
5V ±10% (unless otherwise specified).
Note:
4. This is measured per pin. All other inputs are held at V
CC
Ground.
AC Electrical Characteristics
V
CC
=
5V, T
A
=
25°C, C
L
=
15 pF, t
r
=
t
f
=
6ns.
Symbol Parameter Conditions
T
A
=
Units
25°C
–40°C to
85°C
–55°C to
125°C
Typ. Guaranteed Limits
V
IH
Minimum HIGH Level
Input Voltage
2.0 2.0 2.0 V
V
IL
Maximum LOW Level
Input Voltage
0.8 0.8 0.8 V
V
OH
Minimum HIGH Level
Output Voltage
V
IN
=
V
IH
or V
IL
, |I
OUT
|
=
20µA V
CC
V
CC
– 0.1 V
CC
– 0.1 V
CC
– 0.1 V
V
IN
=
V
IH
or V
IL
, |I
OUT
|
=
4.0mA,
V
CC
=
4.5V
4.2 3.98 3.84 3.7
V
IN
=
V
IH
or V
IL
, |I
OUT
|
=
4.8mA,
V
CC
=
5.5V
5.2 4.98 4.84 4.7
V
OL
Maximum LOW Level
Voltage
V
IN
=
V
IH
or V
IL
, |I
OUT
|
=
20µA 0 0.1 0.1 0.1 V
V
IN
=
V
IH
or V
IL
, |I
OUT
|
=
4.0mA,
V
CC
=
4.5V
0.2 0.26 0.33 0.4
V
IN
=
V
IH
or V
IL
, |I
OUT
|
=
4.8mA,
V
CC
=
5.5V
0.2 0.26 0.33 0.4
I
IN
Maximum Input
Current
V
IN
=
V
CC
or GND, V
IH
or V
IL
±0.5 ±0.5 ±1.0 µA
I
CC
Maximum Quiescent
Supply Current
V
IN
=
V
CC
or GND, I
OUT
=
0µA 2.0 20 80 µA
V
IN
=
2.4V or 0.5V
(4)
0.3 0.4 0.5 mA
Symbol Parameter Conditions Typ.
Guaranteed
Limit Units
f
MAX
Maximum Operating Frequency from Clock to
Q or Q
50 30 MHz
t
PHL
, t
PLH
Maximum Propagation Delay Clock to Q or Q 18 30 ns
t
PHL
, t
PLH
Maximum Propagation Delay from Preset or
Clear to Q or Q
18 30 ns
t
REM
Minimum Removal Time, Preset or Clear to
Clock
20 ns
t
SMinimum Setup Time Data to Clock 20 ns
tHMinimum Hold Time Clock to Data –3 0 ns
tWMinimum Pulse Width Clock, Preset or Clear 8 16 ns
©1984 Fairchild Semiconductor Corporation www.fairchildsemi.com
MM74HCT74 Rev. 1.4.0 5
MM74HCT74 — Dual D-Type Flip-Flop with Preset and Clear
AC Electrical Characteristics
VCC = 5.0V ± 10%, CL = 50 pF, tr = tf = 6ns unless otherwise specified.
Note:
5. CPD determines the no load dynamic power consumption, PD = CPD VCC2 f + ICC VCC, and the no load dynamic
current consumption, IS = CPD VCC f + ICC.
Symbol Parameter Conditions
TA = 25°C TA = –40° to +85°C
UnitsTyp. Guaranteed Limits
fMAX Maximum Operating Frequency 27 21 MHz
tPHL, tPLH Maximum Propagation Delay from
Clock to Q or Q
21 35 44 ns
tPHL, tPLH Maximum Propagation Delay from
Preset or Clear to Q or Q
21 35 44 ns
tREM Minimum Removal Time Preset or
Clear to Clock
20 25 ns
tSMinimum Setup Time Data to
Clock
20 25 ns
tHMinimum Hold Time Clock to Data –3 0 0 ns
tWMinimum Pulse Width Clock,
Preset or Clear
916 20 ns
tr, tfMaximum Clock Input Rise and
Fall Time
500 500 ns
tTHL, tTLH Maximum Output Rise and Fall
Time
15 19 ns
CPD Power Dissipation Capacitance(5) (per flip-flop) 10 pF
CIN Maximum Input Capacitance 5 10 10 pF
©1984 Fairchild Semiconductor Corporation www.fairchildsemi.com
MM74HCT74 Rev. 1.4.0 6
MM74HCT74 — Dual D-Type Flip-Flop with Preset and Clear
Physical Dimensions
Figure 1. 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/
LAND PATTERN RECOMMENDATION
NOTES: UNLESS OTHERWISE SPECIFIED
A) THIS PACKAGE CONFORMS TO JEDEC
MS-012, VARIATION AB, ISSUE C,
B) ALL DIMENSIONS ARE IN MILLIMETERS.
C) DIMENSIONS DO NOT INCLUDE MOLD
FLASH OR BURRS.
D) LANDPATTERN STANDARD:
SOIC127P600X145-14M
E) DRAWING CONFORMS TO ASME Y14.5M-1994
F) DRAWING FILE NAME: M14AREV13
PIN ONE
INDICATOR
8°
0°
SEATING PLANE
DETAIL A
SCALE: 20:1
GAGE PLANE
0.25
X45°
1
0.10
C
C
BC A
7
M
14 B
A
8
SEE DETAIL A
5.60
0.65
1.70 1.27
8.75
8.50
7.62
6.00 4.00
3.80
(0.33)
1.27 0.51
0.35
1.75 MAX
1.50
1.25
0.25
0.10
0.25
0.19
(1.04)
0.90
0.50
0.36
R0.10
R0.10
0.50
0.25
©1984 Fairchild Semiconductor Corporation www.fairchildsemi.com
MM74HCT74 Rev. 1.4.0 7
MM74HCT74 — Dual D-Type Flip-Flop with Preset and Clear
Physical Dimensions (Continued)
Figure 2. 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/
©1984 Fairchild Semiconductor Corporation www.fairchildsemi.com
MM74HCT74 Rev. 1.4.0 8
MM74HCT74 — Dual D-Type Flip-Flop with Preset and Clear
Physical Dimensions (Continued)
Figure 3. 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/
C. DIMENSIONS ARE EXCLUSIVE OF BURRS, MOLD FLASH,
AND TIE BAR EXTRUSIONS
F. DRAWING FILE NAME: MTC14REV6
R0.09 min
12.00°TOP & BOTTO
M
0.43 TYP
1.00
D. DIMENSIONING AND TOLERANCES PER ANSI
Y14.5M, 1982
R0.09min
E. LANDPATTERN STANDARD: SOP65P640X110-14M
0.65
6.10
1.65
0.45
A. CONFORMS TO JEDEC REGISTRATION MO-153,
VARIATION AB, REF NOTE 6
B. DIMENSIONS ARE IN MILLIMETERS
©1984 Fairchild Semiconductor Corporation www.fairchildsemi.com
MM74HCT74 Rev. 1.4.0 9
MM74HCT74 — Dual D-Type Flip-Flop with Preset and Clear
Physical Dimensions (Continued)
Figure 4. 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/
14 8
7
1
NOTES: UNLESS OTHERWISE SPECIFIED
A)
THIS PACKAGE CONFORMS TO
JEDEC MS-001 VARIATION BA
B) ALL DIMENSIONS ARE IN MILLIMETERS.
C)
DIMENSIONS ARE EXCLUSIVE OF BURRS,
MOLD FLASH, AND TIE BAR EXTRUSIONS.
D) DIMENSIONS AND TOLERANCES PER
ASME Y14.5-1994
E) DRAWING FILE NAME: MKT-N14AREV7
6.60
6.09
8.12
7.62
0.35
0.20
19.56
18.80
3.56
3.30 5.33 MAX
0.38 MIN
1.77
1.14
0.58
0.35 2.54
3.81
3.17 8.82
(1.74)
©1984 Fairchild Semiconductor Corporation www.fairchildsemi.com
MM74HCT74 Rev. 1.4.0 10
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when properly used in accordance with instructions for use
provided in the labeling, can be reasonably expected to
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PRODUCT STATUS DEFINITIONS
Definition of Terms
Datasheet Identification Product Status Definition
Advance Information Formative or In Design This datasheet contains the design specifications for product
development. Specifications may change in any manner without notice.
Preliminary First Production
This datasheet contains preliminary data; supplementary data will be
published at a later date. Fairchild Semiconductor reserves the right to
make changes at any time without notice to improve design.
No Identification Needed Full Production
This datasheet contains final specifications. Fairchild Semiconductor
reserves the right to make changes at any time without notice to improve
the design.
Obsolete Not In Production
This datasheet contains specifications on a product that has been
discontinued by Fairchild Semiconductor. The datasheet is printed for
reference information only.
Rev. I33
MM74HCT74 — Dual D-Type Flip-Flop with Preset and Clear
