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CY7C1041G Automotive
4-Mbit (256K words × 16-bit) Static RAM
with Error-Correcting Code (ECC)
Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600
Document Number: 001-91255 Rev. *J Revised July 16, 2018
4-Mbit (256K w ords × 16-bit) Static RAM with Er ror-Correcti ng Code (ECC)
Features
■AEC-Q100 qualified
■High speed
❐tAA = 10 ns
■Temperature range
❐Automotive-E: –40 °C to 125 °C
❐Automotive-A: –40 °C to 85 °C
■Embedded ECC for single-bit error correction[1, 2]
■Low active and standby currents
❐Active current ICC = 40 mA typical
❐Standby current ISB2 = 6 mA typical
■Operating voltage range: 2.2 V to 3.6 V
■1.0 V data retention
■TTL- compatible inputs and outputs
■Pb-free 48-ball VFBGA and 44-pin TSOP II packages
Functional Description
CY7C1041G is a high-performance CMOS fast static RAM
automotive part with embedded ECC. This device has a single
Chip Enable (CE) input and is accessed by asserting it LOW.
Data writes are performed by asserting the Write Enable (WE)
input LOW, while providing the data on I/O0 through I/O15 and
the address on A0 through A17 pins. The Byte High Enable (BHE)
and Byte Low Enable (BLE) inputs control write operations to the
upper and lower bytes of the specified memory location. BHE
controls I/O8 through I/O15 and BLE controls I/O0 through I/O7.
Data reads are performed by asserting the Output Enable (OE)
input and providing the required address on the address lines.
Read data is accessible on the I/O lines (I/O0 through I/O15).
Byte accesses can be performed by asserting the required byte
enable signal (BHE or BLE) to read either the upper byte or the
lower byte of data from the specified address location.
All I/Os (I/O0 through I/O15) are placed in a HI-Z state when the
device is deselected (CE LOW), or when the control signals are
deasserted (OE, BLE, BHE). Refer to the following logic block
diagram.
Logic Block Diagram – CY7C1041G
MEMORY
ARRAY
ROWDECODER
A1
A2
A3
A4
A5
A6
A7
A8
A9
A0
COLUMNDECODER
A10
SENSE
AMPLIFIERS
ECCDECODER
A11
A12
A13
A14
A15
A16
A17
ECCENCODER INPUTBUFFER
I/O0‐I/O7
I/O8‐I/O15
BHE
WE
OE
BLE
CE2
CE1
Note
1. This device does not support automatic write-back on error detection.
2. SER FIT Rate <0.1 FIT/Mb. Refer AN88889 for details.
Document Number: 001-91255 Rev. *J Page 2 of 16
CY7C1041G Automotive
Contents
Pin Configurations ........................................................... 3
Product Portfolio .............................................................. 3
Maximum Ratings ............................................................. 4
Operating Range ............................................................... 4
DC Electrical Characteristics .......................................... 4
Capacitance ...................................................................... 5
Thermal Resistance .......................................................... 5
AC Test Loads and Waveforms ....................................... 5
Data Retention Characteristics ....................................... 6
Data Retention Waveform ................................................ 6
AC Switching Characteristics ......................................... 7
Switching Waveforms ...................................................... 8
Truth Table ...................................................................... 11
Ordering Information ...................................................... 12
Ordering Code Definitions ......................................... 12
Package Diagrams .......................................................... 13
Acronyms ........................................................................ 14
Document Conventions ................................................. 14
Units of Measure ....................................................... 14
Document History Page ................................................. 15
Sales, Solutions, and Legal Information ...................... 16
Worldwide Sales and Design Support ....................... 16
Products .................................................................... 16
PSoC® Solutions ...................................................... 16
Cypress Developer Community ................................. 16
Technical Support ..................................................... 16
Document Number: 001-91255 Rev. *J Page 3 of 16
CY7C1041G Automotive
Pin Configurations
Figure 1. 48-ball VFBGA Pinout [3]
Figure 2. 44-pin TSOP II Pinout [3]
OEBLE A0A2
A1NC
BHEI/O8A3CEA4I/O0
I/O10
I/O9A5I/O1
A6I/O2
I/O11
VSS A17 I/O3
A7VCC
I/O12
VCC NC I/O4
A16 VSS
I/O13
I/O14 A14 I/O5
A15 I/O6
NCI/O15 A12 WEA13 I/O7
A8
NC A9A11
A10 NC
12 3456
A
B
C
D
E
F
G
H
A1 243
A2 342
A3 441
A15
738
A16
639
/CE
I/O7
I/O0
936
I/O6
I/O1
10 35
VSSVCC 11 34
VCCVSS 12 33
I/O4
I/O2
13 32
I/O5
I/O3
14 31
A14
/WE
15 30
A13
A5
16 29
A12
A6
17 28
A11
A7
18 27
A10
A8
19 26
A9
20 25
NC
21 24
22 23
A0 144
/OE
837
A17
A4 540
44-pin TSOP II
I/O8
I/O9
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15
/BH E
/BLE
Notes
3. NC pins are not connected internally to the die.
4. Typical values are included for reference only and are not guaranteed or tested.
Product Portfolio
Product Range VCC Range (V) Speed
(ns)
Power Dissipation
Operating ICC, (mA), f = fmax Standby, ISB2 (mA)
Typ[4] Max Typ[4] Max
CY7C1041G Automotive-E 2.2 V–3.6 V 10 40 50 6 14
Automotive-A 38 45 6 8
Document Number: 001-91255 Rev. *J Page 4 of 16
CY7C1041G Automotive
Maximum Ratings
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Storage temperature ................................ –65 C to +150 C
Ambient temperature
with power applied ................................... –55 C to +125 C
Supply voltage
on VCC relative to GND[5] .....................–0.5 V to Vcc +0.3 V
DC voltage applied to outputs
in HI-Z State[5] ......................................–0.3 V to Vcc +0.3 V
DC input voltage[5] .............................. –0.3 V to VCC + 0.3 V
Current into outputs (in low state) ............................... 20 mA
Static discharge voltage
(MIL-STD-883, Method 3015) ................................. > 2001 V
Latch-up current .................................................... > 140 mA
Operating Range
Grade Ambient Temperature VCC
Automotive-E –40 C to +125 C 2.2 V to 3.6 V
Automotive-A –40 C to +85 C 2.2 V to 3.6 V
DC Electrical Characteristics
Over the Operating Range
Parameter Description Test Conditions 10 ns (Automotive-E) 10 ns (Automotive-A) Unit
Min Typ Max Min Typ Max
VOH Output
HIGH
voltage
2.2 V to 2.7 V VCC = Min, IOH = –1.0 mA 2 – – 2 – – V
2.7 V to 3.0 V VCC = Min, IOH = –4.0 mA 2.2 – – 2.2 – –
3.0 V to 3.6 V VCC = Min, IOH = –4.0 mA 2.4 – – 2.4 – –
VOL Output
LOW
voltage
2.2 V to 2.7 V VCC = Min, IOL = 2 mA – – 0.4 – – 0.4 V
2.7 V to 3.6 V VCC = Min, IOL = 8 mA – – 0.4 – – 0.4
VIH Input HIGH
voltage
2.2 V to 2.7 V – 2 – VCC + 0.3[5] 2–V
CC + 0.3[5] V
2.7 V to 3.6 V – 2 – VCC + 0.3[5] 2–V
CC + 0.3[5]
VIL Input LOW
voltage
2.2 V to 2.7 V – –0.3[5] – 0.6 –0.3[5] –0.6V
2.7 V to 3.6 V – –0.3[5] – 0.8 –0.3[5] –0.8
IIX Input leakage current GND < VIN < VCC –5 – +5 –1 – +1 A
IOZ Output leakage current GND < VOUT < VCC,
Output disabled
–5 – +5 –1 – +1 A
ICC Operating supply current VCC = 3.6 V,
IOUT = 0 mA,
CMOS
levels
f = fMAX = 1/tRC – 40 50 – 38 45 mA
ISB1 Automatic CE power down
current – TTL inputs
VCC = 3.6 V, CE > VIH,
VIN > VIH or VIN < VIL,
f = fMAX
–– 24 –– 15 mA
ISB2 Automatic CE power down
current – CMOS inputs
VCC = 3.6 V,
CE > VCC – 0.2 V,
VIN > VCC – 0.2 V or
VIN < 0.2 V,
f = 0
–6 14 –6 8 mA
Note
5. VIL(min) = –2.0 V and VIH(max) = VCC + 2 V for pulse durations of less than 20 ns.
Document Number: 001-91255 Rev. *J Page 5 of 16
CY7C1041G Automotive
Capacitance
Parameter[6] Description Test Conditions All Packages Unit
CIN Input capacitance TA = 25 C, f = 1 MHz, VCC = VCC(typ) 10 pF
COUT I/O capacitance 10 pF
Thermal Resistance
Parameter[6] Description Test Conditions 48-ball VFBGA 44-pin TSOPII Unit
JA Thermal resistance
(junction to ambient)
Still air, soldered on a 3 × 4.5 inch,
four-layer printed circuit board
30.68 66.82 C/W
JC Thermal resistance
(junction to case)
14.83 15.97 C/W
AC Test Loads and Waveforms
Figure 3. AC Test Loads and Waveforms [7]
90%
10%
VHIGH
GND
90%
10%
All Input Pulses
VCC
Output
5 pF*
* Including
jig and
scope (b)
R1
R2
Rise Time: Fall Time:
> 1 V/ns
(c)
Output
50
Z
0
= 50
V
TH
30 pF*
* Capacitive load consists
of all components of the
test environment
High-Z Characteristics:
(a)
> 1 V/ns
Parameters 3.0 V Unit
R1 317
R2 351
VTH 1.5 V
VHIGH 3V
Notes
6. Tested initially and after any design or process change that may affect these parameters.
7. Full-device AC operation assumes a 100 µs ramp time from 0 to VCC(min) and a 100 µs wait time after VCC stabilization.
Document Number: 001-91255 Rev. *J Page 6 of 16
CY7C1041G Automotive
Data Retention Characteristics
Over the Operating Range
Parameter Description Conditions Automotive-E Automotive-A Unit
Min Max Min Max
VDR VCC for data retention – 1 – 1 – V
ICCDR Data retention current VCC = 1.2 V,
CE > VCC – 0.2 V,
VIN > VCC – 0.2 V or
VIN < 0.2 V
–14– 8mA
tCDR[8] Chip deselect to data retention
time
– 0–0–ns
tR[8, 9] Operation recovery time VCC > 2.2 V 10 – 10 – ns
Data Retention Waveform
Figure 4. Data Retention Waveform [9]
Notes
8. These parameters are guaranteed by design.
9. Full-device operation requires linear VCC ramp from VDR to VCC(min.) > 100 s or stable at VCC(min.) > 100 s.
Document Number: 001-91255 Rev. *J Page 7 of 16
CY7C1041G Automotive
AC Switching Characteristics
Over the Operating Range
Parameter[10] Description 10 ns (Automotive-A/Automotive-E) Unit
Min Max
Read Cycle
tRC Read cycle time 10 – ns
tAA Address to data – 10 ns
tOHA Data 3 – ns
tACE CE LOW to data[11] –10ns
tDOE OE LOW to data – 4.5 ns
tLZOE OE LOW to low impedance[12, 13] 0–ns
tHZOE OE HIGH to HI-Z[12, 13] –5ns
tLZCE CE LOW to low impedance[11, 12, 13] 3–ns
tHZCE CE HIGH to HI-Z[11, 12, 13] –5ns
tPU CE LOW to power up[11, 13] 0–ns
tPD CE HIGH to power down[11, 13] –10ns
tDBE Byte enable to data valid – 4.5 ns
tLZBE Byte enable to low impedance[13] 0–ns
tHZBE Byte disable to HI-Z[13] –6ns
Write Cycle[14, 15]
tWC Write cycle time 10 – ns
tSCE CE LOW to write end[10] 7–ns
tAW Address setup to write end 7 – ns
tHA Address hold from write end 0–ns
tSA Address setup to write start 0 – ns
tPWE WE pulse width 7 – ns
tSD Data setup to write end 5 – ns
tHD Data hold from write end 0 – ns
tLZWE WE HIGH to low impedance[12, 13] 3–ns
tHZWE WE LOW to HI-Z[12, 13] –5ns
tBW Byte Enable to write end 7–ns
Notes
10. Test conditions assume a signal transition time (rise/fall) of 3 ns or less, timing reference levels of 1.5 V (for VCC > 3 V) and VCC/2 (for VCC < 3 V), and input pulse
levels of 0 to 3 V (for VCC > 3 V) and 0 to VCC (for VCC < 3 V). Test conditions for the read cycle use output loading shown in part (a) of Figure 3 on page 5, unless specified otherwise.
11. For all dual chip enable devices, CE is the logical combination of CE1 and CE2. When CE1 is LOW and CE2 is HIGH, CE is LOW; when CE1 is HIGH or CE2 is LOW,
CE is HIGH.
12. tHZOE, tHZCE, tHZWE, tHZBE, tLZOE, tLZCE, tLZWE, and tLZBE are specified with a load capacitance of 5 pF as in (b) of Figure 3 on page 5. Transition is measured 200 mV from steady
state voltage.
13. These parameters are guaranteed by design and are not tested.
14. The internal write time of the memory is defined by the overlap of WE = VIL, CE = VIL and BHE or BLE = VIL. These signals must be LOW to initiate a write, and the
HIGH transition of any of these signals can terminate the operation. The input data setup and hold timing should be referenced to the edge of the signal that terminates
the write.
15. The minimum write cycle pulse width for Write Cycle No. 2 (WE Controlled, OE LOW) should be equal to sum of tSD and tHZWE.
Document Number: 001-91255 Rev. *J Page 8 of 16
CY7C1041G Automotive
Switching Waveforms
Figure 5. Read Cycle No. 1 of CY7C1041G (Address Transition Controlled) [16, 17]
Figure 6. Read Cycle No. 2 (OE Controlled) [17]
ADDRESS
DATA I/O PREVIOUS DATAOUT
VALID DATAOUT VALID
tRC
tOHA
tAA
tRC
tHZCE
tPD
tACE
tDOE
tLZOE
tDBE
tLZBE
tLZCE
tPU
HIGH IMPEDANCE DATA OUT VALID HIGH
IMPEDANCE
ADDRESS
CE
OE
BHE/
BLE
V
CC
SUPPLY
CURRENT
tHZOE
tHZBE
ISB
DATA I /O
Notes
16. The device is continuously selected, OE = VIL, CE = VIL, BHE or BLE or both = VIL.
17. WE is HIGH for read cycle.
Document Number: 001-91255 Rev. *J Page 9 of 16
CY7C1041G Automotive
Figure 7. Write Cycle No. 1 (CE Controlled) [18, 19, 20]
Figure 8. Write Cycle No. 2 (WE Controlled, OE LOW) [18, 19, 20, 21]
Switching Waveforms (continued)
ADDRESS
CE
WE
BHE/
BLE
DATA I/O
OE
tWC
tSCE
tAW
tSA
tPWE
tHA
tBW
tHD
tHZOE tSD
DATAIN VALID
ADDRESS
CE
DATA I/O
tWC
tSCE
tHD
tSD
tBW
BHE
/
BLE
tAW tHA
tSA tPWE
tLZWE
tHZWE
WE
DATA
IN VALID
Notes
18. Address valid prior to or coincident with CE LOW transition.
19. The internal write time of the memory is defined by the overlap of WE = VIL, CE = VIL and BHE or BLE = VIL. These signals must be LOW to initiate a write, and the
HIGH transition of any of these signals can terminate the operation. The input data setup and hold timing should be referenced to the edge of the signal that terminates
the write.
20. Data I/O is in HI-Z state if CE = VIH, or OE = VIH or BHE, and/or BLE = VIH.
21. The minimum write cycle pulse width should be equal to sum of tSD and tHZWE.
Document Number: 001-91255 Rev. *J Page 10 of 16
CY7C1041G Automotive
Figure 9. Write Cycle No. 3 (BLE or BHE Controlled) [22, 23]
Figure 10. Write Cycle No. 4 (WE Controlled) [22, 23, 24]
Switching Waveforms (continued)
DATAIN VALID
ADDRESS
CE
WE
DATA I/O
tWC
tSCE
tAW
tSA
tBW
tHA
tHD
tHZWE tSD
BHE/
BLE
tPWE
tLZWE
ADDRESS
CE
DATA I/O
tWC
tSCE
tHD
tSD
tBW
BHE
/
BLE
tAW tHA
tSA tPWE
tLZWE
tHZWE
WE
DATA
IN VALID
Notes
22. The internal write time of the memory is defined by the overlap of WE = VIL, CE = VIL and BHE or BLE = VIL. These signals must be LOW to initiate a write, and the
HIGH transition of any of these signals can terminate the operation. The input data setup and hold timing should be referenced to the edge of the signal that terminates
the write.
23. Data I/O is in HI-Z state if CE = VIH, or OE = VIH or BHE, and/or BLE = VIH.
24. Data I/O is high impedance if OE = VIH.
25. During this period the I/Os are in output state. Do not apply input signals.
Document Number: 001-91255 Rev. *J Page 11 of 16
CY7C1041G Automotive
Truth Table
CE OE WE BLE BHE I/O0–I/O7I/O8–I/O15 Mode Power
H X X X X HI-Z HI-Z Power down Standby (ISB)
L L H L L Data out Data out Read all bits Active (ICC)
L L H L H Data out HI-Z Read lower bits only Active (ICC)
L L H H L HI-Z Data out Read upper bits only Active (ICC)
L X L L L Data in Data in Write all bits Active (ICC)
L X L L H Data in HI-Z Write lower bits only Active (ICC)
L X L H L HI-Z Data in Write upper bits only Active (ICC)
L H H X X HI-Z HI-Z Selected, outputs disabled Active (ICC)
Document Number: 001-91255 Rev. *J Page 12 of 16
CY7C1041G Automotive
Ordering Code Definitions
Ordering Information
Speed
(ns) Voltage Range Ordering Code Package
Diagram
Package Type
(all Pb-free)
Operating
Range
10 2.2 V–3.6 V CY7C1041G30-10BAJXE 001-85259 48-ball VFBGA Automotive-E
CY7C1041G30-10BAJXET 001-85259 48-ball VFBGA, Tape and Reel
CY7C1041G30-10ZSXE 51-85087 44-pin TSOP II
CY7C1041G30-10ZSXET 51-85087 44-pin TSOP II, Tape and Reel
CY7C1041G30-10ZSXA 51-85087 44-pin TSOP II Automotive-A
CY7C1041G30-10ZSXAT 51-85087 44-pin TSOP II, Tape and Reel
X = blank or T
blank = Bulk; T = Tape and Reel
Temperature Range: X = E or A
E = Automotive-E; A= Automotive-A
Pb-free
J = JEDEC Compliant
Package Type: XX = BA or ZS
BA = 48-ball VFBGA; ZS = 44-pin TSOP II
Speed: 10 ns
Voltage Range: 30 = 2.2 V–3.6 V
Process Technology: Revision Code “G” = 65 nm
Data Width: 1 = × 16-bits
Density: 04 = 4-Mbit
Family Code: 1 = Fast Asynchronous SRAM family
Technology Code: C = CMOS
Marketing Code: 7 = SRAM
Company ID: CY = Cypress
CCY 1 -10 X
704 G1 XX
30 JXX
Document Number: 001-91255 Rev. *J Page 13 of 16
CY7C1041G Automotive
Package Diagrams
Figure 11. 48-ball VFBGA (6 × 8 × 1.2 mm) BA48M/BK48M (0.35 mm Ball Diameter) Package Outline, 001-85259
Figure 12. 44-pin TSOP Z44-II Package Outline, 51-85087
001-85259 *A
001-85259 *A
51-85087 *E
Document Number: 001-91255 Rev. *J Page 14 of 16
CY7C1041G Automotive
Acronyms Document Conventions
Units of Measure
Table 1. Acronyms Used in this Document
Acronym Description
BHE Byte High Enable
BLE Byte Low Enable
CE Chip Enable
CMOS Complementary Metal Oxide Semiconductor
I/O Input/Output
OE Output Enable
SRAM Static Random Access Memory
TSOP Thin Small Outline Package
TTL Transistor-Transistor Logic
VFBGA Very Fine-Pitch Ball Grid Array
WE Write Enable
Table 2. Units of Measure
Symbol Unit of Measure
°C degree Celsius
MHz megahertz
Amicroampere
smicrosecond
mA milliampere
mm millimeter
ns nanosecond
ohm
%percent
pF picofarad
Vvolt
Wwatt
Document Number: 001-91255 Rev. *J Page 15 of 16
CY7C1041G Automotive
Document History Page
Document Title: CY7C1041G Automotive, 4-Mbit (256K words × 16-bit) Static RAM with Error-Correcting Code (ECC)
Document Number: 001-91255
Rev. ECN No. Orig. of
Change
Submission
Date Description of Change
*F 4996293 NILE 10/30/2015 Changed status from Preliminary to Final.
*G 5026902 NILE 11/25/2015 Added Automotive-A Temperature Range related information in all instances
across the document.
Updated Ordering Information:
Updated part numbers.
*H 5427560 NILE 09/07/2016 Updated Maximum Ratings:
Updated Note 5 (Replaced “2 ns” with “20 ns”).
Updated DC Electrical Characteristics:
Removed details of VOH parameter corresponding to Test Condition
“2.7 V to 3.6 V”.
Added details of VOH parameter corresponding to Test Conditions
“2.7 V to 3.0 V” and “3.0 V to 3.6 V”.
Updated Ordering Information:
Updated part numbers.
Updated to new template.
*I 5787756 NILE 06/27/2017 Updated to new template.
Completing Sunset Review.
*J 6249178 NILE 07/16/2018 Updated Features:
Added “AEC-Q100 qualified”.
Added Note 2 and referred the same note in “Embedded ECC for single-bit
error correction”.
Updated to new template.
Completing Sunset Review.
Document Number: 001-91255 Rev. *J Revised July 16, 2018 Page 16 of 16
CY7C1041G Automotive
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