256K Military X28C 256M 32K x 8 Bit Electrically Erasable PROM FEATURES LOW Power CMOS 60 mA Active Current Max. 200 wA Standby Current Max. Fast Write Cycle Times 64-Byte Page Write Operation Byte or Page Write Cycle: 5 ms Typical Complete Memory Rewrite: 2.5 Sec. Typical Effective Byte Write Cycle Time: 78 ps Typical Software Data Protection @ End of Write Detection DATA Polling Toggle Bit Simple Byte and Page Write Single TTL Compatible WE Signal Internally Latched Address and Data Automatic Write Timing e Upward Compatible with X2864A @ JEDEC Approved Byte-Wide Pinout DESCRIPTION The Xicor X28C256 is a 32K x 8 E2PROM, fabricated with Xicors proprietary, high performance, floating gate CMOS technology. Like all Xicor programmable non- volatile memories the X28C256 is a 5V only device. The X28C256 features the JEDEC approved pinout for byte-wide memories, compatible with industry standard RAMs. The X28C256 supports a 64-byte page write operation, effectively providing a 78 ys/byte write cycle and en- abling the entire memory to be typically written in less than 2.5 seconds. The X28C256 also features DATA Polling, a system software support scheme used to in- dicate the early completion of a write cycle. In addition, the X28C256 includes a user-optional software data protection mode that further enhances Xicors hard- ware write protect capability. Xicor E2PROMs are designed and tested for applica- tions requiring extended endurance. Data retention is specified to be greater than 10 years. PIN CONFIGURATIONS CERDIP FLAT PACK PGA Aut NA 2e[] Voc Ar Avz Ais NC Vcc WE Ars Van len en ven es Av C2 27 |] WE @'@ 0 @ ArO3 26[7 Ars o @ @ @ ey AcC]4 25[_} As Ak a he AsC]5 24] Ao 4 * exes, @ @ As(J6 23au X28C256 de Ay Ms OE Any ast]? 2 LOE (TOP VIEW) o 8 e cL] s %28C256 2 Dav @" @ @ @ e" Ailys 20 (7) CE te ty Ang Eng Ao L] 10 19 |] vor 0' @ @ Oo 1 18 [7] 0s i i 0065-21 0+] 12 17[-} Os WOs Oa Vss NC 1/03 1/04 HOs woz] 13 16[-] V0. ooes2 PIN NAMES Ves] 14 30) vos Ao-A14 Address Inputs 0065-1 1/O9-1/07 Data {nput/Output WE WE Write Enable CE Chip Enable OE Output Enable Vec +5V Vss Ground NC No Connect Xicor, 1988 Patents Pending Characteristics subject to change without noticeX28C256M ABSOLUTE MAXIMUM RATINGS* Terr perature Under Bias Storage Temperature Voltage on any Pin with 65C to + 135C 65C to + 150C *COMMENT Stresses above those listed under Absolute Maximum Rat- ings may cause permanent damage to the device. This is a stress rating only and the functional operation of the device at Raspect to Ground................-..0..008- 1.0V to +7V these or any other conditions above those indicated in the op- D.C. Output Current... 0... eee teenies 5SmA erational sections of this specification is not implied. Exposure Lead Temperature to absolute maximum rating conditions for extended periods (Soldering, 10 Seconds) ..........-..-...0.22 2c eee 300C may affect device reliability. D.C. OPERATING CHARACTERISTICS Ta = 55C to +125C, Voc = +5V 410%, unless otherwise specified. Symbol Parameter Limits Units Test Conditions Min. | Typ.) | Max. Ioc Vcc Current (Active) 60 mA | CE = OE = Vi, WE = Vin (TTL Inputs) All |/O's = Open Address Inputs = TTL Levels @ f = 5 MHz ISB, Voc Current (Standby) 2 mA | CE = Vin, OE = Vit (TTL Inputs) Alll/Os = Open Other Inputs = Vy ISBo Vec Current (Standby) 100 200 pA | CE = Voc 0.3V, OE = Vi, (CMOS Inputs) All |/Os = Open Other Inputs = Voc lu Input Leakage Current 10 pA | Vin = GND to Vcc Lo Output Leakage Current 10 wA | Vout = GND to Voc, GE = Vin Vj} (2) Input Low Voltage 1.0 0.8 Vv Vin) Input High Voltage 2.0 Veco +1.0| V Vor Output Low Voltage 0.4 Vo flot = 2.1mA Vou Output High Voltage 2.4 Vs} lon = 400 pA POWER-UP TIMING Symbol Parameter Max. Units tpur?) Power-Up to Read Operation 100 ys teyw/'3) Power-Up to Write Operation 5 ms CAPACITANCE Ta = 25C, f = 1.0 MHz, Vcc = 5V Symboi Test Max. Units Conditions Co) Input/Output Capacitance 10 pF Vio = OV Cin) Input Capacitance 6 pF Vin = OV A.C. CONDITIONS OF TEST MODE SELECTION input Pulse Levels| OV to 3.0V cE OE WE Mode 1/0 Power Input Rise and 10 L L H Read Dout Active Fall Times ns l L H L Write Din Active Input and Output 1.5V H x x Standbyand | HighZ | Standby Tining Levels Write Inhibit Output Load 1 TTL Gate and xX L Write Inhibit _ _ GC. = 100 pF ; _ xX x H Write Inhibit _ Notes: (1) Typical values are for Ta = 25C and nominal supply voltage. (2) Vi_ min. and Vj max. are for reference only and are not tested. (3) This parameter is periodically sampled and not 100% tested. 2 -168X28C256M A.C. CHARACTERISTICS Ta = 55C to + 125C, Voc = +5V +10%, unless otherwise specified. Reaci Cycle Limits Symbol Parameter X28C256M-20 | X28C256M-25 X28C256M X28C256M-35 Units Min. | Max. | Min. | Max. | Min. ; Max. | Min. | Max. trac Read Cycle Time 200 250 300 350 ns toe Chip Enable Access Time 200 250 300 350 ns tAa Address Access Time 200 250 300 350 ns toe Output Enable Access Time 80 100 100 100 ns tiz | CE Low to Active Output 0 0 0 0 ns to_z(4)_ | OE Low to Active Output 0 0 0 0) ns tyz) | CE High to High Z Output 0 50 0 50 0 50 0 50 ns touz(5) | OE High to High Z Output 0 50 0 50 0 50 0 50 ns tow Output Hold from 0 0 0 0 ns Address Change Read Cycle | tac > ADDRESS x Xx <tce_ > re Sr cE ~\ ) OE Zs / Vin WE gtiz ae | tonz r! torr j* t- tuz HIGH Z DATA 1/0 DATA VALID o065-4 Notes: (4) t_z min. and to_z min. are shown for reference only, they are periodically characterized and are not tested. (5) tyz max. and toyz max. are measured from the point when CE or GE return high (whichever occurs first) to the time when the outputs are no longer driven. tyz min. and toyz min. are shown for reference only, they are periodically characterized and are not tested. 2-169X28C256M Write Cycle Limits Symbol Parameter Min. Typ.(6) Max. Units two Write Cycle Time 5 10 ms tas Address Setup Time 0 ns taH Address Hold Time 150 ns log Write Setup Time 0 ns CH Write Hold Time Q ns tow CE Pulse Width 100 ns toes OE High Setup Time 10 ns toeH OE High Hold Time 10 ns twp WE Putse Width 100 ns tweH WE High Recovery 200 ns tov Data Valid 1 ps tos Data Setup 50 ns too Data Hold 10 ns tow Delay to Next Write 10 ps tBic Byte Load Cycle 1 100 BS WE Controlled Write Cycle ADDRESS DATA IN DATA VALID tos HIGH Z 0065-5 Note: (6) Typical values are for Ta = 25C and nominal supply voltage. 2-170X28C256M E Controlled Write Cycle ADDRESS DATA IN DATA VALID HIGH Z DATA OUT 0065-6 Page Write Cycle oe LT] UU a Sf (8) saponess XXX XX I a vo SRRERRRREX XXX sree) BYTEO BYTE BYTE2 ~~ BYTEn BYTE n#1 BYTEn#2 twe *For each successive write within the page write operation, Ag-A;4 should be the same or writes to an unknown address could occur. Notes: (7) Between successive byte writes within a page write operation, OE can be strobed LOW: e.g. this can_be done with CE and WE HIGH to fetch data from another memory device within the system for the next write; or with WE HIGH and CE LOW effectively performing a polling operation. (8) The timings shown above are unique to page write operations. Individual byte load operations within the page write must conform to either the CE or WE controlled write cycle timing. 2-171X28C256M DATA Polling Timing Diagram(9) ADORESS An OOK An XN OOK A OOO e _ mm \ OTN WE oN af N toe tors tow Ve) EE )_$Ca)$ Souk we 0065-9 Toggle Bit Timing Diagram cs TINIAN we L. +| toes + oe i \ / \ | \ j tow + 0g Yr ee twe 0065-8 * 1/Og beginning and ending state will vary, depending upon actual two. SYMBOL TABLE WAVEFORM INPUTS OUTPUTS Must be Will be steady steady May change WII change LD from Low to from Low to High High May change Will change ~ QQ. from High to from High to Low Low Don't Care: Changing: XXX Changes State Not Allowed Known Center Line yy KK N/A is High impedance Note: (9) Polling operations are by definition read cycles and are therefore subject to read cycle timings. 2-172X28C256M PIN DESCRIPTIONS Addresses (Ag-A14) The Address inputs select an 8-bit memory location during a read or write operation. Chip Enable (CE) The Chip Enable input must be LOW to enable all read/write operations. When CE is HIGH, power con- sumption is reduced. Output Enable (OE) The Output Enable input controls the data output buff- ers and is used to initiate read operations. Data In/Data Out (I/O9-1/07) Data is written to or read from the X28C256 through the I/O pins. Write Enable (WE) The Write Enable input controls the writing of data to the X28C256. DEVICE OPERATION Reaci Read operations are initiated by both OE and CE LOW. The read operation is terminated by either CE or OE returning HIGH. This 2-line control architecture elimi- nates bus contention in a system environment. The data bus will be in a high impedance state when either OE or CE is HIGH. Write Write operations are initiated when both CE and WE are LOW and OE is HIGH. The X28C256 supports both a CE and WE controlled write cycle. That is, the ad- dress is latched by the falling edge of either CE or WE, whichever occurs last. Similarly, the data is latched in- ternally by the rising edge of either CE or WE, whichev- er occurs first. A byte write operation, once initiated, will automatically continue to completion, typically with- in 5 ms. Page Write Operation The page write feature of the X28C256 allows the en- tire memory to be written in 2.56 seconds. Page write allows two to sixty-four bytes of data to be consecu- tively written to the X28C256 prior to the commence- ment of the internal programming cycle. The host can fetch data from another location within the system dur- ing a page write operation (change the source ad- dress), but the page address (Ag through A;4) for each subsequent valid write cycle to the part during this op- eration must be the same as the initial page address. The page write mode can be initiated during any write operation. Following the initial byte write cycle, the host can write an additional one to sixty-three bytes in the same manner as the first byte was written. Each suc- cessive byte load cycle, started by the WE HIGH to LOW transition, must begin within 100 ps of the falling edge of the preceding WE. If a subsequent WE HIGH to LOW transition is not detected within 100 us, the internal automatic programming cycle will commence. There is no page write window limitation. Effectively the page write window is infinitely wide, so long as the host continues to access the device within the byte load cy- cle time of 100 ps. Write Operation Status Bits The X28C256 provides the user two write operation status bits. These can be used to optimize a system write cycle time. The status bits are mapped onto the I/O bus as shown in Figure 1. Figure 1: Status Bit Assignment vo [pp|ts}s[4][3f[2]1]o RESERVED __--_- TOGGLE BIT BATA POLLING 0065-10 DATA Polling (1/07) The X28C256 features DATA Polling as a method to indicate to the host system that the byte write or page write cycle has completed. DATA Polling aliows a sim- ple bit test operation to determine the status of the X28C256, eliminating additional interrupt inputs or ex- ternal hardware. During the internal programming cycle, any attempt to read the last byte written will produce the complement of that data on 1/07 (i.e., write data = Ox xxxx, read data = 1xxx xx). Once the program- ming cycle is complete, 1/07 will reflect true data. Note: If the X28C256 is in the protected state and an illegal write operation is attempted DATA Polling will not operate. Toggle Bit (1/Og) The X28C256 also provides another method for deter- mining when the internal write cycle is complete. Dur- ing the internal programming cycle |/Og will toggie from one to zero and zero to one on subsequent attempts to read the device. When the interna! cycle is complete the toggling will cease and the device will be accessi- ble for additional read or write operations. 2-173X28C256M DATA POLLING I/07 Figure 2a: DATA Polling Bus Sequence LAST we / Vw eS VI VIVA SIPS FV VWI PV STAAL ST fb vo, HIGH Z f | vom OS PLO thr SS X26C256 rc [READY Bom-Ai4 An xX An x An x An xX An An xX An af 0065-11 Figure 2b: DATA Polling Software Flow WAITE DATA WRITES COMPLETE? SAVE LAST DATA AND ADDRESS NO READ LAST ADORESS vo, COMPARE? YES X20C256 READY 0065-12 DATA Polling can effectively halve the time for writing to the X28C256. The timing diagram in Figure 2a illus- trates the sequence of events on the bus. The software flow diagram in Figure 2b illustrates one method of im- plementing the routine. 2-174X28C256M THE TOGGLE BIT 1/0, Figure 3a: Toggie Bit Bus Sequence we vo i \ HIGH 2 [0 . Vf J J x2ec288 > READY 0065-13 *Beginning and ending state of I/Og will vary. Figure 3b: Toggle Bit Software Flow The Toggle Bit can eliminate the software housekeep- ing chore of saving and fetching the last address and data written to a device in order to implement DATA Polling. This can be especially helpful in an array com- LAST WRITE prised of multiple X28C256 memories that is frequently updated. The timing diagram in Figure 3a illustrates the , sequence of events on the bus. The software flow dia- gram in Figure 3b illustrates a method for testing the LOAD ACCUM : From ADDR S Toggle Bit. COMPARE ACCUM WITH ADOR n ad COMPARE OK YES READY 0065-14 2-175X28C256M HARDWARE DATA PROTECTION The X28G256 provides three hardware features (com- patible with X2864A) that protect nonvolatile data from inadvertent writes. Noise ProtectionA WE pulse less than 20 ns will not initiate a write cycle. Default Voc SenseAll write functions are inhibited when Vcc is <9V. Write InhibitHolding either OE LOW, WE HIGH, or CE HIGH will prevent an inadvertent write cycle during power-on and power-off, maintaining data integrity. SOFTWARE DATA PROTECTION The 28C256 offers a software controlled data protec- tion feature. The X28C256 is shipped from Xicor with the software data protection NOT ENABLED; that is, the cevice will be in the standard operating mode. In this rnode data should be protected during power-up/- dowri operations through the use of external circuits. The host would then have open read and write access of tha device once Vcc was stable. The X28C256 can be automatically protected during power-up and power-down without the need for exter- nal circuits by employing the software data protection feature. The internal software data protection circuit is enabled after the first write operation utilizing the soft- ware algorithm. This circuit is nonvolatile and will re- main set for the life of the device unless the reset com- mand is issued. Once the software protection is enabled, the X28C256 is also protected from inadvertent and accidental writes in the powered-on state. That is, the software algorithm must be issued prior to writing additional data to the device. SOFTWARE ALGORITHM Selecting the software data protection mode requires the host system to precede data write operations by a series of three write operations to three specific ad- dresses. Refer to Figure 4a and 4b for the sequence. The three byte sequence opens the page write window enabling the host to write from one to sixty-four bytes of data.(19) Once the page load cycle has been com- pleted, the device will automatically be returned to the data protected state. Note: (10) Once the three byte sequence is issued it must be followed by a valid byte or page write operation. 2-176X28C256M SOFTWARE DATA PROTECTION Figure 4a: Timing SequenceByte or Page Write [ f (Vee) Vee _ / J OV DATA AA 55 AO ADDRESS 5555 2AAA 5555 |e wrITe wane we PROTECTED a, BYTE oR PAGE 0065-15 eigure oo wie, Sequence for Regardless of whether the device has previously been Software Data Protection protected or not, once the software data protected al- gorithm is used and data has been written, the WRITE DATA AA X28C256 will automatically disable further writes unless To another command is issued to cancel it. If no further ADDRESS 5555 commands are issued the X28C256 will be write pro- tected during power-down and after any subsequent q power-up. WRITE DATA 55 Note: Once initiated, the sequence of write opera- To ADDRESS 2AAA tlons should not be interrupted. y WRITE DATA AO ADDRESS 5555 BYTE/PAGE LOAD 1 ENABLED WRITE DATA XX TO ANY ADDRESS ' ' ' vy WRITE LAST BYTE TO LAST ADDRESS AFTER two RE-ENTERS DATA PROTECTED STATE 0065-16 2-177X28C256M RESETTING SOFTWARE DATA PROTECTION Figure 5a: Reset Software Data Protection Timing Sequence + [ ff Veo JJ iJ DATA AA 58 80 AA 55 20 ADDRESS 5555 2AAA 5555 5555 2AAA 5555 2 twe ~~ SpenaniiG J ff MODE cE A PWNMANS 0065-17 Figure Sb: Software Sequence to Deactivate In the event the user wants to deactivate the software Software Data Protection data protection feature for testing or reprogramming in an E2PROM programmer, the following six step algo- WRITE DATA AA rithm will reset the internal protection circuit. After two, TO the X28C256 will be in standard operating mode. ADDRESS 5555 Note: Once initiated, the sequence of write opera- tions should not be interrupted. WRITE DATA 55 TO ADDRESS 2AAA i WRITE DATA 80 TO ADDRESS 5555 WRITE DATA AA To ADDRESS 5555 , WRITE DATA 55 To ADDRESS 2AAA WRITE DATA 20 TO ADDRESS 5555 0065-18 2-178X28C256M SYSTEM CONSIDERATIONS Because the X28C256 is frequently used in large mem- ory arrays it is provided with a two line control architec- ture for both read and write operations. Proper usage can provide the lowest possible power dissipation and eliminate the possibility of contention where multiple |1/O pins share the same bus. To gain the most benefit it is recommended that CE be decoded from the address bus and be used as the pri- mary device selection input. Both OE and WE would then be common among all devices in the array. For a read operation this assures that all deselected devices are in their standby mode and that only the selected device(s) is outputting data on the bus. Because the X28C256 has two power modes, standby and active, proper decoupling of the memory array is of prime concern. Enabling CE will cause transient current spikes. The magnitude of these spikes is dependent on the output capacitive loading of the I/Os. Therefore, the larger the array sharing a common bus, the larger the transient spikes. The voltage peaks associated with the current transients can be suppressed by the proper selection and placement of decoupling capacitors. As a minimum, it is recommended that a 0.1 uF high fre- quency ceramic capacitor be used between Voc and GND at each device. Depending on the size of the ar- ray, the value of the capacitor may have to be larger. In addition, it is recommended that a 4.7 2F electrolytic bulk capacitor be placed between Vcc and GND for each eight devices employed in the array. This bulk ca- pacitor is employed to overcome the voltage droop caused by the inductive effects of the PC board traces. FUNCTIONAL DIAGRAM - x ] BUFFERS 256K-BIT 7] carcues F E2PROM J ANO ARRAY Ac-Arg | { DECODER ADDRESS } INPUTS 1 I Y a erence 0 BUFFERS J "ano AND LATCHES { DECODER aE | CONTROL =e Logic _ = AND 09-107 WET timinG | DATA INPUTS/OUTPUTS Voc O Vss o. 0065-3 2-179X28C256M Normalized Active Supply Current vs. Ambient Temperature Normalized Standby Supply Current vs. Ambient Temperature NORMALIZED lec 1.4 Voc = 5-0V 0.8 0.6 55 #25 #125 AMBIENT TEMPERATURE (C) 0065-19 NORMALIZED Isp, 1.4 .>--__ \ Veg = 5.0V 1.2 1.0 0.8 0.6 =55 +25 #125 AMBIENT TEMPERATURE (C) 0065-20 2-180X28C256M ORDERING INFORMATION 256K E2PROMSs iis O0UVH AZ qo ed n = mn np oO max Hoel ll Device J Order forganizaton rere eee ceeecty| | Peceesie X28C256DM-20 | 32768x8 M |200ns| CMOS Standard X28C256DM-25 | 32768x8 M | 250ns| CMOS Standard X28C0256DM 32768 x 8 M | 300ns CMOS Standard X28C256DM-35 32768 x 8 M_ | 350 ns CMOS Standard X28C256DMB-20| 32768 x8 M | 200ns CMOS _ |883 Rev. C, Class B X28C256DMB-25| 32768x8 M |250ns} CMOS _ [883 Rev. C, Class B X28C256DMB 32768 x B M |300ns| CMOS {883 Rev. C, Ciass B X28C256DMB-35| 32768 x 8 M_ | 350 ns CMOS _ [883 Rev. C, Class B X28(0256FM-20 32768 x 8 M_ | 200ns CMOS Standard X28C0256FM-25 32768 x 8 M_ | 250 ns CMOS Standard X28C256FM 32768 x 8 M |300ns CMOS Standard X28C256FM-35 32768 x 8 M |350ns CMOS Standard X28C256FMB-20; 32768x8 M |200ns; CMOS {883 Rev. C, Class B X28C256FMB-25| 32768 x8 M |250ns| CMOS /|883 Rev. C, Class B X28C256FMB 32768 x 8 M |300ns| CMOS |883 Rev. C, Class B X28C256FMB-35| 32768x8 M | 350ns CMOS _ /883 Rev. C, Class BI Ke Blank = Commercial = 0C to + 70C Industrial = 40C to + 85C Military = 55C to + 125C Ultra High Temp. = 0C to + 150C Plastic Small Outline Gull Wing Plastic DIP 28-Lead Cerdip Side Braze Ceramic Flat Pack for X2864A, X2864B and X2864H 28-Lead Ceramic Flat Pack for X28256 and X28C256 28-Pin Geramic Pin Grid Array J-Hook Plastic Leaded Chip Carrier 32-Pad Ceramic Leadless Chip Carrier (Solder Seal) 32-Pad Ceramic Leadiess Chip Carrier (Glass Frit Seal}X28C256M ORDERING INFORMATION 256K E2PROMs (Continued) ruduss QO0UVH AZ Hout tod a = mn nn Oo max iol ll Device Order [organization Fem Accel Process | Presse X28C:256KM-20 32768 x 8 M_ | 200ns CMOS Standard X28C:256KM-25 32768 x 8 M | 250 ns CMOS Standard X28C-256KM 32768 x 8 M | 300ns CMOS Standard X28C256KM-35 32768 x 8 M | 350ns CMOS Standard X28C256KMB-20] 32768 x8 M |200ns| CMOS _ /883 Rev. C, Class B X28C256KMB-25] 32768x8 M |250ns| CMOS /883 Rev. C, Class Bi X28C256KMB 32768 x8 M |300ns CMOS __ |883 Rev. C, Class B X28C256KMB-35| 32768 x 8 M |350ns CMOS __ /883 Rev. C, Class B X28C256EM-20 | 32768x8 M |200ns}| CMOS Standard X28C256EM-25 | 32768x8 M |250ns| CMOS Standard X28C256EM 32768 x 8 M |300ns| CMOS Standard X28C256EM-35 | 32768x8 M |350ns| CMOS Standard X28C256EMB-20] 32768x8 M |200ns| CMOS [883 Rev. C, Class B X28C256EMB-25| 32768 x8 M |250ns} CMOS |883 Rev. C, Class B X28C256EMB 32768 x 8 M |300ns| CMOS {883 Rev.C, Class B X28(5256EMB-35| 32768 x 8 M | 350 ns CMOS __ |883 Rev. C, Class B Ke Blank = Commercial = 0C to + 70C Industrial = 40C to + 85C Military = 55C to + 125C Ultra High Temp. = O0C to + 150C Plastic Smail Outline Gull Wing Plastic DIP 28-Lead Cerdip Side Braze Ceramic Flat Pack for X2864A, X2864B and X2864H 28-Lead Ceramic Flat Pack for X28256 and X28C256 28-Pin Ceramic Pin Grid Array J-Hook Plastic Leaded Chip Carrier 32-Pad Ceramic Leadless Chip Carrier (Solder Seal) 32-Pad Ceramic Leadless Chip Carrier (Glass Frit Seal)X28C256M ORDERING INFORMATION 256K E2PROMs (Continued) Device Order Organization Package Temp.|Access| Process Processing Number Range| Time |Technology Level $|P|D/C/F1IJF2;) kK) J/E/G X28C256GM-20 32768 x 8 M 200 ns CMOS Standard X28C256GM-25 32768 x8 e M 250 ns CMOS Standard X28C256GM 32768 x8 e M 300 ns CMOS Standard X28C256GM-35 32768 x 8 e M 350 ns CMOS Standard X28C256GMB-20| 32768 x8 M 200 ns CMOS 883 Rev. C, Class B X28C256GMB-25| 32768 x8 e M 250 ns CMOS 883 Rev. C, Class B X28C256GMB 32768 x 8 e M 300 ns CMOS 883 Rev. C, Class B X28C256GMB-35| 32768 x8 M 350 ns CMOS 883 Rev. C, Class B Key: Tt = Blank = Commercial = 0C to + 70C { = Industrial = 40C to + 85C M = Military = 55C to + 125C T = Ultra High Temp. = OC to + 150C S = Plastic Smail Outline Gull Wing P = Plastic DIP D = 28-Lead Cerdip C = Side Braze F1 = Ceramic Flat Pack for X2864A, X2864B and X2864H F2 = 28-Lead Ceramic Flat Pack for X28256 and X28C256 K = 28-Pin Ceramic Pin Grid Array J = J-Hook Plastic Leaded Chip Carrier E = 32-Pad Ceramic Leadiess Chip Carrier (Solder Seal) G = 32-Pad Ceramic Leadless Chip Carrier (Glass Frit Seal) LIMITED WARRANTY Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, inc. reserves the right to discontinue production and change specifications and prices at any time and without notice. Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, licenses are imptiec. U.S. PATENTS Xicor products are covered by one or more of the following U.S. Patents: 4,263,664; 4,274,012; 4,300,212; 4,314,265; 4,326,134; 4,393,481; 4,404,475; 4,450,102; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932. Foreign patents and additional patents pending. LIFE RELATED POLICY In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection and correction, redundancy and back-up features to prevent such an occurrence. Xicor's products are not authorized for use as critical components in life support devices or systems. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when property used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injuy to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 2-183X28C256M PACKAGING INFORMATION 28-LEAD HERMETIC DUAL IN-LINE PACKAGE TYPE D 1.490 (37.85) 1.435 (36.45) oor oonnoYm 0.610(15.49) 0.500 (12.70) l __ l pn 1 ot CCT oe 7 0.100 (2.54) 1.300 (33.02) foe REF. 0.035 (0.89) r SEATING PLANE _. l 4 0.225 (5.72) __ ? | Sra ee) 140 (3.56) 0.200 (5.08) 0.125 (3.18) 0.060 (1.52) 0.015 (0.38) __ 0.070 (1.78) 0.050(0.76) _ |. 0.026 (0.66) 0.110(2.79 ; 0.110(2-79) fj TYP. 0.055 (1.40) 0.014 (0.36) 0.090 (2.29) TYP. 0.018 (0.46) TYP. 0.018 (0.46) 0.620 (15.75) 0.590 (14.99) TYP. 0.614 (15.60) j _| T TYP. 0.010 (0.25) NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) HO1028 2-184X28C 256M PACKAGING INFORMATION 28-LEAD CERAMIC FLAT PACK TYPE F2 1.000 0.010 PIN 1 INDEX 0.019 (0.48) 0.015 (0.38) my 0.740 (18.80) MAX, LT 0.050 (1.27) BSC ~F poe (1.14) MAX. 0.440 (11.18) MAX. 0.006 (0.15) [0.003 (0.08) 0.130 (3.30) 4 po at 0.090 (2.29) 0.370 (9.40) __| os (6.35) L 0.180 (4.57) 0.040 (1.02) | TYP. 0.300 2 PLCS. MIN. 0.026 (0.66) CFF028 NOTES: 1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 2. CASE OUTLINE FOR X28256 AND X28C256 2-185X28C256M PACKAGING INFORMATION 28-PIN CERAMIC PIN GRID ARRAY PACKAGE TYPE K @ @ @ G) @) @) CROROROROMC() -@ @ -O 0.650 0.010 (16.51 0.25) | 0.005 --| TYP. - | 0.075 Lf 0.100 40.005 ALL LEADS 4 CORNERS ; 1 INDEX Te |_____o.ss00.01 0 i (14.00 20.25) @15 : rool 4 [+ 0.008 | (== 0.050 F ----*A MOTE: LEADS 4,12, 18 & 26 0.090 0.010 (2.340.25) 0.067 0.005 0.018 40.002 Ss TTT L---+A l 0.180% 0.005 (4.570.13) CKCo028 NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 2-186X28C256M PACKAGING INFORMATION 32-PAD CERAMIC LEADLESS CHIP CARRIER PACKAGE TYPE E 0.020 (0.51) x 45 REF. __ 9.020(0.51) | | 0.107 (2.72) 0.077 (1.96) 0.015 (0.38) J B19 (0.98) 0.003 (0.08) 0.055 (1.39) 0.045 (1.14) TYP. (4) PLCS. R TYP. | LL t 0.040 (1.02) x 45 REF. > 0.050 (1.27) BSC (3) PLCS. 0.028 (0.71) (32) PLCs 0.022 (0.56) 0.458 (11.63) 0.088 (2.24) I 0.442 (11.22) 0.050 (1.27) 0.458 (11.63) 0.120(3.05) 1+-0.300 (7.62)->} 0.060 (1.52) | 0.400 (10.16) 0.560 (14.22) 0.540 (13.71) 0.558 (14.17) {| tot 32 1 PIN 1 INDEX CORNER CEGOS2 NOTES: 1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 2. TOLERANCE: + 1% NLT + 0.005 (0.127) 2-187X28C256M PACKAGING INFORMATION 32-PAD CERAMIC LEADLESS CHIP CARRIER (GLASS FRIT SEAL) PACKAGE TYPE G f 0.020 (0.51) x 45REF. | 0.107 (2.72) 0.077 (1.96) 0.015 (0.38) 1 0.003(0.08) TYP- 0.055 (1.39) 0.048 G 14) \ 0.015 (0.38) TYP. (4) PLCS. oy FE 1040 (1.02) x 45 REF. | lho. 050(1.27)Bsc 74 Csres. F 0.028(0-71) (5) pi og 0.022 (0.56) . 0.458 (11.63) 0.088 (2.24) 0.442(11.22) 0.050 (1.27) 0.458 (11.63) 0.120(3.05) 0,300 (7.62) 0. |] 008004 52) I] 0.400 (10.16) 0.560 (14.22) 0.540(13.71) 0.558 (14.17) 32 1 PIN 1 INDEX CORNER ~ CGGo32 NOTES: 1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 2. TOLERANCE: + 1% NLT + 0.005 (0.127) 3. FOR EXTENDED STORAGE TEMPERATURE ENVIRONMENTS 2-188