Synchronous Current-Mode with Constant On-Time, PWM Buck Controller ADP1872/ADP1873 Data Sheet FEATURES TYPICAL APPLICATIONS CIRCUIT VIN = 2.75V TO 20V ADP1872/ ADP1873 BST COMP/EN VOUT CIN CBST RTOP FB DRVH RBOT CVDD2 VDD = 2.75V TO 5.5V GND SW VDD DRVL PGND Q1 L VOUT COUT Q2 RRES + LOAD 5A CVDD Figure 1. 100 VDD = 5.5V, VIN = 5.5V (PSM) VDD = 5.5V, VIN = 5.5V 95 90 85 VDD = 5.5V, VIN = 13.0V (PSM) 80 75 70 VDD = 5.5V, VIN = 16.5V (PSM) 65 TA = 25C VOUT = 1.8V fSW = 300kHz 60 55 WURTH INDUCTOR: 744325120, L = 1.2H, DCR = 1.8m INFINEON FETs: BSC042N03MS G (UPPER/LOWER) 50 45 100 1k 10k 100k LOAD CURRENT (mA) 08297-002 Telecom and networking systems Mid to high end servers Set-top boxes DSP core power supplies CC2 RC EFFICIENCY (%) APPLICATIONS VIN CC 08297-001 Power input voltage as low as 2.75 V to 20 V Bias supply voltage range: 2.75 V to 5.5 V Minimum output voltage: 0.6 V 0.6 V reference voltage with 1.0% accuracy Supports all N-channel MOSFET power stages Available in 300 kHz, 600 KHz, and 1.0 MHz options No current-sense resistor required Power saving mode (PSM) for light loads (ADP1873 only) Resistor-programmable current-sense gain Thermal overload protection Short-circuit protection Precision enable input Integrated bootstrap diode for high-side drive 140 A shutdown supply current Starts into a precharged load Small, 10-lead MSOP package Figure 2. ADP1872 Efficiency vs. Load Current (VOUT = 1.8 V, 300 kHz) GENERAL DESCRIPTION The ADP1872/ADP1873 are versatile current-mode, synchronous step-down controllers that provide superior transient response, optimal stability, and current limit protection by using a constant on-time, pseudo-fixed frequency with a programmable currentsense gain, current-control scheme. In addition, these devices offer optimum performance at low duty cycles by using valley currentmode control architecture. This allows the ADP1872/ADP1873 to drive all N-channel power stages to regulate output voltages as low as 0.6 V. The ADP1873 is the power saving mode (PSM) version of the device and is capable of pulse skipping to maintain output regulation while achieving improved system efficiency at light loads (see the Power Saving Mode (PSM) Version (ADP1873) section for more information). Available in three frequency options (300 kHz, 600 kHz, and 1.0 MHz, plus the PSM option), the ADP1872/ADP1873 are well suited for a wide range of applications. These ICs not only operate from a 2.75 V to 5.5 V bias supply, but can also accept a power input as high as 20 V. In addition, an internally fixed, soft start period is included to limit input in-rush current from the input supply during startup and to provide reverse current protection during soft start for a precharged output. The low-side current-sense, current-gain scheme and integration of a boost diode, along with the PSM/forced pulsewidth modulation (PWM) option, reduce the external part count and improve efficiency. The ADP1872/ADP1873 operate over the -40C to +125C junction temperature range and are available in a 10-lead MSOP. Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2009-2012 Analog Devices, Inc. All rights reserved. ADP1872/ADP1873 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Timer Operation ........................................................................ 21 Applications ....................................................................................... 1 Pseudo-Fixed Frequency ........................................................... 22 Typical Applications Circuit............................................................ 1 Applications Information .............................................................. 23 General Description ......................................................................... 1 Feedback Resistor Divider ........................................................ 23 Revision History ............................................................................... 2 Inductor Selection ...................................................................... 23 Specifications..................................................................................... 3 Output Ripple Voltage (VRR) .................................................. 23 Absolute Maximum Ratings............................................................ 5 Output Capacitor Selection....................................................... 23 Thermal Resistance ...................................................................... 5 Compensation Network ............................................................ 24 Boundary Condition .................................................................... 5 Efficiency Consideration ........................................................... 25 ESD Caution .................................................................................. 5 Input Capacitor Selection .......................................................... 26 Pin Configuration and Function Descriptions ............................. 6 Thermal Considerations............................................................ 27 Typical Performance Characteristics ............................................. 7 Design Example .......................................................................... 27 ADP1872/ADP1873 Block Digram.............................................. 17 External Component Recommendations .................................... 30 Theory of Operation ...................................................................... 18 Layout Considerations ................................................................... 32 Startup .......................................................................................... 18 IC Section (Left Side of Evaluation Board) ............................. 37 Soft Start ...................................................................................... 18 Power Section ............................................................................. 37 Precision Enable Circuitry ........................................................ 18 Differential Sensing .................................................................... 37 Undervoltage Lockout ............................................................... 18 Typical Application Circuits ......................................................... 38 Thermal Shutdown..................................................................... 18 Dual-Input, 300 kHz High Current Application Circuit ...... 38 Programming Resistor (RES) Detect Circuit .......................... 19 Single-Input, 600 kHz Application Circuit ............................. 38 Valley Current-Limit Setting .................................................... 19 Dual-Input, 300 kHz High Current Application Circuit ...... 39 Hiccup Mode During Short Circuit ......................................... 20 Outline Dimensions ....................................................................... 40 Synchronous Rectifier ................................................................ 21 Ordering Guide .......................................................................... 40 Power Saving Mode (PSM) Version (ADP1873) .................... 21 REVISION HISTORY 7/12--Rev. A to Rev. B Changed RON = 15 m/100 k Valley Current Level Value from 7.5 to 3.87; Table 6 .......................................................................... 20 Changes to Ordering Guide .......................................................... 40 3/10--Rev. 0 to Rev. A Changes to Figure 1 .......................................................................... 1 Changes to Table 1 ............................................................................ 3 Changes to Table 2 ............................................................................ 5 Changes to Figure 59 Caption and Figure 60 Caption .............. 16 Changes to Figure 64 ...................................................................... 17 Changes to Timer Operation Section .......................................... 22 Changes to Table 7 .......................................................................... 23 Changes to Inductor Section ......................................................... 28 Changes to Table 9.......................................................................... 31 Changes to Figure 82...................................................................... 32 Changes to Figure 83...................................................................... 33 Changes to Figure 84...................................................................... 34 Changes to Figure 85...................................................................... 35 Changes to Figure 86...................................................................... 36 Changes to Differential Sensing Section and Figure 88 ............ 37 Changes to Figure 89 and Figure 90............................................. 38 Changes to Figure 91...................................................................... 39 Updated Outline Dimensions ....................................................... 40 10/09--Revision 0: Initial Version Rev. B | Page 2 of 40 Data Sheet ADP1872/ADP1873 SPECIFICATIONS All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC). VDD = 5 V, BST - SW = 5 V, VIN = 13 V. The specifications are valid for TJ = -40C to +125C, unless otherwise specified. Table 1. Parameter POWER SUPPLY CHARACTERISTICS High Input Voltage Range Low Input Voltage Range Quiescent Current Shutdown Current Undervoltage Lockout UVLO Hysteresis SOFT START Soft Start Period ERROR AMPLIFER FB Regulation Voltage Transconductance FB Input Leakage Current CURRENT-SENSE AMPLIFIER GAIN Programming Resistor (RES) Value from DRVL to PGND SWITCHING FREQUENCY ADP1872ARMZ-0.3/ ADP1873ARMZ-0.3 (300 kHz) On-Time Minimum On-Time Minimum Off-Time ADP1872ARMZ-0.6/ ADP1873ARMZ-0.6 (600 kHz) On-Time Minimum On-Time Minimum Off-Time ADP1872ARMZ-1.0/ ADP1873ARMZ-1.0 (1.0 MHz) On-Time Minimum On-Time Minimum Off-Time Symbol Conditions Min Typ Max Unit VIN ADP1872ARMZ-0.3/ADP1873ARMZ-0.3 (300 kHz) ADP1872ARMZ-0.6/ADP1873ARMZ-0.6 (600 kHz) ADP1872ARMZ-1.0/ADP1873ARMZ-1.0 (1.0 MHz) CIN = 1 F to PGND, CIN = 0.22 F to GND ADP1872ARMZ-0.3/ADP1873ARMZ-0.3 (300 kHz) ADP1872ARMZ-0.6/ADP1873ARMZ-0.6 (600 kHz) ADP1872ARMZ-1.0/ADP1873ARMZ-1.0 (1.0 MHz) FB = 1.5 V, no switching COMP/EN < 285 mV Rising VDD (See Figure 34 for temperature variation) Falling VDD from operational state 2.75 2.75 3.0 12 12 12 20 20 20 V V V 2.75 2.75 3.0 5 5 5 1.1 140 2.65 190 5.5 5.5 5.5 V V V mA A V mV VDD IQ_DD + IQ_BST IDD, SD + IBST, SD UVLO See Figure 57 VFB GM IFB, LEAK TJ = 25C TJ = -40C to +85C TJ = -40C to +125C 215 3.0 ms 595.5 594.2 300 600 600 600 515 1 605.4 606.5 730 50 mV mV mV s nA RES = 47 k 1% 2.7 3 3.3 V/V RES = 22 k 1% RES = none RES = 100 k 1% Typical values measured at 50% time points with 0 nF at DRVH and DRVL; maximum values are guaranteed by bench evaluation 1 5.5 11 22 6 12 24 6.5 13 26 V/V V/V V/V FB = 0.6 V, COMP/EN = released 300 kHz VIN = 5 V, VOUT = 2 V, TJ = 25C VIN = 20 V 84% duty cycle (maximum) 1120 1200 145 320 600 1280 190 385 ns ns ns kHz VIN = 5 V, VOUT = 2 V, TJ = 25C VIN = 20 V, VOUT = 0.8 V 65% duty cycle (maximum) 500 520 82 320 1.0 580 110 385 ns ns ns MHz VIN = 5 V, VOUT = 2 V, TJ = 25C VIN = 20 V 45% duty cycle (maximum) 285 312 60 320 340 85 385 ns ns ns Rev. B | Page 3 of 40 ADP1872/ADP1873 Data Sheet Parameter OUTPUT DRIVER CHARACTERISTICS High-Side Driver Output Source Resistance Output Sink Resistance Rise Time 2 Fall Time2 Low-Side Driver Output Source Resistance Output Sink Resistance Rise Time2 Fall Time2 Propagation Delays DRVL Fall to DRVH Rise2 DRVH Fall to DRVL Rise2 SW Leakage Current Integrated Rectifier Channel Impedance PRECISION ENABLE THRESHOLD Logic High Level Enable Hysteresis COMP VOLTAGE COMP Clamp Low Voltage Symbol Conditions COMP Clamp High Voltage COMP Zero Current Threshold THERMAL SHUTDOWN Thermal Shutdown Threshold Thermal Shutdown Hysteresis Hiccup Current Limit Timing VCOMP (HIGH) VCOMP_ZCT TTMSD 1 2 Typ Max Unit 2 0.8 25 11 3.5 2 tr, DRVH tf, DRVH ISOURCE = 1.5 A, 100 ns, positive pulse (0 V to 5 V) ISINK = 1.5 A, 100 ns, negative pulse (5 V to 0 V) BST - SW = 4.4 V, CIN = 4.3 nF (see Figure 59) BST - SW = 4.4 V, CIN = 4.3 nF (see Figure 60) ns ns 1.7 0.75 18 16 3 2 tr, DRVL tf, DRVL ISOURCE = 1.5 A, 100 ns, positive pulse (0 V to 5 V) ISINK = 1.5 A, 100 ns, negative pulse (5 V to 0 V) VDD = 5.0 V, CIN = 4.3 nF (see Figure 60) VDD = 5.0 V, CIN = 4.3 nF (see Figure 59) ns ns ttpdh, DRVH ttpdh, DRVL ISW, LEAK BST - SW = 4.4 V (see Figure 59) BST - SW = 4.4 V (see Figure 60) BST = 25 V, SW = 20 V, VDD = 5.5 V 22 24 ISINK = 10 mA 22 VCOMP (LOW) Min 110 VIN = 2.9 V to 20 V, VDD = 2.75 V to 5.5 V VIN = 2.9 V to 20 V, VDD = 2.75 V to 5.5 V 235 From disable state, release COMP/EN pin to enable device (2.75 V VDD 5.5 V) (2.75 V VDD 5.5 V) (2.75 V VDD 5.5 V) 0.47 Rising temperature 285 35 330 mV mV V 1.15 2.55 V V 155 15 6 C C ms The maximum specified values are with the closed loop measured at 10% to 90% time points (see Figure 59 and Figure 60), CGATE = 4.3 nF and upper- and lower-side MOSFETs being Infineon BSC042N03MS G. Not automatic test equipment (ATE) tested. Rev. B | Page 4 of 40 ns ns A Data Sheet ADP1872/ADP1873 ABSOLUTE MAXIMUM RATINGS Absolute maximum ratings apply individually only, not in combination. Unless otherwise specified, all other voltages are referenced to PGND. Table 2. Parameter VDD to GND VIN to PGND FB, COMP/EN to GND DRVL to PGND SW to PGND SW to PGND BST to SW BST to PGND DRVH to SW PGND to GND Operating Junction Temperature Range Storage Temperature Range Soldering Conditions Maximum Soldering Lead Temperature (10 sec) Rating -0.3 V to +6 V -0.3 V to +28 V -0.3 V to (VDD + 0.3 V) -0.3 V to (VDD + 0.3 V) -0.3 V to +28 V -2 V pulse (20 ns) -0.6 V to (VDD + 0.3 V) -0.3 V to +28 V -0.3 V to VDD 0.3 V -40C to +125C THERMAL RESISTANCE JA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. Table 3. Thermal Resistance Package Type JA (10-Lead MSOP) 2-Layer Board 4-Layer Board JA Unit 213.1 171.7 C/W C/W BOUNDARY CONDITION -65C to +150C JEDEC J-STD-020 300C In determining the values given in Table 2 and Table 3, natural convection was used to transfer heat to a 4-layer evaluation board. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION Rev. B | Page 5 of 40 ADP1872/ADP1873 Data Sheet VIN 1 COMP/EN 2 FB 3 GND 4 VDD 5 10 BST ADP1872 9 SW TOP VIEW (Not to Scale) 8 DRVH 7 PGND 6 DRVL 08297-003 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Figure 3. Pin Configuration Table 4. Pin Function Descriptions Pin No. 1 2 3 4 Mnemonic VIN COMP/EN FB GND 5 VDD 6 DRVL 7 8 9 10 PGND DRVH SW BST Description High Input Voltage. Connect VIN to the drain of the upper-side MOSFET. Output of the Internal Error Amplifier/IC Enable. When this pin functions as EN, applying 0 V to this pin disables the IC. Noninverting Input of the Internal Error Amplifier. This is the node where the feedback resistor is connected. Analog Ground Reference Pin of the IC. All sensitive analog components should be connected to this ground plane (see the Layout Considerations Section). Bias Voltage Supply for the ADP1872/ADP1873 Controller (Includes the Output Gate Drivers). A bypass capacitor of 1 F directly from this pin to PGND and a 0.1 F across VDD and GND are recommended. Drive Output for the External Lower Side, N-Channel MOSFET. This pin also serves as the current-sense gain setting pin (see Figure 68). Power GND. Ground for the lower side gate driver and lower side, N-channel MOSFET. Drive Output for the External Upper Side, N-Channel MOSFET. Switch Node Connection. Bootstrap for the Upper Side MOSFET Gate Drive Circuitry. An internal boot rectifier (diode) is connected between VDD and BST. A capacitor from BST to SW is required. An external Schottky diode can also be connected between VDD and BST for increased gate drive capability. Rev. B | Page 6 of 40 Data Sheet ADP1872/ADP1873 100 VDD = 5.5V, VIN = 13V (PSM) 95 VDD = 5.5V, VIN = 5.5V VDD = 5.5V, VIN = 16.5V (PSM) 90 85 VDD = 3.6V, VIN = 5.5V VDD = 5.5V, 75 VIN = 5.5V VDD = 5.5V, VIN = 13V (PSM) VDD = 3.6V, VIN = 13V 65 60 VDD = 5.5V, VIN = 16.5V 55 VDD = 3.6V, VIN = 16.5V 50 45 40 30 100 1k 10k 100k LOAD CURRENT (mA) 08297-004 WURTH IND: 744355147, L = 0.47H, DCR: 0.80m INFINEON FETs: BSC042N03MS G (UPPER/LOWER) TA = 25C 35 LOAD CURRENT (mA) Figure 4. Efficiency--300 kHz, VOUT = 0.8 V 95 VDD = 5.5V, VIN = 5.5V (PSM) 100 VDD = 5.5V, VIN = 5.5V 95 90 90 85 85 80 75 EFFICIENCY (%) VDD = 5.5V, VIN = 16.5V (PSM) VDD = 5.5V, VIN = 16.5V 70 65 VDD = 5.5V, VIN = 13V (PSM) 60 55 VDD = 3.6V, VIN = 3.6V 50 VDD = 5.5V, VIN = 13V 45 40 25 100 1k 65 60 VDD = 5.5V, VIN = 13V (PSM) 55 50 VDD = 3.6V, VIN = 5.5V VDD = 5.5V, VIN = 13V 35 WURTH IND: 744325120, L = 1.2H, DCR: 1.8m INFINEON FETS: BSC042N03MS G (UPPER/LOWER) TA = 25C 30 VDD = 5.5V, VIN = 16.5V (PSM) 70 40 VDD = 3.6V, VIN = 5.5V 35 VDD = 5.5V, VIN = 16.5V 75 45 10k 100k LOAD CURRENT (mA) 25 100 90 85 85 80 EFFICIENCY (%) VDD = 5.5V, VIN = 16V (PSM) 65 60 VDD = 2.7V VDD = 3.6V VDD = 5.5V 55 13VIN 13V IN 13V IN 50 16.5V IN 16.5V IN 16.5V IN 35 30 100 100k VDD = 3.6V,VIN = 13V 75 70 65 60 VDD = 5.5V, VIN = 13V VDD = 5.5V, VIN = 16.5V (PSM) VDD = 3.6V, VIN = 16.5V VDD = 5.5V, VIN = 16.5V 55 50 45 40 VDD = 5.5V, 95 VIN = 13V (PSM) 45 40 WURTH IND: 7443551200, L = 2H, DCR: 2.6m INFINEON FETs: BSC042N03MS G (UPPER/LOWER) TA = 25C 1k 10k LOAD CURRENT (mA) 100k 35 08297-006 EFFICIENCY (%) 100 VDD = 5.5V, VIN = 16.5V (PSM) 90 70 10k Figure 8. Efficiency--600 kHz, VOUT = 1.8 V 100 75 1k LOAD CURRENT (mA) Figure 5. Efficiency--300 kHz, VOUT = 1.8 V 80 WURTH IND: 744325120, L = 1.2H, DCR: 1.8m INFINEON FETS: BSC042N03MS G (UPPER/LOWER) TA = 25C 30 08297-005 EFFICIENCY (%) 80 95 VDD = 5.5V, VIN = 5.5V VDD = 5.5V, = VIN = 5.5(PSM) 08297-008 100 Figure 7. Efficiency--600 kHz, VOUT = 0.8 V Figure 6. Efficiency--300 kHz, VOUT = 7 V 30 100 WURTH IND: 7443551200, L = 2H, DCR: 2.6m INFINEON FETs: BSC042N03MS G (UPPER/LOWER) TA = 25C 1k 10k LOAD CURRENT (mA) Figure 9. Efficiency--600 kHz, VOUT = 5 V Rev. B | Page 7 of 40 100k 08297-009 70 EFFICIENCY (%) EFFICIENCY (%) 80 100 VDD = 5.5V, VIN = 13V (PSM) VDD = 5.5V, VIN = 5.5V 95 VDD = 5.5V, VIN = 5.5V (PSM) 90 85 80 75 V = 5.5V, VDD = 3.6V, VIN = 5.5V 70 VDD= 16.5V IN VDD = 5.5V, VIN = 13V 65 (PSM) 60 VDD = 5.5V, VIN = 16.5V 55 50 45 40 35 30 WURTH IND: 744355147, L = 0.47H, DCR: 0.80m 25 INFINEON FETs: BSC042N03MS G (UPPER/LOWER) 20 TA = 25C 15 100 1k 10k 100k 08297-007 TYPICAL PERFORMANCE CHARACTERISTICS ADP1872/ADP1873 0.8030 VDD = 5.5V, VIN = 5.5V 0.8025 VIN = 5.5V (PSM) 0.8020 0.8015 VDD = 3.6V, VIN = 5.5V VDD = 3.6V, VIN = 3.6V 10k 100k LOAD CURRENT (mA) 0.7960 VIN = 16.5V +125C +25C -40C VIN = 5.5V +125C +25C -40C 0 2000 4000 6000 8000 10,000 12,000 14,000 16,000 LOAD CURRENT (mA) 1.821 OUTPUT VOLTAGE (V) 1.816 1.811 1.806 1.801 1.796 VIN = 5.5V +125C +25C -40C 1.791 1.786 0 1500 3000 4500 VIN = 13V +125C +25C -40C 6000 7500 VIN = 16.5V +125C +25C -40C 9000 10,500 12,000 13,500 15,000 LOAD CURRENT (mA) Figure 11. Efficiency--1.0 MHz, VOUT = 1.8 V Figure 14. Output Voltage Accuracy--300 kHz, VOUT = 1.8 V 100 VDD = 5.5V, VIN = 5V (PSM) VDD = 5.5V, VIN = 16.5V (PSM) 95 90 85 80 VDD = 5V, 75 VIN = 13V 7.000 VDD = 3.6V, VIN = 13V VDD = 3.6V, VIN = 16.5V 6.995 OUTPUT VOLTAGE (V) 6.990 VDD = 5V, VIN = 16.5V 6.985 6.980 6.975 6.970 6.965 WURTH IND: 744325072, L = 0.72H, DCR: 1.65m INFINEON FETs: BSC042N03MS G (UPPER/LOWER) TA = 25C 1k LOAD CURRENT (mA) 10k 6.960 08297-012 EFFICIENCY (%) 0.7980 0.7965 08297-011 EFFICIENCY (%) LOAD CURRENT (mA) 20 100 VIN = 13V +125C +25C -40C 0.7985 Figure 13. Output Voltage Accuracy--300 kHz, VOUT = 0.8 V 100 VDD = 5.5V, VIN = 5V (PSM) V = 5.5V, 95 VDD= 16.5V (PSM) IN 90 85 VDD = 5.5V, 80 VIN = 5V VDD = 5.5V, = 5.5V, V = 16.5V V 75 VIN = 13V DD IN VDD = 3.6V, VIN = 13V 70 (PSM) VDD = 3.6V, VIN = 16.5V 65 VDD = 5.5V, VIN = 13V 60 55 50 45 40 35 30 WURTH IND: 744303022, L = 0.22H, DCR: 0.33m INFINEON FETs: BSC042N03MS G (UPPER/LOWER) 25 TA = 25C 20 100 1k 10k 100k 40 35 30 25 0.7990 0.7970 Figure 10. Efficiency--1.0 MHz, VOUT = 0.8 V 70 65 60 55 50 45 0.7995 0.7975 WURTH IND: 744303012, L = 0.12H, DCR: 0.33m INFINEON FETs: BSC042N03MS G (UPPER/LOWER) TA = 25C 1k 0.8000 08297-013 30 25 20 100 VDD = 5.5V, VIN = 16.5V VDD = 5.5V, VIN = 13V 0.8005 Figure 12. Efficiency--1.0 MHz, VOUT = 4 V 6.955 +125C +25C -40C 0 VDD = 5.5V, VIN = 13V VDD = 5.5V, VIN = 16.5V 1000 2000 3000 4000 5000 6000 7000 8000 9000 10,000 LOAD CURRENT (mA) Figure 15. Output Voltage Accuracy--300 kHz, VOUT = 7 V Rev. B | Page 8 of 40 08297-015 60 55 50 45 40 35 0.8010 08297-014 VDD = 5.5V, VIN = 16.5V (PSM) OUTPUT VOLTAGE (V) 90 85 80 75 70 65 DD 08297-010 EFFICIENCY (%) 100 V = 5.5V, VIN = 13V (PSM) 95 DD V = 5.5V, Data Sheet ADP1872/ADP1873 1.801 1.810 1.800 1.809 1.799 1.808 1.798 1.807 OUTPUT VOLTAGE (V) 1.797 1.796 1.795 1.794 1.793 1.792 1.804 1.803 1.802 1.801 1.789 0 1500 3000 4500 6000 7500 9000 10,500 12,000 13,500 15,000 LOAD CURRENT (mA) 1.798 0 5.040 OUTPUT VOLTAGE (V) 5.038 5.036 5.034 5.032 5.030 5.028 5.026 5.024 VDD = 5.5V, VIN = 13V VDD = 5.5V, VIN = 16.5V 1000 2000 3000 4000 5000 6000 7000 8000 9000 10,000 LOAD CURRENT (mA) 08297-017 0 1500 3000 4500 6000 7500 9000 10,500 12,000 13,500 15,000 Figure 19. Output Voltage Accuracy--1.0 MHz, VOUT = 1.8 V 5.042 5.020 VIN = 16.5V +125C +25C -40C LOAD CURRENT (mA) 5.044 5.022 VIN = 13V +125C +25C -40C 1.797 Figure 16. Output Voltage Accuracy--600 kHz, VOUT = 1.8 V +125C +25C -40C VIN = 5.5V +125C +25C -40C 1.799 08297-019 VIN = 16.5V +125C +25C -40C 4.050 4.045 4.040 4.035 4.030 4.025 4.020 4.015 4.010 4.005 4.000 3.995 3.990 3.985 3.980 3.975 3.970 VIN = 13V +125C +25C -40C 0 800 VIN = 16.5V +125C +25C -40C 1600 2400 3200 4000 4800 5600 6400 7200 8000 LOAD CURRENT (mA) Figure 17. Output Voltage Accuracy--600 kHz, VOUT = 5 V 08297-020 VIN = 13V +125C +25C -40C 08297-016 1.790 OUTPUT VOLTAGE (V) 1.805 1.800 VIN = 5.5V +125C +25C -40C 1.791 Figure 20. Output Voltage Accuracy--1.0 MHz, VOUT = 4 V 0.807 0.6030 VIN = 5.5V +125C +25C -40C 0.806 0.6025 0.6020 FEEDBACK VOLTAGE (V) 0.805 0.804 0.803 0.802 0.801 0.6015 0.6010 0.6005 0.6000 0.5995 0.5990 0.800 VIN = 13V +125C +25C -40C 0.799 0.798 0 2000 4000 6000 8000 0.5985 VIN = 16.5V +125C +25C -40C 10,000 12,000 14,000 16,000 LOAD CURRENT (mA) 0.5980 08297-018 OUTPUT VOLTAGE (V) 1.806 Figure 18. Output Voltage Accuracy--1 MHz, VOUT = 0.8 V 0.5975 -40.0 VDD = 2.7V, VIN = 2.7V, 3.6V VDD = 3.6V, VIN = 3.6V TO 16.5V VDD = 5.5V, VIN = 5.5V, 13V, 16.5V -7.5 25.0 57.5 90.0 TEMPERATURE (C) Figure 21. Feedback Voltage vs. Temperature Rev. B | Page 9 of 40 122.5 08297-021 OUTPUT VOLTAGE (V) Data Sheet ADP1872/ADP1873 325 VDD = 5.5V VDD = 3.6V +125C +25C -40C 340 NO LOAD 315 FREQUENCY (kHz) FREQUENCY (kHz) 295 285 275 265 255 295 280 265 250 235 220 235 205 225 10.8 11.0 11.2 11.4 11.6 11.8 12.0 12.2 12.4 12.6 12.8 13.0 13.2 190 08297-022 245 VIN (V) 0 VDD = 5.5V VDD = 3.6V +125C +25C -40C 2000 4000 6000 8000 10,000 12,000 14,000 16,000 LOAD CURRENT (mA) Figure 25. Frequency vs. Load Current, 300 kHz, VOUT = 0.8 V Figure 22. Switching Frequency vs. High Input Voltage, 300 kHz, 10% of 12 V 360 NO LOAD VIN = 5.5V VIN = 13V VIN = 16.5V 350 +125C +25C -40C 340 FREQUENCY (kHz) 600 FREQUENCY (kHz) +125C +25C -40C 310 305 650 VIN = 5.5V VIN = 13V VIN = 16.5V 325 08297-025 335 Data Sheet 550 500 330 320 310 300 290 280 450 270 950 VDD = 5.5V VDD = 3.6V +125C +25C -40C FREQUENCY (kHz) 850 800 750 700 650 600 08297-024 FREQUENCY (kHz) 900 VIN (V) 6000 8000 10,000 12,000 14,000 16,000 18,000 20,000 Figure 26. Frequency vs. Load Current, 300 kHz, VOUT = 1.8 V NO LOAD 550 10.8 11.0 11.2 11.4 11.6 11.8 12.0 12.2 12.4 12.6 12.8 13.0 13.2 4000 LOAD CURRENT (mA) Figure 23. Switching Frequency vs. High Input Voltage, 600 kHz, VOUT = 1.8 V, 10% of 12 V 1000 2000 08297-026 0 358 354 350 346 342 338 334 330 326 322 318 314 310 306 302 298 294 290 VIN = 13V VIN = 16.5V 0 +125C +25C -40C 800 1600 2400 3200 4000 4800 5600 6400 7200 8000 8800 9600 LOAD CURRENT (mA) Figure 27. Frequency vs. Load Current, 300 kHz, VOUT = 7 V Figure 24. Switching Frequency vs. High Input Voltage, 1.0 MHz, 10% of 12 V Rev. B | Page 10 of 40 08297-027 VIN (V) 260 08297-023 400 10.8 11.0 11.2 11.4 11.6 11.8 12.0 12.2 12.4 12.6 12.8 13.0 13.2 700 670 640 610 580 550 520 490 460 430 400 370 340 310 280 250 220 190 ADP1872/ADP1873 VIN = 5.5V VIN = 13V VIN = 16.5V 1300 +125C +25C -40C 1150 FREQUENCY (kHz) 1000 925 850 775 700 625 550 2000 4000 6000 8000 10,000 12,000 14,000 16,000 400 0 4000 6000 8000 10,000 12,000 14,000 16,000 LOAD CURRENT (mA) Figure 28. Frequency vs. Load Current, 600 kHz, VOUT = 0.8 V 815 795 775 755 735 715 695 675 655 635 615 595 575 555 535 515 495 2000 08297-031 475 LOAD CURRENT (mA) Figure 31. Frequency vs. Load Current, VOUT = 1.0 MHz, 0.8 V VIN = 5.5V VIN = 13V VIN = 16.5V 1450 VIN = 5.5V VIN = 13V VIN = 16.5V 1375 1300 MIN-OFF TIME ENCROACHMENT FREQUENCY (kHz) 1225 1150 1075 1000 925 850 775 700 4000 6000 550 08297-029 2000 8000 10,000 12,000 14,000 16,000 18,000 20,000 LOAD CURRENT (mA) 0 VIN = 13V VIN = 16.5V 698 2000 4000 6000 8000 10,000 12,000 14,000 16,000 18,000 20,000 LOAD CURRENT (mA) Figure 32. Frequency vs. Load Current, 1.0 MHz, VOUT = 1.8 V Figure 29. Frequency vs. Load Current, 600 kHz, VOUT = 1.8 V 705 +125C +25C -40C 625 08297-032 +125C +25C -40C 0 1450 +125C +25C -40C VIN = 13V VIN = 16.5V 1400 691 684 +125C +25C -40C 1350 FREQUENCY (kHz) 677 670 663 656 649 642 635 1300 1250 1200 1150 628 1100 621 614 600 0 800 1600 2400 3200 4000 4800 5600 6400 7200 8000 8800 9600 LOAD CURRENT (mA) Figure 30. Frequency vs. Load Current, 600 kHz, VOUT =5 V 1000 0 800 1600 2400 3200 4000 4800 5600 6400 7200 8000 LOAD CURRENT (mA) Figure 33. Frequency vs. Load Current, 1.0 MHz, VOUT = 4 V Rev. B | Page 11 of 40 08297-033 1050 607 08297-030 FREQUENCY (kHz) +125C +25C -40C 1075 0 FREQUENCY (kHz) VIN = 5.5V VIN = 13V VIN = 16.5V 1125 08297-028 FREQUENCY (kHz) Data Sheet ADP1872/ADP1873 Data Sheet 2.658 680 2.657 630 580 MINIMUM OFF-TIME (ns) 2.656 2.654 2.653 2.652 2.651 530 480 430 380 330 280 2.650 0 20 40 60 80 100 120 TEMPERATURE (C) 180 -40 08297-034 -20 VDD = 2.7V VDD = 3.6V VDD = 5.5V 95 80 100 120 +125C +25C -40C 580 75 70 65 60 55 530 480 430 380 330 280 50 500 600 700 800 900 1000 FREQUENCY (kHz) 180 2.7 08297-035 400 3.5 3.9 4.3 4.7 5.1 5.5 VDD (V) Figure 35. Maximum Duty Cycle vs. Frequency VDD = 3.6V VDD = 5.5V 3.1 08297-038 230 45 Figure 38. Minimum Off-Time vs. VDD (Low Input Voltage) 800 +125C +25C -40C 720 VDD = 2.7V VDD = 3.6V VDD = 5.5V +125C +25C -40C RECTIFIER DROP (mV) 640 560 480 400 320 240 160 4.8 6.0 7.2 8.4 9.6 10.8 12.0 13.2 14.4 15.6 VIN (V) 08297-036 MAXIMUM DUTY CYCLE (%) 60 630 80 84 82 80 78 76 74 72 70 68 66 64 62 60 58 56 54 52 50 48 46 44 42 40 3.6 40 680 +125C +25C -40C 85 40 300 20 Figure 37. Minimum Off-Time vs. Temperature MINIMUM OFF-TIME (ns) MAXIMUM DUTY CYCLE (%) 90 0 TEMPERATURE (C) Figure 34. UVLO vs. Temperature 100 -20 08297-037 230 Figure 36. Maximum Duty Cycle vs. High Voltage Input (VIN) 80 300 400 500 600 700 800 900 FREQUENCY (kHz) Figure 39. Internal Rectifier Drop vs. Frequency Rev. B | Page 12 of 40 1000 08297-039 UVLO (V) 2.655 2.649 -40 VDD = 2.7V VDD = 3.6V VDD = 5.5V Data Sheet 1280 1200 1120 ADP1872/ADP1873 VIN = 5.5V VIN = 13V VIN = 16.5V 1MHz 300kHz TA = 25C OUTPUT VOLTAGE 1 RECTIFIER DROP (mV) 1040 960 880 800 INDUCTOR CURRENT 720 2 640 560 SW NODE 480 400 3 320 240 3.1 3.5 3.9 4.3 4.7 5.1 5.5 VDD (V) 640 300kHz 1MHz CH2 5A CH4 5V M400ns T 35.8% A CH2 3.90A Figure 43. Power Saving Mode (PSM) Operational Waveform, 100 mA Figure 40. Internal Boost Rectifier Drop vs. VDD (Low Input Voltage) over VIN Variation 720 CH1 50mV BW CH3 10V BW 08297-040 80 2.7 LOW SIDE 4 08297-043 160 +125C +25C -40C OUTPUT VOLTAGE RECTIFIER DROP (mV) 1 560 INDUCTOR CURRENT 480 2 400 320 SW NODE 240 3 160 LOW SIDE 3.1 3.5 3.9 4.3 4.7 5.1 5.5 VDD (V) CH1 50mV BW CH3 10V BW 08297-041 80 2.7 A CH2 3.90A OUTPUT VOLTAGE +125C +25C -40C 4 64 56 INDUCTOR CURRENT 48 40 32 1 24 SW NODE 16 3.1 3.5 3.9 4.3 VDD (V) 4.7 5.1 5.5 Figure 42. Lower Side MOSFET Body Conduction Time vs. VDD (Low Input Voltage) Rev. B | Page 13 of 40 CH1 5A CH3 10V CH4 100mV B W M400ns T 30.6% A CH3 Figure 45. CCM Operation at Heavy Load, 18 A (See Figure 91 for Application Circuit) 2.20V 08297-045 8 2.7 3 08297-042 BODY DIODE CONDUCTION TIME (ns) 300kHz 1MHz 72 M4.0s T 35.8% Figure 44. PSM Waveform at Light Load, 500 mA Figure 41. Internal Boost Rectifier Drop vs. VDD 80 CH2 5A CH4 5V 08297-044 4 ADP1872/ADP1873 Data Sheet OUTPUT VOLTAGE 2 4 OUTPUT VOLTAGE 20A STEP 20A STEP 1 LOW SIDE 1 SW NODE 3 2 SW NODE LOW SIDE 4 B W M2ms T 75.6% A CH1 3.40A 3 CH1 10A CH3 20V Figure 46. Load Transient Step--PSM Enabled, 20 A (See Figure 91 Application Circuit) CH2 5V CH4 200mV B W M2ms T 15.6% A CH1 6.20A 08297-049 CH2 200mV CH4 5V 08297-046 CH1 10A CH3 20V Figure 49. Load Transient Step--Forced PWM at Light Load, 20 A (See Figure 91 Application Circuit) OUTPUT VOLTAGE OUTPUT VOLTAGE 2 4 20A POSITIVE STEP 20A POSITIVE STEP SW NODE 1 LOW SIDE 1 3 2 SW NODE LOW SIDE 4 B W M20s T 30.6% A CH1 3.40A CH1 10A CH3 20V Figure 47. Positive Step During Heavy Load Transient Behavior--PSM Enabled, 20 A, VOUT = 1.8 V (See Figure 91 Application Circuit) 2 CH2 5V CH4 200mV B W M20s T 43.8% A CH1 6.20A 08297-050 CH2 200mV CH4 5V 08297-047 3 CH1 10A CH3 20V Figure 50. Positive Step During Heavy Load Transient Behavior--Forced PWM at Light Load, 20 A, VOUT = 1.8 V (See Figure 91 Application Circuit) OUTPUT VOLTAGE 2 OUTPUT VOLTAGE 20A NEGATIVE STEP 20A NEGATIVE STEP 1 1 SW NODE SW NODE 3 3 4 CH1 10A CH3 20V CH2 200mV CH4 5V B W M20s T 48.2% A CH1 3.40A 08297-048 4 CH1 10A CH3 20V Figure 48. Negative Step During Heavy Load Transient Behavior--PSM Enabled, 20 A (See Figure 91 Application Circuit) CH2 200mV CH4 5V B W M10s T 23.8% A CH1 5.60A 08297-051 LOW SIDE LOW SIDE Figure 51. Negative Step During Heavy Load Transient Behavior--Forced PWM at Light Load, 20 A (See Figure 91 Application Circuit) Rev. B | Page 14 of 40 Data Sheet ADP1872/ADP1873 OUTPUT VOLTAGE OUTPUT VOLTAGE 1 1 INDUCTOR CURRENT 2 INDUCTOR CURRENT LOW SIDE 2 LOW SIDE 4 4 SW NODE SW NODE 3 M4ms T 49.4% A CH1 920mV CH1 2V BW CH2 5A CH3 10V CH4 5V Figure 52. Output Short-Circuit Behavior Leading to Hiccup Mode 1 M4ms T 41.6% A CH1 720mV 08297-055 CH1 2V BW CH2 5A CH3 10V CH4 5V 08297-052 3 Figure 55. Power-Down Waveform During Heavy Load OUTPUT VOLTAGE OUTPUT VOLTAGE 1 INDUCTOR CURRENT INDUCTOR CURRENT 2 2 SW NODE SW NODE 3 3 LOW SIDE LOW SIDE 4 A CH2 8.20A CH1 50mV BW CH3 10V BW Figure 53. Magnified Waveform During Hiccup Mode CH2 5A CH4 5V M2s T 35.8% A CH2 3.90A 08297-056 M10s T 36.2% 08297-053 4 CH1 5V BW CH2 10A CH3 10V CH4 5V Figure 56. Output Voltage Ripple Waveform During PSM Operation at Light Load, 2 A OUTPUT VOLTAGE 1 OUTPUT VOLTAGE 1 INDUCTOR CURRENT LOW SIDE 2 4 LOW SIDE SW NODE 4 3 INDUCTOR CURRENT SW NODE 3 M2ms T 32.8% A CH1 720mV CH1 1V BW CH3 10V BW Figure 54. Start-Up Behavior at Heavy Load, 18 A, 300 kHz (See Figure 91 Application Circuit) CH2 5A CH4 2V M1ms T 63.2% A CH1 Figure 57. Soft Start and RES Detect Waveform Rev. B | Page 15 of 40 1.56V 08297-057 CH1 2V BW CH2 5A CH3 10V CH4 5V 08297-054 2 ADP1872/ADP1873 Data Sheet TA = 25C VDD = 5.5V VDD = 3.6V VDD = 2.7V 570 TRANSCONDUCTANCE (S) LOW SIDE 4 HIGH SIDE SW NODE 3 2 550 530 510 490 470 450 M M40ns T 29.0% A CH2 4.20V 430 -40 08297-058 CH3 5V MATH 2V 40ns CH2 5V CH4 2V 20 40 60 80 100 680 +125C +25C -40C TRANSCONDUCTANCE (S) 630 4 120 Figure 61. Transconductance (GM) vs. Temperature TA = 25C 16ns (tf, DRVL) 0 TEMPERATURE (C) Figure 58. Output Drivers and SW Node Waveforms LOW SIDE -20 08297-061 HS MINUS SW 22ns (tpdh, DRVH) HIGH SIDE 25ns (tr, DRVH) SW NODE 580 530 480 430 3 2 CH2 5V CH3 5V CH4 2V MATH 2V 40ns M40ns T 29.0% A CH2 4.20V 330 2.7 3.0 3.3 3.6 3.9 4.2 4.5 4.8 5.1 5.4 VDD (V) Figure 59. Upper Side Driver Rising and Lower Side Falling Edge Waveforms (CGATE = 4.3 nF (Upper/Lower Side MOSFET), QTOTAL = 27 nC (VGS = 4.4 V (Q1), VGS = 5 V (Q3)) 08297-062 380 HS MINUS SW 08297-059 M Figure 62. Transconductance (GM) vs. VDD 1.30 18ns (tr, DRVL) LOW SIDE 1.25 QUIESCENT CURRENT (mA) 1.20 4 HIGH SIDE HS MINUS SW 24ns (tpdh, DRVL) 11ns (tf, DRVH) SW NODE 3 2 1.15 +125C 1.10 1.05 +25C 1.00 0.95 -40C 0.90 0.85 0.80 M M20ns T 39.2% A CH2 4.20V 0.70 2.7 08297-060 CH2 5V CH3 5V CH4 2V MATH 2V 20ns 3.1 3.5 3.9 4.3 4.7 5.1 VDD (V) Figure 60. Upper Side Driver Falling and Lower Side Rising Edge Waveforms (CGATE = 4.3 nF (Upper/Lower Side MOSFET), QTOTAL = 27 nC (VGS = 4.4 V (Q1), VGS = 5 V (Q3)) Rev. B | Page 16 of 40 Figure 63. Quiescent Current vs. VDD (VIN = 13 V) 5.5 08297-163 0.75 TA = 25C Data Sheet ADP1872/ADP1873 ADP1872/ADP1873 BLOCK DIGRAM TO ENABLE ALL BLOCKS PRECISION ENABLE BLOCK COMP/EN tON BIAS BLOCK VDD ADP1872/ ADP1873 VIN FILTER VDD VDD BST REF_ZERO ISS DRVH PFM STATE MACHINE CSS SS_REF DRIVERS ERROR AMP SW 300k SS COMP DRVL 8k FB IREV COMP VREG LOWER COMP CLAMP REF_ZERO PGND PWM 800k CS AMP CS GAIN SET ADC CS GAIN PROGRAMMING GND Figure 64. ADP1872/ADP1873 Block Diagram Rev. B | Page 17 of 40 08297-063 0.6V ADP1872/ADP1873 Data Sheet THEORY OF OPERATION ADP1872/ADP1873 The ADP1872/ADP1873 are versatile current-mode, synchronous step-down controllers that provide superior transient response, optimal stability, and current limit protection by using a constant on-time, pseudo-fixed frequency with a programmable currentsense gain, current-control scheme. In addition, these devices offer optimum performance at low duty cycles by using valley currentmode control architecture. This allows the ADP1872/ ADP1873 to drive all N-channel power stages to regulate output voltages as low as 0.6 V. FB VDD SS COMP/EN ERROR AMPLIFIER CC RC 0.6V PRECISION ENABLE CC2 The ADP1872/ADP1873 have an input low voltage pin (VDD) for biasing and supplying power for the integrated MOSFET drivers. A bypass capacitor should be located directly across the VDD (Pin 5) and PGND (Pin 7) pins. Included in the power-up sequence is the biasing of the current-sense amplifier, the current-sense gain circuit (see the Programming Resistor (RES) Detect Circuit section), the soft start circuit, and the error amplifier. The rise time of the output voltage is determined by the soft start and error amplifier blocks (see the Soft Start section). At the beginning of a soft start, the error amplifier charges the external compensation capacitor, causing the COMP/EN pin to rise above the enable threshold of 285 mV, thus enabling the ADP1872/ADP1873. SOFT START The ADP1872/ADP1873 have digital soft start circuitry, which involves a counter that initiates an incremental increase in current, by 1 A, via a current source on every cycle through a fixed internal capacitor. The output tracks the ramping voltage by producing PWM output pulses to the upper side MOSFET. The purpose is to limit the in-rush current from the high voltage input supply (VIN) to the output (VOUT). PRECISION ENABLE CIRCUITRY The ADP1872/ADP1873 employ precision enable circuitry. The enable threshold is 285 mV typical with 35 mV of hysteresis. The devices are enabled when the COMP/EN pin is released, allowing the error amplifier output to rise above the enable threshold (see Figure 65). Grounding this pin disables the ADP1872/ADP1873, reducing the supply current of the devices to approximately 140 A. For more information, see Figure 66. Figure 65. Release COMP/EN Pin to Enable the ADP1872/ADP1873 COMP/EN >2.4V 2.4V 1.0V HICCUP MODE INITIALIZED MAXIMUM CURRENT (UPPER CLAMP) ZERO CURRENT USABLE RANGE ONLY AFTER SOFT START PERIOD IF CONTUNUOUS CONDUCTION MODE OF OPERATION IS SELECTED. 500mV 285mV 0V LOWER CLAMP PRECISION ENABLE THRESHOLD 35mV HYSTERESIS 08297-065 The current-sense blocks provide valley current information (see the Programming Resistor (RES) Detect Circuit section) and are a variable of the compensation equation for loop stability (see the Compensation Network section). The valley current information is extracted by forcing 0.4 V across the DRVL output and the PGND pin, which generates a current depending on the resistor across DRVL and PGND in a process performed by the RES detect circuit. The current through the resistor is used to set the current-sense amplifier gain. This process takes approximately 800 s, after which the drive signal pulses appear at the DRVL and DRVH pins synchronously and the output voltage begins to rise in a controlled manner through the soft start sequence. 285mV 08297-064 TO ENABLE ALL BLOCKS STARTUP Figure 66. COMP/EN Voltage Range UNDERVOLTAGE LOCKOUT The undervoltage lockout (UVLO) feature prevents the part from operating both the upper side and lower side MOSFETs at extremely low or undefined input voltage (VDD) ranges. Operation at an undefined bias voltage may result in the incorrect propagation of signals to the high-side power switches. This, in turn, results in invalid output behavior that can cause damage to the output devices, ultimately destroying the device tied at the output. The UVLO level has been set at 2.65 V (nominal). THERMAL SHUTDOWN The thermal shutdown is a self-protection feature to prevent the IC from damage due to a very high operating junction temperature. If the junction temperature of the device exceeds 155C, the part enters the thermal shutdown state. In this state, the device shuts off both the upper side and lower side MOSFETs and disables the entire controller immediately, thus reducing the power consumption of the IC. The part resumes operation after the junction temperature of the part cools to less than 140C. Rev. B | Page 18 of 40 Data Sheet ADP1872/ADP1873 PROGRAMMING RESISTOR (RES) DETECT CIRCUIT VALLEY CURRENT-LIMIT SETTING Upon startup, one of the first blocks to become active is the RES detect circuit. This block powers up before soft start begins. It forces a 0.4 V reference value at the DRVL output (see Figure 67) and is programmed to identify four possible resistor values: 47 k, 22 k, open, and 100 k. The architecture of the ADP1872/ADP1873 is based on valley current-mode control. The current limit is determined by three components: the RON of the lower side MOSFET, the error amplifier output voltage swing (COMP), and the current-sense gain. The COMP range is internally fixed at 1.4 V. The current-sense gain is programmable via an external resistor at the DRVL pin (see the Programming Resistor (RES) Detect Circuit section). The RON of the lower side MOSFET can vary over temperature and usually has a positive TC (meaning that it increases with temperature); therefore, it is recommended to program the current-sense gain resistor based on the rated RON of the MOSFET at 125C. The RES detect circuit digitizes the value of the resistor at the DRVL pin (Pin 6). An internal ADC outputs a 2-bit digital code that is used to program four separate gain configurations in the current-sense amplifier (see Figure 68). Each configuration corresponds to a current-sense gain (ACS) of 3 V/V, 6 V/V, 12 V/V, 24 V/V, respectively (see Table 5 and Table 6). This variable is used for the valley current-limit setting, which sets up the appropriate current-sense gain for a given application and sets the compensation necessary to achieve loop stability (see the Valley Current-Limit Setting and Compensation Network sections). Because the ADP1872/ADP1873 are based on valley current control, the relationship between ICLIM and ILOAD is K I CLIM I LOAD 1 I 2 ADP1872 Q1 DRVH where: ICLIM is the desired valley current limit. ILOAD is the current load. KI is the ratio between the inductor ripple current and the desired average load current (see Figure 10). Establishing KI helps to determine the inductor value (see the Inductor Selection section), but in most cases, KI = 0.33. SW Q2 RRES CS GAIN PROGRAMMING 08297-066 DRVL Figure 67. Programming Resistor Location SW CS AMP RIPPLE CURRENT = PGND LOAD CURRENT ADC 0.4V DRVL VALLEY CURRENT LIMIT 08297-068 CS GAIN SET ILOAD 3 08297-067 Figure 69. Valley Current Limit to Average Current Relation RES Figure 68. RES Detect Circuit for Current-Sense Gain Programming When the desired valley current limit (ICLIM) has been determined, the current-sense gain can be calculated by I CLIM Table 5. Current-Sense Gain Programming Resistor 47 k 22 k Open 100 k ACS (V/V) 3 6 12 24 1. 4 V ACS RON where: ACS is the current-sense gain multiplier (see Table 5 and Table 6). RON is the channel impedance of the lower side MOSFET. Although the ADP1872/ADP1873 have only four discrete currentsense gain settings for a given RON variable, Table 6 and Figure 70 outline several available options for the valley current setpoint based on various RON values. Rev. B | Page 19 of 40 ADP1872/ADP1873 Data Sheet Table 6. Valley Current Limit Program1 RON (m) 1.5 2 2.5 3 3.5 4.5 5 5.5 10 15 18 Valley Current Level 22 k Open ACS = 6 V/V ACS = 12 V/V 47 k ACS = 3 V/V 39.0 33.4 26.0 23.4 21.25 11.7 7.75 6.5 23.3 15.5 13.0 31.0 26.0 100 k ACS = 24 V/V 38.9 29.2 23.3 19.5 16.7 13 11.7 10.6 5.83 3.87 3.25 The valley current limit is programmed as outlined in Table 6 and Figure 70. The inductor chosen must be rated to handle the peak current, which is equal to the valley current from Table 6 plus the peak-to-peak inductor ripple current (see the Inductor Selection section). In addition, the peak current value must be used to compute the worst-case power dissipation in the MOSFETs (see Figure 71). 49A MAXIMUM DC LOAD CURRENT INDUCTOR CURRENT I = 33% OF 30A 39.5A I = 65% OF 37A 35A 37A COMP OUTPUT I = 45% 32.25A OF 32.25A 30A 2.4V Refer to Figure 70 for more information and a graphical representation. COMP OUTPUT SWING RES = 47k ACS = 3V/V 0A RES = NO RES ACS = 12V/V Figure 71. Valley Current-Limit Threshold in Relation to Inductor Ripple Current RES = 22k ACS = 6V/V HICCUP MODE DURING SHORT CIRCUIT RES = 100k ACS = 24V/V 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 RON (m) 1V Figure 70. Valley Current-Limit Value vs. RON of the Lower Side MOSFET for Each Programming Resistor (RES) A current-limit violation occurs when the current across the source and drain of the lower side MOSFET exceeds the currentlimit setpoint. When 32 current-limit violations are detected, the controller enters idle mode and turns off the MOSFETs for 6 ms, allowing the converter to cool down. Then, the controller re-establishes soft start and begins to cause the output to ramp up again (see Figure 72). While the output ramps up, COMP is monitored to determine if the violation is still present. If it is still present, the idle event occurs again, followed by the full-chip power-down sequence. This cycle continues until the violation no longer exists. If the violation disappears, the converter is allowed to switch normally, maintaining regulation. REPEATED CURRENT LIMIT VIOLATION DETECTED HS A PREDETERMINED NUMBER SOFT START IS OF PULSES IS COUNTED TO REINITIALIZED TO ALLOW THE CONVERTER MONITOR IF THE TO COOL DOWN VIOLATION STILL EXISTS 08297-071 CLIM 08297-070 39 37 35 33 31 29 27 25 23 21 19 17 15 13 11 9 7 5 3 VALLEY CURRENT LIMIT THRESHOLD (SET FOR 25A) 08297-069 VALLEY CURRENT LIMIT (A) 1 ZERO CURRENT Figure 72. Idle Mode Entry Sequence Due to Current-Limit Violations Rev. B | Page 20 of 40 Data Sheet ADP1872/ADP1873 SYNCHRONOUS RECTIFIER The ADP1872/ADP1873 employ an internal lower side MOSFET driver to drive the external upper side and lower side MOSFETs. The synchronous rectifier not only improves overall conduction efficiency but also ensures proper charging to the bootstrap capacitor located at the upper side driver input. This is beneficial during startup to provide sufficient drive signal to the external upper side MOSFET and attain fast turn-on response, which is essential for minimizing switching losses. The integrated upper and lower side MOSFET drivers operate in complementary fashion with built-in anticross conduction circuitry to prevent unwanted shoot-through current that may potentially damage the MOSFETs or reduce efficiency as a result of excessive power loss. As soon as the forward current through the lower side MOSFET decreases to a level where 10 mV = IQ2 x RON(Q2) the zero-cross comparator (or IREV comparator) emits a signal to turn off the lower side MOSFET. From this point, the slope of the inductor current ramping down becomes steeper (see Figure 75) as the body diode of the lower side MOSFET begins to conduct current and continues conducting current until the remaining energy stored in the inductor has been depleted. ANOTHER tON EDGE IS TRIGGERED WHEN VOUT FALLS BELOW REGULATION SW tON POWER SAVING MODE (PSM) VERSION (ADP1873) HS AND LS IN IDLE MODE LS ZERO-CROSS COMPARATOR DETECTS 10mV OFFSET AND TURNS OFF LS ILOAD 0A 10mV = RON x ILOAD HS 08297-074 The power saving mode version of the ADP1872 is the ADP1873. The ADP1873 operates in the discontinuous conduction mode (DCM) and pulse skips at light load to midload currents. It outputs pulses as necessary to maintain output regulation. Unlike the continuous conduction mode (CCM), DCM operation prevents negative current, thus allowing improved system efficiency at light loads. Current in the reverse direction through this pathway, however, results in power dissipation and therefore a decrease in efficiency. Figure 75. 10 mV Offset to Ensure Prevention of Negative Inductor Current tON The system remains in idle mode until the output voltage drops below regulation. A PWM pulse is then produced, turning on the upper side MOSFET to maintain system regulation. The ADP1873 does not have an internal clock; therefore, it switches purely as a hysteretic controller, as described in this section. HS AND LS ARE OFF OR IN IDLE MODE LS tOFF TIMER OPERATION AS THE INDUCTOR CURRENT APPROACHES ZERO CURRENT, THE STATE MACHINE TURNS OFF THE LOWER SIDE MOSFET. 08297-072 ILOAD 0A Figure 73. Discontinuous Mode of Operation (DCM) To minimize the chance of negative inductor current buildup, an on-board, zero-cross comparator turns off all upper side and lower side switching activities when the inductor current approaches the zero current line, causing the system to enter idle mode, where the upper side and lower side MOSFETs are turned off. To ensure idle mode entry, a 10 mV offset, connected in series at the SW node, is implemented (see Figure 74). ZERO-CROSS COMPARATOR The ADP1872/ADP1873 employ a constant on-time architecture, which provides a variety of benefits, including improved load and line transient response when compared with a constant (fixed) frequency current-mode control loop of comparable loop design. The constant on-time timer, or tON timer, senses the high input voltage (VIN) and the output voltage (VOUT) using SW waveform information to produce an adjustable one-shot PWM pulse that varies the on-time of the upper side MOSFET in response to dynamic changes in input voltage, output voltage, and load current conditions to maintain regulation. It then generates an on-time (tON) pulse that is inversely proportional to VIN. t ON K SW IQ2 08297-073 Q2 VIN where K is a constant that is trimmed using an RC timer product for the 300 kHz, 600 kHz, and 1.0 MHz frequency options. 10mV LS VOUT Figure 74. Zero-Cross Comparator with 10 mV of Offset Rev. B | Page 21 of 40 ADP1872/ADP1873 Data Sheet To illustrate this feature more clearly, this section describes one such load transient event--a positive load step--in detail. During load transient events, the high-side driver output pulse width stays relatively consistent from cycle to cycle; however, the off-time (DRVL on-time) dynamically adjusts according to the instantaneous changes in the external conditions mentioned. VIN C I R (TRIMMED) 08297-075 SW INFORMATION Figure 76. Constant On-Time Timer The constant on-time (tON) is not strictly constant because it varies with VIN and VOUT. However, this variation occurs in such a way as to keep the switching frequency virtually independent of VIN and VOUT. The tON timer uses a feedforward technique, applied to the constant on-time control loop, making it pseudo-fixed frequency to a first order. Second-order effects, such as dc losses in the external power MOSFETs (see the Efficiency Consideration section), cause some variation in frequency vs. load current and line voltage. These effects are shown in Figure 22 to Figure 33. The variations in frequency are much reduced compared with the variations generated when the feedforward technique is not used. The feedforward technique establishes the following relationship: fSW = 1/K where fSW is the controller switching frequency (300 kHz, 600 kHz, and 1.0 MHz). The tON timer senses VIN and VOUT to minimize frequency variation with VIN and VOUT as previously explained. This provides a pseudo-fixed frequency, see the Pseudo-Fixed Frequency section for additional information. To allow headroom for VIN/VOUT sensing, the following two equations must be adhered to. For typical applications where VDD is 5 V, these equations are not relevant; however, for lower VDD, care may be required. VDD VIN/8 + 1.5 VDD VOUT/4 PSEUDO-FIXED FREQUENCY When a positive load step occurs, the error amplifier (out of phase of the output, VOUT) produces new voltage information at its output (COMP). In addition, the current-sense amplifier senses new inductor current information during this positive load transient event. The error amplifier's output voltage reaction is compared to the new inductor current information that sets the start of the next switching cycle. Because current information is produced from valley current sensing, it is sensed at the down ramp of the inductor current, whereas the voltage loop information is sensed through the counter action upswing of the error amplifier's output (COMP). The result is a convergence of these two signals (see Figure 77), which allows an instantaneous increase in switching frequency during the positive load transient event. In summary, a positive load step causes VOUT to transient down, which causes COMP to transient up and therefore shortens the off time. This resulting increase in frequency during a positive load transient helps to quickly bring VOUT back up in value and within the regulation window. Similarly, a negative load step causes the off time to lengthen in response to VOUT rising. This effectively increases the inductor demagnetizing phase, helping to bring VOUT to within regulation. In this case, the switching frequency decreases, or experiences a foldback, to help facilitate output voltage recovery. Because the ADP1872/ADP1873 has the ability to respond rapidly to sudden changes in load demand, the recovery period in which the output voltage settles back to its original steady state operating point is much quicker than it would be for a fixed-frequency equivalent. Therefore, using a pseudo-fixed frequency, results in significantly better load transient performance than using a fixed frequency. The ADP1872/ADP1873 employ a constant on-time control scheme. During steady state operation, the switching frequency stays relatively constant, or pseudo-fixed. This is due to the oneshot tON timer that produces a high-side PWM pulse with a fixed duration, given that external conditions such as input voltage, output voltage, and load current are also at steady state. During load transients, the frequency momentarily changes for the duration of the transient event so that the output comes back within regulation quicker than if the frequency were fixed or if it were to remain unchanged. After the transient event is complete, the frequency returns to a pseudo-fixed value to a first-order. LOAD CURRENT DEMAND CS AMP OUTPUT ERROR AMP OUTPUT PWM OUTPUT VALLEY TRIP POINTS fSW >fSW 08297-076 VDD tON Figure 77. Load Transient Response Operation Rev. B | Page 22 of 40 Data Sheet ADP1872/ADP1873 APPLICATIONS INFORMATION FEEDBACK RESISTOR DIVIDER Table 7. Recommended Inductors The required resistor divider network can be determine for a given VOUT value because the internal band gap reference (VREF) is fixed at 0.6 V. Selecting values for RT and RB determines the minimum output load current of the converter. Therefore, for a given value of RB, the RT value can be determined by L (H) 0.12 0.22 0.47 0.72 0.9 1.2 1.0 1.4 2.0 0.8 RT = R B x (VOUT - 0.6 V) 0. 6 V INDUCTOR SELECTION The inductor value is inversely proportional to the inductor ripple current. The peak-to-peak ripple current is given by I L = K I x I LOAD 3 Dimensions (mm) 10.2 x 7 10.2 x 7 14.2 x 12.8 10.5 x 10.2 13 x 12.8 10.5 x 10.2 10.5 x 10.2 14 x 12.8 13.2 x 12.8 Manufacturer Wurth Elektronic Wurth Elektronic Wurth Elektronic Wurth Elektronic Wurth Elektronic Wurth Elektronic Wurth Elektronic Wurth Elektronic Wurth Elektronic Sumida Model No. 744303012 744303022 744355147 744325072 744355090 744325120 7443552100 744318180 7443551200 CEP125U-0R8 The output ripple voltage is the ac component of the dc output voltage during steady state. For a ripple error of 1.0%, the output capacitor value needed to achieve this tolerance can be determined using the following equation. (Note that an accuracy of 1.0% is only possible during steady state conditions, not during load transients.) The equation for the inductor value is given by (VIN - VOUT ) VOUT x I L x f SW VIN VRR = (0.01) x VOUT where: VIN is the high voltage input. VOUT is the desired output voltage. fSW is the controller switching frequency (300 kHz, 600 kHz, and 1.0 MHz). OUTPUT CAPACITOR SELECTION When selecting the inductor, choose an inductor saturation rating that is above the peak current level and then calculate the inductor current ripple (see the Valley Current-Limit Setting section and Figure 78). 52 50 48 46 44 42 40 38 36 34 32 30 28 26 24 22 20 18 16 14 12 10 8 I = 50% I = 40% The primary objective of the output capacitor is to facilitate the reduction of the output voltage ripple; however, the output capacitor also assists in the output voltage recovery during load transient events. For a given load current step, the output voltage ripple generated during this step event is inversely proportional to the value chosen for the output capacitor. The speed at which the output voltage settles during this recovery period depends on where the crossover frequency (loop bandwidth) is set. This crossover frequency is determined by the output capacitor, the equivalent series resistance (ESR) of the capacitor, and the compensation network. To calculate the small signal voltage ripple (output ripple voltage) at the steady state operating point, use the following equation: I = 33% 1 COUT = I L x [ ] 8 x x V - ( I x ESR ) f RIPPLE L SW 6 8 10 12 14 16 18 20 22 24 26 28 VALLEY CURRENT LIMIT (A) 30 08297-077 PEAK INDUCTOR CURRENT (A) ISAT (A) 55 30 50 35 28 25 20 24 22 27.5 OUTPUT RIPPLE VOLTAGE (VRR) I LOAD where KI is typically 0.33. L= DCR (m) 0.33 0.33 0.8 1.65 1.6 1.8 3.3 3.2 2.6 where ESR is the equivalent series resistance of the output capacitors. To calculate the output load step, use the following equation: Figure 78. Peak Current vs. Valley Current Threshold for 33%, 40%, and 50% of Inductor Ripple Current COUT = 2 x f SW I LOAD x (VDROOP - (I LOAD x ESR)) where VDROOP is the amount that VOUT is allowed to deviate for a given positive load current step (ILOAD). Rev. B | Page 23 of 40 ADP1872/ADP1873 Data Sheet Ceramic capacitors are known to have low ESR. However, the trade-off of using X5R technology is that up to 80% of its capacitance may be lost due to derating because the voltage applied across the capacitor is increased (see Figure 79). Although X7R series capacitors can also be used, the available selection is limited to only up to 22 F. Error Amplifier Output Impedance (ZCOMP) Assuming CC2 is significantly smaller than CCOMP, CC2 can be omitted from the output impedance equation of the error amplifier. The transfer function simplifies to R COMP ( f CROSS + f ZERO ) Z COMP = f CROSS 20 and 10 X7R (50V) fCROSS = -10 -20 1 x f SW 12 where fZERO, the zero frequency, is set to be 1/4th of the crossover frequency for the ADP1872. -30 -40 Error Amplifier Gain (GM) -50 X5R (25V) -60 The error amplifier gain (transconductance) is -70 X5R (16V) -80 GM = 500 A/V 10F TDK 25V, X7R, 1210 C3225X7R1E106M 22F MURATA 25V, X7R, 1210 GRM32ER71E226KE15L 47F MURATA 16V, X5R, 1210 GRM32ER61C476KE15L -90 -100 0 5 10 15 20 25 Current-Sense Loop Gain (GCS) 30 DC VOLTAGE (VDC) 08297-078 CAPACITANCE CHARGE (%) 0 The current-sense loop gain is G CS = Figure 79. Capacitance vs. DC Voltage Characteristics for Ceramic Capacitors Electrolytic capacitors satisfy the bulk capacitance requirements for most high current applications. Because the ESR of electrolytic capacitors is much higher than that of ceramic capacitors, when using electrolytic capacitors, several MLCCs should be mounted in parallel to reduce the overall series resistance. COMPENSATION NETWORK Due to its current-mode architecture, the ADP1872/ADP1873 require Type II compensation. To determine the component values needed for compensation (resistance and capacitance values), it is necessary to examine the converter's overall loop gain (H) at the unity gain frequency (fSW/10) when H = 1 V/V. H = 1 V/V = G M x GCS x VOUT x Z COMP x Z FILT VREF where: ACS (V/V) is programmable for 3 V/V, 6 V/V, 12 V/V, and 24 V/V (see the Programming Resistor (RES) Detect Circuit and Valley Current-Limit Setting sections). RON is the channel impedance of the lower side MOSFET. Crossover Frequency The crossover frequency is the frequency at which the overall loop (system) gain is 0 dB (H = 1 V/V). It is recommended for current-mode converters, such as the ADP1872, that the user set the crossover frequency between 1/10th and 1/15th of the switching frequency. The relationship between CCOMP and fZERO (zero frequency) is f ZERO = Output Filter Impedance (ZFILT) Z FILTER = 1 f SW 12 fCROSS = Examining each variable at high frequency enables the unity gain transfer function to be simplified to provide expressions for the RCOMP and CCOMP component values. Examining the filter's transfer function at high frequencies simplifies to 1 (A/V) ACS x RON 1 2 x RCOMP x CCOMP The zero frequency is set to 1/4th of the crossover frequency. Combining all of the above parameters results in 1 sC OUT at the crossover frequency (s = 2fCROSS). Rev. B | Page 24 of 40 RCOMP = 2fCROSSCOUT VOUT fCROSS x x fCROSS + f ZERO GM GCS VREF CCOMP = 1 2 x x RCOMP x f ZERO Data Sheet ADP1872/ADP1873 EFFICIENCY CONSIDERATION 800 One of the important criteria to consider in constructing a dc-to-dc converter is efficiency. By definition, efficiency is the ratio of the output power to the input power. For high power applications at load currents up to 20 A, the following are important MOSFET parameters that aid in the selection process: 720 VGS (TH): the MOSFET support voltage applied between the gate and the source. RDS (ON): the MOSFET on resistance during channel conduction. QG: the total gate charge CN1: the input capacitance of the upper side switch CN2: the input capacitance of the lower side switch The following are the losses experienced through the external component during normal switching operation: Channel conduction loss (both the MOSFETs) MOSFET driver loss MOSFET switching loss Body diode conduction loss (lower side MOSFET) Inductor loss (copper and core loss) Channel Conduction Loss During normal operation, the bulk of the loss in efficiency is due to the power dissipated through MOSFET channel conduction. Power loss through the upper side MOSFET is directly proportional to the duty cycle (D) for each switching period, and the power loss through the lower side MOSFET is directly proportional to 1 - D for each switching period. The selection of MOSFETs is governed by the amount of maximum dc load current that the converter is expected to deliver. In particular, the selection of the lower side MOSFET is dictated by the maximum load current because a typical high current application employs duty cycles of less than 50%. Therefore, the lower side MOSFET is in the on state for most of the switching period. 2 PN1, N2 (CL) = [D x RN1 (ON) + (1 - D) x RN2 (ON)] x I LOAD 320 80 300 +125C +25C -40C 400 500 600 700 800 900 1000 FREQUENCY (kHz) Figure 80. Internal Rectifier Voltage Drop vs. Switching Frequency MOSFET Switching Loss The SW node transitions due to the switching activities of the upper side and lower side MOSFETs. This causes removal and replenishing of charge to and from the gate oxide layer of the MOSFET, as well as to and from the parasitic capacitance associated with the gate oxide edge overlap and the drain and source terminals. The current that enters and exits these charge paths presents additional loss during these transition times. This can be approximately quantified by using the following equation, which represents the time in which charge enters and exits these capacitive regions. tSW-TRANS = RGATE x CTOTAL where: RGATE is the gate input resistance of the MOSFET. CTOTAL is the CGD + CGS of the external MOSFET used. The ratio of this time constant to the period of one switching cycle is the multiplying factor to be used in the following expression: PSW ( LOSS) t SW -TRANS t SW I LOAD VIN 2 or PSW (LOSS) = fSW x RGATE x CTOTAL x ILOAD x VIN x 2 PDR( LOSS ) VDR f SW CupperFETVDR I BIAS VDD fSW ClowerFETVDD I BIAS 400 160 Other dissipative elements are the MOSFET drivers. The contributing factors are the dc current flowing through the driver during operation and the QGATE parameter of the external MOSFETs. 480 240 MOSFET Driver Loss 560 08297-079 640 RECTIFIER DROP (mV) VDD = 2.7V VDD = 3.6V VDD = 5.5V where: CupperFET is the input gate capacitance of the upper-side MOSFET. ClowerFET is the input gate capacitance of the lower-side MOSFET. VDR is the driver bias voltage (that is, the low input voltage (VDD) minus the rectifier drop (see Figure 80)). IBIAS is the dc current flowing into the upper- and lower-side drivers. VDD is the bias voltage. Rev. B | Page 25 of 40 ADP1872/ADP1873 Data Sheet Body Diode Conduction Loss INPUT CAPACITOR SELECTION The ADP1872/ADP1873 employ anticross conduction circuitry that prevents the upper side and lower side MOSFETs from conducting current simultaneously. This overlap control is beneficial, avoiding large current flow that may lead to irreparable damage to the external components of the power stage. However, this blanking period comes with the trade-off of a diode conduction loss occurring immediately after the MOSFETs change states and continuing well into idle mode. The amount of loss through the body diode of the lower side MOSFET during the antioverlap state is given by The goal in selecting an input capacitor is to reduce or to minimize input voltage ripple and to reduce the high frequency source impedance, which is essential for achieving predictable loop stability and transient performance. PBODY ( LOSS ) t BODY ( LOSS ) t SW I LOAD VF 2 where: tBODY (LOSS) is the body conduction time (refer to Figure 81 for dead time periods). tSW is the period per switching cycle. VF is the forward drop of the body diode during conduction. (Refer to the selected external MOSFET data sheet for more information about the VF parameter.) If bulk capacitors are to be used, it is recommended to use multilayered ceramic capacitors (MLCC) in parallel due to their low ESR values. This dramatically reduces the input voltage ripple amplitude as long as the MLCCs are mounted directly across the drain of the upper side MOSFET and the source terminal of the lower side MOSFET (see the Layout Considerations section). Improper placement and mounting of these MLCCs may cancel their effectiveness due to stray inductance and an increase in trace impedance. +125C +25C -40C 1MHz 300kHz 72 I CIN , RMS I LOAD , MAX 64 48 40 32 VOUT VMAX, RIPPLE = VRIPP + (ILOAD, MAX x ESR) 24 16 8 2.7 VOUT VIN VOUT The maximum input voltage ripple and maximum input capacitor rms current occur at the end of the duration of 1 - D while the upper side MOSFET is in the off state. The input capacitor rms current reaches its maximum at time D. When calculating the maximum input voltage ripple, account for the ESR of the input capacitor as follows: 56 3.4 4.1 VDD (V) 4.8 5.5 08297-080 BODY DIODE CONDUCTION TIME (ns) 80 The problem with using bulk capacitors, other than their physical geometries, is their large equivalent series resistance (ESR) and large equivalent series inductance (ESL). Aluminum electrolytic capacitors have such high ESR that they cause undesired input voltage ripple magnitudes and are generally not effective at high switching frequencies. Figure 81. Body Diode Conduction Time vs. Low Voltage Input (VDD) Inductor Loss During normal conduction mode, further power loss is caused by the conduction of current through the inductor windings, which have dc resistance (DCR). Typically, larger sized inductors have smaller DCR values. The inductor core loss is a result of the eddy currents generated within the core material. These eddy currents are induced by the changing flux, which is produced by the current flowing through the windings. The amount of inductor core loss depends on the core material, the flux swing, the frequency, and the core volume. Ferrite inductors have the lowest core losses, whereas powdered iron inductors have higher core losses. It is recommended to use shielded ferrite core material type inductors with the ADP1872/ADP1873 for a high current, dc-to-dc switching application to achieve minimal loss and negligible electromagnetic interference (EMI). where: VRIPP is usually 1% of the minimum voltage input. ILOAD, MAX is the maximum load current. ESR is the equivalent series resistance rating of the input capacitor used. Inserting VMAX, RIPPLE into the charge balance equation to calculate the minimum input capacitor requirement gives C IN, min I LOAD , MAX VMAX , RIPPLE D(1 D) f SW or C IN, min I LOAD , MAX 4 f SWVMAX , RIPPLE where D = 50%. 2 PDCR (LOSS) = DCR x I LOAD + Core Loss Rev. B | Page 26 of 40 Data Sheet ADP1872/ADP1873 THERMAL CONSIDERATIONS The ADP1872/ADP1873 are used for dc-to-dc, step down, high current applications that have an on-board controller and on-board MOSFET drivers. Because applications may require up to 20 A of load current delivery and be subjected to high ambient temperature surroundings, the selection of external upper side and lower side MOSFETs must be associated with careful thermal consideration to not exceed the maximum allowable junction temperature of 125C. To avoid permanent or irreparable damage if the junction temperature reaches or exceeds 155C, the part enters thermal shutdown, turning off both external MOSFETs, and does not re-enable until the junction temperature cools to 140C (see the Thermal Shutdown section). The maximum junction temperature allowed for the ADP1872/ ADP1873 ICs is 125C. This means that the sum of the ambient temperature (TA) and the rise in package temperature (TR), which is caused by the thermal impedance of the package and the internal power dissipation, should not exceed 125C, as dictated by TJ = TR x TA For example, if the external MOSFET characteristics are JA (10-lead MSOP) = 171.2C/W, fSW = 300 kHz, IBIAS = 2 mA, CupperFET = 3.3 nF, ClowerFET = 3.3 nF, VDR = 5.12 V, and VDD = 5.5 V, then the power loss is PDR (LOSS) = [VDR x (fSWCupperFETVDR + IBIAS)] + [VDD x (fSWClowerFETVDD + IBIAS)] = [5.12 x (300 x 103 x 3.3 x 10-9 x 5.12 + 0.002)] + [5.5 x (300 x 103 x3.3 x 10-9 x 5.5 + 0.002)] = 77.13 mW The rise in package temperature is TR = JA x PDR (LOSS) = 171.2C x 77.13 mW = 13.2C Assuming a maximum ambient temperature environment of 85C, the junction temperature is TJ = TR x TA = 13.2C + 85C = 98.2C which is below the maximum junction temperature of 125C. DESIGN EXAMPLE where: TJ is the maximum junction temperature. TR is the rise in package temperature due to the power dissipated from within. TA is the ambient temperature. The ADP1872/ADP1873 are easy to use, requiring only a few design criteria. For example, the example outlined in this section uses only four design criteria: VOUT = 1.8 V, ILOAD = 15 A (pulsing), VIN = 12 V (typical), and fSW = 300 kHz. The rise in package temperature is directly proportional to its thermal impedance characteristics. The following equation represents this proportionality relationship: The maximum input voltage ripple is usually 1% of the minimum input voltage (11.8 V x 0.01 = 120 mV). Input Capacitor VRIPP = 120 mV TR = JA x PDR (LOSS) VMAX, RIPPLE = VRIPP - (ILOAD, MAX x ESR) = 120 mV - (15 A x 0.001) = 45 mV where: JA is the thermal resistance of the package from the junction to the outside surface of the die, where it meets the surrounding air. PDR (LOSS) is the overall power dissipated by the IC. The bulk of the power dissipated is due to the gate capacitance of the external MOSFETs. The power loss equation of the MOSFET drivers (see the MOSFET Driver Loss section in the Efficiency Consideration section) is C IN, min = I LOAD, MAX 4 f SW VMAX , RIPPLE = 15 A 4 x 300 x 103 x 105 mV = 120 F Choose five 22 F ceramic capacitors. The overall ESR of five 22 F ceramic capacitors is less than 1 m. IRMS = ILOAD/2 = 7.5 A PDR (LOSS) = [VDR x (fSWCupperFETVDR + IBIAS)] + [VDD x (fSWClowerFETVDD + IBIAS)] PCIN = (IRMS)2 x ESR = (7.5A)2 x 1 m = 56.25 mW where: CupperFET is the input gate capacitance of the upper side MOSFET. ClowerFET is the input gate capacitance of the lower side MOSFET. IBIAS is the dc current (2 mA) flowing into the upper side and lower side drivers. VDR is the driver bias voltage (that is, the low input voltage (VDD) minus the rectifier drop (see Figure 80)). VDD is the bias voltage Inductor Determining inductor ripple current amplitude: I L I LOAD =5A 3 so calculating for the inductor value L= = (VIN , MAX - VOUT ) I L x f SW (13.2 V - 1.8 V) 5 V x 300 x 10 = 1.03 H Rev. B | Page 27 of 40 3 x x VOUT VIN, MAX 1. 8 V 13.2 V ADP1872/ADP1873 Data Sheet Choose five 270 F polymer capacitors. The inductor peak current is approximately The rms current through the output capacitor is 15 A + (5 A x 0.5) = 17.5 A Therefore, an appropriate inductor selection is 1.0 H with DCR = 3.3 m (7443552100) from Table 7 with peak current handling of 20 A. PDCR ( LOSS ) = I RMS = = 2 DCR x I LOAD = 0.003 x (15 A)2 = 675 mW PCOUT = (IRMS)2 x ESR = (1.5 A)2 x 1.4 m = 3.15 mW The valley current is approximately Feedback Resistor Network Setup 15 A - (5 A x 0.5) = 12.5 A Assuming a lower side MOSFET RON of 4.5 m, choosing 13 A as the valley current limit from Table 6 and Figure 70 indicates that a programming resistor (RES) of 100 k corresponds to an ACS of 24 V/V. Choose a programmable resistor of RRES = 100 k for a currentsense gain of 24 V/V. Output Capacitor Assume a load step of 15 A occurs at the output and no more than 5% is allowed for the output to deviate from the steady state operating point. The ADP1872's advantage is, because the frequency is pseudo-fixed, the converter is able to respond quickly because of the immediate, though temporary, increase in switching frequency. VDROOP = 0.05 x 1.8 V = 90 mV Assuming the overall ESR of the output capacitor ranges from 5 m to 10 m, It is recommended to use RB = 15 k. Calculate RT as RT = 15 k x GCS = = 30 k 1 1 = = 8.33 A/V ACS RON 24 x 0.005 where ACS and RON are taken from setting up the current limit (see the Programming Resistor (RES) Detect Circuit and Valley Current-Limit Setting sections). The crossover frequency is 1/12th of the switching frequency: 300 kHz/12 = 25 kHz The zero frequency is 1/4th of the crossover frequency: 25 kHz/4 = 6.25 kHz RCOMP = 2fCROSSCOUT VOUT fCROSS x x GM GCS VREF fCROSS + f ZERO 25 x 103 2 x 3.141 x 25 x 103 x 1.11 x 10 -3 1.8 x x 500 x 10 -6 x 8.3 0. 6 25 x 103 + 6.25 x 103 = 100 k = Assuming an overshoot of 45 mV, determine if the output capacitor that was calculated previously is adequate: = 0. 6 V To calculate RCOMP, CCOMP, and CPAR, the transconductance parameter and the current-sense gain variable are required. The transconductance parameter (GM) is 500 A/V, and the currentsense loop gain is Therefore, an appropriate inductor selection is five 270 F polymer capacitors with a combined ESR of 3.5 m. ((VOUT (1.8 V - 0.6 V) Compensation Network = 1.11 mF COUT = 1 1 (13.2 V - 1.8 V) 1.8 V x x = 1.49 A 2 3 1 F x 300 x 10 3 13.2 V The power loss dissipated through the ESR of the output capacitor is Current Limit Programming I LOAD COUT = 2 x f SW x (VDROOP ) 15 A = 2x 300 x 103 x (90 mV) 1 1 (V IN , MAX - VOUT ) VOUT x x 2 L x f SW V IN , MAX 3 C COMP = (L x I 2 LOAD ) - VOVSHT )2 - (VOUT )2 ) 1 2RCOMP f ZERO 1 2 x 3.14 x 100 x 103 x 6.25 x 103 = 250 pF = 1 x 10 -6 x (15 A)2 (1.8 - 45 mV)2 - (1.8)2 = 1.4 mF Rev. B | Page 28 of 40 Data Sheet ADP1872/ADP1873 Loss Calculations PSW (LOSS) = fSW x RGATE x CTOTAL x ILOAD x VIN x 2 = 300 x 103 x 1.5 x 3.3 x 10-9 x 15 A x 12 x 2 = 534.6 mW Duty cycle = 1.8/12 V = 0.15 RON (N2) = 5.4 m [ ( )] PDR ( LOSS ) = VDR x f SW CupperFETVDR + I BIAS + tBODY(LOSS) = 20 ns (body conduction time) QN1, N2 = 17 nC (total MOSFET gate charge) [VDD x ( f SW ClowerFETVDD + I BIAS )] = (5.12 x (300 x 103 x 3.3 x 10-9 x 5.12 + 0.002)) + (5.5 x (300 x 103 x3.3 x10-9 x5.5 + 0.002)) = 77.13 mW RGATE = 1.5 (MOSFET gate input resistance) PCOUT = (IRMS)2 x ESR = (1.5 A)2 x 1.4 m = 3.15 mW VF = 0.84 V (MOSFET forward voltage) CIN = 3.3 nF (MOSFET gate input capacitance) [ ] 2 PN1, N2(CL) = D x RN1(ON) + (1 - D ) x RN2(ON) x I LOAD 2 = 0.003 x (15 A)2 = 675 mW PDCR ( LOSS ) = DCR x I LOAD = (0.15 x 0.0054 + 0.85 x 0.0054) x (15 A)2 = 1.215 W PBODY ( LOSS ) = PCIN = (IRMS)2 x ESR = (7.5 A)2 x 1 m = 56.25 mW PLOSS = PN1, N2 + PBODY (LOSS) + PSW + PDCR + PDR + PCOUT + PCIN = 1.215 W + 151.2 mW + 534.6 mW + 77.13 mW + 3.15 mW + 675 mW + 56.25 mW = 2.62 W t BODY ( LOSS ) x I LOAD x VF x 2 t SW = 20 ns x 300 x 103 x 15 A x 0.84 x 2 = 151.2 mW Rev. B | Page 29 of 40 ADP1872/ADP1873 Data Sheet EXTERNAL COMPONENT RECOMMENDATIONS The configurations listed in Table 8 are with fCROSS = 1/12 x fSW, fZERO = 1/4 x fCROSS, RRES = 100 k, RBOT = 15 k, RON = 5.4 m (BSC042N03MS G), VDD = 5 V, and a maximum load current of 14 A. The ADP1873 models listed in Table 8 are the PSM versions of the device. Table 8. External Component Values Marking Code SAP Model ADP1872ARMZ-0.3-R7/ ADP1873ARMZ-0.3-R7 ADP1872ARMZ-0.6-R7/ ADP1873ARMZ-0.6-R7 ADP1872ARMZ-1.0-R7/ ADP1873ARMZ-1.0-R7 ADP1872 LDT LDT LDT LDT LDT LDT LDT LDT LDT LDT LDT LDT LDT LDU LDU LDU LDU LDU LDU LDU LDU LDU LDU LDU LDU LDU LDU LDU LDV LDV LDV LDV LDV LDV LDV LDV LDV LDV LDV LDV LDV ADP1873 LDF LDF LDF LDF LDF LDF LDF LDF LDF LDF LDF LDF LDF LDK LDK LDK LDK LDK LDK LDK LDK LDK LDK LDK LDK LDK LDK LDK LDL LDL LDL LDL LDL LDL LDL LDL LDL LDL LDL LDL LDL VOUT (V) 0.8 1.2 1.8 2.5 3.3 5 7 1.2 1.8 2.5 3.3 5 7 0.8 1.2 1.8 2.5 1.2 1.8 2.5 3.3 5 1.2 1.8 2.5 3.3 5 7 0.8 1.2 1.8 2.5 1.2 1.8 2.5 3.3 5 1.2 1.8 2.5 3.3 VIN (V) 13 13 13 13 13 13 13 16.5 16.5 16.5 16.5 16.5 16.5 5.5 5.5 5.5 5.5 13 13 13 13 13 16.5 16.5 16.5 16.5 16.5 16.5 5.5 5.5 5.5 5.5 13 13 13 13 13 16.5 16.5 16.5 16.5 CIN (F) 5 x 22 2 5 x 222 4 x 222 4 x 222 5 x 222 4 x 222 4 x 222 4 x 222 3 x 222 3 x 222 3 x 222 3 x 222 3 x 222 5 x 222 5 x 222 5 x 222 5 x 222 3 x 222 5 x 10 9 5 x 109 5 x 109 5 x 109 3 x 109 4 x 109 4 x 109 4 x 109 4 x 109 4 x 109 5 x 222 5 x 222 3 x 222 3 x 222 3 x 109 4 x 109 4 x 109 5 x 109 4 x 109 3 x 109 3 x 109 4 x 109 4 x 109 Rev. B | Page 30 of 40 COUT (F) 5 x 560 3 4 x 5603 4 x 270 4 3 x 2704 2 x 330 5 3305 222 + (4 x 47 6) 4 x 5603 4 x 2704 4 x 2704 2 x 3305 2 x 150 7 222 + 4 x 476 4 x 5603 4 x 2704 3 x 2704 3 x 180 8 5 x 2704 3 x 3305 3 x 2704 2 x 2704 1507 4 x 2704 2 x 3305 3 x 2704 3305 4 x 476 3 x 476 4 x 2704 2 x 3305 3 x 1808 2704 3 x 3305 3 x 2704 2704 2704 3 x 476 4 x 2704 3 x 2704 3 x 1808 2704 L1 (H) 0.72 1.0 1.0 1.53 2.0 3.27 3.44 1.0 1.0 1.67 2.00 3.84 4.44 0.22 0.47 0.47 0.47 0.47 0.47 0.90 1.00 1.76 0.47 0.72 0.90 1.0 2.0 2.0 0.22 0.22 0.22 0.22 0.22 0.47 0.47 0.72 1.0 0.47 0.47 0.72 0.72 RC (k) 47 47 47 47 47 34 34 47 47 47 47 34 34 47 47 47 47 47 47 47 47 34 47 47 47 47 34 34 47 47 47 47 47 47 47 47 34 47 47 47 47 CCOMP (pF) 740 740 571 571 571 800 800 740 592 592 592 829 829 339 326 271 271 407 307 307 307 430 362 326 326 296 415 380 223 223 163 163 233 210 210 210 268 326 261 233 217 CPAR (pF) 74 74 57 57 57 80 80 74 59 59 59 83 83 34 33 27 27 41 31 31 31 43 36 33 33 30 41 38 22 22 16 16 23 21 21 21 27 33 26 23 22 RTOP (k) 5.0 15.0 30.0 47.5 67.5 110.0 160.0 15.0 30.0 47.5 67.5 110.0 160.0 5.0 15.0 30.0 47.5 15.0 30.0 47.5 67.5 110.0 15.0 30.0 47.5 67.5 110.0 160.0 5.0 15.0 30.0 47.5 15.0 30.0 47.5 67.5 110.0 15.0 30.0 47.5 67.5 Data Sheet ADP1872/ADP1873 Marking Code SAP Model ADP1872 LDV LDV VOUT (V) 5 7 ADP1873 LDL LDL VIN (V) 16.5 16.5 CIN (F) 3 x 109 3 x 109 COUT (F) 3 x 476 222 + 476 L1 (H) 1.0 1.0 RC (k) 34 34 CCOMP (pF) 268 228 CPAR (pF) 27 23 RTOP (k) 110.0 160.0 See the Inductor Selection section (See Table 9). 22 F Murata 25 V, X7R, 1210 GRM32ER71E226KE15L (3.2 mm x 2.5 mm x 2.5 mm). 3 560 F Panasonic (SP-series) 2 V, 7 m, 3.7 A EEFUE0D561LR (4.3 mm x 7.3 mm x 4.2 mm). 4 270 F Panasonic (SP-series) 4 V, 7 m, 3.7 A EEFUE0G271LR (4.3 mm x 7.3 mm x 4.2 mm). 5 330 F Panasonic (SP-series) 4 V, 12 m, 3.3 A EEFUE0G331R (4.3 mm x 7.3 mm x 4.2 mm). 6 47 F Murata 16 V, X5R, 1210 GRM32ER61C476KE15L (3.2 mm x 2.5 mm x 2.5 mm). 7 150 F Panasonic (SP-series) 6.3 V, 10 m, 3.5 A EEFUE0J151XR (4.3 mm x 7.3 mm x 4.2 mm). 8 180 F Panasonic (SP-series) 4 V, 10 m, 3.5 A EEFUE0G181XR (4.3 mm x 7.3 mm x 4.2 mm). 9 10 F TDK 25 V, X7R, 1210 C3225X7R1E106M. 1 2 Table 9. Recommended Inductors L (H) 0.12 0.22 0.47 0.72 0.9 1.2 1.0 1.4 2.0 0.8 DCR (m) 0.33 0.33 0.8 1.65 1.6 1.8 3.3 3.2 2.6 ISAT (A) 55 30 50 35 28 25 20 24 22 27.5 Dimension (mm) 10.2 x 7 10.2 x 7 14.2 x 12.8 10.5 x 10.2 13 x 12.8 10.5 x 10.2 10.5 x 10.2 14 x 12.8 13.2 x 12.8 Manufacturer Wurth Elektronik Wurth Elektronik Wurth Elektronik Wurth Elektronik Wurth Elektronic Wurth Elektronic Wurth Elektronic Wurth Elektronic Wurth Elektronic Sumida Model Number 744303012 744303022 744355147 744325072 744355090 744325120 7443552100 744318180 7443551200 CEP125U-0R8 Table 10. Recommended MOSFETs VGS = 4.5 V Upper-Side MOSFET (Q1/Q2) Lower-Side MOSFET (Q3/Q4) RON (m) 5.4 ID (A) 47 VDS (V) 30 CIN (nF) 3.2 QTOTAL (nC) 20 Package PG-TDSON8 Manufacturer Infineon Model Number BSC042N03MS G 10.2 6.0 9 5.4 53 19 14 47 30 30 30 30 1.6 10 35 25 20 PG-TDSON8 SO-8 SO-8 PG-TDSON8 Infineon Vishay International Rectifier Infineon BSC080N03MS G Si4842DY IRF7811 BSC042N03MS G 10.2 6.0 82 19 30 30 1.6 10 35 PG-TDSON8 SO-8 Infineon Vishay BSC080N03MS G Si4842DY 2.4 3.2 Rev. B | Page 31 of 40 ADP1872/ADP1873 Data Sheet LAYOUT CONSIDERATIONS Figure 82 shows the schematic of a typical ADP1872/ADP1873 used for a high power application. Blue traces denote high current pathways. VIN, PGND, and VOUT traces should be wide and possibly replicated, descending down into the multiple layers. Vias should populate, mainly around the positive and negative terminals of the input and output capacitors, alongside the source of Q1/Q2, the drain of Q3/Q4, and the inductor. The performance of a dc-to-dc converter depends highly on how the voltage and current paths are configured on the printed circuit board (PCB). Optimizing the placement of sensitive analog and power components are essential to minimize output ripple, maintain tight regulation specifications, and reduce PWM jitter and electromagnetic interference. LOW VOLTAGE INPUT VDD = 5.0V HIGH VOLTAGE INPUT VIN = 12V JP1 CF 57pF VOUT R1 30k C2 0.1F R2 15k C1 1F ADP1872/ ADP1873 BST 10 1 VIN 2 COMP/EN 3 FB DRVH 8 4 GND PGND 7 5 VDD DRVL 6 C12 100nF C3 22F Q1 C4 22F Q2 SW 9 1.0H Q3 C7 22F C6 22F C5 22F Q4 R5 100k C20 R6 270F 2 C13 1.5nF VOUT = 1.8V, 15A + C21 270F + C22 270F + C23 270F + MURATA: (HIGH VOLTAGE INPUT CAPACITORS) 22F, 25V, X7R, 1210 GRM32ER71E226KE15 L PANASONIC: (OUTPUT CAPACITORS) 270F (SP-SERIES) 4V, 7m EEFUE0G271LR INFINEON MOSFETs: BSC042N03MS G (LOWER-SIDE) BSC080N03MS G (UPPER-SIDE) WURTH INDUCTORS: 1H, 3.3m, 20A 7443552100 Figure 82. ADP1872/ADP1873 High Current Evaluation Board Schematic (Blue Traces Indicate High Current Paths) Rev. B | Page 32 of 40 08297-081 CC 571pF RC 47k Data Sheet ADP1872/ADP1873 SENSITIVE ANALOG COMPONENTS LOCATED FAR FROM THE NOISY POWER SECTION. SW SEPARATE ANALOG GROUND PLANE FOR THE ANALOG COMPONENTS (THAT IS, COMPENSATION AND FEEDBACK RESISTORS). OUTPUT CAPACITORS ARE MOUNTED ON THE RIGHTMOST AREA OF THE EVB, WRAPPING BACK AROUND TO THE MAIN POWER GROUND PLANE, WHERE IT MEETS WITH THE NEGATIVE TERMINALS OF THE INPUT CAPACITORS BYPASS POWER CAPACITOR (C1) FOR VREG BIAS DECOUPLING AND HIGH FREQUENCY CAPACITOR (C2) AS CLOSE AS POSSIBLE TO THE IC. 08297-082 INPUT CAPACITORS ARE MOUNTED CLOSE TO DRAIN OF Q1/Q2 AND SOURCE OF Q3/Q4. Figure 83. Overall Layout of the ADP1872 High Current Evaluation Board Rev. B | Page 33 of 40 Data Sheet 08297-083 ADP1872/ADP1873 Figure 84. Layer 2 of Evaluation Board Rev. B | Page 34 of 40 Data Sheet ADP1872/ADP1873 TOP RESISTOR FEEDBACK TAP 08297-084 VOUT SENSE TAP LINE EXTENDING BACK TO THE TOP RESISTOR IN THE FEEDBACK DIVIDER NETWORK (SEE FIGURE 82). THIS OVERLAPS WITH PGND SENSE TAP LINE EXTENDING BACK TO THE ANALOG PLANE (SEE FIGURE 86, LAYER 4 FOR PGND TAP). Figure 85. Layer 3 of Evaluation Board Rev. B | Page 35 of 40 ADP1872/ADP1873 Data Sheet BOTTOM RESISTOR TAP TO THE ANALOG GROUND PLANE 08297-085 PGND SENSE TAP FROM NEGATIVE TERMINALS OF OUTPUT BULK CAPACITORS. THIS TRACK PLACEMENT SHOULD BE DIRECTLY BELOW THE VOUT SENSE LINE FROM FIGURE 84. Figure 86. Layer 4 (Bottom Layer) of Evaluation Board Rev. B | Page 36 of 40 Data Sheet ADP1872/ADP1873 IC SECTION (LEFT SIDE OF EVALUATION BOARD) A dedicated plane for the analog ground plane (GND) should be separate from the main power ground plane (PGND). With the shortest path possible, connect the analog ground plane to the GND pin (Pin 4). This plane should only be on the top layer of the evaluation board. To avoid crosstalk interference, there should not be any other voltage or current pathway directly below this plane on Layer 2, Layer 3, or Layer 4. Connect the negative terminals of all sensitive analog components to the analog ground plane. Examples of such sensitive analog components include the resistor divider's bottom resistor, the high frequency bypass capacitor for biasing (0.1 F), and the compensation network. As shown in Figure 83, an appropriate configuration to localize large current transfer from the high voltage input (VIN) to the output (VOUT) and then back to the power ground is to put the VIN plane on the left, the output plane on the right, and the main power ground plane in between the two. Current transfers from the input capacitors to the output capacitors, through Q1/Q2, during the on state (see Figure 87). The direction of this current (yellow arrow) is maintained as Q1/Q2 turns off and Q3/Q4 turns on. When Q3/Q4 turns on, the current direction continues to be maintained (red arrow) as it circles from the bulk capacitor's power ground terminal to the output capacitors, through the Q3/Q4. Arranging the power planes in this manner minimizes the area in which changes in flux occur if the current through Q1/Q2 stops abruptly. Sudden changes in flux, usually at source terminals of Q1/Q2 and drain terminals of Q3/Q4, cause large dV/dts at the SW node. The SW node is near the top of the evaluation board. The SW node should use the least amount of area possible and be away from any sensitive analog circuitry and components because this is where most sudden changes in flux density occur. When possible, replicate this pad onto Layer 2 and Layer 3 for thermal relief and eliminate any other voltage and current pathways directly beneath the SW node plane. Populate the SW node plane with vias, mainly around the exposed pad of the inductor terminal and around the perimeter of the source of Q1/Q2 and the drain of Q3/Q4. The output voltage power plane (VOUT) is at the rightmost end of the evaluation board. This plane should be replicated, descending down to multiple layers with vias surrounding the inductor terminal and the positive terminals of the output bulk capacitors. Ensure that the negative terminals of the output capacitors are placed close to the main power ground (PGND), as previously mentioned. All of these points form a tight circle (component geometry permitting) that minimizes the area of flux change as the event switches between D and 1 - D. VIN PGND Figure 87. Primary Current Pathways During the On State of the Upper-Side MOSFET (Left Arrow) and the On State of the Lower-Side MOSFET (Right Arrow) DIFFERENTIAL SENSING Because the ADP1872/ADP1873 operate in valley currentmode control, a differential voltage reading is taken across the drain and source of the lower-side MOSFET. The drain of the lower-side MOSFET should be connected as close as possible to the SW pin (Pin 9) of the IC. Likewise, the source should be connected as close as possible to the PGND pin (Pin 7) of the IC. When possible, both of these track lines should be narrow and away from any other active device or voltage/current paths. SW PGND LAYER 1: SENSE LINE FOR SW (DRAIN OF LOWER MOSFET) LAYER 1: SENSE LINE FOR PGND (SOURCE OF LOWER MOSFET) 08297-087 POWER SECTION VOUT 08297-086 Mount a 1 F bypass capacitor directly across the VDD pin (Pin 5) and the PGND pin (Pin 7). In addition, a 0.1 F should be tied across the VDD pin (Pin 5) and the GND pin (Pin 4). SW Figure 88. Drain/Source Tracking Tapping of the Lower-Side MOSFET for CS Amp Differential Sensing (Yellow Sense Line on Layer 2) Differential sensing should also be applied between the outermost output capacitor to the feedback resistor divider (see Figure 85 and Figure 86). Connect the positive terminal of the output capacitor to the top resistor (RT). Connect the negative terminal of the output capacitor to the negative terminal of the bottom resistor, which connects to the analog ground plane as well. Both of these track lines, as previously mentioned, should be narrow and away from any other active device or voltage/ current paths. Rev. B | Page 37 of 40 ADP1872/ADP1873 Data Sheet TYPICAL APPLICATION CIRCUITS DUAL-INPUT, 300 kHz HIGH CURRENT APPLICATION CIRCUIT LOW VOLTAGE INPUT VDD = 5.0V HIGH VOLTAGE INPUT VIN = 12V JP1 CF 57pF VOUT ADP1872/ ADP1873 1 R1 30k R2 15k C2 0.1F BST 10 VIN C12 100nF Q1 COMP/EN FB DRVH 8 4 GND PGND 7 5 VDD DRVL 6 C1 1F 1.0H Q3 C7 22F C6 22F C5 22F Q2 SW 9 2 3 C4 22F C3 22F C20 R6 270F 2 C13 1.5nF Q4 VOUT = 1.8V, 15A + C21 270F + C22 270F + C23 270F + MURATA: (HIGH VOLTAGE INPUT CAPACITORS) 22F, 25V, X7R, 1210 GRM32ER71E226KE15 L PANASONIC: (OUTPUT CAPACITORS) 270F (SP-SERIES) 4V, 7m EEFUE0G271LR INFINEON MOSFETs: BSC042N03MS G (LOWER-SIDE) BSC080N03MS G (UPPER-SIDE) WURTH INDUCTORS: 1H, 3.3m, 20A 7443552100 R5 100k Figure 89. Application Circuit for 12 V Input, 1.8 V Output, 15 A, 300 kHz (Q2/Q4 No Connect). SINGLE-INPUT, 600 kHz APPLICATION CIRCUIT HIGH VOLTAGE INPUT VIN = 5.5V JP1 VOUT R1 47.5k C2 0.1F R2 15k C1 1F ADP1872/ ADP1873 BST 10 1 VIN 2 COMP/EN 3 FB DRVH 8 4 GND PGND 7 5 VDD DRVL 6 C12 100nF C3 22F Q1 C4 22F 0.47H R5 100k C7 22F Q2 SW 9 Q3 C6 22F C5 22F Q4 R6 2 C13 1.5nF VOUT = 2.5V, 15A C20 180F + C21 180F + C22 180F + MURATA: (HIGH VOLTAGE INPUT CAPACITORS) 22F, 25V, X7R, 1210 GRM32ER71E226KE15 L PANASONIC: (OUTPUT CAPACITORS) 180F (SP-SERIES) 4V, 10m EEFUE0G181XR INFINEON MOSFETs: BSC042N03MS G (LOWER-SIDE) BSC080N03MS G (UPPER-SIDE) WURTH INDUCTORS: 0.47H, 0.8m, 50A 744355147 Figure 90. Application Circuit for 5.5 V Input, 2.5 V Output, 15 A, 600 kHz (Q2/Q4 No Connect) Rev. B | Page 38 of 40 08297-089 CF 27pF CC 271pF RC 47k 08297-088 CC 571pF RC 47k Data Sheet ADP1872/ADP1873 DUAL-INPUT, 300 kHz HIGH CURRENT APPLICATION CIRCUIT LOW VOLTAGE INPUT VDD = 5V HIGH VOLTAGE INPUT VIN = 13V JP1 CF 80pF VOUT R1 30k R2 15k C2 0.1F ADP1872/ ADP1873 1 VIN 2 COMP/EN BST 10 3 FB DRVH 8 4 GND PGND 7 5 VDD DRVL 6 C12 100nF C3 22F Q1 C4 22F C5 22F C7 22F Q2 SW 9 0.8H Q3 C6 22F Q4 C1 1F C20 R6 270F 2 C13 1.5nF VOUT = 1.8V, 20A + C21 270F + C22 270F + C23 270F + MURATA: (HIGH VOLTAGE INPUT CAPACITORS) 22F, 25V, X7R, 1210 GRM32ER71E226KE15 L PANASONIC: (OUTPUT CAPACITORS) 270F (SP-SERIES) 4V, 7m EEFUE0G271LR INFINEON MOSFETs: BSC042N03MS G (LOWER-SIDE) BSC080N03MS G (UPPER-SIDE) WURTH INDUCTORS: 0.72H, 1.65m, 35A 744325072 Figure 91. Application Circuit for 13 V Input, 1.8 V Output, 20 A, 300 kHz (Q2/Q4 No Connect) Rev. B | Page 39 of 40 08297-090 CC 800pF RC 33.5k ADP1872/ADP1873 Data Sheet OUTLINE DIMENSIONS 3.10 3.00 2.90 10 3.10 3.00 2.90 5.15 4.90 4.65 6 1 5 PIN 1 IDENTIFIER 0.50 BSC 0.95 0.85 0.75 15 MAX 1.10 MAX 0.30 0.15 6 0 0.23 0.13 COMPLIANT TO JEDEC STANDARDS MO-187-BA 0.70 0.55 0.40 091709-A 0.15 0.05 COPLANARITY 0.10 Figure 92. 10-Lead Mini Small Outline Package [MSOP] (RM-10) Dimensions shown in millimeters ORDERING GUIDE Model1 ADP1872ARMZ-0.3-R7 ADP1872ARMZ-0.6-R7 ADP1872ARMZ-1.0-R7 ADP1872-0.3-EVALZ ADP1872-0.6-EVALZ ADP1872-1.0-EVALZ ADP1873ARMZ-0.3-R7 ADP1873ARMZ-0.6-R7 ADP1873ARMZ-1.0-R7 ADP1873-0.3-EVALZ ADP1873-0.6-EVALZ ADP1873-1.0-EVALZ 1 Temperature Range -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C Package Description 10-Lead Mini Small Outline Package [MSOP] 10-Lead Mini Small Outline Package [MSOP] 10-Lead Mini Small Outline Package [MSOP] Forced PWM, 300 kHz Evaluation Board Forced PWM, 600 kHz Evaluation Board Forced PWM, 1 MHz Evaluation Board 10-Lead Mini Small Outline Package [MSOP] 10-Lead Mini Small Outline Package [MSOP] 10-Lead Mini Small Outline Package [MSOP] Power Saving Mode, 300 kHz Evaluation Board Power Saving Mode, 600 kHz Evaluation Board Power Saving Mode, 1 MHz Evaluation Board Z = RoHS Compliant Part. (c)2009-2012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D08297-0-7/12(B) Rev. B | Page 40 of 40 Package Option RM-10 RM-10 RM-10 Branding LDT LDU LDV RM-10 RM-10 RM-10 LDF LDK LDL