Synchronous Current-Mode with
Constant On-Time, PWM Buck Controller
Data Sheet
ADP1872/ADP1873
Rev. B
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FEATURES
Power input voltage as low as 2.75 V to 20 V
Bias supply voltage range: 2.75 V to 5.5 V
Minimum output voltage: 0.6 V
0.6 V reference voltage with ±1.0% accuracy
Supports all N-channel MOSFET power stages
Available in 300 kHz, 600 KHz, and 1.0 MHz options
No current-sense resistor required
Power saving mode (PSM) for light loads (ADP1873 only)
Resistor-programmable current-sense gain
Thermal overload protection
Short-circuit protection
Precision enable input
Integrated bootstrap diode for high-side drive
140 µA shutdown supply current
Starts into a precharged load
Small, 10-lead MSOP package
APPLICATIONS
Telecom and networking systems
Mid to high end servers
Set-top boxes
DSP core power supplies
TYPICAL APPLICATIONS CIRCUIT
+
COMP/EN BST
FB DRVH
GND SW
VDD DRVL
PGND
VIN
C
C
C
VDD
C
VDD2
C
C2
R
C
R
TOP
R
BOT
V
OUT
V
DD
= 2.75V
TO 5.5V
Q1
Q2
R
RES
L
C
OUT
V
OUT
C
BST
LOAD
5A
C
IN
V
IN
= 2.75V TO 20V
ADP1872/
ADP1873
08297-001
Figure 1.
100
95
90
85
80
75
70
65
60
55
50
45
100 1k 10k 100k
EF FICIENCY ( %)
LOAD CURRENT ( mA)
V
DD
= 5.5V , V
IN
= 5.5V (PSM)
V
DD
= 5.5V , V
IN
= 16.5V (PSM)
V
DD
= 5.5V , V
IN
= 13.0V (PSM)
V
DD
= 5.5V , V
IN
= 5.5V
T
A
= 25° C
V
OUT
= 1.8V
f
SW
= 300kHz
WURTH INDUCTO R:
744325120, L = 1.2µH, DCR = 1.8mΩ
INFINEON FETs:
BSC042N03MS G (UPP E R/L OW E R)
08297-002
Figure 2. ADP1872 Efficiency vs. Load Current (VOUT = 1.8 V, 300 kHz)
GENERAL DESCRIPTION
The ADP1872/ADP1873 are versatile current-mode, synchronous
step-down controllers that provide superior transient response,
optimal stability, and current limit protection by using a constant
on-time, pseudo-fixed frequency with a programmable current-
sense gain, current-control scheme. In addition, these devices offer
optimum performance at low duty cycles by using valley current-
mode control architecture. This allows the ADP1872/ADP1873
to drive all N-channel power stages to regulate output voltages
as low as 0.6 V.
The ADP1873 is the power saving mode (PSM) version of the
device and is capable of pulse skipping to maintain output
regulation while achieving improved system efficiency at light
loads (see the Power Saving Mode (PSM) Version (ADP1873)
section for more information).
Available in three frequency options (300 kHz, 600 kHz, and
1.0 MHz, plus the PSM option), the ADP1872/ADP1873 are
well suited for a wide range of applications. These ICs not only
operate from a 2.75 V to 5.5 V bias supply, but can also accept a
power input as high as 20 V.
In addition, an internally fixed, soft start period is included to limit
input in-rush current from the input supply during startup and
to provide reverse current protection during soft start for a pre-
charged output. The low-side current-sense, current-gain scheme
and integration of a boost diode, along with the PSM/forced pulse-
width modulation (PWM) option, reduce the external part count
and improve efficiency.
The ADP1872/ADP1873 operate over the −40°C to +125°C
junction temperature range and are available in a 10-lead MSOP.
ADP1872/ADP1873 Data Sheet
Rev. B | Page 2 of 40
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Typical Applications Circuit ............................................................ 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Absolute Maximum Ratings ............................................................ 5
Thermal Resistance ...................................................................... 5
Boundary Condition .................................................................... 5
ESD Caution .................................................................................. 5
Pin Configuration and Function Descriptions ............................. 6
Typical Performance Characteristics ............................................. 7
ADP1872/ADP1873 Block Digram .............................................. 17
Theory of Operation ...................................................................... 18
Startup .......................................................................................... 18
Soft Start ...................................................................................... 18
Precision Enable Circuitry ........................................................ 18
Undervoltage Lockout ............................................................... 18
Thermal Shutdown ..................................................................... 18
Programming Resistor (RES) Detect Circuit .......................... 19
Valley Current-Limit Setting .................................................... 19
Hiccup Mode During Short Circuit ......................................... 20
Synchronous Rectifier ................................................................ 21
Power Saving Mode (PSM) Version (ADP1873) .................... 21
Timer Operation ........................................................................ 21
Pseudo-Fixed Frequency ........................................................... 22
Applications Information .............................................................. 23
Feedback Resistor Divider ........................................................ 23
Inductor Selection ...................................................................... 23
Output Ripple Voltage (VRR) .................................................. 23
Output Capacitor Selection ....................................................... 23
Compensation Network ............................................................ 24
Efficiency Consideration ........................................................... 25
Input Capacitor Selection .......................................................... 26
Thermal Considerations ............................................................ 27
Design Example .......................................................................... 27
External Component Recommendations .................................... 30
Layout Considerations ................................................................... 32
IC Section (Left Side of Evaluation Board) ............................. 37
Power Section ............................................................................. 37
Differential Sensing .................................................................... 37
Typical Application Circuits ......................................................... 38
Dual-Input, 300 kHz High Current Application Circuit ...... 38
Single-Input, 600 kHz Application Circuit ............................. 38
Dual-Input, 300 kHz High Current Application Circuit ...... 39
Outline Dimensions ....................................................................... 40
Ordering Guide .......................................................................... 40
REVISION HISTORY
7/12—Rev. A to Rev. B
Changed RON = 15 m/100 kΩ Valley Current Level Value from
7.5 to 3.87; Table 6 .......................................................................... 20
Changes to Ordering Guide .......................................................... 40
3/10—Rev. 0 to Rev. A
Changes to Figure 1 .......................................................................... 1
Changes to Table 1 ............................................................................ 3
Changes to Table 2 ............................................................................ 5
Changes to Figure 59 Caption and Figure 60 Caption .............. 16
Changes to Figure 64 ...................................................................... 17
Changes to Timer Operation Section .......................................... 22
Changes to Table 7 .......................................................................... 23
Changes to Inductor Section ......................................................... 28
Changes to Table 9 .......................................................................... 31
Changes to Figure 82 ...................................................................... 32
Changes to Figure 83 ...................................................................... 33
Changes to Figure 84 ...................................................................... 34
Changes to Figure 85 ...................................................................... 35
Changes to Figure 86 ...................................................................... 36
Changes to Differential Sensing Section and Figure 88 ............ 37
Changes to Figure 89 and Figure 90............................................. 38
Changes to Figure 91 ...................................................................... 39
Updated Outline Dimensions ....................................................... 40
10/09—Revision 0: Initial Version
Data Sheet ADP1872/ADP1873
Rev. B | Page 3 of 40
SPECIFICATIONS
All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC). VDD = 5 V,
BST − SW = 5 V, VIN = 13 V. The specifications are valid for TJ = −40°C to +125°C, unless otherwise specified.
Table 1.
Parameter Symbol Conditions Min Typ Max Unit
POWER SUPPLY CHARACTERISTICS
High Input Voltage Range VIN ADP1872ARMZ-0.3/ADP1873ARMZ-0.3 (300 kHz) 2.75 12 20 V
ADP1872ARMZ-0.6/ADP1873ARMZ-0.6 (600 kHz) 2.75 12 20 V
ADP1872ARMZ-1.0/ADP1873ARMZ-1.0 (1.0 MHz) 3.0 12 20 V
Low Input Voltage Range VDD CIN = 1 µF to PGND, CIN = 0.22 µF to GND
ADP1872ARMZ-0.3/ADP1873ARMZ-0.3 (300 kHz)
2.75
5
5.5
V
ADP1872ARMZ-0.6/ADP1873ARMZ-0.6 (600 kHz) 2.75 5 5.5 V
ADP1872ARMZ-1.0/ADP1873ARMZ-1.0 (1.0 MHz) 3.0 5 5.5 V
Quiescent Current IQ_DD + IQ_BST FB = 1.5 V, no switching 1.1 mA
Shutdown Current IDD, SD + IBST, SD COMP/EN < 285 mV 140 215 µA
Undervoltage Lockout UVLO Rising VDD (See Figure 34 for temperature variation) 2.65 V
UVLO Hysteresis Falling VDD from operational state 190 mV
SOFT START
Soft Start Period See Figure 57 3.0 ms
ERROR AMPLIFER
FB Regulation Voltage VFB TJ = 25°C 600 mV
TJ = −40°C to +85°C 595.5 600 605.4 mV
TJ = −40°C to +125°C 594.2 600 606.5 mV
Transconductance GM 300 515 730 µs
FB Input Leakage Current IFB, LEAK FB = 0.6 V, COMP/EN = released 1 50 nA
CURRENT-SENSE AMPLIFIER GAIN
Programming Resistor (RES)
Value from DRVL to PGND
RES = 47 kΩ ± 1% 2.7 3 3.3 V/V
RES = 22 kΩ ± 1% 5.5 6 6.5 V/V
RES = none 11 12 13 V/V
RES = 100 kΩ ± 1%
22
24
26
V/V
SWITCHING FREQUENCY Typical values measured at 50% time points with
0 nF at DRVH and DRVL; maximum values are
guaranteed by bench evaluation1
ADP1872ARMZ-0.3/
ADP1873ARMZ-0.3 (300 kHz)
300 kHz
On-Time VIN = 5 V, VOUT = 2 V, TJ = 25°C 1120 1200 1280 ns
Minimum On-Time VIN = 20 V 145 190 ns
Minimum Off-Time 84% duty cycle (maximum) 320 385 ns
ADP1872ARMZ-0.6/
ADP1873ARMZ-0.6 (600 kHz)
600 kHz
On-Time VIN = 5 V, VOUT = 2 V, TJ = 25°C 500 520 580 ns
Minimum On-Time VIN = 20 V, VOUT = 0.8 V 82 110 ns
Minimum Off-Time 65% duty cycle (maximum) 320 385 ns
ADP1872ARMZ-1.0/
ADP1873ARMZ-1.0 (1.0 MHz)
1.0 MHz
On-Time VIN = 5 V, VOUT = 2 V, TJ = 25°C 285 312 340 ns
Minimum On-Time VIN = 20 V 60 85 ns
Minimum Off-Time 45% duty cycle (maximum) 320 385 ns
ADP1872/ADP1873 Data Sheet
Rev. B | Page 4 of 40
Parameter Symbol Conditions Min Typ Max Unit
OUTPUT DRIVER CHARACTERISTICS
High-Side Driver
Output Source Resistance ISOURCE = 1.5 A, 100 ns, positive pulse (0 V to 5 V) 2 3.5 Ω
Output Sink Resistance ISINK = 1.5 A, 100 ns, negative pulse (5 V to 0 V) 0.8 2 Ω
Rise Time
2
t
r, DRVH
BST − SW = 4.4 V, C
IN
= 4.3 nF (see Figure 59)
25
ns
Fall Time2 tf, DRVH BST − SW = 4.4 V, CIN = 4.3 nF (see Figure 60) 11 ns
Low-Side Driver
Output Source Resistance ISOURCE = 1.5 A, 100 ns, positive pulse (0 V to 5 V) 1.7 3 Ω
Output Sink Resistance ISINK = 1.5 A, 100 ns, negative pulse (5 V to 0 V) 0.75 2 Ω
Rise Time2 tr, DRVL VDD = 5.0 V, CIN = 4.3 nF (see Figure 60) 18 ns
Fall Time2 tf, DRVL VDD = 5.0 V, CIN = 4.3 nF (see Figure 59) 16 ns
Propagation Delays
DRVL Fall to DRVH Rise2 ttpdh, DRVH BST − SW = 4.4 V (see Figure 59) 22 ns
DRVH Fall to DRVL Rise2 ttpdh, DRVL BST − SW = 4.4 V (see Figure 60) 24 ns
SW Leakage Current ISW, LEAK BST = 25 V, SW = 20 V, VDD = 5.5 V 110 µA
Integrated Rectifier
Channel Impedance ISINK = 10 mA 22 Ω
PRECISION ENABLE THRESHOLD
Logic High Level
VIN = 2.9 V to 20 V, VDD = 2.75 V to 5.5 V
235
285
330
mV
Enable Hysteresis VIN = 2.9 V to 20 V, VDD = 2.75 V to 5.5 V 35 mV
COMP VOLTAGE
COMP Clamp Low Voltage VCOMP (LOW) From disable state, release COMP/EN pin to enable
device (2.75 V ≤ VDD ≤ 5.5 V)
0.47 V
COMP Clamp High Voltage VCOMP (HIGH) (2.75 V ≤ VDD ≤ 5.5 V) 2.55 V
COMP Zero Current Threshold VCOMP_ZCT (2.75 V ≤ VDD ≤ 5.5 V) 1.15 V
THERMAL SHUTDOWN TTMSD
Thermal Shutdown Threshold Rising temperature 155 °C
Thermal Shutdown Hysteresis 15 °C
Hiccup Current Limit Timing 6 ms
1 The maximum specified values are with the closed loop measured at 10% to 90% time points (see Figure 59 and Figure 60), CGATE = 4.3 nF and upper- and lower-side
MOSFETs being Infineon BSC042N03MS G.
2 Not automatic test equipment (ATE) tested.
Data Sheet ADP1872/ADP1873
Rev. B | Page 5 of 40
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter Rating
VDD to GND −0.3 V to +6 V
VIN to PGND −0.3 V to +28 V
FB, COMP/EN to GND −0.3 V to (VDD + 0.3 V)
DRVL to PGND −0.3 V to (VDD + 0.3 V)
SW to PGND −0.3 V to +28 V
SW to PGND −2 V pulse (20 ns)
BST to SW −0.6 V to (VDD + 0.3 V)
BST to PGND
−0.3 V to +28 V
DRVH to SW −0.3 V to VDD
PGND to GND ±0.3 V
Operating Junction Temperature
Range
−40°C to +125°C
Storage Temperature Range −65°C to +150°C
Soldering Conditions JEDEC J-STD-020
Maximum Soldering Lead
Temperature (10 sec)
300°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Absolute maximum ratings apply individually only, not in
combination. Unless otherwise specified, all other voltages are
referenced to PGND.
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Table 3. Thermal Resistance
Package Type θJA Unit
θ
JA
(10-Lead MSOP)
2-Layer Board 213.1 °C/W
4-Layer Board 171.7 °C/W
BOUNDARY CONDITION
In determining the values given in Table 2 and Table 3, natural
convection was used to transfer heat to a 4-layer evaluation board.
ESD CAUTION
ADP1872/ADP1873 Data Sheet
Rev. B | Page 6 of 40
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
VIN
1
COMP/EN
2
FB
3
GND
4
VDD
5
BST
10
SW
9
DRVH
8
PGND
7
DRVL
6
ADP1872
TOP VIEW
(Not t o Scale)
08297-003
Figure 3. Pin Configuration
Table 4. Pin Function Descriptions
Pin No. Mnemonic Description
1 VIN High Input Voltage. Connect VIN to the drain of the upper-side MOSFET.
2 COMP/EN Output of the Internal Error Amplifier/IC Enable. When this pin functions as EN, applying 0 V to this pin disables the IC.
3 FB Noninverting Input of the Internal Error Amplifier. This is the node where the feedback resistor is connected.
4 GND Analog Ground Reference Pin of the IC. All sensitive analog components should be connected to this ground
plane (see the Layout Considerations Section).
5 VDD Bias Voltage Supply for the ADP1872/ADP1873 Controller (Includes the Output Gate Drivers). A bypass capacitor
of 1 µF directly from this pin to PGND and a 0.1 µF across VDD and GND are recommended.
6 DRVL Drive Output for the External Lower Side, N-Channel MOSFET. This pin also serves as the current-sense gain
setting pin (see Figure 68).
7 PGND Power GND. Ground for the lower side gate driver and lower side, N-channel MOSFET.
8 DRVH Drive Output for the External Upper Side, N-Channel MOSFET.
9 SW Switch Node Connection.
10 BST Bootstrap for the Upper Side MOSFET Gate Drive Circuitry. An internal boot rectifier (diode) is connected
between VDD and BST. A capacitor from BST to SW is required. An external Schottky diode can also be
connected between VDD and BST for increased gate drive capability.
Data Sheet ADP1872/ADP1873
Rev. B | Page 7 of 40
TYPICAL PERFORMANCE CHARACTERISTICS
100
30
35
40
45
50
55
60
65
70
75
80
85
90
95
100 100k10k1k
EFFICIENCY (%)
LOAD CURRENT (mA)
WURTH IND: 744355147, L = 0.47µH, DCR: 0.80mΩ
INFINEON FETs: BSC042N03MS G (UPPER/LOWER)
TA = 25°C
V
DD
= 5.5V, V
IN
= 13V (PSM) V
DD
= 5.5V, V
IN
= 5.5V
V
DD
= 3.6V, V
IN
= 5.5V
V
DD
= 5.5V, V
IN
= 13V
V
DD
= 3.6V, V
IN
= 13V
V
DD
= 5.5V, V
IN
= 16.5V
V
DD
= 3.6V, V
IN
= 16.5V
V
DD
= 5.5V,
V
IN
= 16.5V (PSM)
V
DD
= 5.5V,
V
IN
= 5.5V
(PSM)
08297-004
Figure 4. Efficiency—300 kHz, VOUT = 0.8 V
100
25
30
35
40
45
50
55
60
65
70
75
80
85
90
95
100 100k10k1k
EFFICIENCY (%)
LOAD CURRENT (mA)
WURTH IND: 744325120, L = 1.2µH, DCR: 1.8mΩ
INFINEON FETS: BSC042N03MS G (UPPER/LOWER)
TA = 25°C
V
DD
= 5.5V, V
IN
= 5.5V (PSM)
V
DD
= 5.5V, V
IN
= 16.5V (PSM)
V
DD
= 5.5V, V
IN
= 5.5V
V
DD
= 5.5V, V
IN
= 16.5V
V
DD
= 5.5V, V
IN
= 13V (PSM)
V
DD
= 3.6V, V
IN
= 3.6V
V
DD
= 5.5V, V
IN
= 13V
V
DD
= 3.6V, V
IN
= 5.5V
08297-005
Figure 5. Efficiency—300 kHz, VOUT = 1.8 V
100
30
35
40
45
50
55
60
65
70
75
80
85
90
95
100 100k10k1k
EFFICIENCY (%)
LOAD CURRENT (mA)
WURTH IND: 7443551200, L = 2µH, DCR: 2.6mΩ
INFINEON FETs: BSC042N03MS G (UPPER/LOWER)
TA = 25°C
13V
IN
16.5V
IN
V
DD
= 2.7V
13V
IN
16.5V
IN
V
DD
= 3.6V
13V
IN
16.5V
IN
V
DD
= 5.5V
V
DD
= 5.5V, V
IN
= 16.5V (PSM)
V
DD
= 5.5V,
V
IN
= 16V
(PSM)
08297-006
Figure 6. Efficiency—300 kHz, VOUT = 7 V
100
15
25
35
20
30
40
45
50
55
60
65
70
75
80
85
90
95
100 100k10k1k
EFFICIENCY (%)
LOAD CURRENT (mA)
WURTH IND: 744355147, L = 0.47µH, DCR: 0.80mΩ
INFINEON FETs: BSC042N03MS G (UPPER/LOWER)
TA = 25°C
V
DD
= 5.5V, V
IN
= 13V (PSM)
V
DD
= 5.5V, V
IN
= 5.5V (PSM)
V
DD
= 5.5V, V
IN
= 5.5V
V
DD
= 3.6V, V
IN
= 5.5V
V
DD
= 5.5V, V
IN
= 13V
V
DD
= 5.5V, V
IN
= 16.5V
V
DD
= 5.5V,
V
IN
= 16.5V
(PSM)
08297-007
Figure 7. Efficiency—600 kHz, VOUT = 0.8 V
100
25
30
35
40
45
50
55
60
65
70
75
80
85
90
95
100 100k10k1k
EFFICIENCY (%)
LOAD CURRENT (mA)
WURTH IND: 744325120, L = 1.2µH, DCR: 1.8mΩ
INFINEON FETS: BSC042N03MS G (UPPER/LOWER)
TA = 25°C
V
DD
= 5.5V
,
= V
IN
= 5.5(PSM) V
DD
= 5.5V, V
IN
= 5.5V
V
DD
= 5.5V, V
IN
= 16.5V
V
DD
= 5.5V, V
IN
= 16.5V (PSM)
V
DD
= 5.5V, V
IN
= 13V (PSM)
V
DD
= 3.6V, V
IN
= 5.5V
V
DD
= 5.5V, V
IN
= 13V
08297-008
Figure 8. Efficiency—600 kHz, VOUT = 1.8 V
100
30
35
40
45
50
55
60
65
70
75
80
85
90
95
100 100k10k1k
EFFICIENCY (%)
LOAD CURRENT (mA)
WURTH IND: 7443551200, L = 2µH, DCR: 2.6mΩ
INFINEON FETs: BSC042N03MS G (UPPER/LOWER)
TA = 25°C
V
DD
= 5.5V,
V
IN
= 13V (PSM)
V
DD
= 3.6V,V
IN
= 13V
V
DD
= 5.5V, V
IN
= 16.5V (PSM)
V
DD
= 5.5V, V
IN
= 13V
V
DD
= 3.6V, V
IN
= 16.5V
V
DD
= 5.5V, V
IN
= 16.5V
08297-009
Figure 9. Efficiency—600 kHz, VOUT = 5 V
ADP1872/ADP1873 Data Sheet
Rev. B | Page 8 of 40
100
20
30
25
35
40
45
50
55
60
65
70
75
80
85
90
95
100 100k10k1k
EFFICIENCY (%)
LOAD CURRENT (mA)
WURTH IND: 744303012, L = 0.12µH, DCR: 0.33mΩ
INFINEON FETs: BSC042N03MS G (UPPER/LOWER)
TA = 25°C
V
DD
= 5.5V, V
IN
= 5.5V
V
DD
= 5.5V,
V
IN
= 5.5V (PSM)
V
DD
= 5.5V, V
IN
= 16.5V
V
DD
= 3.6V, V
IN
= 5.5V
V
DD
= 3.6V, V
IN
= 3.6V
V
DD
= 5.5V,
V
IN
= 16.5V
(PSM)
V
DD
= 5.5V, V
IN
= 13V (PSM)
V
DD
= 5.5V, V
IN
= 13V
08297-010
Figure 10. Efficiency—1.0 MHz, VOUT = 0.8 V
100
20
30
25
35
40
45
50
55
60
65
70
75
80
85
90
95
100 100k10k1k
EFFICIENCY (%)
LOAD CURRENT (mA)
WURTH IND: 744303022, L = 0.22µH, DCR: 0.33mΩ
INFINEON FETs: BSC042N03MS G (UPPER/LOWER)
TA = 25°C
V
DD
= 5.5V,
V
IN
= 16.5V (PSM)
V
DD
= 5.5V, V
IN
= 5V (PSM)
V
DD
= 5.5V, V
IN
= 16.5V
V
DD
= 3.6V, V
IN
= 13V
V
DD
= 3.6V, V
IN
= 16.5V
V
DD
= 5.5V,
V
IN
= 13V
(PSM)
V
DD
= 5.5V, V
IN
= 13V
V
DD
= 5.5V,
V
IN
= 5V
08297-011
Figure 11. Efficiency—1.0 MHz, VOUT = 1.8 V
100
20
30
25
35
40
45
50
55
60
65
70
75
80
85
90
95
100 10k1k
EFFICIENCY (%)
LOAD CURRENT (mA)
WURTH IND: 744325072, L = 0.72µH, DCR: 1.65mΩ
INFINEON FETs: BSC042N03MS G (UPPER/LOWER)
TA = 25°C
V
DD
= 5.5V, V
IN
= 5V (PSM) V
DD
= 5.5V, V
IN
= 16.5V (PSM)
V
DD
= 5V, V
IN
= 16.5V
V
DD
= 5V,
V
IN
= 13V
08297-012
Figure 12. Efficiency—1.0 MHz, VOUT = 4 V
0.8030
0.8025
0.8020
0.8015
0.8010
0.8005
0.8000
0.7995
0.7990
0.7985
0.7980
0.7975
0.7970
0.7965
0.7960
0 2000 4000 6000 8000 10,000 12,000 14,000 16,000
OUTPUT VOLTAGE (V)
LOAD CURRENT (mA)
+125°C
+25°C
–40°C
V
IN
= 5.5V
+125°C
+25°C
–40°C
V
IN
= 13V
+125°C
+25°C
–40°C
V
IN
= 16.5V
08297-013
Figure 13. Output Voltage Accuracy—300 kHz, VOUT = 0.8 V
1.821
1.816
1.811
1.806
1.801
1.796
1.791
1.786
0 1500 3000 4500 6000 7500 9000 10,500 12,000 13,500 15,000
OUTPUT VOLTAGE (V)
LOAD CURRENT (mA)
+125°C
+25°C
–40°C
VIN = 5.5V
+125°C
+25°C
–40°C
VIN = 13V
+125°C
+25°C
–40°C
VIN = 16.5V
08297-014
Figure 14. Output Voltage Accuracy—300 kHz, VOUT = 1.8 V
7.000
6.955
6.960
6.965
6.970
6.975
6.980
6.985
6.990
6.995
0 1000 2000 3000 4000 5000 6000 7000 8000 9000 10,000
OUTPUT VOLTAGE (V)
LOAD CURRENT (mA)
+125°C
+25°C
–40°C
VDD = 3.6V, VIN = 13V
VDD = 3.6V, VIN = 16.5V
VDD = 5.5V, VIN = 13V
VDD = 5.5V, VIN = 16.5V
08297-015
Figure 15. Output Voltage Accuracy—300 kHz, VOUT = 7 V
Data Sheet ADP1872/ADP1873
Rev. B | Page 9 of 40
1.801
1.789
1.790
1.791
1.792
1.793
1.794
1.795
1.796
1.797
1.798
1.799
1.800
0 1500 3000 4500 6000 7500 9000 10,500 12,000 13,500 15,000
OUTPUT VOLTAGE (V)
LO AD CURRENT (mA)
+125°C
+25°C
–40°C
VIN = 5.5V +125°C
+25°C
–40°C
VIN = 13V +125°C
+25°C
–40°C
VIN = 16.5V
08297-016
Figure 16. Output Voltage Accuracy—600 kHz, VOUT = 1.8 V
5.044
5.042
5.040
5.038
5.036
5.034
5.032
5.030
5.028
5.026
5.024
5.022
5.020 0 1000 2000 3000 4000 5000 6000 7000 8000 9000 10,000
OUTPUT VOLTAGE (V)
LO AD CURRENT (mA)
+125°C
+25°C
–40°C
V
DD
= 5. 5V, V
IN
= 13V
V
DD
= 5. 5V, V
IN
= 16. 5V
08297-017
Figure 17. Output Voltage Accuracy—600 kHz, VOUT = 5 V
0.807
0.806
0.805
0.804
0.803
0.802
0.801
0.800
0.799
0.798 0 2000 4000 6000 8000 10,000 12,000 14,000 16,000
OUTPUT VOLTAGE (V)
LO AD CURRENT (mA)
+125°C
+25°C
–40°C
V
IN
= 5. 5V
+125°C
+25°C
–40°C
V
IN
= 13V +125°C
+25°C
–40°C
V
IN
= 16. 5V
08297-018
Figure 18. Output Voltage Accuracy—1 MHz, VOUT = 0.8 V
1.810
1.809
1.808
1.807
1.806
1.805
1.804
1.803
1.802
1.801
1.800
1.799
1.798
1.797
0 1500 3000 4500 6000 7500 9000 10,500 12,000 13,500 15,000
OUTPUT VOLTAGE (V)
LO AD CURRENT (mA)
+125°C
+25°C
–40°C
V
IN
= 5.5V +125°C
+25°C
–40°C
V
IN
= 13V +125°C
+25°C
–40°C
V
IN
= 16.5V
08297-019
Figure 19. Output Voltage Accuracy—1.0 MHz, VOUT = 1.8 V
4.050
4.045
4.040
4.035
4.030
4.025
4.020
4.015
4.010
4.005
4.000
3.995
3.990
3.985
3.980
3.975
3.970 0 800 1600 2400 3200 4000 4800 5600 6400 7200 8000
OUTPUT VOLTAGE (V)
LOAD CURRENT ( mA)
+125°C
+25°C
–40°C
V
IN
= 13V +125°C
+25°C
–40°C
V
IN
= 16.5V
08297-020
Figure 20. Output Voltage Accuracy—1.0 MHz, VOUT = 4 V
0.6030
0.5975
0.5980
0.5985
0.5990
0.5995
0.6000
0.6005
0.6010
0.6015
0.6020
0.6025
–40.0 –7.5 122.590.057.525.0
FEE DBACK V OLTAGE (V)
TEM P ERATURE (°C)
V
DD
= 2. 7V, V
IN
= 2.7V , 3. 6V
V
DD
= 3. 6V, V
IN
= 3. 6 V TO 16 .5V
V
DD
= 5. 5V, V
IN
= 5.5V , 13V , 16. 5V
08297-021
Figure 21. Feedback Voltage vs. Temperature
ADP1872/ADP1873 Data Sheet
Rev. B | Page 10 of 40
335
325
315
305
295
285
275
265
255
245
235
225
10.8 11.0 11.2 11.4 11.6 11.8 12.0 12.2 12.4 12.6 12.8 13.0 13.2
FREQUENCY ( kHz )
V
IN
(V)
+125°C
+25°C
–40°C
NO LOADV
DD
= 5.5V
V
DD
= 3.6V
08297-022
Figure 22. Switching Frequency vs. High Input Voltage,
300 kHz, ±10% of 12 V
650
600
550
500
450
400
10.8 11.0 11.2 11.4 11.6 11.8 12.0 12.2 12.4 12.6 12.8 13.0 13.2
FREQUENCY ( kHz )
V
IN
(V)
08297-023
NO L O AD
+125°C
+25°C
–40°C
V
DD
= 5.5V
V
DD
= 3.6V
Figure 23. Switching Frequency vs. High Input Voltage,
600 kHz, VOUT = 1.8 V, ±10% of 12 V
1000
550
600
650
700
750
800
850
900
950
10.8 11.0 11.2 11.4 11.6 11.8 12.0 12.2 12.4 12.6 12.8 13.0 13.2
FREQUENCY ( kHz )
V
IN
(V)
+125°C
+25°C
–40°C
V
DD
= 5.5V
V
DD
= 3.6V
08297-024
NO LOAD
Figure 24. Switching Frequency vs. High Input Voltage,
1.0 MHz, ±10% of 12 V
340
325
310
295
280
265
250
235
220
205
190 0 16,00014,00012,00010,0008000600040002000
FREQUENCY ( kHz )
LO AD CURRENT (mA)
V
IN
= 5. 5V
V
IN
= 13V
V
IN
= 16.5V
+125°C
+25°C
–40°C
08297-025
Figure 25. Frequency vs. Load Current, 300 kHz, VOUT = 0.8 V
360
350
340
330
320
310
300
290
280
270
260 020,00016,000 18,00014,00012,00010,0008000600040002000
FREQUENCY ( kHz )
LO AD CURRENT (mA)
VIN = 5.5V
VIN = 13V
VIN = 16.5V
+125°C
+25°C
–40°C
08297-026
Figure 26. Frequency vs. Load Current, 300 kHz, VOUT = 1.8 V
358
290
294
298
302
306
310
314
318
322
326
330
334
338
342
346
350
354
096006400 7200 8000 8800560048004000320024001600800
FREQUENCY ( kHz )
LO AD CURRENT (mA)
VIN = 13V
VIN = 16.5V +125°C
+25°C
–40°C
08297-027
Figure 27. Frequency vs. Load Current, 300 kHz, VOUT = 7 V
Data Sheet ADP1872/ADP1873
Rev. B | Page 11 of 40
700
190
220
250
280
310
340
370
400
430
460
490
520
550
580
610
640
670
0 16,00014,00012,00010,0008000600040002000
FREQUENCY ( kHz )
LOAD CURRENT ( mA)
V
IN
= 5.5V
V
IN
= 16.5V
V
IN
= 13V +125°C
+25°C
–40°C
08297-028
Figure 28. Frequency vs. Load Current, 600 kHz, VOUT = 0.8 V
815
495
515
535
555
575
595
615
635
655
675
695
715
735
755
775
795
020,00016,000 18,00014,00012,00010,0008000600040002000
FREQUENCY ( kHz )
LOAD CURRENT ( mA)
V
IN
= 5.5V
V
IN
= 16.5V
V
IN
= 13V
+125°C
+25°C
–40°C
08297-029
Figure 29. Frequency vs. Load Current, 600 kHz, VOUT = 1.8 V
705
698
691
684
677
670
663
656
649
642
635
628
621
614
607
600
096008800800072006400560048004000320024001600800
FREQUENCY ( kHz )
LO AD CURRENT (mA)
V
IN
= 13V
V
IN
= 16.5V +125°C
+25°C
–40°C
08297-030
Figure 30. Frequency vs. Load Current, 600 kHz, VOUT =5 V
1300
1125
1150
1075
1000
925
850
775
700
625
550
475
400 0 16,00014,00012,00010,0008000600040002000
FREQUENCY ( kHz )
LOAD CURRENT ( mA)
V
IN
= 5.5V
V
IN
= 16.5V
V
IN
= 13V +125°C
+25°C
–40°C
08297-031
Figure 31. Frequency vs. Load Current, VOUT = 1.0 MHz, 0.8 V
550
625
700
775
850
925
1000
1075
1150
1225
1300
1375
1450
020,00016,000 18,00014,00012,00010,0008000600040002000
FREQUENCY ( kHz )
LOAD CURRENT ( mA)
V
IN
= 5.5V
V
IN
= 16.5V
V
IN
= 13V
+125°C
+25°C
–40°C
MIN-OFF TIME
ENCROACHMENT
08297-032
Figure 32. Frequency vs. Load Current, 1.0 MHz, VOUT = 1.8 V
1000
1450
1400
1350
1300
1250
1200
1150
1100
1050
0 8000800 1600 2400 3200 4000 4800 5600 6400 7200
FREQUENCY ( kHz )
LO AD CURRENT (mA)
V
IN
= 16.5V
V
IN
= 13V +125°C
+25°C
–40°C
08297-033
Figure 33. Frequency vs. Load Current, 1.0 MHz, VOUT = 4 V
ADP1872/ADP1873 Data Sheet
Rev. B | Page 12 of 40
2.649
2.658
2.657
2.656
2.655
2.654
2.653
2.652
2.651
2.650
–40 120100806040200–20
UVLO (V)
TE M P ERATURE (°C)
08297-034
Figure 34. UVLO vs. Temperature
40
45
50
55
60
65
70
75
80
85
90
95
100
300 400 500 600 700 800 900 1000
MAXI M UM DUTY CY CLE (%)
FREQ UE NCY (kHz )
V
DD
= 2. 7V
V
DD
= 5. 5V
V
DD
= 3. 6V +125°C
+25°C
–40°C
08297-035
Figure 35. Maximum Duty Cycle vs. Frequency
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
3.6 4.8 6.0 7.2 8.4 9.6 10.8 12.0 13.2 14.4 15.6
MAXI M UM DUTY CY CLE (%)
V
IN
(V)
V
DD
= 5. 5V
V
DD
= 3. 6V +125°C
+25°C
–40°C
08297-036
Figure 36. Maximum Duty Cycle vs. High Voltage Input (VIN)
180
680
630
580
530
480
430
380
330
280
230
–40 120100806040200–20
MINIMUM OFF-TIME (ns)
TEM P ERATURE (°C)
V
DD
= 2. 7V
V
DD
= 5. 5V
V
DD
= 3. 6V
08297-037
Figure 37. Minimum Off-Time vs. Temperature
180
680
630
580
530
480
430
380
330
280
230
2.7 5.55.14.74.33.93.53.1
MINIMUM OFF-TIME (ns)
V
DD
(V)
+125°C
+25°C
–40°C
08297-038
Figure 38. Minimum Off-Time vs. VDD (Low Input Voltage)
80
800
720
640
560
480
400
320
240
160
300 400 500 600 700 800 900 1000
RECTIFIER DRO P (mV)
FREQ UE NCY (kHz )
V
DD
= 2.7V
V
DD
= 5.5V
V
DD
= 3.6V +125°C
+25°C
–40°C
08297-039
Figure 39. Internal Rectifier Drop vs. Frequency
Data Sheet ADP1872/ADP1873
Rev. B | Page 13 of 40
80
1280
720
640
560
480
1040
1120
1200
960
880
800
400
320
240
160
2.73.13.53.94.34.75.15.5
RECTIFIER DROP (mV)
V
DD
(V)
V
IN
= 5.5V
V
IN
= 16.5V
V
IN
= 13V
1MHz
300kHz
08297-040
T
A
= 25°C
Figure 40. Internal Boost Rectifier Drop vs. VDD (Low Input Voltage)
over VIN Variation
80
720
640
560
480
400
320
240
160
2.73.13.53.94.34.75.15.5
RECTIFIER DROP (mV)
V
DD
(V)
1MHz
300kHz +125°C
+25°C
–40°C
08297-041
Figure 41. Internal Boost Rectifier Drop vs. VDD
8
80
64
72
56
48
40
32
24
16
2.73.13.53.94.34.75.15.5
BODY DIODE CONDUCTION TIME (ns)
V
DD
(V)
1MHz
300kHz +125°C
+25°C
–40°C
08297-042
Figure 42. Lower Side MOSFET Body Conduction Time vs. VDD (Low Input Voltage)
CH1 50mV
BW
CH2 5A Ω
CH3 10V
BW
CH4 5V
M400ns A CH2 3.90A
T 35.8%
1
2
3
4
OUTPUT VOLTAGE
INDUCTOR CURRENT
SW NODE
LOW SIDE
08297-043
Figure 43. Power Saving Mode (PSM) Operational Waveform, 100 mA
CH1 50mV
BW
CH2 5A Ω
CH3 10V
BW
CH4 5V
M4.0µs A CH2 3.90A
T 35.8%
1
2
3
4
OUTPUT VOLTAGE
INDUCTOR CURRENT
SW NODE
LOW SIDE
08297-044
Figure 44. PSM Waveform at Light Load, 500 mA
CH1 5A Ω
CH3 10V CH4 100mV
BW
M400ns A CH3 2.20V
T 30.6%
1
3
4
OUTPUT VOLTAGE
INDUCTOR CURRENT
SW NODE
08297-045
Figure 45. CCM Operation at Heavy Load, 18 A
(See Figure 91 for Application Circuit)
ADP1872/ADP1873 Data Sheet
Rev. B | Page 14 of 40
CH1 10A Ω CH2 200mV BW
CH3 20V CH4 5V M2ms A CH1 3. 40A
T 75.6%
1
2
3
4
OUTPUT VOLTAGE
20A ST E P
SW NODE
LOW SIDE
08297-046
Figure 46. Load Transient Step—PSM Enabled, 20 A
(See Figure 91 Application Circuit)
CH1 10A Ω CH2 200mV
BW
CH3 20V CH4 5V M20µs A CH1 3.40A
T 30.6%
1
2
3
4
OUTPUT VOLTAGE
20A POSIT I VE ST EP
SW NODE
LOW SIDE
08297-047
Figure 47. Positive Step During Heavy Load Transient Behavior—PSM Enabled,
20 A, VOUT = 1.8 V (See Figure 91 Application Circuit)
CH1 10A Ω CH2 200mV
BW
CH3 20V CH4 5V M20µs A CH1 3.40A
T 48.2%
1
2
3
4
OUTPUT VOLTAGE
20A NEG ATIV E S TEP
SW NODE
LOW SIDE
08297-048
Figure 48. Negative Step During Heavy Load Transient Behavior—PSM Enabled,
20 A (See Figure 91 Application Circuit)
CH1 10A Ω CH2 5V
CH3 20V CH4 200mV
BW
M2ms A CH1 6. 20A
T 15.6%
1
2
3
4
OUTPUT VOLTAGE
20A ST E P
SW NODE
LOW SIDE
08297-049
Figure 49. Load Transient Step—Forced PWM at Light Load, 20 A
(See Figure 91 Application Circuit)
CH1 10A Ω CH2 5V
CH3 20V CH4 200mV BW
M20µs A CH1 6.20A
T 43.8%
1
2
3
4
OUTPUT VOLTAGE
20A POSIT I VE ST EP
SW NODE
LOW SIDE
08297-050
Figure 50. Positive Step During Heavy Load Transient Behavior—Forced PWM
at Light Load, 20 A, VOUT = 1.8 V (See Figure 91 Application Circuit)
CH1 10A Ω CH2 200mV
BW
CH3 20V CH4 5V M10µs A CH1 5.60A
T 23.8%
1
2
3
4
OUTPUT VOLTAGE
20A NEG ATIV E S TEP
SW NODE
LOW
SIDE
08297-051
Figure 51. Negative Step During Heavy Load Transient Behavior—Forced PWM
at Light Load, 20 A (See Figure 91 Application Circuit)
Data Sheet ADP1872/ADP1873
Rev. B | Page 15 of 40
CH1 2V
BW
CH2 5A Ω
CH3 10V CH4 5V M4ms A CH1 920mV
T 49.4%
1
2
3
4
OUTPUT VOLTAGE
INDUCTOR CURRE NT
SW NODE
LOW SIDE
08297-052
Figure 52. Output Short-Circuit Behavior Leading to Hiccup Mode
CH1 5V
BW
CH2 10A Ω
CH3 10V CH4 5V M10µs A CH2 8.20A
T 36.2%
1
2
3
4
OUTPUT VOLTAGE
INDUCTOR CURRE NT
SW NODE
LOW SIDE
08297-053
Figure 53. Magnified Waveform During Hiccup Mode
CH1 2V
BW
CH2 5A Ω
CH3 10V CH4 5V M2ms A CH1 720mV
T 32.8%
1
2
3
4
OUTPUT VOLTAGE
INDUCTOR CURRE NT
SW NODE
LOW SIDE
08297-054
Figure 54. Start-Up Behavior at Heavy Load, 18 A, 300 kHz
(See Figure 91 Application Circuit)
CH1 2V
BW
CH2 5A Ω
CH3 10V CH4 5V M4ms A CH1 720mV
T 41.6%
1
2
3
4
OUTPUT VOLTAGE
INDUCTOR CURRE NT
SW NODE
LOW SIDE
08297-055
Figure 55. Power-Down Waveform During Heavy Load
CH1 50mV BWCH2 5A Ω
CH3 10V BWCH4 5V M2µs A CH2 3.90A
T 35.8%
1
2
3
4
OUTPUT VOLTAGE
INDUCTOR CURRE NT
SW NODE
LOW SIDE
08297-056
Figure 56. Output Voltage Ripple Waveform During PSM Operation
at Light Load, 2 A
CH1 1V BWCH2 5A Ω
CH3 10V BWCH4 2V M1ms A CH1 1.56V
T 63.2%
1
2
3
4
OUTPUT VOLTAGE
INDUCTOR CURRE NT
SW NODE
LOW SIDE
08297-057
Figure 57. Soft Start and RES Detect Waveform
ADP1872/ADP1873 Data Sheet
Rev. B | Page 16 of 40
2
CH2 5V
CH3 5V
MATH 2V 40ns CH4 2V M40ns A CH2 4.20V
T 29.0%
3
M
4
HIG H S IDE
HS MI NUS
SW
SW NODE
LOW SIDE
08297-058
T
A
= 25°C
Figure 58. Output Drivers and SW Node Waveforms
2
CH2 5V
CH3 5V
MATH 2V 40ns CH4 2V M40ns A CH2 4.20V
T 29.0%
3
M
4
HI GH S IDE
HS MINUS
SW
SW NODE
LOW SIDE 16ns (
t
f
, DRV L
)
25ns (
t
r
, DRV H
)
22ns (
t
pdh
, DRVH
)
08297-059
T
A
= 25°C
Figure 59. Upper Side Driver Rising and Lower Side Falling Edge Waveforms
(CGATE = 4.3 nF (Upper/Lower Side MOSFET),
QTOTAL = 27 nC (VGS = 4.4 V (Q1), VGS = 5 V (Q3))
2
CH2 5V
CH3 5V
MATH 2V 20ns CH4 2V M20ns A CH2 4.20V
T 39.2%
3
M
4
HIG H S IDE
HS MI NUS
SW SW NODE
LOW SIDE
18ns (
t
r
, DRVL
)
24ns (
t
pdh
, DRVL
)
11ns (
t
f
, DRVH
)
08297-060
T
A
= 25°C
Figure 60. Upper Side Driver Falling and Lower Side Rising Edge Waveforms
(CGATE = 4.3 nF (Upper/Lower Side MOSFET),
QTOTAL = 27 nC (VGS = 4.4 V (Q1), VGS = 5 V (Q3))
570
550
530
510
490
470
450
430
–40 –20 120100806040200
TRANSCONDUCTANCE ( µ S)
TE M P ERATURE (°C)
V
DD
= 5. 5V
V
DD
= 3. 6V
V
DD
= 2. 7V
08297-061
Figure 61. Transconductance (GM) vs. Temperature
680
330
380
430
480
530
580
630
2.7 3.0 5.44.8 5.14.54.23.93.63.3
TRANSCONDUCTANCE ( µ S)
V
DD
(V)
+125°C
+25°C
–40°C
08297-062
Figure 62. Transconductance (GM) vs. VDD
1.30
1.25
1.20
1.15
1.10
1.05
1.00
0.95
0.90
0.85
0.80
0.75
0.702.7 5.55.14.74.3
–40°C
+25°C
+125°C
3.93.53.1
QUI ESCENT CURRENT (mA)
V
DD
(V)
08297-163
Figure 63. Quiescent Current vs. VDD (VIN = 13 V)
Data Sheet ADP1872/ADP1873
Rev. B | Page 17 of 40
ADP1872/ADP1873 BLOCK DIGRAM
TO ENABL E
ALL BLOCKS
COMP/EN
VIN
PRECISI ON ENABLE
BLOCK
t
ON
STATE
MACHINE DRIVERS
VDD
VDD
FILTER
PGND
BST
DRVH
SW
DRVL
PFM
REF_ZERO
GND
SS
COMP
ERROR
AMP
SS_REF
0.6V
LOWER
COMP
CLAMP
CS G AIN
PROGRAMMING
V
REG
REF_ZERO CS GAI N S E T
CS
AMP
PWM
ADC
I
REV
COMP
VDD
FB
BIAS
BLOCK
I
SS
C
SS
300kΩ
8kΩ
800kΩ
ADP1872/
ADP1873
08297-063
Figure 64. ADP1872/ADP1873 Block Diagram
ADP1872/ADP1873 Data Sheet
Rev. B | Page 18 of 40
THEORY OF OPERATION
The ADP1872/ADP1873 are versatile current-mode, synchronous
step-down controllers that provide superior transient response,
optimal stability, and current limit protection by using a constant
on-time, pseudo-fixed frequency with a programmable current-
sense gain, current-control scheme. In addition, these devices offer
optimum performance at low duty cycles by using valley current-
mode control architecture. This allows the ADP1872/
ADP1873 to drive all N-channel power stages to regulate output
voltages as low as 0.6 V.
STARTUP
The ADP1872/ADP1873 have an input low voltage pin (VDD) for
biasing and supplying power for the integrated MOSFET drivers. A
bypass capacitor should be located directly across the VDD (Pin 5)
and PGND (Pin 7) pins. Included in the power-up sequence is
the biasing of the current-sense amplifier, the current-sense gain
circuit (see the Programming Resistor (RES) Detect Circuit
section), the soft start circuit, and the error amplifier.
The current-sense blocks provide valley current information
(see the Programming Resistor (RES) Detect Circuit section)
and are a variable of the compensation equation for loop stability
(see the Compensation Network section). The valley current
information is extracted by forcing 0.4 V across the DRVL output
and the PGND pin, which generates a current depending on the
resistor across DRVL and PGND in a process performed by the
RES detect circuit. The current through the resistor is used to set
the current-sense amplifier gain. This process takes approximately
800 µs, after which the drive signal pulses appear at the DRVL
and DRVH pins synchronously and the output voltage begins to
rise in a controlled manner through the soft start sequence.
The rise time of the output voltage is determined by the soft start
and error amplifier blocks (see the Soft Start section). At the
beginning of a soft start, the error amplifier charges the external
compensation capacitor, causing the COMP/EN pin to rise above the
enable threshold of 285 mV, thus enabling the ADP1872/ADP1873.
SOFT START
The ADP1872/ADP1873 have digital soft start circuitry, which
involves a counter that initiates an incremental increase in current,
by 1 µA, via a current source on every cycle through a fixed internal
capacitor. The output tracks the ramping voltage by producing
PWM output pulses to the upper side MOSFET. The purpose is to
limit the in-rush current from the high voltage input supply (VIN)
to the output (VOUT).
PRECISION ENABLE CIRCUITRY
The ADP1872/ADP1873 employ precision enable circuitr y. The
enable threshold is 285 mV typical with 35 mV of hysteresis.
The devices are enabled when the COMP/EN pin is released,
allowing the error amplifier output to rise above the enable
threshold (see Figure 65). Grounding this pin disables the
ADP1872/ADP1873, reducing the supply current of the devices
to approximately 140 µA. For more information, see Figure 66.
0.6V
285mV
SS
VDD
FB
COMP/EN
PRECISION
ENABLE
ERROR
AMPLIFIER
TO ENABL E
ALL BLOCKS
CCCC2
RC
ADP1872/ADP1873
08297-064
Figure 65. Release COMP/EN Pin to Enable the ADP1872/ADP1873
COMP/EN
>2.4V
2.4V
1.0V
500mV
285mV
0V
HICCUP MODE INITIALIZED
MAXIMUM CURRE NT (UP P E R CLAMP )
ZE RO CURRENT
USABLE RANG E ONLY AFT ER SOFT START
PERI OD I F CONTUNUOUS CO NDUCT IO N
MODE O F OPERATI O N IS SELECTED.
LOWE R CLAMP
PRECISI ON ENABLE THRESHOL D
35mV HYSTERESIS
08297-065
Figure 66. COMP/EN Voltage Range
UNDERVOLTAGE LOCKOUT
The undervoltage lockout (UVLO) feature prevents the part
from operating both the upper side and lower side MOSFETs
at extremely low or undefined input voltage (VDD) ranges.
Operation at an undefined bias voltage may result in the incorrect
propagation of signals to the high-side power switches. This, in
turn, results in invalid output behavior that can cause damage
to the output devices, ultimately destroying the device tied at
the output. The UVLO level has been set at 2.65 V (nominal).
THERMAL SHUTDOWN
The thermal shutdown is a self-protection feature to prevent the IC
from damage due to a very high operating junction temperature.
If the junction temperature of the device exceeds 155°C, the
part enters the thermal shutdown state. In this state, the device
shuts off both the upper side and lower side MOSFETs and
disables the entire controller immediately, thus reducing the
power consumption of the IC. The part resumes operation after
the junction temperature of the part cools to less than 140°C.
Data Sheet ADP1872/ADP1873
Rev. B | Page 19 of 40
PROGRAMMING RESISTOR (RES) DETECT CIRCUIT
Upon startup, one of the first blocks to become active is the RES
detect circuit. This block powers up before soft start begins. It
forces a 0.4 V reference value at the DRVL output (see Figure 67)
and is programmed to identify four possible resistor values: 47 kΩ,
22 kΩ, open, and 100 kΩ.
The RES detect circuit digitizes the value of the resistor at the
DRVL pin (Pin 6). An internal ADC outputs a 2-bit digital code
that is used to program four separate gain configurations in the
current-sense amplifier (see Figure 68). Each configuration
corresponds to a current-sense gain (ACS) of 3 V/V, 6 V/V, 12 V/V,
24 V/V, respectively (see Table 5 and Table 6). This variable is used
for the valley current-limit setting, which sets up the appropriate
current-sense gain for a given application and sets the compensation
necessary to achieve loop stability (see the Valley Current-Limit
Setting and Compensation Network sections).
DRVH
DRVL
Q1
SW
Q2
R
RES
ADP1872
CS GAI N
PROGRAMMING
08297-066
Figure 67. Programming Resistor Location
SW
PGND
CS GAIN SET
CS
AMP
ADC
DRVL
RES
0.4V
08297-067
Figure 68. RES Detect Circuit for Current-Sense Gain Programming
Table 5. Current-Sense Gain Programming
Resistor ACS (V/V)
47 kΩ 3
22 kΩ 6
Open 12
100 kΩ 24
VALLEY CURRENT-LIMIT SETTING
The architecture of the ADP1872/ADP1873 is based on valley
current-mode control. The current limit is determined by three
components: the RON of the lower side MOSFET, the error amplifier
output voltage swing (COMP), and the current-sense gain. The
COMP range is internally fixed at 1.4 V. The current-sense gain
is programmable via an external resistor at the DRVL pin (see
the Programming Resistor (RES) Detect Circuit section). The
RON of the lower side MOSFET can vary over temperature and
usually has a positive TC (meaning that it increases with
temperature); therefore, it is recommended to program the
current-sense gain resistor based on the rated RON of the
MOSFET at 125°C.
Because the ADP1872/ADP1873 are based on valley current
control, the relationship between ICLIM and ILOAD is
2
1I
LOADCLIM
K
II
where:
ICLIM is the desired valley current limit.
ILOAD is the current load.
KI is the ratio between the inductor ripple current and the
desired average load current (see Figure 10). Establishing KI
helps to determine the inductor value (see the Inductor
Selection section), but in most cases, KI = 0.33.
LO AD CURRENT
VALL E Y CURRENT L I M I T
RIPP L E CURRENT = I
LOAD
3
0
8297-068
Figure 69. Valley Current Limit to Average Current Relation
When the desired valley current limit (ICLIM) has been determined,
the current-sense gain can be calculated by
ONCS
CLIM RA
I
V4.1
where:
ACS is the current-sense gain multiplier (see Table 5 and Table 6).
RON is the channel impedance of the lower side MOSFET.
Although the ADP1872/ADP1873 have only four discrete current-
sense gain settings for a given RON variable, Table 6 and Figure 70
outline several available options for the valley current setpoint
based on various RON values.
ADP1872/ADP1873 Data Sheet
Rev. B | Page 20 of 40
Table 6. Valley Current Limit Program1
RON
(mΩ)
Valley Current Level
47 kΩ 22 kΩ Open 100 kΩ
ACS = 3 V/V ACS = 6 V/V ACS = 12 V/V ACS = 24 V/V
1.5 38.9
2 29.2
2.5 23.3
3 39.0 19.5
3.5 33.4 16.7
4.5 26.0 13
5 23.4 11.7
5.5 21.25 10.6
10 23.3 11.7 5.83
15 31.0 15.5 7.75 3.87
18 26.0 13.0 6.5 3.25
1 Refer to Figure 70 for more information and a graphical representation.
1234567891011121314151617181920
VALLEY CURRENT LIMIT (A)
RON (mΩ)
39
37
35
33
31
29
27
25
23
21
19
17
15
13
11
9
7
5
3
RES = 47kΩ
ACS = 3V/V
RES = 22kΩ
ACS = 6V/V
RES = NO RES
ACS = 12V/V
RES = 100kΩ
ACS = 24V/V
08297-069
Figure 70. Valley Current-Limit Value vs. RON of the Lower Side MOSFET
for Each Programming Resistor (RES)
The valley current limit is programmed as outlined in Table 6
and Figure 70. The inductor chosen must be rated to handle the
peak current, which is equal to the valley current from Table 6
plus the peak-to-peak inductor ripple current (see the Inductor
Selection section). In addition, the peak current value must be
used to compute the worst-case power dissipation in the MOSFETs
(see Figure 71).
INDUCTOR
CURRENT
VALLEY CURRENT LIMIT
THRESHOLD (SET FOR 25A)
∆I = 33%
OF 30A
COMP
OUTPUT
SWING
COMP
OUTPUT
2.4V
1V0A
35A
30A
32.25A
37A
49
A
39.5A
∆I = 45%
OF 32.25A
∆I = 65%
OF 37A
MAXIMUM DC LOAD
CURRENT
08297-070
Figure 71. Valley Current-Limit Threshold in Relation to Inductor Ripple Current
HICCUP MODE DURING SHORT CIRCUIT
A current-limit violation occurs when the current across the
source and drain of the lower side MOSFET exceeds the current-
limit setpoint. When 32 current-limit violations are detected,
the controller enters idle mode and turns off the MOSFETs for
6 ms, allowing the converter to cool down. Then, the controller
re-establishes soft start and begins to cause the output to ramp
up again (see Figure 72). While the output ramps up, COMP is
monitored to determine if the violation is still present. If it is still
present, the idle event occurs again, followed by the full-chip
power-down sequence. This cycle continues until the violation
no longer exists. If the violation disappears, the converter is
allowed to switch normally, maintaining regulation.
HS
CLIM
ZERO
CURRENT
REPEATED CURRENT LIMIT
VIOLATION DETECTED
A PREDETERMINED NUMBER
OF PULSES IS COUNTED TO
ALLOW THE CONVERTER
TO COOL DOWN
SOFT START IS
REINITIALIZED T
O
MONITOR IF THE
VIOLATION
STILL EXISTS
08297-071
Figure 72. Idle Mode Entry Sequence Due to Current-Limit Violations
Data Sheet ADP1872/ADP1873
Rev. B | Page 21 of 40
SYNCHRONOUS RECTIFIER
The ADP1872/ADP1873 employ an internal lower side MOSFET
driver to drive the external upper side and lower side MOSFETs.
The synchronous rectifier not only improves overall conduction
efficiency but also ensures proper charging to the bootstrap
capacitor located at the upper side driver input. This is beneficial
during startup to provide sufficient drive signal to the external
upper side MOSFET and attain fast turn-on response, which is
essential for minimizing switching losses. The integrated upper
and lower side MOSFET drivers operate in complementary
fashion with built-in anticross conduction circuitry to prevent
unwanted shoot-through current that may potentially damage the
MOSFETs or reduce efficiency as a result of excessive power loss.
POWER SAVING MODE (PSM) VERSION (ADP1873)
The power saving mode version of the ADP1872 is the ADP1873.
The ADP1873 operates in the discontinuous conduction mode
(DCM) and pulse skips at light load to midload currents. It
outputs pulses as necessary to maintain output regulation. Unlike
the continuous conduction mode (CCM), DCM operation
prevents negative current, thus allowing improved system
efficiency at light loads. Current in the reverse direction through
this pathway, however, results in power dissipation and therefore
a decrease in efficiency.
HS
HS AND LS ARE OFF
OR IN IDLE MODE
LS
0A
I
LOAD
AS THE I NDUCT O R
CURRENT APP ROACHES
ZERO CURRENT, T HE STAT E
MACHINE TURNS O FF T HE
LOWER SIDE MOSFET.
t
ON
t
OFF
08297-072
Figure 73. Discontinuous Mode of Operation (DCM)
To minimize the chance of negative inductor current buildup,
an on-board, zero-cross comparator turns off all upper side
and lower side switching activities when the inductor current
approaches the zero current line, causing the system to enter
idle mode, where the upper side and lower side MOSFETs are
turned off. To ensure idle mode entry, a 10 mV offset, connected
in series at the SW node, is implemented (see Figure 74).
10mV
ZERO-CROSS
COMPARATOR
Q2
LS
SW I
Q2
08297-073
Figure 74. Zero-Cross Comparator with 10 mV of Offset
As soon as the forward current through the lower side MOSFET
decreases to a level where
10 mV = IQ2 × RON(Q2)
the zero-cross comparator (or IREV comparator) emits a signal to
turn off the lower side MOSFET. From this point, the slope of the
inductor current ramping down becomes steeper (see Figure 75)
as the body diode of the lower side MOSFET begins to conduct
current and continues conducting current until the remaining
energy stored in the inductor has been depleted.
HS AND LS
IN IDLE MODE
10mV = R
ON
× I
LOAD
ZERO-CRO SS COM P ARATOR
DETE CTS 10mV OFFSET AND
TURNS OFF L S
SW
LS
0A
I
LOAD
tON
ANOTHER
tON
EDGE IS
TRI GG ERE D WHEN V
OUT
FALLS BELOW REGULATION
08297-074
Figure 75. 10 mV Offset to Ensure Prevention of Negative Inductor Current
The system remains in idle mode until the output voltage drops
below regulation. A PWM pulse is then produced, turning on the
upper side MOSFET to maintain system regulation. The ADP1873
does not have an internal clock; therefore, it switches purely as a
hysteretic controller, as described in this section.
TIMER OPERATION
The ADP1872/ADP1873 employ a constant on-time architecture,
which provides a variety of benefits, including improved load
and line transient response when compared with a constant
(fixed) frequency current-mode control loop of comparable
loop design. The constant on-time timer, or tON timer, senses
the high input voltage (VIN) and the output voltage (VOUT) using
SW waveform information to produce an adjustable one-shot
PWM pulse that varies the on-time of the upper side MOSFET in
response to dynamic changes in input voltage, output voltage, and
load current conditions to maintain regulation. It then generates
an on-time (tON) pulse that is inversely proportional to VIN.
VI
N
V
Kt OUT
ON
where K is a constant that is trimmed using an RC timer product
for the 300 kHz, 600 kHz, and 1.0 MHz frequency options.
ADP1872/ADP1873 Data Sheet
Rev. B | Page 22 of 40
C
R(TRIMMED)
VDD
t
ON
VIN
I
SW
INFORMATION
08297-075
Figure 76. Constant On-Time Timer
The constant on-time (tON) is not strictly constant because it varies
with VIN and VOUT. However, this variation occurs in such a
way as to keep the switching frequency virtually independent
of VIN and VOUT.
The tON timer uses a feedforward technique, applied to the constant
on-time control loop, making it pseudo-fixed frequency to a first
order. Second-order effects, such as dc losses in the external power
MOSFETs (see the Efficiency Consideration section), cause some
variation in frequency vs. load current and line voltage. These
effects are shown in Figure 22 to Figure 33. The variations in
frequency are much reduced compared with the variations
generated when the feedforward technique is not used.
The feedforward technique establishes the following relationship:
fSW = 1/K
where fSW is the controller switching frequency (300 kHz,
600 kHz, and 1.0 MHz).
The tON timer senses VIN and VOUT to minimize frequency variation
with VIN and VOUT as previously explained. This provides a
pseudo-fixed frequency, see the Pseudo-Fixed Frequency section
for additional information. To allow headroom for VIN/VOUT
sensing, the following two equations must be adhered to. For
typical applications where VDD is 5 V, these equations are not
relevant; however, for lower VDD, care may be required.
VDD ≥ VIN/8 + 1.5
VDD ≥ VOUT/4
PSEUDO-FIXED FREQUENCY
The ADP1872/ADP1873 employ a constant on-time control
scheme. During steady state operation, the switching frequency
stays relatively constant, or pseudo-fixed. This is due to the one-
shot tON timer that produces a high-side PWM pulse with a fixed
duration, given that external conditions such as input voltage,
output voltage, and load current are also at steady state. During
load transients, the frequency momentarily changes for the
duration of the transient event so that the output comes back
within regulation quicker than if the frequency were fixed or if
it were to remain unchanged. After the transient event is complete,
the frequency returns to a pseudo-fixed value to a first-order.
To illustrate this feature more clearly, this section describes
one such load transient event—a positive load step—in detail.
During load transient events, the high-side driver output pulse
width stays relatively consistent from cycle to cycle; however,
the off-time (DRVL on-time) dynamically adjusts according to
the instantaneous changes in the external conditions mentioned.
When a positive load step occurs, the error amplifier (out of
phase of the output, VOUT) produces new voltage information
at its output (COMP). In addition, the current-sense amplifier
senses new inductor current information during this positive
load transient event. The error amplifier’s output voltage
reaction is compared to the new inductor current information
that sets the start of the next switching cycle. Because current
information is produced from valley current sensing, it is sensed
at the down ramp of the inductor current, whereas the voltage
loop information is sensed through the counter action upswing
of the error amplifier’s output (COMP).
The result is a convergence of these two signals (see Figure 77),
which allows an instantaneous increase in switching frequency
during the positive load transient event. In summary, a positive
load step causes VOUT to transient down, which causes COMP to
transient up and therefore shortens the off time. This resulting
increase in frequency during a positive load transient helps to
quickly bring VOUT back up in value and within the regulation
window.
Similarly, a negative load step causes the off time to lengthen in
response to VOUT rising. This effectively increases the inductor
demagnetizing phase, helping to bring VOUT to within regulation.
In this case, the switching frequency decreases, or experiences a
foldback, to help facilitate output voltage recovery.
Because the ADP1872/ADP1873 has the ability to respond
rapidly to sudden changes in load demand, the recovery period
in which the output voltage settles back to its original steady
state operating point is much quicker than it would be for a
fixed-frequency equivalent. Therefore, using a pseudo-fixed
frequency, results in significantly better load transient
performance than using a fixed frequency.
VALLEY
TRIP POINTS
LO AD C URRE NT
DEMAND
ERRO R AMP
OUTPUT
PWM OUTPUT
f
SW
>
f
SW
CS AMP
OUTPUT
08297-076
Figure 77. Load Transient Response Operation
Data Sheet ADP1872/ADP1873
Rev. B | Page 23 of 40
APPLICATIONS INFORMATION
FEEDBACK RESISTOR DIVIDER
The required resistor divider network can be determine for a
given VOUT value because the internal band gap reference (VREF)
is fixed at 0.6 V. Selecting values for RT and RB determines the
minimum output load current of the converter. Therefore, for a
given value of RB, the RT value can be determined by
V6.0
V)6.0(
−
×= OUT
B
T
V
RR
INDUCTOR SELECTION
The inductor value is inversely proportional to the inductor
ripple current. The peak-to-peak ripple current is given by
3
LOAD
LOAD
IL
I
IKI ≈×=∆
where KI is typically 0.33.
The equation for the inductor value is given by
VIN
V
fI
VVIN
L
OUT
SW
L
OUT
×
×∆
−
=)(
where:
VIN is the high voltage input.
VOUT is the desired output voltage.
fSW is the controller switching frequency (300 kHz, 600 kHz,
and 1.0 MHz).
When selecting the inductor, choose an inductor saturation rating
that is above the peak current level and then calculate the
inductor current ripple (see the Valley Current-Limit Setting
section and Figure 78).
52
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
6 8 10 12 14 16 18 20 22 24 26 28 30
PEAK INDUCTOR CURRENT (A)
VAL LEY CURRE NT L IMIT ( A)
ΔI = 50%
ΔI = 40%
ΔI = 33%
08297-077
Figure 78. Peak Current vs. Valley Current Threshold for
33%, 40%, and 50% of Inductor Ripple Current
Table 7. Recommended Inductors
L
(µH)
DCR
(mΩ)
ISAT
(A)
Dimensions
(mm) Manufacturer Model No.
0.12 0.33 55 10.2 × 7 Würth Elektronic 744303012
0.22 0.33 30 10.2 × 7 Würth Elektronic 744303022
0.47 0.8 50 14.2 × 12.8 Würth Elektronic 744355147
0.72 1.65 35 10.5 × 10.2 Würth Elektronic 744325072
0.9 1.6 28 13 × 12.8 Würth Elektronic 744355090
1.2 1.8 25 10.5 × 10.2 Würth Elektronic 744325120
1.0 3.3 20 10.5 × 10.2 Würth Elektronic 7443552100
1.4 3.2 24 14 × 12.8 Würth Elektronic 744318180
2.0 2.6 22 13.2 × 12.8 Würth Elektronic 7443551200
0.8 27.5 Sumida CEP125U-0R8
OUTPUT RIPPLE VOLTAGE (ΔVRR)
The output ripple voltage is the ac component of the dc output
voltage during steady state. For a ripple error of 1.0%, the output
capacitor value needed to achieve this tolerance can be determined
using the following equation. (Note that an accuracy of 1.0% is
only possible during steady state conditions, not during load
transients.)
ΔVRR = (0.01) × VOUT
OUTPUT CAPACITOR SELECTION
The primary objective of the output capacitor is to facilitate
the reduction of the output voltage ripple; however, the output
capacitor also assists in the output voltage recovery during load
transient events. For a given load current step, the output voltage
ripple generated during this step event is inversely proportional
to the value chosen for the output capacitor. The speed at which
the output voltage settles during this recovery period depends
on where the crossover frequency (loop bandwidth) is set. This
crossover frequency is determined by the output capacitor, the
equivalent series resistance (ESR) of the capacitor, and the
compensation network.
To calculate the small signal voltage ripple (output ripple
voltage) at the steady state operating point, use the following
equation:
[ ]
×∆−∆××
×∆= )(8
1
ESRIV
f
IC
LRIPPLE
SW
L
OUT
where ESR is the equivalent series resistance of the output
capacitors.
To calculate the output load step, use the following equation:
))((
2ESRIVf
I
C
LOADDROOPSW
LOAD
OUT ×∆−∆×
∆
×=
where ΔVDROOP is the amount that VOUT is allowed to deviate for
a given positive load current step (ΔILOAD).
ADP1872/ADP1873 Data Sheet
Rev. B | Page 24 of 40
Ceramic capacitors are known to have low ESR. However, the
trade-off of using X5R technology is that up to 80% of its capaci-
tance may be lost due to derating because the voltage applied
across the capacitor is increased (see Figure 79). Although X7R
series capacitors can also be used, the available selection is
limited to only up to 22 µF.
20
10
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100 0 5 10 15 20 25
30
CAPACI TANCE CHARG E ( %)
DC VOLTAGE (V
DC
)
X7R (50V )
X5R (25V )
X5R (16V )
10µF TDK 25V, X7R, 1210 C3225X 7R1E 106M
22µF M URATA 25V, X7R, 1210 GRM32E R71E 226KE 15L
47µF M URATA 16V, X5R, 1210 GRM32E R61C476KE 15L
08297-078
Figure 79. Capacitance vs. DC Voltage Characteristics for Ceramic Capacitors
Electrolytic capacitors satisfy the bulk capacitance requirements
for most high current applications. Because the ESR of electrolytic
capacitors is much higher than that of ceramic capacitors, when
using electrolytic capacitors, several MLCCs should be mounted
in parallel to reduce the overall series resistance.
COMPENSATION NETWORK
Due to its current-mode architecture, the ADP1872/ADP1873
require Type II compensation. To determine the component
values needed for compensation (resistance and capacitance
values), it is necessary to examine the converter’s overall loop
gain (H) at the unity gain frequency (fSW/10) when H = 1 V/V.
FILT
COMP
REF
OUT
CS
MZZ
V
V
GGH ××××== V/V1
Examining each variable at high frequency enables the unity
gain transfer function to be simplified to provide expressions
for the RCOMP and CCOMP component values.
Output Filter Impedance (ZFILT)
Examining the filter’s transfer function at high frequencies
simplifies to
OUT
FILTER
sC
Z1
=
at the crossover frequency (s = 2πfCROSS).
Error Amplifier Output Impedance (ZCOMP)
Assuming CC2 is significantly smaller than CCOMP, CC2 can be
omitted from the output impedance equation of the error amplifier.
The transfer function simplifies to
CROSS
ZERO
CROSSCOMP
COMP
f
ffR
Z)( +
=
and
SWCROSS
ff ×= 12
1
where fZERO, the zero frequency, is set to be 1/4th of the crossover
frequency for the ADP1872.
Error Amplifier Gain (GM)
The error amplifier gain (transconductance) is
GM = 500 µA/V
Current-Sense Loop Gain (GCS)
The current-sense loop gain is
ONCS
CS
RA
G×
=1
(A/V)
where:
ACS (V/V) is programmable for 3 V/V, 6 V/V, 12 V / V, and 24 V/V
(see the Programming Resistor (RES) Detect Circuit and Valley
Current-Limit Setting sections).
RON is the channel impedance of the lower side MOSFET.
Crossover Frequency
The crossover frequency is the frequency at which the overall
loop (system) gain is 0 dB (H = 1 V/V). It is recommended for
current-mode converters, such as the ADP1872, that the user
set the crossover frequency between 1/10th and 1/15th of the
switching frequency.
SWCROSS
ff 12
1
=
The relationship between CCOMP and fZERO (zero frequency) is
COMPCOMP
ZERO
CR
f××
=π2
1
The zero frequency is set to 1/4th of the crossover frequency.
Combining all of the above parameters results in
REF
OUT
CS
M
OUT
CROSS
ZERO
CROSS
CROSS
COMP
V
V
GG
Cf
ff
f
R××
+
=π2
ZERO
COMP
COMP
fR
C×××
=π2
1
Data Sheet ADP1872/ADP1873
Rev. B | Page 25 of 40
EFFICIENCY CONSIDERATION
One of the important criteria to consider in constructing a dc-to-dc
converter is efficiency. By definition, efficiency is the ratio of the
output power to the input power. For high power applications at
load currents up to 20 A, the following are important MOSFET
parameters that aid in the selection process:
VGS (TH): the MOSFET support voltage applied between the
gate and the source.
RDS (ON): the MOSFET on resistance during channel
conduction.
QG: the total gate charge
CN1: the input capacitance of the upper side switch
CN2: the input capacitance of the lower side switch
The following are the losses experienced through the external
component during normal switching operation:
Channel conduction loss (both the MOSFETs)
MOSFET driver loss
MOSFET switching loss
Body diode conduction loss (lower side MOSFET)
Inductor loss (copper and core loss)
Channel Conduction Loss
During normal operation, the bulk of the loss in efficiency is due
to the power dissipated through MOSFET channel conduction.
Power loss through the upper side MOSFET is directly proportional
to the duty cycle (D) for each switching period, and the power
loss through the lower side MOSFET is directly proportional to
1 − D for each switching period. The selection of MOSFETs is
governed by the amount of maximum dc load current that the
converter is expected to deliver. In particular, the selection of
the lower side MOSFET is dictated by the maximum load
current because a typical high current application employs duty
cycles of less than 50%. Therefore, the lower side MOSFET is in
the on state for most of the switching period.
PN1, N2 (CL) = [D × RN1 (ON) + (1 − D) × RN2 (ON)] × 2
LOAD
I
MOSFET Driver Loss
Other dissipative elements are the MOSFET drivers. The
contributing factors are the dc current flowing through the
driver during operation and the QGATE parameter of the external
MOSFETs.
BIAS
DD
lowerFET
SW
DD
BIAS
DR
upperFET
SW
DR
LOSSDR
IVCfV
IVCfVP
)(
where:
CupperFET is the input gate capacitance of the upper-side MOSFET.
ClowerFET is the input gate capacitance of the lower-side MOSFET.
VDR is the driver bias voltage (that is, the low input voltage (VDD)
minus the rectifier drop (see Figure 80)).
IBIAS is the dc current flowing into the upper- and lower-side drivers.
VDD is the bias voltage.
800
720
640
560
480
400
320
240
160
80
300 1000900800700600500400
RECTIFIER DRO P (mV)
FREQ UE NCY (kHz )
+125°C
+25°C
–40°C
V
DD
= 2. 7V
V
DD
= 3. 6V
V
DD
= 5. 5V
08297-079
Figure 80. Internal Rectifier Voltage Drop vs. Switching Frequency
MOSFET Switching Loss
The SW node transitions due to the switching activities of the
upper side and lower side MOSFETs. This causes removal and
replenishing of charge to and from the gate oxide layer of the
MOSFET, as well as to and from the parasitic capacitance
associated with the gate oxide edge overlap and the drain and
source terminals. The current that enters and exits these charge
paths presents additional loss during these transition times.
This can be approximately quantified by using the following
equation, which represents the time in which charge enters and
exits these capacitive regions.
tSW-TRANS = RGATE × CTOTAL
where:
RGATE is the gate input resistance of the MOSFET.
CTOTAL is the CGD + CGS of the external MOSFET used.
The ratio of this time constant to the period of one switching cycle
is the multiplying factor to be used in the following expression:
2
-
)( VINI
t
t
PLOAD
SW
TRANSSW
LOSSSW
or
PSW (LOSS) = fSW × RGATE × CTOTAL × ILOAD × VIN × 2
ADP1872/ADP1873 Data Sheet
Rev. B | Page 26 of 40
Body Diode Conduction Loss
The ADP1872/ADP1873 employ anticross conduction circuitry
that prevents the upper side and lower side MOSFETs from
conducting current simultaneously. This overlap control is
beneficial, avoiding large current flow that may lead to
irreparable damage to the external components of the power
stage. However, this blanking period comes with the trade-off of
a diode conduction loss occurring immediately after the
MOSFETs change states and continuing well into idle mode.
The amount of loss through the body diode of the lower side
MOSFET during the antioverlap state is given by
2
)(
)( F
LOAD
SW
LOSSBODY
LOSSBODY VI
t
t
P
where:
tBODY (LOSS) is the body conduction time (refer to Figure 81 for
dead time periods).
tSW is the period per switching cycle.
VF is the forward drop of the body diode during conduction.
(Refer to the selected external MOSFET data sheet for more
information about the VF parameter.)
80
72
64
56
48
40
32
24
16
8
2.7 5.54.84.13.4
BODY DIODE CONDUCTIO N TIM E (ns)
V
DD
(V)
+125°C
+25°C
–40°C
1MHz
300kHz
08297-080
Figure 81. Body Diode Conduction Time vs. Low Voltage Input (VDD)
Inductor Loss
During normal conduction mode, further power loss is caused
by the conduction of current through the inductor windings,
which have dc resistance (DCR). Typically, larger sized inductors
have smaller DCR values.
The inductor core loss is a result of the eddy currents generated
within the core material. These eddy currents are induced by the
changing flux, which is produced by the current flowing through
the windings. The amount of inductor core loss depends on the
core material, the flux swing, the frequency, and the core volume.
Ferrite inductors have the lowest core losses, whereas powdered iron
inductors have higher core losses. It is recommended to use shielded
ferrite core material type inductors with the ADP1872/ADP1873
for a high current, dc-to-dc switching application to achieve
minimal loss and negligible electromagnetic interference (EMI).
PDCR (LOSS) = DCR × 2
LOAD
I+ Core Loss
INPUT CAPACITOR SELECTION
The goal in selecting an input capacitor is to reduce or to minimize
input voltage ripple and to reduce the high frequency source
impedance, which is essential for achieving predictable loop
stability and transient performance.
The problem with using bulk capacitors, other than their physical
geometries, is their large equivalent series resistance (ESR) and
large equivalent series inductance (ESL). Aluminum electrolytic
capacitors have such high ESR that they cause undesired input
voltage ripple magnitudes and are generally not effective at high
switching frequencies.
If bulk capacitors are to be used, it is recommended to use multi-
layered ceramic capacitors (MLCC) in parallel due to their low
ESR values. This dramatically reduces the input voltage ripple
amplitude as long as the MLCCs are mounted directly across
the drain of the upper side MOSFET and the source terminal of
the lower side MOSFET (see the Layout Considerations section).
Improper placement and mounting of these MLCCs may cancel
their effectiveness due to stray inductance and an increase in
trace impedance.
OUT
OUTOUT
MAXLOADRMSCIN V
VVINV
II
,,
The maximum input voltage ripple and maximum input capacitor
rms current occur at the end of the duration of 1 − D while the
upper side MOSFET is in the off state. The input capacitor rms
current reaches its maximum at time D. When calculating the
maximum input voltage ripple, account for the ESR of the input
capacitor as follows:
VMAX, RIPPLE = VRIPP + (ILOAD, MAX × ESR)
where:
VRIPP is usually 1% of the minimum voltage input.
ILOAD, MAX is the maximum load current.
ESR is the equivalent series resistance rating of the input
capacitor used.
Inserting VMAX, RIPPLE into the charge balance equation to calculate
the minimum input capacitor requirement gives
SWRIPPLEMAX
MAXLOAD
minIN, f
DD
V
I
C)1(
,
,
or
RIPPLEMAXSW
MAXLOAD
minIN, Vf
I
C
,
,
4
where D = 50%.
Data Sheet ADP1872/ADP1873
Rev. B | Page 27 of 40
THERMAL CONSIDERATIONS
The ADP1872/ADP1873 are used for dc-to-dc, step down, high
current applications that have an on-board controller and on-board
MOSFET drivers. Because applications may require up to 20 A of
load current delivery and be subjected to high ambient temperature
surroundings, the selection of external upper side and lower side
MOSFETs must be associated with careful thermal consideration
to not exceed the maximum allowable junction temperature
of 125°C. To avoid permanent or irreparable damage if the
junction temperature reaches or exceeds 155°C, the part enters
thermal shutdown, turning off both external MOSFETs, and
does not re-enable until the junction temperature cools to 140°C
(see the Thermal Shutdown section).
The maximum junction temperature allowed for the ADP1872/
ADP1873 ICs is 125°C. This means that the sum of the ambient
temperature (TA) and the rise in package temperature (TR), which
is caused by the thermal impedance of the package and the internal
power dissipation, should not exceed 125°C, as dictated by
TJ = TR × TA
where:
TJ is the maximum junction temperature.
TR is the rise in package temperature due to the power
dissipated from within.
TA is the ambient temperature.
The rise in package temperature is directly proportional to its
thermal impedance characteristics. The following equation
represents this proportionality relationship:
TR = θJA × PDR (LOSS)
where:
θJA is the thermal resistance of the package from the junction to
the outside surface of the die, where it meets the surrounding air.
PDR (LOSS) is the overall power dissipated by the IC.
The bulk of the power dissipated is due to the gate capacitance
of the external MOSFETs. The power loss equation of the
MOSFET drivers (see the MOSFET Driver Loss section in the
Efficiency Consideration section) is
PDR (LOSS) = [VDR × (fSWCupperFETVDR + IBIAS)] + [VDD ×
(fSWClowerFETVDD + IBIAS)]
where:
CupperFET is the input gate capacitance of the upper side MOSFET.
ClowerFET is the input gate capacitance of the lower side MOSFET.
IBIAS is the dc current (2 mA) flowing into the upper side and
lower side drivers.
VDR is the driver bias voltage (that is, the low input voltage (VDD)
minus the rectifier drop (see Figure 80)).
VDD is the bias voltage
For example, if the external MOSFET characteristics are θJA
(10-lead MSOP) = 171.2°C/W, fSW = 300 kHz, IBIAS = 2 mA,
CupperFET = 3.3 nF, ClowerFET = 3.3 nF, VDR = 5.12 V, and VDD = 5 . 5 V,
then the power loss is
PDR (LOSS) = [VDR × (fSWCupperFETVDR + IBIAS)] + [VDD ×
(fSWClowerFETVDD + IBIAS)]
= [5.12 × (300 × 103 × 3.3 × 10−9 × 5.12 + 0.002)] +
[5.5 × (300 × 103 ×3.3 × 10−9 × 5.5 + 0.002)]
= 77.13 mW
The rise in package temperature is
TR = θJA × PDR (LOSS)
= 171.2°C × 77.13 mW
= 13.2°C
Assuming a maximum ambient temperature environment of 85°C,
the junction temperature is
TJ = TR × TA = 13.2°C + 85°C = 98.2°C
which is below the maximum junction temperature of 125°C.
DESIGN EXAMPLE
The ADP1872/ADP1873 are easy to use, requiring only a few
design criteria. For example, the example outlined in this section
uses only four design criteria: VOUT = 1.8 V, ILOAD = 15 A (pulsing),
VIN = 12 V (typical), and fSW = 300 kHz.
Input Capacitor
The maximum input voltage ripple is usually 1% of the
minimum input voltage (11.8 V × 0.01 = 120 mV).
VRIPP = 120 mV
VMAX, RIPPLE = VRIPP − (ILOAD, MAX × ESR)
= 120 mV − (15 A × 0.001) = 45 mV
mV105103004
A15
43
,
,
×××
==
RIPPLEMAXSW
MAXLOAD
minIN, Vf
I
C
= 120 µF
Choose five 22 µF ceramic capacitors. The overall ESR of five
22 µF ceramic capacitors is less than 1 mΩ.
IRMS = ILOAD/2 = 7.5 A
PCIN = (IRMS)2 × ESR = (7.5A)2 × 1 mΩ = 56.25 mW
Inductor
Determining inductor ripple current amplitude:
3
LOAD
L
I
I≈∆
= 5 A
so calculating for the inductor value
V2.13
V8.1
10300V5
)V8.1V2.13(
)(
3
,
×
××
−
=
×
×∆
−
=
MAXIN,
OUT
SW
L
OUT
MAXIN
V
V
fI
VV
L
= 1.03 µH
ADP1872/ADP1873 Data Sheet
Rev. B | Page 28 of 40
The inductor peak current is approximately
15 A + (5 A × 0.5) = 17.5 A
Therefore, an appropriate inductor selection is 1.0 µH with
DCR = 3.3 mΩ (7443552100) from Table 7 with peak current
handling of 20 A.
2
)( LOAD
LOSSDCR
IDCRP×=
= 0.003 × (15 A)2 = 675 mW
Current Limit Programming
The valley current is approximately
15 A − (5 A × 0.5) = 12.5 A
Assuming a lower side MOSFET RON of 4.5 mΩ, choosing 13 A
as the valley current limit from Table 6 and Figure 70 indicates
that a programming resistor (RES) of 100 kΩ corresponds to an
ACS of 24 V / V.
Choose a programmable resistor of RRES = 100 kΩ for a current-
sense gain of 24 V / V.
Output Capacitor
Assume a load step of 15 A occurs at the output and no more
than 5% is allowed for the output to deviate from the steady
state operating point. The ADP1872’s advantage is, because the
frequency is pseudo-fixed, the converter is able to respond
quickly because of the immediate, though temporary, increase
in switching frequency.
ΔVDROOP = 0.05 × 1.8 V = 90 mV
Assuming the overall ESR of the output capacitor ranges from
5 mΩ to 10 mΩ,
)mV90(10300
15
2
)(
2
3××
×=
∆×
∆
×=
A
Vf
I
C
DROOPSW
LOAD
OUT
= 1.11 mF
Therefore, an appropriate inductor selection is five 270 µF
polymer capacitors with a combined ESR of 3.5 mΩ.
Assuming an overshoot of 45 mV, determine if the output
capacitor that was calculated previously is adequate:
( )
( )
22
26
2
2
2
)8.1()mV458.1(
)A15(101
)(
)(
−−
××
=
−∆−
×
=
−
OUTOVSHTOUT
LOAD
OUT
VVV
IL
C
= 1.4 mF
Choose five 270 µF polymer capacitors.
The rms current through the output capacitor is
A49.1
V2.13
V8.1
10300μF1
)V8.1V2.13(
3
1
2
1
)(
3
1
2
1
3
,
,
=×
××
−
×=
×
×
−
×=
MAXIN
OUT
SW
OUT
MAXIN
RMS V
V
fL
VV
I
The power loss dissipated through the ESR of the output
capacitor is
PCOUT = (IRMS)2 × ESR = (1.5 A)2 × 1.4 mΩ = 3.15 mW
Feedback Resistor Network Setup
It is recommended to use RB = 15 kΩ. Calculate RT as
kΩ30
V6.0
V)6.0V8.1(
kΩ15 =
−
×=
T
R
Compensation Network
To calculate RCOMP, CCOMP, and CPA R , the transconductance
parameter and the current-sense gain variable are required. The
transconductance parameter (GM) is 500 µA/V, and the current-
sense loop gain is
A/V33.8
005.024
11 =
×
==
ONCS
CS RA
G
where ACS and RON are taken from setting up the current limit
(see the Programming Resistor (RES) Detect Circuit and Valley
Current-Limit Setting sections).
The crossover frequency is 1/12th of the switching frequency:
300 kHz/12 = 25 kHz
The zero frequency is 1/4th of the crossover frequency:
25 kHz/4 = 6.25 kHz
6.0
8.1
3.810500
1011.11025141.3
2
1025.61025
1025
2
6
33
33
3×
××
×××××
×
×+
×
×
=
×
π
×
+
=
−
−
REF
OUT
CS
M
OUT
CROSS
ZERO
CROSS
CROSS
COMP V
V
GG
Cf
f
f
f
R
= 100 kΩ
ZERO
COMP
COMP fR
Cπ
=2
1
=
33 1025.61010014.32
1
×××××
= 250 pF
Data Sheet ADP1872/ADP1873
Rev. B | Page 29 of 40
Loss Calculations
Duty cycle = 1.8/12 V = 0.15
RON (N2) = 5.4 mΩ
tBODY(LOSS) = 20 ns (body conduction time)
VF = 0.84 V (MOSFET forward voltage)
CIN = 3.3 nF (MOSFET gate input capacitance)
QN1, N2 = 17 nC (total MOSFET gate charge)
RGATE = 1.5 Ω (MOSFET gate input resistance)
( )
[ ]
2
1LOAD
N2(ON)N1(ON)N2(CL)N1, IRDRDP ××−+×=
= (0.15 × 0.0054 + 0.85 × 0.0054) × (15 A)2
= 1.215 W
2
)(
)( ××
×=
F
LOAD
SW
LOSSBODY
LOSSBODY
VI
t
t
P
= 20 ns × 300 × 103 × 15 A × 0.84 × 2
= 151.2 mW
PSW (LOSS) = fSW × RGATE × CTOTAL × ILOAD × VIN × 2
= 300 × 103 × 1.5 Ω × 3.3 × 10−9 × 15 A × 12 × 2
= 534.6 mW
( )
[ ]
( )
[ ]
BIAS
DD
lowerFET
SW
DD
BIAS
DR
upperFET
SW
DR
LOSSDR
IVCfV
IVCf
VP
+×
++×=
)(
= (5.12 × (300 × 103 × 3.3 × 10−9 × 5.12 + 0.002)) +
(5.5 × (300 × 103 ×3.3 ×10−9 ×5.5 + 0.002))
= 77.13 mW
PCOUT = (IRMS)2 × ESR = (1.5 A)2 × 1.4 mΩ = 3.15 mW
2
)( LOAD
LOSSDCR
IDCRP×=
= 0.003 × (15 A)2 = 675 mW
PCIN = (IRMS)2 × ESR = (7.5 A)2 × 1 mΩ = 56.25 mW
PLOSS = PN1, N2 + PBODY (LOSS) + PSW + PDCR + PDR + PCOUT + PCIN
= 1.215 W + 151.2 mW + 534.6 mW + 77.13 mW +
3.15 mW + 675 mW + 56.25 mW
= 2.62 W
ADP1872/ADP1873 Data Sheet
Rev. B | Page 30 of 40
EXTERNAL COMPONENT RECOMMENDATIONS
The configurations listed in Table 8 are with fCROSS = 1/12 × fSW, fZERO = ¼ × fCROSS, RRES = 100 kΩ, RBOT = 15 kΩ, RON = 5.4 mΩ (BSC042N03MS G),
VDD = 5 V, and a maximum load current of 14 A.
The ADP1873 models listed in Table 8 are the PSM versions of the device.
Table 8. External Component Values
Marking Code
SAP Model ADP1872 ADP1873
VOUT
(V)
VIN
(V) CIN (µF) COUT (µF)
L1
(µH)
RC
(kΩ)
CCOMP
(pF)
CPAR
(pF)
RTOP
(kΩ)
ADP1872ARMZ-0.3-R7/
ADP1873ARMZ-0.3-R7
LDT LDF 0.8 13 5 × 222 5 × 5603 0.72 47 740 74 5.0
LDT LDF 1.2 13 5 × 222 4 × 5603 1.0 47 740 74 15.0
LDT LDF 1.8 13 4 × 222 4 × 2704 1.0 47 571 57 30.0
LDT LDF 2.5 13 4 × 222 3 × 2704 1.53 47 571 57 47.5
LDT
LDF
3.3
13
5 × 22
2
2 × 330
5
2.0
47
571
57
67.5
LDT LDF 5 13 4 × 222 3305 3.27 34 800 80 110.0
LDT LDF 7 13 4 × 222 222 + (4 × 476) 3.44 34 800 80 160.0
LDT LDF 1.2 16.5 4 × 222 4 × 5603 1.0 47 740 74 15.0
LDT LDF 1.8 16.5 3 × 222 4 × 2704 1.0 47 592 59 30.0
LDT LDF 2.5 16.5 3 × 222 4 × 2704 1.67 47 592 59 47.5
LDT LDF 3.3 16.5 3 × 222 2 × 3305 2.00 47 592 59 67.5
LDT LDF 5 16.5 3 × 222 2 × 1507 3.84 34 829 83 110.0
LDT LDF 7 16.5 3 × 222 222 + 4 × 476 4.44 34 829 83 160.0
ADP1872ARMZ-0.6-R7/
ADP1873ARMZ-0.6-R7
LDU LDK 0.8 5.5 5 × 222 4 × 5603 0.22 47 339 34 5.0
LDU LDK 1.2 5.5 5 × 222 4 × 2704 0.47 47 326 33 15.0
LDU LDK 1.8 5.5 5 × 222 3 × 2704 0.47 47 271 27 30.0
LDU LDK 2.5 5.5 5 × 222 3 × 1808 0.47 47 271 27 47.5
LDU LDK 1.2 13 3 × 222 5 × 2704 0.47 47 407 41 15.0
LDU LDK 1.8 13 5 × 109 3 × 3305 0.47 47 307 31 30.0
LDU LDK 2.5 13 5 × 109 3 × 2704 0.90 47 307 31 47.5
LDU LDK 3.3 13 5 × 109 2 × 2704 1.00 47 307 31 67.5
LDU LDK 5 13 5 × 109 1507 1.76 34 430 43 110.0
LDU LDK 1.2 16.5 3 × 109 4 × 2704 0.47 47 362 36 15.0
LDU LDK 1.8 16.5 4 × 109 2 × 3305 0.72 47 326 33 30.0
LDU LDK 2.5 16.5 4 × 109 3 × 2704 0.90 47 326 33 47.5
LDU LDK 3.3 16.5 4 × 109 3305 1.0 47 296 30 67.5
LDU LDK 5 16.5 4 × 109 4 × 476 2.0 34 415 41 110.0
LDU LDK 7 16.5 4 × 109 3 × 476 2.0 34 380 38 160.0
ADP1872ARMZ-1.0-R7/
ADP1873ARMZ-1.0-R7
LDV LDL 0.8 5.5 5 × 222 4 × 2704 0.22 47 223 22 5.0
LDV LDL 1.2 5.5 5 × 222 2 × 3305 0.22 47 223 22 15.0
LDV LDL 1.8 5.5 3 × 222 3 × 1808 0.22 47 163 16 30.0
LDV LDL 2.5 5.5 3 × 222 2704 0.22 47 163 16 47.5
LDV LDL 1.2 13 3 × 109 3 × 3305 0.22 47 233 23 15.0
LDV LDL 1.8 13 4 × 109 3 × 2704 0.47 47 210 21 30.0
LDV LDL 2.5 13 4 × 109 2704 0.47 47 210 21 47.5
LDV LDL 3.3 13 5 × 109 2704 0.72 47 210 21 67.5
LDV LDL 5 13 4 × 109 3 × 476 1.0 34 268 27 110.0
LDV LDL 1.2 16.5 3 × 109 4 × 2704 0.47 47 326 33 15.0
LDV LDL 1.8 16.5 3 × 109 3 × 2704 0.47 47 261 26 30.0
LDV LDL 2.5 16.5 4 × 109 3 × 1808 0.72 47 233 23 47.5
LDV LDL 3.3 16.5 4 × 109 2704 0.72 47 217 22 67.5
Data Sheet ADP1872/ADP1873
Rev. B | Page 31 of 40
Marking Code
SAP Model ADP1872 ADP1873
VOUT
(V)
VIN
(V) CIN (µF) COUT (µF)
L1
(µH)
RC
(kΩ)
CCOMP
(pF)
CPAR
(pF)
RTOP
(kΩ)
LDV LDL 5 16.5 3 × 109 3 × 476 1.0 34 268 27 110.0
LDV LDL 7 16.5 3 × 109 222 + 476 1.0 34 228 23 160.0
1 See the Inductor Selection section (See Table 9).
2 22 µF Murata 25 V, X7R, 1210 GRM32ER71E226KE15L (3.2 mm × 2.5 mm × 2.5 mm).
3 560 µF Panasonic (SP-series) 2 V, 7 mΩ, 3.7 A EEFUE0D561LR (4.3 mm × 7.3 mm × 4.2 mm).
4 270 µF Panasonic (SP-series) 4 V, 7 mΩ, 3.7 A EEFUE0G271LR (4.3 mm × 7.3 mm × 4.2 mm).
5 330 µF Panasonic (SP-series) 4 V, 12 mΩ, 3.3 A EEFUE0G331R (4.3 mm × 7.3 mm × 4.2 mm).
6 47 µF Murata 16 V, X5R, 1210 GRM32ER61C476KE15L (3.2 mm × 2.5 mm × 2.5 mm).
7 150 µF Panasonic (SP-series) 6.3 V, 10 mΩ, 3.5 A EEFUE0J151XR (4.3 mm × 7.3 mm × 4.2 mm).
8 180 µF Panasonic (SP-series) 4 V, 10 mΩ, 3.5 A EEFUE0G181XR (4.3 mm × 7.3 mm × 4.2 mm).
9 10 µF TDK 25 V, X7R, 1210 C3225X7R1E106M.
Table 9. Recommended Inductors
L (µH) DCR (mΩ) ISAT (A) Dimension (mm) Manufacturer Model Number
0.12 0.33 55 10.2 × 7 Würth Elektronik 744303012
0.22 0.33 30 10.2 × 7 Würth Elektronik 744303022
0.47 0.8 50 14.2 × 12.8 Würth Elektronik 744355147
0.72 1.65 35 10.5 × 10.2 Würth Elektronik 744325072
0.9 1.6 28 13 × 12.8 Würth Elektronic 744355090
1.2 1.8 25 10.5 × 10.2 Würth Elektronic 744325120
1.0 3.3 20 10.5 × 10.2 Würth Elektronic 7443552100
1.4 3.2 24 14 × 12.8 Würth Elektronic 744318180
2.0 2.6 22 13.2 × 12.8 Würth Elektronic 7443551200
0.8 27.5 Sumida CEP125U-0R8
Table 10. Recommended MOSFETs
VGS = 4.5 V
RON
(mΩ)
ID
(A)
VDS
(V)
CIN
(nF)
QTOTAL
(nC) Package Manufacturer Model Number
Upper-Side MOSFET
(Q1/Q2)
5.4 47 30 3.2 20 PG-TDSON8 Infineon BSC042N03MS G
10.2 53 30 1.6 10 PG-TDSON8 Infineon BSC080N03MS G
6.0 19 30 35 SO-8 Vishay Si4842DY
9 14 30 2.4 25 SO-8 International Rectifier IRF7811
Lower-Side MOSFET
(Q3/Q4)
5.4 47 30 3.2 20 PG-TDSON8 Infineon BSC042N03MS G
10.2 82 30 1.6 10 PG-TDSON8 Infineon BSC080N03MS G
6.0 19 30 35 SO-8 Vishay Si4842DY
ADP1872/ADP1873 Data Sheet
Rev. B | Page 32 of 40
LAYOUT CONSIDERATIONS
The performance of a dc-to-dc converter depends highly on
how the voltage and current paths are configured on the printed
circuit board (PCB). Optimizing the placement of sensitive
analog and power components are essential to minimize output
ripple, maintain tight regulation specifications, and reduce
PWM jitter and electromagnetic interference.
Figure 82 shows the schematic of a typical ADP1872/ADP1873
used for a high power application. Blue traces denote high current
pathways. VIN, PGND, and VOUT traces should be wide and
possibly replicated, descending down into the multiple layers.
Vias should populate, mainly around the positive and negative
terminals of the input and output capacitors, alongside the source
of Q1/Q2, the drain of Q3/Q4, and the inductor.
MURATA: (HIG H V OLTAGE INPUT CAPACITORS)
22µF, 25V, X 7R, 1210 G RM 32E R71E 226KE 15 L
PANASONI C: ( OUT P UT CA PACITORS)
270µF (SP-SERIES) 4V, 7mΩ EEFUE0G271LR
INFINEON MOSFETs:
BSC042N03MS G (L OW E R- S IDE)
BSC080N03MS G (UPP E R- S IDE)
WURTH INDUCTO RS :
1µH, 3.3mΩ, 20A 7443552100
R5
100kΩ
Q3 Q4
Q1 Q2
HIGH VOLTAGE INPUT
VI N = 12V
C12
100nF
VOUT = 1. 8V , 15A
C3
22µF C4
22µF
C5
22µF C6
22µF C7
22µF
C23
270µF +
C22
270µF +
C21
270µF +
C20
270µF +
1.0µH
R6
2Ω
C13
1.5nF
R1 30kΩ
R2
15kΩ
V
OUT
1
VIN
10
BST
2
COMP/EN
9
SW
3
FB
8
DRVH
4
GND
7
PGND
5
VDD
6
DRVL
ADP1872/
ADP1873
C
C
571pF
C
F
57pF R
C
47kΩ
C1
1µF
C2
0.1µF
LOW VOLTAGE INPUT
V
DD
= 5.0V
JP1
08297-081
Figure 82. ADP1872/ADP1873 High Current Evaluation Board Schematic (Blue Traces Indicate High Current Paths)
Data Sheet ADP1872/ADP1873
Rev. B | Page 33 of 40
08297-082
OUTPUT CAP ACIT ORS
ARE MOUNTE D ON T HE
RIGHTMOST AREA OF
THE E V B, WRAP P ING
BACK AROUND TO THE
MAI N P OWE R GRO UND
PLANE, WHERE IT MEETS
WITH THE NEGATIVE
TERMINALS OF THE
INP UT CAPACI TO RS
INP UT CAPACI TO RS
ARE MOUNTE D CLO S E
TO DRAIN OF Q1/Q2
AND SO URCE OF Q3/ Q4.
BYPAS S P OWE R CAP ACIT OR (C1)
FOR VREG BI AS DE COUPLING
AND HIGH FRE QUENCY
CAPACI TOR ( C2) AS CLO S E AS
POSSIBLE TO THE IC.
SENSITIVE ANALOG
COMPONENTS
LOCATE D FAR
FROM THE NOISY
POWER SECTIO N.
SEP ARATE ANAL OG GRO UND
PL ANE FOR THE ANALO G
COMPONENTS (THAT IS,
COM P E NS ATION AND
FE E DBACK RE S IST ORS) .
Figure 83. Overall Layout of the ADP1872 High Current Evaluation Board
SW
ADP1872/ADP1873 Data Sheet
Rev. B | Page 34 of 40
08297-083
Figure 84. Layer 2 of Evaluation Board
Data Sheet ADP1872/ADP1873
Rev. B | Page 35 of 40
TOP RESISTOR
FE E DBACK TAP
VO UT SENS E TAP LI NE E X TENDI NG BACK
TO THE TOP RESISTOR IN THE FEEDBACK
DIV IDER NETW ORK (S E E FIGURE 82) . T HIS
OVERLAPS WIT H PGND SENSE TAP LINE
EXTENDI NG BACK T O T HE ANALOG
PL ANE ( S E E FIGURE 86, L AY E R 4 FOR
PG ND TAP).
08297-084
Figure 85. Layer 3 of Evaluation Board
ADP1872/ADP1873 Data Sheet
Rev. B | Page 36 of 40
08297-085
BOTTOM RESISTOR
TAP TO THE ANALOG
GROUND PL ANE
PGND SENSE TAP FROM
NEGATIVE TERMINALS OF
OUTPUT BULK CAPACIT ORS.
THIS T RACK P LACEM E NT
SHO ULD BE DI RE CTL Y
BELOW T HE VOUT SENSE
LINE FROM FIGURE 84.
Figure 86. Layer 4 (Bottom Layer) of Evaluation Board
Data Sheet ADP1872/ADP1873
Rev. B | Page 37 of 40
IC SECTION (LEFT SIDE OF EVALUATION BOARD)
A dedicated plane for the analog ground plane (GND) should
be separate from the main power ground plane (PGND). With
the shortest path possible, connect the analog ground plane to
the GND pin (Pin 4). This plane should only be on the top layer
of the evaluation board. To avoid crosstalk interference, there
should not be any other voltage or current pathway directly
below this plane on Layer 2, Layer 3, or Layer 4. Connect the
negative terminals of all sensitive analog components to the
analog ground plane. Examples of such sensitive analog com-
ponents include the resistor divider’s bottom resistor, the high
frequency bypass capacitor for biasing (0.1 µF), and the
compensation network.
Mount a 1 µF bypass capacitor directly across the VDD pin
(Pin 5) and the PGND pin (Pin 7). In addition, a 0.1 µF should
be tied across the VDD pin (Pin 5) and the GND pin (Pin 4).
POWER SECTION
As shown in Figure 83, an appropriate configuration to localize
large current transfer from the high voltage input (VIN) to the
output (VOUT) and then back to the power ground is to put the
VIN plane on the left, the output plane on the right, and the main
power ground plane in between the two. Current transfers from
the input capacitors to the output capacitors, through Q1/Q2,
during the on state (see Figure 87). The direction of this current
(yellow arrow) is maintained as Q1/Q2 turns off and Q3/Q4
turns on. When Q3/Q4 turns on, the current direction continues to
be maintained (red arrow) as it circles from the bulk capacitor’s
power ground terminal to the output capacitors, through the
Q3/Q4. Arranging the power planes in this manner minimizes
the area in which changes in flux occur if the current through
Q1/Q2 stops abruptly. Sudden changes in flux, usually at source
terminals of Q1/Q2 and drain terminals of Q3/Q4, cause large
dV/dts at the SW node.
The SW node is near the top of the evaluation board. The SW
node should use the least amount of area possible and be away
from any sensitive analog circuitry and components because
this is where most sudden changes in flux density occur. When
possible, replicate this pad onto Layer 2 and Layer 3 for thermal
relief and eliminate any other voltage and current pathways directly
beneath the SW node plane. Populate the SW node plane with
vias, mainly around the exposed pad of the inductor terminal
and around the perimeter of the source of Q1/Q2 and the drain
of Q3/Q4. The output voltage power plane (VOUT) is at the right-
most end of the evaluation board. This plane should be replicated,
descending down to multiple layers with vias surrounding the
inductor terminal and the positive terminals of the output bulk
capacitors. Ensure that the negative terminals of the output
capacitors are placed close to the main power ground (PGND),
as previously mentioned. All of these points form a tight circle
(component geometry permitting) that minimizes the area of
flux change as the event switches between D and 1 − D.
VOUT
SW
VIN PGND
08297-086
Figure 87. Primary Current Pathways During the On State of the Upper-Side
MOSFET (Left Arrow) and the On State of the Lower-Side MOSFET (Right Arrow)
DIFFERENTIAL SENSING
Because the ADP1872/ADP1873 operate in valley current-
mode control, a differential voltage reading is taken across the
drain and source of the lower-side MOSFET. The drain of the
lower-side MOSFET should be connected as close as possible to
the SW pin (Pin 9) of the IC. Likewise, the source should be
connected as close as possible to the PGND pin (Pin 7) of the
IC. When possible, both of these track lines should be narrow
and away from any other active device or voltage/current paths.
08297-087
LAYER 1: SENSE LINE FO R SW
(DRAIN OF LOWER MOSFET) LAYER 1: SENSE LINE FOR PGND
(SOURCE OF LOWER MOSFET)
SW
PGND
Figure 88. Drain/Source Tracking Tapping of the Lower-Side MOSFET for CS
Amp Differential Sensing (Yellow Sense Line on Layer 2)
Differential sensing should also be applied between the
outermost output capacitor to the feedback resistor divider (see
Figure 85 and Figure 86). Connect the positive terminal of the
output capacitor to the top resistor (RT). Connect the negative
terminal of the output capacitor to the negative terminal of the
bottom resistor, which connects to the analog ground plane as
well. Both of these track lines, as previously mentioned, should
be narrow and away from any other active device or voltage/
current paths.
ADP1872/ADP1873 Data Sheet
Rev. B | Page 38 of 40
TYPICAL APPLICATION CIRCUITS
DUAL-INPUT, 300 kHz HIGH CURRENT APPLICATION CIRCUIT
MURATA: (HIG H V OLTAGE INPUT CAPACITORS)
22µF, 25V, X 7R, 1210 G RM 32E R71E 226KE 15 L
PANASONI C: ( OUT P UT CA PACITORS)
270µF (SP-SERIES) 4V, 7mΩ EEFUE0G271LR
INFINEON MOSFETs:
BSC042N03MS G (L OW E R- S IDE)
BSC080N03MS G (UPP E R- S IDE)
WURTH INDUCTO RS :
1µH, 3.3mΩ, 20A 7443552100
R5
100kΩ
Q3 Q4
Q1 Q2
HIGH VOLTAGE INPUT
VI N = 12V
C12
100nF
V
OUT
= 1.8V , 15A
C3
22µF C4
22µF
C5
22µF C6
22µF C7
22µF
C23
270µF +
C22
270µF +
C21
270µF +
C20
270µF +
1.0µH
R6
2Ω
C13
1.5nF
R1 30kΩ
R2
15kΩ
V
OUT
1
VIN
10
BST
2
COMP/EN
9
SW
3
FB
8
DRVH
4
GND
7
PGND
5
VDD
6
DRVL
ADP1872/
ADP1873
C
C
571pF
C
F
57pF R
C
47kΩ
C1
1µF
C2
0.1µF
LOW VOLTAGE INPUT
V
DD
= 5.0V
JP1
08297-088
Figure 89. Application Circuit for 12 V Input, 1.8 V Output, 15 A, 300 kHz (Q2/Q4 No Connect).
SINGLE-INPUT, 600 kHz APPLICATION CIRCUIT
MURATA: (HIG H V OLTAGE INPUT CAPACITORS)
22µF, 25V, X 7R, 1210 G RM 32E R71E 226KE 15 L
PANASONI C: ( OUT P UT CA PACITORS)
180µF (SP-SERIES) 4V, 10mΩ EEFUE0G181XR
INFINEON MOSFETs:
BSC042N03MS G (L OW E R- S IDE)
BSC080N03MS G (UPP E R- S IDE)
WURTH INDUCTO RS :
0.47µH, 0.8mΩ, 50A 744355147
R5
100kΩ
Q3 Q4
Q1 Q2
HIGH VOLTAGE INPUT
VI N = 5.5V
C12
100nF
V
OUT
= 2.5V , 15A
C3
22µF C4
22µF C5
22µF C6
22µF C7
22µF
C22
180µF +
C21
180µF +
C20
180µF +
0.47µH
R6
2Ω
C13
1.5nF
R1 47.5kΩ
R2
15kΩ
V
OUT
1
VIN
10
BST
2
COMP/EN
9
SW
3
FB
8
DRVH
4
GND
7
PGND
5
VDD
6
DRVL
ADP1872/
ADP1873
C
C
271pF
C
F
27pF R
C
47kΩ
C1
1µF
C2
0.1µF
JP1
08297-089
Figure 90. Application Circuit for 5.5 V Input, 2.5 V Output, 15 A, 600 kHz (Q2/Q4 No Connect)
Data Sheet ADP1872/ADP1873
Rev. B | Page 39 of 40
DUAL-INPUT, 300 kHz HIGH CURRENT APPLICATION CIRCUIT
MURATA: (HIG H V OLTAGE INPUT CAPACITORS)
22µF, 25V, X 7R, 1210 G RM 32E R71E 226KE 15 L
PANASONI C: ( OUT P UT CA PACITORS)
270µF (SP-SERIES) 4V, 7mΩ EEFUE0G271LR
INFINEON MOSFETs:
BSC042N03MS G (L OW E R- S IDE)
BSC080N03MS G (UPP E R- S IDE)
WURTH INDUCTO RS :
0.72µH, 1.65mΩ, 35A 744325072
Q3 Q4
Q1 Q2
HIGH VOLTAGE INPUT
VI N = 13V
LOW VOLTAGE INPUT
V
DD
= 5V
C12
100nF
V
OUT
= 1.8V , 20A
C3
22µF C4
22µF C5
22µF C6
22µF C7
22µF
C23
270µF +
C22
270µF +
C21
270µF +
C20
270µF +
0.8µH
R6
2Ω
C13
1.5nF
R1 30kΩ
R2
15kΩ
V
OUT
1
VIN
10
BST
2
COMP/EN
9
SW
3
FB
8
DRVH
4
GND
7
PGND
5
VDD
6
DRVL
ADP1872/
ADP1873
C
C
800pF
C
F
80pF R
C
33.5kΩ
C1
1µF
C2
0.1µF
JP1
08297-090
Figure 91. Application Circuit for 13 V Input, 1.8 V Output, 20 A, 300 kHz (Q2/Q4 No Connect)
ADP1872/ADP1873 Data Sheet
Rev. B | Page 40 of 40
OUTLINE DIMENSIONS
COMPLIANT TO JEDEC STANDARDS MO-187-BA
091709-A
6°
0°
0.70
0.55
0.40
5
10
1
6
0.50 BSC
0.30
0.15
1.10 MAX
3.10
3.00
2.90
COPLANARITY
0.10
0.23
0.13
3.10
3.00
2.90
5.15
4.90
4.65
PIN 1
IDENTIFIER
15° MAX
0.95
0.85
0.75
0.15
0.05
Figure 92. 10-Lead Mini Small Outline Package [MSOP]
(RM-10)
Dimensions shown in millimeters
ORDERING GUIDE
Model1 Temperature Range Package Description Package Option Branding
ADP1872ARMZ-0.3-R7 −40°C to +125°C 10-Lead Mini Small Outline Package [MSOP] RM-10 LDT
ADP1872ARMZ-0.6-R7 −40°C to +125°C 10-Lead Mini Small Outline Package [MSOP] RM-10 LDU
ADP1872ARMZ-1.0-R7 −40°C to +125°C 10-Lead Mini Small Outline Package [MSOP] RM-10 LDV
ADP1872-0.3-EVALZ Forced PWM, 300 kHz Evaluation Board
ADP1872-0.6-EVALZ Forced PWM, 600 kHz Evaluation Board
ADP1872-1.0-EVALZ Forced PWM, 1 MHz Evaluation Board
ADP1873ARMZ-0.3-R7 −40°C to +125°C 10-Lead Mini Small Outline Package [MSOP] RM-10 LDF
ADP1873ARMZ-0.6-R7 −40°C to +125°C 10-Lead Mini Small Outline Package [MSOP] RM-10 LDK
ADP1873ARMZ-1.0-R7 −40°C to +125°C 10-Lead Mini Small Outline Package [MSOP] RM-10 LDL
ADP1873-0.3-EVALZ Power Saving Mode, 300 kHz Evaluation Board
ADP1873-0.6-EVALZ Power Saving Mode, 600 kHz Evaluation Board
ADP1873-1.0-EVALZ Power Saving Mode, 1 MHz Evaluation Board
1 Z = RoHS Compliant Part.
©2009–2012 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D08297-0-7/12(B)
