UC3844, UC3845, UC2844, UC2845 High Performance Current Mode Controllers The UC3844, UC3845 series are high performance fixed frequency current mode controllers. They are specifically designed for Off-Line and DC-to-DC converter applications offering the designer a cost effective solution with minimal external components. These integrated circuits feature an oscillator, a temperature compensated reference, high gain error amplifier, current sensing comparator, and a high current totem pole output ideally suited for driving a power MOSFET. Also included are protective features consisting of input and reference undervoltage lockouts each with hysteresis, cycle-by-cycle current limiting, a latch for single pulse metering, and a flip-flop which blanks the output off every other oscillator cycle, allowing output dead times to be programmed for 50% to 70%. These devices are available in an 8-pin dual-in-line plastic package as well as the 14-pin plastic surface mount (SOIC-14). The SOIC-14 package has separate power and ground pins for the totem pole output stage. The UCX844 has UVLO thresholds of 16 V (on) and 10 V (off), ideally suited for off-line converters. The UCX845 is tailored for lower voltage applications having UVLO thresholds of 8.5 V (on) and 7.6 V (off). Features * * * * * * * * * * Current Mode Operation to 500 kHz Output Switching Frequency Output Deadtime Adjustable from 50% to 70% Automatic Feed Forward Compensation Latching PWM for Cycle-By-Cycle Current Limiting Internally Trimmed Reference with Undervoltage Lockout High Current Totem Pole Output Input Undervoltage Lockout with Hysteresis Low Startup and Operating Current Direct Interface with ON Semiconductor SENSEFETt Products Pb-Free Packages are Available 5.0V Reference R RTCT 4(7) Voltage Feedback 2(3) 1(1) Output Comp. Oscillator + - 8 1 SOIC-14 D SUFFIX CASE 751A 14 1 SOIC-8 D1 SUFFIX CASE 751A 8 1 PIN CONNECTIONS Compensation 1 8 Vref Voltage Feedback 2 7 VCC Current Sense 3 6 Output RT/CT 4 5 GND (Top View) Compensation 1 14 Vref NC 2 13 NC Voltage Feedback 3 12 VCC NC 4 11 VC 10 Output Current Sense 7(12) NC 6 9 GND VCC Undervoltage Lockout RT/CT 7 8 Power Ground Vref Undervoltage Lockout R PDIP-8 N SUFFIX CASE 626 5 VCC Vref 8(14) http://onsemi.com (Top View) VC Flip Flop & Latching PWM Error Amplifier 7(11) Output 6(10) PWR GND 5(8) Current Sense 3(5) ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 14 of this data sheet. DEVICE MARKING INFORMATION See general marking information in the device marking section on page page 14 of this data sheet. GND 5(9) Pin numbers in parenthesis are for the D suffix SOIC-14 package. Figure 1. Simplified Block Diagram (c) Semiconductor Components Industries, LLC, 2006 July, 2006 - Rev. 7 1 Publication Order Number: UC3844/D UC3844, UC3845, UC2844, UC2845 MAXIMUM RATINGS Rating Symbol Value Unit (ICC + IZ) 30 mA Output Current, Source or Sink (Note 1) IO 1.0 A Output Energy (Capacitive Load per Cycle) W 5.0 mJ Current Sense and Voltage Feedback Inputs Vin - 0.3 to + 5.5 V Error Amp Output Sink Current IO 10 mA PD RqJA 862 145 mW C/W PD RqJA 1.25 100 W C/W Operating Junction Temperature TJ + 150 C Operating Ambient Temperature UC3844, UC3845 UC2844, UC2845 TA Storage Temperature Range Tstg Total Power Supply and Zener Current Power Dissipation and Thermal Characteristics D Suffix, Plastic Package, Case 751A Maximum Power Dissipation @ TA = 25C Thermal Resistance Junction-to-Air N Suffix, Plastic Package, Case 626 Maximum Power Dissipation @ TA = 25C Thermal Resistance Junction-to-Air C 0 to + 70 - 25 to + 85 - 65 to + 150 C Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. Maximum Package power dissipation limits must be observed. ELECTRICAL CHARACTERISTICS (VCC = 15 V, (Note 2), RT = 10 k, CT = 3.3 nF, TA = Tlow to Thigh (Note 3), unless otherwise noted.) UC284X Characteristics UC384X Symbol Min Typ Max Min Typ Max Unit Vref 4.95 5.0 5.05 4.9 5.0 5.1 V Line Regulation (VCC = 12 V to 25 V) Regline - 2.0 20 - 2.0 20 mV Load Regulation (IO = 1.0 mA to 20 mA) Regload - 3.0 25 - 3.0 25 mV Temperature Stability TS - 0.2 - - 0.2 - mV/C Total Output Variation over Line, Load, Temperature Vref 4.9 - 5.1 4.82 - 5.18 V Output Noise Voltage (f = 10 Hz to kHz, TJ = 25C) Vn - 50 - - 50 - mV Long Term Stability (TA = 125C for 1000 Hours) S - 5.0 - - 5.0 - mV ISC - 30 - 85 - 180 - 30 - 85 - 180 mA 47 46 52 - 57 60 47 46 52 - 57 60 REFERENCE SECTION Reference Output Voltage (IO = 1.0 mA, TJ = 25C) Output Short Circuit Current OSCILLATOR SECTION Frequency TJ = 25C TA = Tlow to Thigh fosc kHz Frequency Change with Voltage (VCC = 12 V to 25 V) Dfosc/DV - 0.2 1.0 - 0.2 1.0 % Frequency Change with Temperature TA = Tlow to Thigh Dfosc/DT - 5.0 - - 5.0 - % Vosc - 1.6 - - 1.6 - V Idischg - 10.8 - - 10.8 - mA VFB 2.45 2.5 2.55 2.42 2.5 2.58 V IIB - -0.1 -1.0 - -0.1 -2.0 mA AVOL 65 90 - 65 90 - dB Oscillator Voltage Swing (Peak-to-Peak) Discharge Current (Vosc = 2.0 V, TJ = 25C) ERROR AMPLIFIER SECTION Voltage Feedback Input (VO = 2.5 V) Input Bias Current (VFB = 2.7 V) Open Loop Voltage Gain (VO = 2.0 V to 4.0 V) 2. Adjust VCC above the Startup threshold before setting to 15 V. 3. Low duty cycle pulse techniques are used during test to maintain junction temperature as close to ambient as possible. Thigh = +70C for UC3844, UC3845 Tlow = 0C for UC3844, UC3845 -25C for UC2844, UC2845 +85C for UC2844, UC2845 http://onsemi.com 2 UC3844, UC3845, UC2844, UC2845 ELECTRICAL CHARACTERISTICS (VCC = 15 V, (Note 4), RT = 10 k, CT = 3.3 nF, TA = Tlow to Thigh (Note 5), unless otherwise noted.) UC284X Characteristics UC384X Symbol Min Typ Max Min Typ Max Unit BW 0.7 1.0 - 0.7 1.0 - MHz PSRR 60 70 - 60 70 - dB ISink 2.0 -0.5 12 -1.0 - - 2.0 -0.5 12 -1.0 - - VOH VOL 5.0 - 6.2 0.8 - 1.1 5.0 - 6.2 0.8 - 1.1 AV 2.85 3.0 3.15 2.85 3.0 3.15 Vth 0.9 1.0 1.1 0.9 1.0 1.1 ERROR AMPLIFIER SECTION (continued) Unity Gain Bandwidth (TJ = 25C) Power Supply Rejection Ratio (VCC = 12 V to 25 V) Output Current Sink (VO = 1.1 V, VFB = 2.7 V) Source (VO = 5.0 V, VFB = 2.3 V) mA ISource Output Voltage Swing High State (RL = 15 k to ground, VFB = 2.3 V) Low State (RL = 15 k to Vref, VFB = 2.7 V) V CURRENT SENSE SECTION Current Sense Input Voltage Gain (Notes 6 & 7) Maximum Current Sense Input Threshold (Note 6) Power Supply Rejection Ratio VCC = 12 V to 25 V (Note 6) PSRR Input Bias Current Propagation Delay (Current Sense Input to Output) V/V V dB - 70 - - 70 - IIB - -2.0 -10 - -2.0 -10 mA tPLH(IN/OUT) - 150 300 - 150 300 ns VOL - - 12 12 0.1 1.6 13.5 13.4 0.4 2.2 - - - - 13 12 0.1 1.6 13.5 13.4 0.4 2.2 - - - 0.1 1.1 - 0.1 1.1 OUTPUT SECTION V Output Voltage Low State (ISink = 20 mA) (ISink = 200 mA) High State (ISink = 20 mA) (ISink = 200 mA) VOH Output Voltage with UVLO Activated VCC = 6.0 V, ISink = 1.0 mA VOL(UVLO) V Output Voltage Rise Time (CL = 1.0 nF, TJ = 25C) tr - 50 150 - 50 150 ns Output Voltage Fall Time (CL = 1.0 nF, TJ = 25C) tf - 50 150 - 50 150 ns 15 7.8 16 8.4 17 9.0 14.5 7.8 16 8.4 17.5 9.0 9.0 7.0 10 7.6 11 8.2 8.5 7.0 10 7.6 11.5 8.2 46 - 48 - 50 0 47 - 48 - 50 0 UNDERVOLTAGE LOCKOUT SECTION Startup Threshold UCX844 UCX845 Vth Minimum Operating Voltage After Turn-On UCX844 UCX845 VCC(min) V V PWM SECTION Duty Cycle Maximum Minimum % DCmax DCmin TOTAL DEVICE Power Supply Current (Note 4) Startup: (VCC = 6.5 V for UCX845A, (VCC 14 V for UCX844) Operating ICC Power Supply Zener Voltage (ICC = 25 mA) VZ mA - - 0.5 12 1.0 17 - - 0.5 12 1.0 17 30 36 - 30 36 - 4. Adjust VCC above the Startup threshold before setting to 15 V. 5. Low duty cycle pulse techniques are used during test to maintain junction temperature as close to ambient as possible. Thigh = +70C for UC3844, UC3845 Tlow = 0C for UC3844, UC3845 -25C for UC2844, UC2845 +85C for UC2844, UC2845 6. This parameter is measured at the latch trip point with VFB = 0 V. 7. Comparator gain is defined as: AV DV Output Compensation DV Current Sense Input http://onsemi.com 3 V 75 10 0 50 VCC = 15 V TA = 25C % DT, PERCENT OUTPUT DEADTIME 20 10 5.0 2.0 NOTE: Output switches at one-half the oscillator frequency. 1.0 10 k 20 k 50 k 100 k 200 k 500 k 1.0 nF 70 2.0 nF 5.0 nF 65 CT = 10 nF 60 55 50 10 k 1.0 M 20 k 50 k 500 pF 500 k fosc, OSCILLATOR FREQUENCY (Hz) Figure 2. Timing Resistor versus Oscillator Frequency Figure 3. Output Deadtime versus Oscillator Frequency VCC = 15 V AV = -1.0 TA = 25C 2.5 V 2.45 V 1.0 M VCC = 15 V AV = -1.0 TA = 25C 3.0 V 20 mV/DIV 2.5 V 2.0 V 0.5 ms/DIV 1.0 ms/DIV Figure 5. Error Amp Large Signal Transient Response VCC = 15 V VO = 2.0 V to 4.0 V RL = 100 K TA = 25C 80 Gain 60 0 30 60 40 90 Phase 20 120 0 150 100 1.0 k 10 k 100 k , EXCESS PHASE (DEGREES) 100 180 10 M 1.0 M Vth, CURRENT SENSE INPUT THRESHOLD (V) Figure 4. Error Amp Small Signal Transient Response A VOL , OPEN LOOP VOLTAGE GAIN (dB) 200 k fosc, OSCILLATOR FREQUENCY (Hz) 2.55 V -20 10 100 k 100 pF 200 pF 200 mV/DIV RT, TIMING RESISTOR (k ) UC3844, UC3845, UC2844, UC2845 1.2 VCC = 15 V 1.0 0.8 TA = 25C 0.6 TA = 125C 0.4 TA = -55C 0.2 0 0 f, FREQUENCY (Hz) 2.0 4.0 6.0 VO, ERROR AMP OUTPUT VOLTAGE (V) Figure 6. Error Amp Open Loop Gain and Phase versus Frequency Figure 7. Current Sense Input Threshold versus Error Amp Output Voltage http://onsemi.com 4 8.0 , REFERENCE SHORT CIRCUIT CURRENT (mA) SC V ref , REFERENCE VOLTAGE CHANGE (mV) UC3844, UC3845, UC2844, UC2845 0 VCC = 15 V -4.0 -8.0 -12 TA = 125C -16 TA = 25C -20 -24 TA = -55C 0 20 40 60 80 100 120 VCC = 15 V RL 0.1 W 90 70 50 -55 0 25 50 75 100 Figure 9. Reference Short Circuit Current versus Temperature V , OUTPUT VOLTAGE CHANGE (2.0 mV/DIV) V , OUTPUT VOLTAGE CHANGE (2.0 mV/DIV) Figure 8. Reference Voltage Change versus Source Current VCC = 15 V IO = 1.0 mA to 20 mA TA = 25C VCC = 12 V to 25 V TA = 25C O O 2.0 ms/DIV 2.0 ms/DIV Figure 10. Reference Load Regulation V sat , OUTPUT SATURATION VOLTAGE (V) -25 TA, AMBIENT TEMPERATURE (C) I Iref, REFERENCE SOURCE CURRENT (mA) 110 0 Source Saturation (Load to Ground) VCC -1.0 TA = 25C -2.0 Figure 11. Reference Line Regulation VCC = 15 V 80 ms Pulsed Load 120 Hz Rate VCC = 15 V CL = 1.0 nF TA = 25C 90% TA = -55C 3.0 TA = -55C 2.0 TA = 25C 10% 1.0 0 Sink Saturation (Load to VCC) 0 200 400 GN D 600 50 ns/DIV 800 IO, OUTPUT LOAD CURRENT (mA) Figure 12. Output Saturation Voltage versus Load Current Figure 13. Output Waveform http://onsemi.com 5 125 VCC, OUTPUT VOLTAGE UC3844, UC3845, UC2844, UC2845 20 15 5 0 100 ns/DIV UCX844 10 UCX845 ICC, SUPPLY CURRENT 100 mA/DIV ICC, SUPPLY CURRENT (mA) 20 V/DIV 25 VCC = 30 V CL = 15 pF TA = 255C 0 Figure 14. Output Cross Conduction 10 RT = 10 k CT = 3.3 nF VFB = 0 V ISense = 0 V TA = 255C 20 30 VCC, SUPPLY VOLTAGE (V) 40 Figure 15. Supply Current versus Supply Voltage PIN FUNCTION DESCRIPTION Pin 8-Pin 14-Pin Function 1 1 Compensation 2 3 Voltage Feedback This is the inverting input of the Error Amplifier. It is normally connected to the switching power supply output through a resistor divider. 3 5 Current Sense A voltage proportional to inductor current is connected to this input. The PWM uses this information to terminate the output switch conduction. 4 7 RT/CT The Oscillator frequency and maximum Output duty cycle are programmed by connecting resistor RT to Vref and capacitor CT to ground. Operation to 1.0 MHz is possible. 5 - GND This pin is combined control circuitry and power ground (8-pin package only). 6 10 Output 7 12 VCC This pin is the positive supply of the control IC. 8 14 Vref This is the reference output. It provides charging current for capacitor CT through resistor RT. - 8 Power Ground This pin is a separate power ground return (14-pin package only) that is connected back to the power source. It is used to reduce the effects of switching transient noise on the control circuitry. - 11 VC The Output high state (VOH) is set by the voltage applied to this pin (14-pin package only). With a separate power source connection, it can reduce the effects of switching transient noise on the control circuitry. - 9 GND - 2,4,6,13 NC Description This pin is Error Amplifier output and is made available for loop compensation. This output directly drives the gate of a power MOSFET. Peak currents up to 1.0 A are sourced and sunk by this pin. The output switches at one-half the oscillator frequency. This pin is the control circuitry ground return (14-pin package only) and is connected to back to the power source ground. No connection (14-pin package only). These pins are not internally connected. http://onsemi.com 6 UC3844, UC3845, UC2844, UC2845 OPERATING DESCRIPTION The UC3844, UC3845 series are high performance, fixed frequency, current mode controllers. They are specifically designed for Off-Line and DC-to-DC converter applications offering the designer a cost effective solution with minimal external components. A representative block diagram is shown in Figure 16. This occurs when the power supply is operating and the load is removed, or at the beginning of a soft-start interval (Figures 21, 22). The Error Amp minimum feedback resistance is limited by the amplifier's source current (0.5 mA) and the required output voltage (VOH) to reach the comparator's 1.0 V clamp level: Rf(min) Oscillator The oscillator frequency is programmed by the values selected for the timing components RT and CT. Capacitor CT is charged from the 5.0 V reference through resistor RT to approximately 2.8 V and discharged to 1.2 V by an internal current sink. During the discharge of CT, the oscillator generates an internal blanking pulse that holds the center input of the NOR gate high. This causes the Output to be in a low state, thus producing a controlled amount of output deadtime. An internal flip-flop has been incorporated in the UCX844/5 which blanks the output off every other clock cycle by holding one of the inputs of the NOR gate high. This in combination with the CT discharge period yields output deadtimes programmable from 50% to 70%. Figure 2 shows RT versus Oscillator Frequency and Figure 3, Output Deadtime versus Frequency, both for given values of CT. Note that many values of RT and CT will give the same oscillator frequency but only one combination will yield a specific output deadtime at a given frequency. In many noise sensitive applications it may be desirable to frequency-lock the converter to an external system clock. This can be accomplished by applying a clock signal to the circuit shown in Figure 18. For reliable locking, the free-running oscillator frequency should be set about 10% less than the clock frequency. A method for multi unit synchronization is shown in Figure 19. By tailoring the clock waveform, accurate Output duty cycle clamping can be achieved to realize output deadtimes of greater than 70%. 3.0 (1.0 V) + 1.4 V = 8800 W 0.5 mA Current Sense Comparator and PWM Latch The UC3844, UC3845 operate as a current mode controller, whereby output switch conduction is initiated by the oscillator and terminated when the peak inductor current reaches the threshold level established by the Error Amplifier Output/Compensation (Pin 1). Thus the error signal controls the inductor current on a cycle-by-cycle basis. The current Sense Comparator PWM Latch configuration used ensures that only a single pulse appears at the Output during any given oscillator cycle. The inductor current is converted to a voltage by inserting the ground referenced sense resistor RS in series with the source of output switch Q1. This voltage is monitored by the Current Sense Input (Pin 3) and compared a level derived from the Error Amp Output. The peak inductor current under normal operating conditions is controlled by the voltage at pin 1 where: Ipk = V(Pin 1) - 1.4 V 3 RS Abnormal operating conditions occur when the power supply output is overloaded or if output voltage sensing is lost. Under these conditions, the Current Sense Comparator threshold will be internally clamped to 1.0 V. Therefore the maximum peak switch current is: Ipk(max) = 1.0 V RS When designing a high power switching regulator it becomes desirable to reduce the internal clamp voltage in order to keep the power dissipation of RS to a reasonable level. A simple method to adjust this voltage is shown in Figure 20. The two external diodes are used to compensate the internal diodes yielding a constant clamp voltage over temperature. Erratic operation due to noise pickup can result if there is an excessive reduction of the Ipk(max) clamp voltage. A narrow spike on the leading edge of the current waveform can usually be observed and may cause the power supply to exhibit an instability when the output is lightly loaded. This spike is due to the power transformer interwinding capacitance and output rectifier recovery time. The addition of an RC filter on the Current Sense Input with a time constant that approximates the spike duration will usually eliminate the instability; refer to Figure 24. Error Amplifier A fully compensated Error Amplifier with access to the inverting input and output is provided. It features a typical dc voltage gain of 90 dB, and a unity gain bandwidth of 1.0 MHz with 57 degrees of phase margin (Figure 6). The noninverting input is internally biased at 2.5 V and is not pinned out. The converter output voltage is typically divided down and monitored by the inverting input. The maximum input bias current is -2.0 mA which can cause an output voltage error that is equal to the product of the input bias current and the equivalent input divider source resistance. The Error Amp Output (Pin 1) is provide for external loop compensation (Figure 29). The output voltage is offset by two diode drops ( 1.4 V) and divided by three before it connects to the inverting input of the Current Sense Comparator. This guarantees that no drive pulses appear at the Output (Pin 6) when Pin 1 is at its lowest state (VOL). http://onsemi.com 7 UC3844, UC3845, UC2844, UC2845 VCC VCC Vref 8(14) R Internal Bias 2.5V RT R 3.6V + + - - 7(12) 36V + Reference Regulator VCC UVLO - Vin + - VC 7(11) Vref UVLO Output Q1 Oscillator 4(7) + CT Voltage Feedback Input 2(3) Output Compensation 1(1) 6(10) T Q 1.0mA Power Ground S + - - + 2R Error Amplifier R Q R 5(8) PWM Latch Current Sense Input 1.0V Current Sense Comparator GND 5(9) 3(5) + - = Sink Only Positive True Logic Pin numbers in parenthesis are for the D suffix SOIC-14 package. Figure 16. Representative Block Diagram Capacitor CT Latch ``Set'' Input Output/ Compensation Current Sense Input Latch ``Reset'' Input Output Large RT/Small CT Small RT/Large CT Figure 17. Timing Diagram http://onsemi.com 8 RS UC3844, UC3845, UC2844, UC2845 Undervoltage Lockout designer added flexibility in tailoring the drive voltage independent of VCC. A zener clamp is typically connected to this input when driving power MOSFETs in systems where VCC is greater the 20 V. Figure 23 shows proper power and control ground connections in a current sensing power MOSFET application. Two undervoltage lockout comparators have been incorporated to guarantee that the IC is fully functional before the output stage is enabled. The positive power supply terminal (VCC and the reference output (Vref) are each monitored by separate comparators. Each has built-in hysteresis to prevent erratic output behavior as their respective thresholds are crossed. The VCC comparator upper and lower thresholds are 16 V/10 V for the UCX844, and 8.4 V/7.6 V for the UCX845. The Vref comparator upper and lower thresholds are 3.6 V/3/4 V. The large hysteresis and low startup current of the UCX844 makes it ideally suited in off-line converter applications where efficient bootstrap startup techniques later required (Figure 30). The UCX845 is intended for lower voltage DC-to-DC converter applications. A 36 V zener is connected as a shunt regulator from VCC to ground. Its purpose is to protect the IC from excessive voltage that can occur during system startup. The minimum operating voltage for the UCX844 is 11 V and 8.2 V for the UCX845. Reference The 5.0 V bandgap reference is trimmed to 1.0% tolerance at TJ = 25C on the UC284X, and 2.0% on the UC384X. Its primary purpose is to supply charging current to the oscillator timing capacitor. The reference has short circuit protection and is capable of providing in excess of 20 mA for powering additional control system circuitry. Design Considerations Do not attempt to construct the converter on wire-wrap or plug-in prototype boards. High frequency circuit layout techniques are imperative to prevent pulsewidth jitter. This is usually caused by excessive noise pick-up imposed on the Current Sense or Voltage Feedback inputs. Noise immunity can be improved by lowering circuit impedances at these points. The printed circuit layout should contain a ground plane with low-current signal and high-current switch and output grounds returning on separate paths back to the input filter capacitor. Ceramic bypass capacitors (0.1 mF) connected directly to VCC, VC, and Vref may be required depending upon circuit layout. This provides a low impedance path for filtering the high frequency noise. All high current loops should be kept as short as possible using heavy copper runs to minimize radiated EMI. The Error Amp compensation circuitry and the converter output voltage divider should be located close to the IC and as far as possible from the power switch and other noise generating components. Output These devices contain a single totem pole output stage that was specifically designed for direct drive of power MOSFETs. It is capable of up to 1.0 A peak drive current and has a typical rise and fall time of 50 ns with a 1.0 nF load. Additional internal circuitry has been added to keep the Output in a sinking mode whenever and undervoltage lockout is active. This characteristic eliminates the need for an external pull-down resistor. The SOIC-14 surface mount package provides separate pins for VC (output supply) and Power Ground. Proper implementation will significantly reduce the level of switching transient noise imposed on the control circuitry. This becomes particularly useful when reducing the Ipk(max) clamp level. The separate VC supply input allows the Vref 8(14) R Bias RT RB 6 OSC 0.01 CT 5 2 + - 47 2(3) 5.0k + - + 4(7) EA 2R R + - Bias R OSC R 3 Q S + 4(7) + - 7 5.0k MC1455 C R 4 8 5.0k External Sync Input 8(14) RA R 2(3) EA 2R R 1 1(1) 1(1) 5(9) The diode clamp is required if the Sync amplitude is large enough to cause the bottom side of CT to go more than 300 mV below ground. 1.44 f= (RA + 2RB)C Figure 18. External Clock Synchronization Dmax = RB RA + 2RB To Additional UCX84XA's Figure 19. External Duty Cycle Clamp and Multi-Unit Synchronization http://onsemi.com 9 5(9) UC3844, UC3845, UC2844, UC2845 VCC Vin 7(12) + - 5.0Vref 8(14) + R Bias R OSC + - R2 2(3) T Bias R Q R Comp/Latch - + 2R R 5(8) 3(5) R2 R1 R2 R1 + R2 + 0.33 x 10-3 + - +1 R1 1.0M 2(3) RS VCC R Bias R + + 4(7) + - 2(3) 7(11) T R2 + R1 VClamp R2 R1 Ipk(max) VClamp RS tSoftstart = - In R1 R2 R1 + R2 + 0.33 x 10-3 +1 1- VC 3VClamp C Control CIrcuitry Ground: To Pin (9) M K RS 1/4 W Power Ground To Input Source Return Virtually lossless current sensing can be achieved with the implement of a SENSEFET power switch. For proper operation during over current conditions, a reduction of the Ipk(max) clamp level must be implemented. Refer to Figures 20 and 22. R1 R2 R1 + R2 Figure 22. Adjustable Buffered Reduction of Clamp Level with Soft-Start Figure 23. Current Sensing Power MOSFET VCC Vin 7(12) + - 5.0Vref + rDM(on) + RS (8) (5) Where: 0 VClamp 1.0 V RS Ipk rDS(on) S (10) G T S Q - R + Comp/Latch RS 1.67 + (11) 3(5) VPin 5 If: SENSEFET = MTP10N10M RS = 200 Then: Vpin 5 = 0.075 Ipk D SENSEFET - 5(8) 5(9) MPSA63 Vin - + - 6(10) 1(1) C + - 5.0Vref Q1 S Q - R + Comp/Latch 1.0V 2R R EA VCC - VClamp 1.0mA 5(9) (12) - OSC Q Vin + + - R Figure 21. Soft-Start Circuit 7(12) 8(14) - + 2R R tSoft-Start 3600C in mF Figure 20. Adjustable Reduction of Clamp Level + - 1.0mA EA 1(1) C Where: 0 VClamp 1.0 V 5.0Vref S 1.0V VClamp Ipk(max) T + 4(7) 5(9) + - - OSC RS 1.67 + S 1.0mA 1.0V VClamp R 6(10) 1(1) R1 8(14) Q1 VClamp EA 5.0Vref 7(11) - + 4(7) - + - + + - + - 7(11) - Q1 T 6(10) S - + Q R Comp/Latch 5(8) R 3(5) C RS The addition of the RC filter will eliminate instability caused by the leading edge spike on the current waveform. Figure 24. Current Waveform Spike Suppression http://onsemi.com 10 UC3844, UC3845, UC2844, UC2845 VCC Base Charge Removal + - - + - + Vin + 0 + - 5.0Vref IB Vin 7(12) C1 7(11) Rg - Q1 Q1 T 6(10) 6(1) 5(8) 5(8) S - + Q R Comp/Latch 3(5) 3(5) RS RS The totem-pole output can furnish negative base current for enhanced transistor turn-off, with the addition of capacitor C1. Series gate resistor Rg will damp any high frequency parasitic oscillations caused by the MOSFET input capacitance and any series wiring inductance in the gate-source circuit. Figure 25. MOSFET Parasitic Oscillations Figure 26. Bipolar Transistor Drive R 8(14) Bias R VCC Vin OSC 7(12) + - 5.0Vref + + - Isolation Boundary + + 0 - - T 6(10) S Q R Comp/Latch R 3(5) C RS NS + 0 - 50% DC Ipk = 5(8) 2(3) 25% DC V(pin 1) - 1.4 3 RS 1(1) Np Rd 2(3) The MCR101 SCR must be selected for a holding of less than 0.5 mA at TA(min). The simple two transistor circuit can be used in place of the SCR as shown. All resistors are 10 k. Figure 28. Latched Shutdown CI Rf From VO + 1.0mA + - EA Rp 2R R Cp 2.5V 2(3) Ri Rd 1(1) Rf 8.8 k 5(9) 2N 3903 NP NS From VO 2.5V 2R R EA 2N 3905 MCR 101 Figure 27. Isolated MOSFET Drive Ri 1.0mA VGS Waveforms Q1 7(11) - + EE E EEE EE - + - + 4(7) CI Rf + - + 1.0mA EA 2R R 1(1) 5(9) 5(9) Error Amp compensation circuit for stabilizing any current-mode topology except for boost and flyback converters operating with continuous inductor current. Error Amp compensation circuit for stabilizing current-mode boost and flyback topologies operating with continuous inductor current. Figure 29. Error Amplifier Compensation http://onsemi.com 11 UC3844, UC3845, UC2844, UC2845 4.7W + MDA 202 3300pF 4.7k 250 T1 1N4935 + + 68 + - 5.0Vref 0.01 + 33k OSC T 18k 150k 12V/0.3A + 2.7k -12V/0.3A L3 1N4937 22W + + - 10 + MUR110 680pF 7(11) 4(7) 1.0nF + + + - 5.0V/4.0A 12V RTN 1000 1N4937 Bias L2 10 47 100 8(14) 100pF + 5.0V RTN + 1000 7(12) 4.7k 1000 MUR110 1N4935 2(3) + 2200 56k 115VA C L1 MBR1635 S - + EA 6(10) Q R 5(8) Comp/Latch 3(5) 1N5819 1.0k 470pF 1(1) MTP 4N50 0.5W 5(9) T1 - Primary: 45 Turns # 26 AWG T1 - Secondary 12 V: 9 Turns # 30 AWG T1 - (2 strands) Bifiliar Wound T1 - Secondary 5.0 V: 4 Turns (six strands) T1 - #26 Hexfiliar Wound T1 - Secondary Feedback: 10 Turns #30 AWG T1 - (2 strands) Bifiliar Wound T1 - Core: Ferroxcube EC35-3C8 T1 - Bobbin: Ferroxcube EC35PCB1 T1 - Gap 0.01" for a primary inductance of 1.0 mH L1 - 15 mH at 5.0 A, Coilcraft Z7156. L2, L3 - 25 mH at 1.0 A, Coilcraft Z7157. Figure 30. 27 Watt Off-Line Flyback Regulator Test Conditions Results Line Regulation: 5.0 V 12 V Vin = 95 VAC to 130 VAC D = 50 mV or 0.5% D = 24 mV or 0.1% Load Regulation: 5.0 V 12 V Vin = 115 VAC, Iout = 1.0 A to 4.0 A Vin = 115 VAC, Iout = 100 mA to 300 mA D = 300 mV or 3.0% D = 60 mV or 0.25% Output Ripple: 5.0 V 12 V Vin = 115 VAC 40 mVpp 80 mVpp Vin = 115 VAC 70% Efficiency All outputs are at nominal load currents, unless otherwise noted. http://onsemi.com 12 UC3844, UC3845, UC2844, UC2845 Vin = 15V UC3845 8(14) R Internal Bias R 10k 3.6V + + - - - VCC UVLO + Vref UVLO 15 10 0.5mA Error Amplifier 1(1) Q R R PWM Latch VO 2 (Vin) + 47 Connect to Pin 2 for closed loop operation. 5(8) S - + 1N5819 + T + - 2(3) 29.9 28.8 28.3 27.4 24.4 7(11) 6(10) 2R VO (V) 0 2 9 18 36 - Oscillator + IO (mA) 1N5819 4(7) 1.0nF Output Load Regulation (open loop configuration) 47 34V + Reference Regulator 2.5V + 7(12) R2 3(5) 1.0V R2 +1 R2 VO = 2.5 Current Sense Comparator R1 5(9) The capacitor's equivalent series resistance must limit the Drive Output current to 1.0 A. An additional series resistor may be required when using tantalum or other low ESR capacitors. The converter's output can provide excellent line and load regulation by connecting the R2/R1 resistor divider as shown. Figure 31. Step-Up Charge Pump Converter Vin = 15V UC3845 8(14) Internal Bias 2.5V R 10k 3.6V + + - - VCC UVLO - 47 34V + Reference Regulator R + 7(12) + - 7(11) Vref UVLO 4(7) 6(10) Oscillator + 1.0nF 2(3) 1(1) + - Error Amplifier + T 0.5mA 1N5819 VO - (Vin) + 1N5819 47 Q - + R 10 5(8) S 2R 15 R PWM Latch 1.0V Output Load Regulation 3(5) Current Sense Comparator 5(9) The capacitor's equivalent series resistance must limit the Drive Output current to 1.0 A. An additional series resistor may be required when using tantalum or other low ESR capacitors. Figure 32. Voltage-Inverting Charge Pump Converter http://onsemi.com 13 IO (mA) VO (V) 0 2 9 18 32 -14.4 -13.2 -12.5 -11.7 -10.6 UC3844, UC3845, UC2844, UC2845 ORDERING INFORMATION Package Shipping UC3844D SOIC-14 55 Units/Rail UC3844DG SOIC-14 (Pb-Free) 55 Units/Rail UC3844DR2 SOIC-14 2500 Tape & Reel UC3844DR2G SOIC-14 (Pb-Free) 2500 Tape & Reel PDIP-8 50 Units/Rail PDIP-8 (Pb-Free) 50 Units/Rail Device Operating Temperature Range UC3844N UC3844NG TA = 0 to +70C SOIC-14 55 Units/Rail UC3845DG SOIC-14 (Pb-Free) 55 Units/Rail UC3845DR2 SOIC-14 2500 Tape & Reel UC3845DR2G SOIC-14 (Pb-Free) 2500 Tape & Reel PDIP-8 50 Units/Rail UC3845NG PDIP-8 (Pb-Free) 50 Units/Rail UC2844D SOIC-14 55 Units/Rail UC2844DG SOIC-14 (Pb-Free) 55 Units/Rail UC2844DR2 SOIC-14 2500 Tape & Reel UC2844DR2G SOIC-14 (Pb-Free) 2500 Tape & Reel PDIP-8 50 Units/Rail PDIP-8 (Pb-Free) 50 Units/Rail UC3845D UC3845N UC2844N UC2844NG TA = -25 to +85C SOIC-14 55 Units/Rail UC2845DG SOIC-14 (Pb-Free) 55 Units/Rail UC2845DR2 SOIC-14 2500 Tape & Reel UC2845DR2G SOIC-14 (Pb-Free) 2500 Tape & Reel PDIP-8 50 Units/Rail PDIP-8 (Pb-Free) 50 Units/Rail UC2845D UC2845N UC2845NG For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. MARKING DIAGRAMS SOIC-14 D SUFFIX CASE 751A PDIP-8 N SUFFIX CASE 626 8 14 UC384xN AWL YYWWG 8 384x ALYW G UC384xDG AWLYWW 1 14 UC284xN AWL YYWWG 1 8 1 1 SOIC-8 D1 SUFFIX CASE 751 UC284xDG AWLYWW 1 http://onsemi.com 14 x A WL, L YY, Y WW, W G or G = 4 or 5 = Assembly Location = Wafer Lot = Year = Work Week = Pb-Free Package UC3844, UC3845, UC2844, UC2845 PACKAGE DIMENSIONS PDIP-8 N SUFFIX CASE 626-05 ISSUE L 8 NOTES: 1. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 2. PACKAGE CONTOUR OPTIONAL (ROUND OR SQUARE CORNERS). 3. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 5 -B- 1 4 DIM A B C D F G H J K L M N F -A- NOTE 2 L C J -T- N SEATING PLANE D MILLIMETERS MIN MAX 9.40 10.16 6.10 6.60 3.94 4.45 0.38 0.51 1.02 1.78 2.54 BSC 0.76 1.27 0.20 0.30 2.92 3.43 7.62 BSC --- 10_ 0.76 1.01 INCHES MIN MAX 0.370 0.400 0.240 0.260 0.155 0.175 0.015 0.020 0.040 0.070 0.100 BSC 0.030 0.050 0.008 0.012 0.115 0.135 0.300 BSC --- 10_ 0.030 0.040 M K G H 0.13 (0.005) M T A M B M SOIC-14 D SUFFIX CASE 751A-03 ISSUE G -A- 14 8 -B- P 7 PL 0.25 (0.010) B M 7 1 G 0.25 (0.010) M T B J M K D 14 PL F R X 45 _ C -T- SEATING PLANE M S A S http://onsemi.com 15 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A B C D F G J K M P R MILLIMETERS MIN MAX 8.55 8.75 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.337 0.344 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.228 0.244 0.010 0.019 UC3844, UC3845, UC2844, UC2845 PACKAGE DIMENSIONS SOIC-8 D1 SUFFIX CASE 751-07 ISSUE AG -X- NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. 751-01 THRU 751-06 ARE OBSOLETE. NEW STANDARD IS 751-07. A 8 5 S B 0.25 (0.010) M Y M 1 4 -Y- K G C N DIM A B C D G H J K M N S X 45 _ SEATING PLANE -Z- 0.10 (0.004) H D 0.25 (0.010) M Z Y S X M J S MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.33 0.51 1.27 BSC 0.10 0.25 0.19 0.25 0.40 1.27 0_ 8_ 0.25 0.50 5.80 6.20 INCHES MIN MAX 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 BSC 0.004 0.010 0.007 0.010 0.016 0.050 0 _ 8 _ 0.010 0.020 0.228 0.244 SOLDERING FOOTPRINT* 1.52 0.060 7.0 0.275 4.0 0.155 0.6 0.024 1.270 0.050 SCALE 6:1 mm inches *For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. SENSEFET is a trademark of Semiconductor Components Industries, LLC. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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